JP2515020B2 - Gallium arsenide semiconductor integrated circuit - Google Patents

Description

The present invention relates to a gallium arsenide semiconductor integrated circuit, and more particularly to the circuit configuration of a gallium arsenide memory device.

[Conventional technology]

Figure 2 shows, for example, the 1984 Gallium Arsenide IC Symposium
Technical digest (GaAs IC Symposium Technica
1 Digest) shows a circuit configuration of a conventional gallium arsenide memory described on pages 117 to 120, 1 is a memory cell array, 2 is an X decoder, 3 is a Y decoder, 4 ₁ to 4 _m is a word line driver, 5 _{1 to} 5 _n are bit line selection signal drivers. Further, 6 is a power source on the high side of the memory cell, 7 is a power source on the high side of the X decoder and the Y decoder, and
The low-side power supplies of the decoder and the Y-decoder are commonly set to the ground potential.

FIG. 3 shows one memory cell included in the memory cell array 1, which uses the normally-on type MESFET 11 as a load and the normally-off type MESFET 13 as a driver.
And a second inverter that uses the normally-on MESFET 12 as a load and the normally-off MESFET 14 as a driver, and has a configuration in which the inputs and outputs of the first and second inverter circuits are cross-connected to each other. The normally-on type MESFET15 is the first transfer gate, the word line 21 is input to the gate, and the other two terminals are the first bit line.
19 and the first storage node 17 are connected. Similarly, the normally-on type MESFET 16 is the second transfer gate,
The word line 21 is input to the gate, and the second bit line 20 and the second storage node 18 are connected to the other two terminals.

FIG. 4 shows one X decoder circuit and word line driver circuit included in the X decoder 2. 30 is NO
Decoder circuit by R circuit, normally-on type MESFE
With T22 as a load, p normally-off MESFETs 23 ₁ to 23 _p
As a parallel driver circuit, the normally-off type MESF
ET23 ₁ to 23 _p gates have X address signals X ₁ to
X _p is input. Further, 31 is a word line driver circuit, the drain of the normally-on type MESFET 24 is connected to the power source 8, the gate is connected to the NOR output 27, the source is connected to the anode of the Schottky diode 25, and the cathode of the Schottky diode 25 is connected to the drain 28 of the normally-on type MESFET 26. The gate and source of the normally-on type MESFET 26 are connected to the negative power supply 29. The node 28 becomes a word line.

FIG. 5 shows one Y decoder circuit included in the Y decoder 3 and a driver circuit for the bit line selection signal. Configuration similar to the X decoder, 39 is a decoder circuit of a NOR circuit, a normally-MESFET32 as a load, and a q-number of normally-off type MESFET33 _{1 ~33 q} and parallel driver circuits, the normally-off MESFENT33 ₁ ~33 _The Y address signals Y _{1 to} Y _q are input to the respective gates of _q . Further, 40 is a driver circuit for a bit line selection signal, and in the normally-on type MESFET 34, the drain is the power source 8 and the gate is NOR.
The output 37 and the source are connected to the anode of the Schottky diode 35, the cathode of the Schottky diode 35 is connected to the drain 38 of the normally-on type MESFET 36, and the gate and source of the normally-on type MESFET 36 are connected to the negative power supply 29. The node 38 becomes a bit line selection signal.

Next, the operation will be described. First, selection in the row direction is performed by the X decoder. That is, since 30 is composed of a NOR circuit, all X address signals X _{1 to} X _p are LOW.
NOR output 27 becomes High level only when the level is set, and X _{1 to} X _p
NOR output 2 if at least one of them is high level
7 becomes LOW level. Normally, X _{1 to} X _p are configured such that all of them are LOW level for only one of the m X decoders for each address combination, so that only one of the m NOR outputs is High level, all other LOW level. Further, since the word line driver 31 operates as a level shift circuit by the source follower, the output signal 28 has the same phase as the input signal 27. That is,
The word line becomes High level only for one LOW, and becomes Low level for all other rows.

Next, the column direction selection is performed by the Y decoder, but the circuit configuration is exactly the same as that of the X decoder. Therefore, by the same operation, the bit line selection signal becomes the high level for only one column out of n. , All other columns are at LOW level.

Transfer gate when word line 21 goes high
15 and 16 become conductive, and the pair of data stored in the storage nodes 17 and 18 are read to the bit lines 19 and 20. Since one word line is commonly input to all columns, the read operation is performed in all columns.
Among these, only in the column in which the bit line selection signal is at the high level, the column is connected to the outside, and it is possible to read the data to the outside and write the data from the outside.

That is, for each combination of address signals, only 1
One memory cell is selected and data is read or written.

[Problems to be Solved by the Invention]

Since the conventional gallium arsenide memory device has the above structure, the current flow in the memory cell, the X decoder and the Y decoder is as follows.

First, in the memory cell, the current is determined by the normally-on type MESFETs 11 and 12 of the load, and this current value is limited by the leakage current from the drain to the source when the gates of the driver FETs 13 and 14 are at the low level. That is, the current of the load 11 or 12 is
This is because if the leak current is equal to or less than the leak current of the FET 13 or 14, the high level of the data is lowered and it becomes impossible to retain the data. Normally, in order to avoid this, the current value of the load 11 or 12 is set to the above driver FE.
It is one or two orders of magnitude higher than the leakage current of T13 or 14, but in the gallium arsenide MESFET, this leakage current is about 100 nA to 1 μA at high temperature, for example, silicon M
The load current is 1 because it is 5 to 6 digits higher than OSFET.
.About.50 .mu.A is required, so that a large amount of through current always flows through the memory cell. This shoot-through current flows regardless of whether the memory cell is selected or not, and does not change with time.

Next, in the X decoder, in the selected NOR circuit, normally-off type MESFETs 23 ₁ to 23 _p are all in the OFF state and no through current flows, but in the non-selected NOR circuit, at least _one of the normally-off type MESFETs 23 ₁ to 23 _p is used. Since one is in the ON state, a through current flows from the power supply 7 to the GND through the normally-on type MESFET 22 and the normally-off type MESFET in the ON state. That is, the selected X
The shoot-through current flows in all X decoders except the decoder. This through current also does not change with time.

The Y decoder is similar to the X decoder, and a time-invariant through current flows in all the Y decoders except one selected Y decoder.

As described above, in the gallium arsenide memory device according to the conventional configuration, a large amount of through current that does not change with time exists in the memory cell, the X decoder, and the Y decoder, and this through current occupies most of the whole current. . The increase in current not only leads to an increase in power consumption, but also leads to a malfunction due to a voltage drop in the wiring in the chip and an increase in the chip size, which is a major factor preventing high integration.

The present invention has been made to solve the above problems, and an object thereof is to obtain a gallium arsenide memory device suitable for high integration with small current in the memory cell, the X decoder, and the Y decoder. .

[Means for solving the problem]

In the gallium arsenide semiconductor integrated circuit according to the present invention, both the node serving as the high-side power source of the NOR circuit in the X and Y decoders and the node serving as the low-side power source of the memory cell array are separated from the power source and made common. is there.

[Action]

The gallium arsenide semiconductor integrated circuit according to the present invention has a structure of X
The through current is reduced by electrically connecting the Y decoder and the memory cell in series.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a memory cell array, 2 is an X decoder, 3 is a Y decoder, 4 ₁ to 4 _m are word line drivers, and 5 ₁ to
5 _n is a driver for the bit line selection signal. 6 is a power supply on the high side of the memory cell, 8 is a power supply node on the low side of the memory cell, 3 nodes are a power supply on the high side of the X decoder and a power supply on the high side of the Y decoder. They are separated and made common. Also, X
The lower power supply nodes of the decoder and the Y decoder are both grounded. Further, in this embodiment, the sum of the through currents in the memory cell array 1 and the sum of the through currents of the NOR circuits in the X decoder and the Y decoder are set to be approximately the same.

The operation of this embodiment is similar to that of the conventional example, but the memory cell array and the X and Y decoders are electrically connected in series via the node 8 as shown in FIG. The through current is half that of the conventional parallel connection shown in b). Also, since this shoot-through current is time-invariant,
The serial connection does not affect the operation.

Although the sum of the through currents in the memory cell array and the sum of the through currents of the NOR circuits in the X decoder and the Y decoder are set to the same level in the above embodiment, they may be different. That is, when there is more shoot-through current in the memory cell array, a current source 41 for current compensation is provided between the node 8 and GND as shown in FIG. However, in the opposite case, a current source 42 for current compensation may be provided between the power source 6 and the node 8 as shown in FIG. 7B.

Further, in the above embodiment, the NOR of the memory cell and the decoder is
Although the one using the normally-on type MESFET as the load element of the circuit has been described, another element such as a resistor may be used and the same effect as the above is obtained.

〔The invention's effect〕

As described above, according to the present invention, the node serving as the high-side power source of the NOR circuit in the X and Y decoders and the node serving as the low-side power source of the memory cell array are separated from the power source and are made common, Since the memory cell array and the X and Y decoders are electrically connected in series, the through current is small, the operation is stable, the chip size is small, and the gallium arsenide memory device suitable for high integration is obtained. is there.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a gallium arsenide memory device according to an embodiment of the present invention, FIG. 2 is a circuit block diagram of a conventional gallium arsenide memory device, and FIG. 3 is a circuit configuration diagram of a conventional memory cell. The figure shows the circuit configuration of a conventional X decoder,
FIG. 5 is a circuit configuration diagram of a conventional Y decoder, FIG. 6 (a).
And (b) are diagrams showing the path of the through current in the embodiment of the present invention and the conventional one, respectively, and FIG. 7 is a circuit block diagram showing another embodiment of the present invention. 1 ... Memory cell array, 2 ... X decoder, 3 ... Y
Decoder, 4 ₁ to 4 _m ... word line driver, 5 _{1 to} 5 _n ... bit line selection signal driver, 6 ... memory cell array power supply, 7 ... X and Y decoder power supply, 8 ... memory cell Lower power supply node and higher power supply nodes for X decoder and Y decoder, 11,12,15,16,22,24,26,32,34,36
...... Normally type MESFET, 13,14,23 ₁ to 23 _p , 33 _{1 to} 33 _q
...... Normally off type MESFET, 17,18 …… 1 of memory cell
Pair of storage nodes, 19, 20 ... Pair of bit lines, 21,
28 …… Word line, X _{1 to} X _p …… X address signal, Y _{1 to} Y _q …
… Y address signal, 25,35 …… Schottky diode, 2
7,37 …… NOR output node, 29 …… Second power supply, 30,39 ……
NOR circuit, 31 ... word line driver, 38 ... bit line selection signal node, 40 ... bit line selection signal driver, 4
1,42 …… Current source for current compensation. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A memory device comprising: a plurality of memory cells formed on a semi-insulating gallium arsenide semiconductor substrate; and a plurality of decoder circuits each comprising a NOR circuit for selecting the memory cells. All or part of the memory cell is connected between the first power supply and the first node as the current supply source of the first power supply and the first node as a current extraction node, and the plurality of NORs are connected. The whole or part of the circuit is connected between the first node and the second power supply by using the first node as a current supply source and the second power supply as a current extraction node. Characteristic gallium arsenide semiconductor integrated circuit.