JP3154508B2 - Power supply reinforcement method and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reinforcing a power supply in a semiconductor device such as a semiconductor integrated circuit, and more particularly to a technique effective when applied to a semiconductor memory device such as a static RAM.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, various input / output buffer circuits are used to amplify signals between circuits connected to external terminals thereof without being affected by signal level mismatch. Provided. For example, in the case of a semiconductor memory device, an address buffer circuit, a data input / output buffer circuit, and another input buffer circuit to which a control signal and the like are supplied are provided. In such a semiconductor memory device, when output data supplied to the outside is changed from a high level to a low level, a relatively high level signal charge on an external data bus coupled to a data output terminal is internally stored in the external terminal. Is supplied to the ground line of the semiconductor memory device via the output buffer circuit connected by the above. The current flowing to the ground line in this manner increases substantially in proportion to the number of bits of output data, in other words, substantially in proportion to the number of output buffer circuits whose output levels are inverted almost simultaneously. When a relatively large current instantaneously flows through the ground line, a counter electromotive force is generated due to a non-negligible inductance component of the circuit, and an undesired rise in the potential of the ground line is generated.

[0003] Incidentally, the above-mentioned undesired rise in the potential of the ground line can cause noise for circuits and the like sharing the ground line. Even if the ground line is not directly shared, noise may be caused by induction or crosstalk. Considering the influence of an undesired rise in the potential of the ground line on the input buffer circuit, for example, when a signal to be regarded as a high level is externally supplied to a predetermined input buffer circuit, the output data becomes high. When the potential of the ground line is undesirably increased due to the change from the low level to the low level, the input buffer circuit inputs the potential fluctuation at that time as noise from the ground line, or the undesired potential increase. , The input signal is regarded as low level, and an internal circuit receiving the input signal may malfunction.

Therefore, conventionally, a power supply line is made thicker to reduce the resistance, or a plurality of power supply lines having the same polarity are formed to divide the power supply for each functional block. A capacitor is arranged between the power supply Vss line and the power supply noise is absorbed by the capacitor.

[0005] An example of a document describing noise caused by fluctuations in power supply voltage is disclosed in November 3, 1984.
There is a description on page 135 of "LSI Handbook" issued by Ohm Co., Ltd. on the 0th.

[0006]

The inventors of the present invention have studied the conventional countermeasures against power supply noise. As a result, in a semiconductor integrated circuit, there is a limit to making the power supply line thicker. It has been found that the method of arranging a capacitor between the power supply Vss line and the power supply Vss line cannot absorb a change in a logic threshold level due to a change in ground level, so that a sufficient noise suppression effect cannot be expected.

An object of the present invention is to provide a technique capable of effectively suppressing power supply noise by a simple method when a plurality of power supply lines having the same polarity are formed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as a first means, a plurality of power supply lines having the same polarity are bridged by an electric circuit element in order to suppress a potential level fluctuation of the power supply line. In a more specific embodiment, the electric circuit element can be a diode, a resistor, an inductor, or a capacitor.

Further, as a second means, when a semiconductor device is formed with a plurality of power lines having the same polarity, the plurality of power lines are connected to the lines so as to bridge the plurality of power lines. This is to provide an electric circuit element for suppressing the fluctuation of the potential of the power supply line. At this time, a diode or a resistor can be used as the electric circuit element.

[0012]

According to the above-mentioned means, the electric circuit element arranged so as to bridge the plurality of power lines having the same polarity can increase the potential of one of the power lines connected by the electric circuit element. Is absorbed by the other power supply line side, thereby suppressing potential fluctuations and reducing power supply noise.

[0013]

FIG. 9 shows a static RAM to which an embodiment of the present invention is applied. Although not particularly limited, the static RAM shown in FIG. 1 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 9, reference numeral 6 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The selection terminals of the memory cells are connected to word lines in every row direction, and the data input / output terminals of the memory cells are column-type. Each direction is coupled to a complementary data line (also referred to as a complementary bit line). Each complementary data line has 1
Y including a plurality of column selection switches coupled one-to-one
Commonly connected to complementary common data lines via a selection switch circuit 9.

Address signals A0 to A input from outside
m, A0 to An are transmitted to X decoder 4 via address buffers 1-0 to 1-n arranged corresponding thereto, and address signals An + 1 to Am are applied to address buffers arranged corresponding thereto. The signal is transmitted to the Y decoder 8 via 1-n + 1 to 1-m. Word driver 5 is X
The word line corresponding to the input address signal is driven to a selected level based on the decode output of the decoder 4. When a predetermined word line is driven, a memory cell connected to this word line is selected. Further, the Y decoder 8 turns on the column selection switch corresponding to the address signal supplied thereto, and conducts to the selected complementary common data line. At this time, the potential of the complementary common data line is amplified by the sense amplifier 10B included in the data input / output circuit 10, and can be output to the outside via the output buffer (D-OUT) 10C. Further, when write data is externally supplied to the data input / output circuit 10, the input buffer (D-IN) 10A included in the data input / output circuit 10 drives the complementary common data line according to the write data. Charge information corresponding to the data is accumulated in a predetermined memory cell via a complementary data line selected by the address signal.

Further, a detection result of an address change detection circuit (also referred to as an ATD circuit) 11 for detecting a change in the address signals A0 to Am is transmitted to the control unit 7, and a chip select as an externally applied selection signal is provided. Signal C
The S * (* indicates that the signal is active low) and the read / write signal WE * are taken into the control unit 7 via the CS * buffer 2 and the WE * buffer 3, respectively. Is generated.

The power supply line of the static RAM shown in FIG. 9 is not particularly limited. However, as shown in FIG. 1, the low-potential-side power supply Vss line as the ground line is set as Vss1, Vss2, and Vss3. 3
Divided into strains. Each system of the low-potential-side power supply line may share an external power supply terminal or may have the terminal independently. Although not particularly limited, the high-potential-side power supply Vcc is one system in this embodiment. The peripheral circuit 21 is connected to the high potential power supply Vcc and the low potential power supply Vss1.
Are connected, and the high-potential-side power supply Vcc and the low-potential-side power supply Vss
2, an output driver 22 is coupled to the high-potential-side power supply Vc.
An output driver 23 is coupled to c and the low potential side power supply Vss3. The peripheral circuit 21 includes the sense amplifier 10B and the address buffers 1-0 to 1-n shown in FIG.
Decoders 4, 8 and other peripheral circuits other than output buffer 10C are included. The output driver 22, 2
3 are included in the output buffer 10C shown in FIG. 9 and can be operated at different timings.

Two diodes D1 and D2 are arranged between the low-potential-side power supply Vss1 line and the low-potential-side power supply Vss2 line so as to bridge them. The cathodes of the diodes D1 and D2 are coupled to the low-potential-side power supply Vss2 line, and the anodes are coupled to the low-potential-side power supply Vss1 line. Further, a diode D3 is arranged between the low-potential-side power supply Vss2 line and the low-potential-side power supply Vss3 line so as to bridge them. The cathode of the diode D3 is coupled to the low-potential power supply Vss3 line, and the anode of the diode D3 is coupled to the low-potential power supply Vss3. In FIG. 1, when the anode-side potential is higher than the cathode-side potential, diodes D1, D2, and D3 connect a forward current, that is, a low-potential-side power supply Vss1 line to a low-potential-side power supply Vss1.
It is an electric circuit element for suppressing a potential fluctuation of the power supply line by allowing a current to the two lines and a current flow from the low potential side power supply Vss2 line to the low potential side power supply Vss3 line.

As shown in FIG. 2, the output driver 2
It is assumed that the operation of the sense amplifier 10B is started when the operations of the sense amplifiers 2 and 23 are not performed. When the operation of the sense amplifier 10B is started, by instantaneously flows through the relatively large current low-potential-side power supply Vss 1 line, the presence of such an inductance component that can not be ignored in the circuit, the low potential side power supply While causing undesired potential increase in vss 1 line, then the diode D1, through D2 low potential side power supply Vss1
A current flows from the line to the low-potential-side power supply Vss2 line, and further from the low-potential-side power supply Vss2 line to the low-potential-side power supply Vss3 line via the diode D3.
An increase in the potential of the low-potential-side power supply Vss1 line is suppressed.
That is, when the diodes D1, D2, and D3 do not exist (no reinforcement), the diodes D1, D2, and D3 are provided, while the low-potential-side power supply Vss1 is increased as shown by a broken line in FIG. In this case (with reinforcement), the potential rise is suppressed as shown by the solid line. With such power supply reinforcement, the potentials of the low-potential-side power supply Vss2 line and the low-potential-side power supply Vss3 line are slightly increased as compared with the case without power supply reinforcement.
Is not in operation, so there is no problem.

Next, at the timing when the operation of the output driver 22 is started, the potential of the low-potential-side power supply Vss2 line is increased by the start of the operation of the output driver 22. Also in this case, when the power supply is not reinforced, the potential of the low-potential-side power supply Vss2 is increased as indicated by a broken line in FIG. 2, whereas when the power is reinforced by a diode, the potential is indicated by a solid line. As a result, the potential rise is suppressed. In addition, although the potential of the low-potential-side power supply Vss3 line is slightly increased by such power supply reinforcement as compared with the case where power supply reinforcement is not performed, there is no problem because the output driver 23 is not operating. At this time, the diode D
2. Due to the directionality of D3, the low-potential-side power supply Vss1 line is not involved in the potential suppression of the low-potential-side power supply Vss2 line. The potential does not rise, and therefore, the output state of the sense amplifier 10B, which has already been determined at that time, is not affected. As described above, by providing the diodes D1, D2, and D3, the low-potential-side power supply Vss1 depends on the direction.
Line, low potential side power supply Vss2 line, low potential side power supply V
The priority order of power supply reinforcement is set in the order of the ss3 lines, and power supply reinforcement is performed in accordance with the priority order. As a result, a rise in the low-potential-side power supply Vss is suppressed, and power supply noise due to a ground level rise is reduced.

According to this embodiment, the following functions and effects can be obtained.

(1) Diodes D1 and D2 are arranged between the low-potential-side power supply Vss1 line and the low-potential-side power supply Vss2 line to bridge them.
Between the ss2 line and the low potential side power supply Vss3 line,
By arranging the diode D3 so as to bridge them, the potential rise of the low-potential-side power supply Vss1 line and the potential rise of the low-potential-side power supply Vss2 line are suppressed,
Although the circuit configuration is very simple, power supply noise caused by the rise in the ground level is reduced.

(2) By applying the diodes D1, D2, and D3 as electric circuit elements for reinforcing the power supply as described above, the low-potential-side power supply V
The priority order of the power supply reinforcement is set in the order of the ss1 line, the low-potential-side power supply Vss2 line, and the low-potential-side power supply Vss3 line, and the power supply reinforcement is performed in accordance with the priorities. The power supply is efficiently reinforced by selecting the low-potential-side power supply Vss line to which it is coupled or determining the connection direction of the diode in consideration of the operation timing and the like of each block. Can do well.

FIG. 3 shows a second embodiment of the present invention.
The circuit shown in the figure is similar to the circuit shown in FIG.
It is a part of the static RAM shown in FIG.

In FIG. 3, the peripheral circuit 21 is coupled to the high-potential power supply Vcc line and the low-potential power supply Vss3 line, and the output driver 22 is connected to the high-potential power supply Vcc line and the low-potential power supply Vss2 line. The output driver 23 is connected to the high potential power supply Vcc line and the low potential power supply Vcc.
ss1 line. In addition, the low potential side power supply Vs
A resistor R1 is connected between the s1 line and the low-potential power supply Vss2 line so as to bridge them. Similarly, a resistor R1 is connected between the low-potential power supply Vss2 line and the low-potential power supply Vss3 line. The resistor R2 is connected so as to be connected. Here, the resistances R1 and R2 are not particularly limited, but are set to 20Ω and 100Ω, respectively, and both are electric circuit elements for suppressing potential fluctuation of the power supply line.

Unlike the case of the first embodiment, since the resistance has no directionality of the current, it is not possible to set the priority order of the power supply reinforcement. However, as shown in FIG. 4, the fluctuation of the low-potential power supply Vss2 can be reinforced by the low-potential power supply Vss1 and the low-potential power supply Vss3. And in that case, R1 <from the relation of R2, the low-potential power supply Vss2, rather than the relationship between the low potential side power supply Vss3 is dense the relationship between the low-potential-side power supply Vss 1, mainly, the low potential side power supply Vss1 Reinforced by.

Thus, even if the resistors R1 and R2 are applied, the low-potential-side power supply Vss can be reinforced in the same manner as in the above embodiment.

FIG. 5 shows a third embodiment of the present invention.
The circuit shown in the figure is similar to the circuit shown in FIG.
It is a part of the static RAM shown in FIG.

In FIG. 5, the peripheral circuit 21 is coupled to the high-potential power supply Vcc line and the low-potential power supply Vss2 line, and the output driver 22 is connected to the high-potential power supply Vcc line and the low-potential power supply Vss3 line. The output driver 23 is connected to the high potential power supply Vcc line and the low potential power supply Vcc.
ss1 line. In addition, the low potential side power supply Vs
An inductor L1 is connected between the s1 line and the low-potential power supply Vss2 line so as to bridge them. Similarly, the low-potential power supply Vss2 line and the low-potential power supply Vss3 are connected.
Between the line and the inductor L
2 are connected. Here, the inductors L1 and L2 are both electric circuit elements for suppressing potential fluctuation of the power supply line.

Unlike the case of the first embodiment, since the inductor has no current directionality, it is not possible to set the priority of power supply reinforcement. Further, due to the nature of the inductor, it cannot be reinforced against a sudden change in potential. However, FIG.
As shown in (1), reinforcement against DC potential change is effective. That is, it is not necessary for the application circuit of the inductors L1 and L2 to reinforce a sudden potential change of the low potential side power supply Vss.
(Low-level output current) increases the low-potential-side power supply Vss1 or Vss2, thereby increasing the DC power supply, such as when the level of VOL (low-level output voltage) is insufficient. Valid when needed.

As described above, even when the inductors L1 and L2 are applied, reinforcement of the low-potential-side power supply Vss, in particular, DC power supply can be achieved.

FIG. 7 shows a fourth embodiment of the present invention.

In FIG. 7, the peripheral circuit 21 is coupled to the high-potential power supply Vcc line and the low-potential power supply Vss2 line, and the output drivers 22 and 23 are connected to the high-potential power supply Vcc line and the low-potential power supply Vss1 line. And combined with. Also, the low-potential-side power supply Vss1 line and the low-potential-side power supply Vss1
A series circuit of an inductor L and a capacitor C is connected between the two lines so as to bridge them. The series circuit of the inductor L and the capacitor C is a band-pass filter, and is an electric circuit element for suppressing a potential fluctuation in a specific frequency band determined by those values.
An N-channel MOSFET Q is connected in parallel to the series circuit of the inductor L and the capacitor C, and the involvement of the band-pass filter can be controlled by turning on / off the MOSFET Q.
That is, as shown in FIG. 8, when the control signal Vg is set to the high level and the MOSFET Q is turned on, the low-potential-side power supply Vss1 line and the low-potential-side power supply Vss2 line are short-circuited. , The series circuit of the inductor L and the capacitor C is not involved in the circuit operation. On the contrary, when the control signal Vg is set to the low level and the MOSFET Q is turned off,
The series circuit of the inductor L and the capacitor C is involved in the circuit as a band-pass filter, and the low-potential-side power supply Vss1
It operates so as to suppress a potential level fluctuation in a predetermined frequency band between the power supply Vss2 and the low-potential-side power supply Vss2.

As described above, when the series circuit of the inductor L and the capacitor C is connected between the low potential side power supply Vss1 line and the low potential side power supply Vss2 line so as to bridge them, Is a band-pass filter circuit capable of passing a potential fluctuation component in a specific frequency band, so that power supply reinforcement against such a potential fluctuation in a specific frequency band is possible.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, in the above embodiment, the low potential side power supply V
Although the power supply reinforcement of the ss has been described, the power supply of the high potential power supply Vcc line can be reinforced by providing an electric circuit element between the plurality of high potential power supply Vcc lines. Alternatively, the voltage may be lowered. Further, it is not necessary to divide the low-potential-side power supply Vss into two systems, one for the output driver and the other for the peripheral circuit. For example, when the power supply in the peripheral circuit and the power supply for the output driver are divided into a plurality of systems, the power supply reinforcement is individually performed. May be performed. Further, the electric circuit elements such as the diode, the resistor, the inductor, and the capacitor can be appropriately combined. By laying out the electric circuit element for reinforcing the power supply below the power supply line (on the back side), it is possible to prevent the chip area from increasing due to the provision of the electric circuit element.

In the above description, the case where the invention made by the present inventor is mainly applied to a static RAM which is a field of application as the background has been described. However, the present invention is not limited to this, and the dynamic RA is not limited thereto.
M and other semiconductor storage devices, memory with built-in microcomputer, mixed analog / digital LSI,
Furthermore, the present invention can be widely applied to semiconductor devices such as a system board on which LSIs and other electronic components are mounted.

The present invention can be applied on condition that at least a power supply line is present.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a rise in the potential of one of the power supply lines coupled by electric circuit elements arranged to bridge a plurality of power supply lines having the same polarity is absorbed by the other power supply line side. As a result, the power supply noise can be effectively reduced in spite of the simple method and the simple configuration.

[Brief description of the drawings]

FIG. 1 is an electrical connection diagram showing a relationship between a main block of a static RAM, a low-potential-side power supply Vss, and an electric circuit element for reinforcing a power supply according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing operation timing of a main part and a low-potential-side power supply Vss in the circuit configuration of FIG. 1;

FIG. 3 is an electrical connection diagram showing a relationship between main blocks of a static RAM, a low-potential-side power supply Vss, and an electric circuit element for reinforcing a power supply according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram showing operation timings of main parts and a low-potential-side power supply Vss in the circuit configuration of FIG. 3;

FIG. 5 shows a static RA according to a third embodiment of the present invention.
FIG. 4 is an electrical connection diagram showing a relationship among a main block of M, a low-potential-side power supply Vss, and an electric circuit element for reinforcing a power supply.

FIG. 6 is a waveform diagram showing operation timings of main parts and a low-potential-side power supply Vss in the circuit configuration of FIG. 5;

FIG. 7 shows a static RA according to a fourth embodiment of the present invention.
FIG. 4 is an electrical connection diagram showing a relationship among a main block of M, a low-potential-side power supply Vss, and an electric circuit element for reinforcing a power supply.

FIG. 8 is a waveform diagram showing operation timing of a main part and a low-potential-side power supply Vss in the circuit configuration of FIG. 7;

FIG. 9 is a block diagram of a static RAM to which a method according to an embodiment of the present invention is applied;

[Description of Signs] 1-0 to 1-m Address buffer 2 CS * buffer 3 WE * buffer 4 X decoder 5 Word driver 6 Memory cell array 7 Control unit 8 Y decoder 9 Y selection switch circuit 10 Data input / output circuit 10A Input buffer 10B Sense amplifier 10C Output buffer 21 Peripheral circuit 22, 23 Output driver D1, D2, D3 Diode R1, R2 Resistance L, L1, L2 Inductor C Capacitor Q N-channel MOSFET Vcc High-potential power supply Vss Low-potential power supply

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-216351 (JP, A) JP-A-63-36557 (JP, A) JP-A-2-113623 (JP, A) JP-A-2- 28362 (JP, A) JP-A-2-111063 (JP, A) JP-A-2-214149 (JP, A) JP-A-3-23594 (JP, A) JP-A-4-111350 (JP, A) JP-A-4-257256 (JP, A) JP-A-4-94568 (JP, A) JP-A-4-6868 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/419 H01L 27/04

Claims (4)

(57) [Claims] 1. A first power supply powered by a first power supply line.
Power supply reinforcement for the first power supply line due to circuit characteristics
Is required when the first circuit starts operating.
A second power supply for supplying power to a second circuit which is not operated by
(2) The power supply line is more excellent in power supply reinforcement than the first power supply line.
The first power supply line, which has a lower priority, has a higher priority for power supply reinforcement.
From the power supply to the second power supply line where the priority of power supply reinforcement is low
The first power supply line so that current flows unilaterally.
And the second power supply line with an electric circuit element.
And a power supply reinforcing method. 2. The power supply reinforcing method according to claim 1, wherein said electric circuit element is a diode. 3. A first circuit, a first power supply line for supplying power to the first circuit, and a non-operation at a timing when the first circuit starts operating.
Power supply for the second circuit and the first power supply line is required.
Sometimes the power supply reinforcement priority is lower than the first power supply line
And the same polarity as the first power supply line.
A second power supply line for supplying power to the second circuit through the first power supply line to the second power supply line.
The first power line is connected to the upper side so that current flows unilaterally.
An electric circuit element bridging with the second power supply line.
A semiconductor device characterized by the above-mentioned. 4. The method according to claim 1, wherein the electric circuit element is a diode.
The semiconductor device according to claim 3.