JP2513613B2 - Image processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In an image arithmetic processing device, arithmetic units commonly used for a plurality of arithmetic modules are separately arranged, and an arithmetic unit and an arithmetic module are used when performing image arithmetic processing. A switching circuit for switching the connection is provided, and the arithmetic unit is commonly used to enable speeding up and downsizing of the circuit.

[Industrial applications]

The present invention relates to a processing device that performs image calculation, and particularly to an image calculation processing device having a plurality of calculation functions.

Image processing is actively performed in the field of information processing devices. There is an image calculation processing device as means for performing this image processing. The image calculation processing device is, for example, a logical filter process,
Various processing such as shape histogram processing and spatial filter processing is performed. Therefore, there is a demand for an image processing unit capable of processing the above-mentioned various processes with a small-scale circuit.

[Conventional technology]

A conventional image arithmetic processing apparatus is configured as shown in FIG. 3, and, for example, arithmetic processing units 4-1 and 4-2 forming an arithmetic module respectively perform arithmetic processing of data in the image memory 6, The result is a control module (control unit) 5
In the case of performing a process for inputting to the image memory 6 based on the instruction of 1, the arithmetic processing units 4-1 and 4-2 require the internal memories 7-1 and 7-2, respectively. For example, the table data must be stored in the internal memories 7-1 and 7-2 before the arithmetic processing is performed. Thus, even for the same data such as table data, it is necessary to provide the area in each of the internal memories 7-1 and 7-2.

The distribution of the orientation of the contours that is most often used for image calculation,
The calculation module for obtaining the shape histogram for knowing the distribution of the inclination of the line segment is as shown in FIG. FIG. 4 shows that 3 × 3 mask processing is performed. An 8-bit input image A is input to a parallel / serial converter (hereinafter referred to as P / S converter) 8-1 and sequentially input to buffers 8-2 and 8-3.

The serial signal converted by the P / S converter 8-1 is input to the shift registers 9-1, 9-2, 9-3 directly or via the buffers 8-2, 8-3, respectively. The 3-bit all 9-bit data of each shift register is masked by the mask processing unit.
The output B of the 9-bit data which is input to 10 (the mask processing unit includes the internal memory of FIG. 3A) and is masked becomes the address of the shape histogram memory 11. The number of times the address is output is increased by the counter 11-1 which counts up by performing scanning. Therefore, when all the scans are completed, the number of outputs generated at each address, that is, the histogram is obtained in the shape histogram memory 11.

Further, a calculation module for extracting feature points often used in image calculation processing is as shown in FIG. Since the portion surrounded by the one-dot chain line in this figure has the same configuration as that in FIG. 4, its explanation is omitted here. Mask processing unit 10
The output B of the 9-bit data is the singularity pattern memory 12
Address. The singular point pattern memory 12 stores singular value data corresponding to the address in advance.

Therefore, the output B causes the singular value data to be output from the singular point pattern memory 12. The output singular value data is input to the singularity flag memory 13. It is the singularity counter 14 that indicates the address of the singularity flag memory 13. The singularity counter 14 is an address counter that increases with each pixel scan.

The X counter 15-1 and the Y counter 15-2 are counters that indicate the position of the pixel of interest, and the X coordinate memory 16
-1, Y coordinate memory 16-2 input.

As described above in the shape histogram calculation module and the feature point extraction calculation module, the circuits up to the 3 × 3 mask processing unit are separately provided. Therefore, various internal memories including a bus buffer that controls the input and output of data in this area also need to be large accordingly, and in order to make the circuit configuration large, the high performance, and the downsized image arithmetic processing device can be manufactured. In particular, it causes a problem in integration.

[Problems to be solved by the invention]

As described above, the conventional image processing apparatus has a problem in reducing the circuit scale and achieving high-density mounting for performing higher-performance image processing.

SUMMARY OF THE INVENTION In view of the above conventional circumstances, the present invention has an object to provide a high-speed image arithmetic processing apparatus having a small circuit scale.

[Means for solving problems]

As shown in FIGS. 1 and 2, the image arithmetic processing apparatus of the present invention includes a plurality of arithmetic modules (1
-1 to 1-n) and the plurality of arithmetic modules 1-1 to 1
The arithmetic unit 2 commonly used from -n is separately arranged, and the arithmetic circuit alone or the combination of the arithmetic module and the arithmetic unit 2 is appropriately selected by the control signal from the control unit 5 and the switching circuit is selected. 3 is an image arithmetic processing device connected to enable the arithmetic unit 2 to be effective, and the arithmetic unit 2 commonly used is a parallel / serial converter 8-1 and m-1 buffer memories 8
-2 and m shift registers 9-1 and a mask processing unit 10 capable of forming a matrix of m × m dots [Operation] When the arithmetic module 1-1 uses the arithmetic unit 2, switching is performed. The circuit 3 makes this connection and the arithmetic unit 2 performs arithmetic processing. Therefore, each of the arithmetic modules 1-1 to 1-n does not need to have its own arithmetic unit composed of the mask processing unit 10 and various internal memories capable of forming a matrix of m × m dots. The circuit configuration is reduced, which is extremely effective in realizing an integrated circuit that is small and requires high-speed operation.

〔Example〕

FIG. 2 is a block diagram of an embodiment according to the present invention, which is a common area between the shape histogram calculation module and the feature point extraction calculation module described above, that is, a portion where the input image A is subjected to 3 × 3 mask processing (second portion). The portion surrounded by the chain line in the figure) is separately configured as the arithmetic unit 2. The same parts as those in the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

The output B of the 3 × 3 mask processing unit 10 is input to the multiplexer 3-1 that operates as the switching circuit 3. The shape histogram memory 11 and the singularity pattern memory 12 are connected to the multiplexer 3-1. Further, the output of the shape histogram memory 11 is connected to the multiplexer 3-2, and the singular point pattern memory 12 is connected to the multiplexer 3-2 via the singular point flag memory 13 and the multiplexer 3-3.

Switching of the multiplexers 3-1 and 3-2 is controlled by the module select signal D. For example, if the module select signal D is logic "1", the operation unit 2 reads the operation output from the shape histogram memory 11, and if it is logic "0", the operation output of the singularity flag is obtained from the singularity flag memory 12. .

〔The invention's effect〕

As is apparent from the above description, according to the present invention, a commonly used arithmetic unit is provided separately from each arithmetic module, the circuit scale of each arithmetic module is reduced, and moreover, the arithmetic module is integrated into an integrated circuit. Will be extremely useful at.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention, FIG. 2 is a block diagram of an embodiment according to the present invention, FIG. 3 is a block diagram of a main portion of a conventional image processing apparatus, and FIG. 4 is a conventional shape. FIG. 5 is a block diagram of a histogram calculation module, and FIG. 5 is a block diagram of a conventional feature point extraction calculation module. In the figure, 1-1 to 1-n are arithmetic modules, 2 is an arithmetic unit, and 3 is a switching circuit.

Claims (1)

(57) [Claims] 1. A plurality of arithmetic modules (1-1 to 1-n) each having a different arithmetic function, and an arithmetic unit (2) commonly used by the plurality of arithmetic modules (1-1 to 1-n). Are separately arranged and the arithmetic module alone or the combination of the arithmetic module and the arithmetic unit (2) is appropriately selected by the control signal from the control unit (5) and the arithmetic unit is selected by the switching circuit (3). In the image arithmetic processing device connected so as to enable (2), the commonly used arithmetic unit (2) includes a parallel / serial converter (8-1) and m-1 buffer memories ( 8-
2), m shift registers (9-1), and a mask processing unit (10) capable of forming a matrix of m × m dots.