JPS57123467A - Conflict controller of plural computer systems - Google Patents

Conflict controller of plural computer systems

Info

Publication number
JPS57123467A
JPS57123467A JP56009240A JP924081A JPS57123467A JP S57123467 A JPS57123467 A JP S57123467A JP 56009240 A JP56009240 A JP 56009240A JP 924081 A JP924081 A JP 924081A JP S57123467 A JPS57123467 A JP S57123467A
Authority
JP
Japan
Prior art keywords
generator
interruption
conflict
state
cpu3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56009240A
Other languages
Japanese (ja)
Inventor
Shigeki Ikeyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56009240A priority Critical patent/JPS57123467A/en
Publication of JPS57123467A publication Critical patent/JPS57123467A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To realize an assured recovery of plural computers from a state of conflict in case these computers utilize the single resources in common to each other, by using a time monitor system for the control during a conflict and at the same time setting a random time interval for the monitor system. CONSTITUTION:Two layers of interruption generators 2/10 and 4/11 are connected to CPU1 and CPU3 respectively, and the working share can be set optionally for these generators by a program of the CPU. In cas a busy state is reported from a controller 8 when an interruption is given from the generator 4, the CPU3 performs a retrial with the interruption given from the generator 11. The timing of the generator 11 is random with no virtual synchronism with the timing of the generator 2. As a result, an idle state of a loop-shaped transmission line 7 is quickly detected by the CPU3 and with the interruption given from the generator 11 to assure a recovery from the state of conflict.
JP56009240A 1981-01-24 1981-01-24 Conflict controller of plural computer systems Pending JPS57123467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56009240A JPS57123467A (en) 1981-01-24 1981-01-24 Conflict controller of plural computer systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56009240A JPS57123467A (en) 1981-01-24 1981-01-24 Conflict controller of plural computer systems

Publications (1)

Publication Number Publication Date
JPS57123467A true JPS57123467A (en) 1982-07-31

Family

ID=11714875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56009240A Pending JPS57123467A (en) 1981-01-24 1981-01-24 Conflict controller of plural computer systems

Country Status (1)

Country Link
JP (1) JPS57123467A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62127977A (en) * 1985-11-28 1987-06-10 Fujitsu Ltd Arithmetic processing unit for image

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62127977A (en) * 1985-11-28 1987-06-10 Fujitsu Ltd Arithmetic processing unit for image

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