JPS63279375A - Image processor - Google Patents

Abstract

PURPOSE:To process images at a high speed by adding an arithmetic and logic operation part to each processor element. CONSTITUTION:Each of processor elements 20-1-20-4 contains a mask data generating circuit 25, a multiplier 27 and an adder 29. A space filtering part is added to apply space filtering to the output signal of the adder 29 and to output the filtered signal as image element data. A multiplexer 30 selects and outputs the output signal of the space filtering part, the data read out of an input image or the output signal of another processor element. Then an arithmetic and logic operation part 32 applies an arithmetic logical operation to the output signal of the multiplexer 30 and output this operation result. Thus it is possible to perform an arithmetic and logical operation at a high speed in both cases where a product sum operation is carried out and not respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an image processing device capable of high-speed processing.

"Prior Art" In recent years, systems have been developed that perform various processes on human images to perform shape recognition, shape classification, and the like. This image processing includes various processes such as image feature detection, for example, contour detection, vertical line, and horizontal line detection. An image processing device is generally composed of a neighborhood arithmetic circuit that performs spatial filtering and an arithmetic logic arithmetic circuit that performs various logical analyzes on the output data of this neighborhood arithmetic circuit. will be explained with reference to FIG. In the figure, 1 is M
x is an input image of N dots, and X+, + (!, j is the row and column number) is the dot data to be processed.

Further, 2 is mask data of an m x n matrix. 3 is a neighborhood arithmetic circuit which performs processing according to the following equation, and the result of the arithmetic operation becomes a new image YIJ.

YIJ-Σ Σ σ to 1・X fl+kl, IJ-1
1... (1) However, m=m 1 + m 2
+1 n=n I+n2+1 In this way, the neighborhood arithmetic circuit calculates new pixel data by performing a predetermined arithmetic operation on pixel data in the vicinity of pixel data subjected to spatial filtering processing.

The arithmetic and logic operation circuit performs sequential processing such as histogram calculation and binarization based on the output data of the neighboring operation circuit.

Further, the neighborhood arithmetic circuit and the arithmetic and logic arithmetic circuit are generally connected as shown in FIG. That is, the neighborhood arithmetic circuit 6 reads human pixel data from the data bus 5 connected to the image memory, and the processed pixel data is supplied to the arithmetic and logic arithmetic circuit 8 via the gate 7 and the data bus 5.

Then, the calculation result of the arithmetic logic operation circuit 8 is transmitted to the gate 9,
The data bus 5 is sequentially opened and the data is stored in a predetermined area of the memory.

The configuration shown in FIG. 7 has the disadvantage that the processing time of the neighborhood arithmetic circuit 6 is long because only one neighborhood arithmetic circuit 6 is provided. In other words, since the neighborhood arithmetic circuit 6 performs the above-mentioned arithmetic operation, the arithmetic time is relatively long, and the interval between spatial filtering processes becomes long, making it impossible to achieve high-speed processing. 6 is equipped with an accumulator that accumulates integrated values, but the contents of the accumulator must be cleared every time the pixel data to be subjected to spatial filtering processing is changed, and as a result, the interval for performing spatial filtering processing becomes longer. It's been long.

On the other hand, in order to solve the above-mentioned drawbacks, there is a circuit in which a mask data generation circuit is built into each of the neighborhood arithmetic circuits, and a plurality of these neighborhood arithmetic circuits are further provided in parallel to perform spatial filtering processing in parallel. developed by humans. The connection relationship between the neighboring arithmetic circuit and the arithmetic and logic arithmetic circuit in this case is as shown in FIG. That is,
10-1 to 10-n are neighboring arithmetic circuits with mask data generation circuits, which read input pixel data via the data bus 5-1. Then, the neighborhood calculation circuit 10-
The output data of 1 to 10-n are each gated If-1=lI
-n to the data bus 5-2, and further supplied to the arithmetic logic circuit 8 via the multiplexer 12. Moreover, the arithmetic logic operation circuit 8 gates the operation result! 3 to the data bus 5-2. in this case,
The data bus 5-1 is connected to neighboring arithmetic circuits 10-1 to 10-.
Since n operates in parallel and always becomes pinot, a separate data bus 5-2 is provided to take out the output data of the neighboring arithmetic circuits. Further, a multiplexer 12 is provided for data switching.

``Problems to be Solved by the Invention'' According to the circuit shown in Figure 8, the sum of products operation ((1)
The neighborhood arithmetic processing using Eq.) has the advantage that it can be shortened by parallel processing. However, when parallel processing is performed,
Since data is output one after another from each neighboring arithmetic circuit, the arithmetic and logic operation circuit 8 must perform sequential arithmetic processing using the gaps between the data outputs, which has the disadvantage that the processing is extremely difficult. Ta.

For example, if the mask data is 3×3 and the calculation of equation (1) is performed in parallel by four neighboring calculation circuits, data will be output every three cycles. This state is shown in FIG. The case shown in FIG. 9 is an example in which an 8×8 dot image is used as the input image and a 3×3 dot image is used as the mask data, as shown in FIG. 1O. Further, the numbers attached to the symbols shown in FIG. 9 correspond to the pixel numbers of the input image shown in FIG. 1O, and are DIOo.

Dll” and D12° are output pixel data, respectively.

In this way, if data is output every 3 cycles,
A problem arises in that the arithmetic logic circuit 8 cannot complete sequential processing during the data output interval.

Furthermore, the circuits shown in FIGS. 8 and 7 have the disadvantage that they cannot speed up processing that does not involve product-sum calculations. That is, processing that does not involve a product-sum operation is, for example, processing that calculates the maximum value within a neighborhood, and this type of processing is performed by the arithmetic logic operation circuit 8, but the circuit shown in FIGS. 8 and 7 Since there is only one arithmetic and logic operation circuit 8, only sequential processing can be performed, which requires a lot of processing time.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide an image processing device that can speed up arithmetic and logical operations both when a sum-of-products operation is performed and when it is not performed.

"Means for Solving the Problem" In order to solve the above-mentioned problem, a plurality of processor elements are provided, each of which is configured to perform image processing in parallel, and each of the processor elements is configured to: (a) A mask data generation circuit outputs mask data used for spatial filtering in a predetermined order, and image data read from a local area corresponding to a pixel to be subjected to spatial filtering is multiplied by output data of the mask data generation circuit. It has a multiplier and an adder that adds the multiplication output of the multiplier and the output of the accumulator and supplies the addition result to the input terminal of the accumulator, and the output signal of the adder is spatially filtered. (b) selecting and outputting any one of the output signal of the spatial filtering section, the data read from the input image, and the output signal of another processor element; It is characterized by comprising a multiplexer and (c) an arithmetic and logic operation unit that performs an arithmetic and logic operation on the output signal of the multiplexer and outputs the processing result.

"Operation" Since each processor element has an arithmetic and logic operation unit, sufficient operation time can be secured for each arithmetic and logic operation unit. Furthermore, by the action of each of the multiplexers, it is possible to switch between the presence and absence of product-sum calculations, and to switch calculations that require output signals from other processor elements, making it possible to handle a variety of image processing. .

"Example" Next, embodiments of the invention will be described.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and 20-1 to 20-4 are processor elements that each perform image processing. This processor element 2
0-1 to 20-4 are configured to exchange pixel data with the image memory brain 22 via data buses 21a and 21b, respectively. Processor elements 20-1 to 2
0-4 both have a circuit configuration as shown in FIG. In FIG. 2, 25 is a mask data generation circuit, which stores mask data in a matrix in advance and outputs these data in a predetermined order.

Reference numeral 26 denotes a product-sum calculation unit that performs the product-sum calculation shown in equation (1) above, and is composed of a multiplier 27, an accumulator 28, and an adder 29. Multiplier 27 is image memory plane 2
The pixel data successively generated from 2 is multiplied by the mask data output from the mask data generation circuit 25, and the multiplication result is supplied to one input terminal of the adder 29. Adder 2
9 adds the multiplication result of the multiplier 27 and the output of the accumulator 28, and sends this addition result to the input terminal 30C of the multiplexer 30.
It is also supplied to the input end of the accumulator 28.

The multiplexer 30 has an input end 30a.

30b or 30c is selected and the selected output is supplied to the register 31. The data in the register 31 is supplied to an arithmetic and logic operation circuit 32, where various operations are performed. The calculation results of the arithmetic and logic operation circuit 32 are output to the data bus 21b via an output terminal, and are also supplied to other processor elements. In other words, as shown in FIG. 1, the output signal of the processor element 20-1 is
2, the output signal of processor element 20-2 is sent to processor element 20-3,
The output signal of 0-3 is sent to the processor element 20-4,
The output signal of processor element 20-4 is supplied to processor element 20-1. In this case, the output signal of each processor element 20-1 to 20-4 is supplied to the input end 30b of the multiplexer 30 in the corresponding processor element. Further, an input end 30a of the multiplexer 30 is connected to the data bus 21a.

A state detection section (not shown) is provided in each of the processor elements 20-1 to 20-4 to detect the state thereof, and state detection data is supplied to the state register 35. The address generation circuit 36 generates an address for accessing the image memory brain 22 based on the contents of the status register 35, and the address register 37
supply to.

Address data output from the address register 37 is supplied to the address bus of the image memory plane 22.

Next, 40 is a control unit that controls the entire device, and controls each unit according to instructions written in an instruction register 41. Sequencer 42 does not read microinstructions in microprogram memory 43 based on the instructions in instruction register 41 and the contents of status register 35 . This read microinstruction is stored in the microinstruction register 44, where it is converted into a "1"/"0" signal on the control line and supplied to each section.

(Operation of Embodiment) Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 3. In this case, it is assumed that the input image and the mask data generated by the mask data generation circuit 25 are the same as those shown in FIG. 1θ.

(a) Operation for performing sum-of-products calculation First, the input image is scanned to capture 8 pixel data. Now, the pixel data DIO, II,! 2°+3.14.
It is assumed that image processing is performed sequentially for 15 (see FIG. 1θ). In this case, the processor element 20-1 performs image processing on pixel data DIO, the processor element 20-2 performs pixel processing on pixel data Dll, and thereafter, each pixel data to be subjected to image processing is The processor elements are assigned sequentially and periodically.

First, in order to process the pixel data DIO, the pixel data DI, D9 . D17, D2, DIO, D
I8 and D3. DI 1. DI9 to the processor element 20-1 (see FIG. 3(a)). Read control in this case is based on the contents of the status register 35.
The address generation circuit 36 performs this. processor element 2
0-1 outputs mask data C1 from the internal mask data generation circuit 25 when pixel data DI is supplied. Then, at the next cycle time, these data are multiplied, and the multiplication result and the output of the accumulator I2 are added. This operation is similar to that of the neighborhood arithmetic circuit shown in FIG. 6 described above. And processor element 2
The product-sum calculation unit 26 in 0-1 performs the same operation as the neighborhood calculation circuit in FIG. 6 in subsequent cycles, and
At step SIO, new image data D10' corresponding to the calculation of equation (1) is supplied to the register 31 via the multiplexer 30, and the accumulator 28 is cleared. Then, the arithmetic and logic operation circuit 32 starts arithmetic processing from this point.

On the other hand, the processor element 20-2 processes the pixel data D
Image processing is performed on pixel data Dll.
Some of the pixel data necessary for processing the pixel data DIO is common to the pixel data necessary for processing the pixel data DIO, and this common pixel data is processed by the processor element 20.
It is supplied at the same timing as -1. That is, at the timing when the image data D2 is supplied to the input terminal of the processor element 20-1 (step S3), the image data D2 is also supplied to the input terminal of the processor element 20-2.
be supplied at the same time. After the image data D2 is supplied, the image data DIO to DI9 are commonly supplied to the processor elements 20-1 and 20-2.
and pixel data D4. DI2. D20 is supplied. The product-sum operation processing for each image data in the processor element 20-2 is similar to the processing in the processor element 20-1. In this way, processor element 2
0-2 contains image data D2. D10, DI8. D3.
DI 1. DI9. D4. DI2. D20 is sequentially supplied.

Further, in the same manner as above, the processor element 20-
3.20-4 performs image processing on each of the pixel data DI2 and DI3. In this case, as shown in FIG. 3, the pixel data D3 to D20 are
2 and 20-3, pixel data D4 to D2
1 is commonly supplied to processor elements 20-3 and 20-4. Then, pixel data D14. Image processing for D15 is performed again by processor element 20-1.
20-2 performs.

When the above operation is performed, the pixel data D
In image processing from IO to DI5, each processor element requires 10 cycles for the product-sum operation, and the processor elements 20-! , 20-2, the next product-sum calculation process starts two cycles after outputting the pixel data DIO'' and DIl', which are the first product-sum calculation results. The arithmetic logic operation circuit 32 within -1 is the pixel data D.
A maximum of 12 cycles can be secured for the time to perform the calculation regarding IO'. Therefore, the processor element 20-I processes from cycle S10 to cycle S21
The pixel data DIO, which is the result of this calculation, is calculated until
" is output in cycle S22. Similarly, the arithmetic and logic operation circuit 32 in the processor element 20-2 performs calculations from cycle S13 to cycle S24, and in cycle S25, the pixel data D11" which is the calculation result is output.
Output. The above calculation operation is similarly performed in other processor elements 20-3, 20-4, and cycle S28. In S31, pixel data DI2''
, D l 3". Processor elements 20-1 and 20-2 output pixel data D14" and DI5" in cycles S34 and S37, respectively.

In this manner, in the above operation, data after image processing is output from each processor element every three cycles. Then, when the image processing for the pixel data D15 is completed, the pixel data D18 to D2 one line below the input screen are
3 (see FIG. 1O), the same process as above is performed.

In this case, since the processor element 20-2 is processing the last pixel data D15 in the above row, the processor element 20-3 is processing the first pixel data D18 in the second row. are allocated sequentially and periodically. Due to this operation, each processor (20-1 to 20-4)
The arithmetic and logic operation circuit 32 within can secure a processing time of 12 cycles. .

Note that the timing at which the first image processing data on the second line is output is the 9th cycle from the time when the face data is output, and after that, image processing data is output every 3 cycles in the same way as above. be exposed.

In the above explanation, for the sake of simplicity, 8×8
Although we assumed an input screen of pixels, the actual input screen is 25 pixels.
Since it is often 6×256 or more, the state in which image processing data is output every three cycles is maintained longer than in the case described above.

Further, in the above operation, if the processing time of the arithmetic and logic circuit 32 is insufficient, a longer calculation time can be secured by increasing the number of processor elements.

(b) Operations that require product-sum operations of other processor elements.

For example, when performing template-type processing, predetermined matrix-like mask data is applied to local areas,
In order to use the maximum value of the result as the edge strength value, the balance calculation results of other processor elements are required. In this case, the input terminal 30 is connected to the multiplexer 30 shown in FIG.
Select b and set it so that it can capture the output of other processor elements. As a result, the operation results of other processor elements are supplied to the arithmetic and logic operation circuit 32 via the multiplexer 30. Therefore, the arithmetic and logic operation circuit 32 can compare its own logic operation results with the operation results of other processor elements.

As an example of the above processing, FIG. 4 [r'rewiLt]
Indicates type mask data. When performing these types of processing, eight processor elements are prepared, each processor element performs a sum-of-products operation using the mask data of MO to M7, and supplies the results of the operations to other processor elements. A processor element to which calculation results are supplied from other processor elements,
The results are compared in size and supplied to the next processor element. Then, this operation is performed one after another, the maximum value is taken as the edge strength value, and the edge direction is detected from the mask number at that time.

(c) Operation when product-sum operation is not performed.

When performing processing such as determining the maximum value within a neighborhood, the multiplexer 30 in each processor element is set to select the input terminal 30a. As a result, image data is directly supplied to the arithmetic logic circuit 32,
Desired operations other than product-sum operations can be performed. In this case, for example, the four processor elements 20-1 to 20-4 are operated in parallel according to the scanning order of pixel data shown in FIG. 3 to perform processing.

The above is the operation of this embodiment.

Note that the pixels to be subjected to spatial filtering can also be shifted in the vertical direction of the input image.

Further, the supply of pixel data to each processor element is not limited to the order shown in FIG. 3, and other supply types may be adopted.

"Effects of the Invention" As explained above, according to the present invention, a plurality of processor elements each configured to perform image processing in parallel are provided, and each of the processor elements is a mask used for spatial filtering. a mask data generation circuit that outputs data in a predetermined order; a multiplier that multiplies the output data of the mask data generation circuit by image data read from a local area corresponding to a pixel to be subjected to spatial filtering; and a multiplier that multiplies the output data of the mask data generation circuit. an adder that adds the multiplication output of the accumulator and the output of the accumulator and supplies the addition result to the input end of the accumulator, and outputs the output signal of the adder as pixel data after spatial filtering. a multiplexer that selects and outputs any one of the output signal of the spatial filtering section, the data read from the input image, and the output signal of another processor element; and an output signal of the multiplexer. Since the present invention includes an arithmetic and logic operation section that performs arithmetic and logic operations on and outputs the processing results, a sufficient amount of operation time can be secured for each arithmetic and logic operation section. Furthermore, by the action of each of the multiplexers, the existence or non-existence of the product-accumulation operation can be switched;
In addition, it is possible to switch operations that require output signals from other processor elements, and it is possible to handle various types of image processing at high speed.

In addition to the above effects, there is also an advantage that the time for reading input pixel data can be shortened and parallel processing of each processor element can be performed efficiently.

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining a horizontal line detection method according to an embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of a processor element in the embodiment, and Fig. 3 shows the operation of the embodiment. Timing chart, Figure 4 is a diagram showing an example of mask data used in template type processing, Figure 5 is a conceptual diagram for explaining data scanning of differential type processing, Figure 6 is for explaining neighborhood processing. FIG. 7 and FIG. 8 are block diagrams showing the connection relationship between the neighborhood arithmetic circuit and arithmetic logic arithmetic circuit, respectively. FIG. 9 is a timing chart showing an example of operation related to the neighborhood arithmetic operation, and FIG.
The figure is a block diagram showing an example of an input image and mask data. 20-1 to 20-4...Processor element, 25...Mask data generation circuit, 26...
...product-sum calculator, 27...multiplier, 28...
...Accumulator, 29...Adder, 30...
...Multiplexer, 31...Register, 3
2... Arithmetic logic operation circuit.

Claims (1)

[Claims] A plurality of processor elements are provided, each of which is configured to perform image processing in parallel, and each of the processor elements (a) outputs mask data used for spatial filtering in a predetermined order. a mask data generation circuit; a multiplier that multiplies image data read from a local region corresponding to pixel data to be subjected to spatial filtering by output data of the mask data generation circuit; and a multiplication output of the multiplier and an accumulator. a spatial filtering section that has an adder that adds the output of the adder and supplies the addition result to the input terminal of the accumulator, and outputs the output signal of the adder as pixel data after spatial filtering; ) a multiplexer that selects and outputs any one of the output signal of the spatial filtering section, the pixel data read out from the input image, and the output signal of another processor element; An image processing device comprising: an arithmetic and logic operation unit that performs an arithmetic and logic operation and outputs a result of the processing.