JPH0687265B2 - Spatial filter circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a spatial filter circuit.

Prior Art and Problems Spatial filtering is effective as a means of image enhancement and is extremely important in computer image processing.

The spatial filter in digital image processing is to consider a space in which an image of interest exists as a two-dimensional plane, and perform spatial frequency scanning on this plane with nine local region pixels called a 3 × 3 window. In the case of a smoothing filter, eight pixels near the center pixel are viewed, the average is calculated from the sum of the density values of these neighboring pixels, and a new median value is obtained. A differential filter and the like are also performed by this spatial filter.

Generally, a spatial filter in pixel processing is basically a two-dimensional product-sum operation. As an input target, for example, one-dimensional television scanning line data is basically used, and it is A / D
After conversion and forming predetermined two-dimensional data, a two-dimensional product-sum operation is performed. In the product-sum operation, in order to process the input video signal directly
High-speed operation is required to perform × 3 (9 pixels) and 5 × 5 (25 pixels) calculations. Therefore, conventionally, in order to perform the above spatial filter operation, it has been considered to perform a product-sum operation using a multiplier and an adder. However,
In the current semiconductor technology, 9 multiplications and 8 additions required for 3 × 3 (9 pixels), or 5 ×
25 multiplications and 24 required for 5 (25 pixels)
It is impossible to complete addition in 70 to 120 ns. That is, if the multiplier is used, there is a problem that the processing speed of the arithmetic unit itself is slow and the device becomes large in scale, so that it is difficult to make the image processing device into an LSI.

Object of the Invention An object of the present invention is to prepare a constant that is frequently used in the 3 × 3 neighborhood operation of a spatial filter in advance, and selectively add the input data multiplied by the constant, thereby eliminating the need for a multiplier and performing high-speed pixel processing. It is to facilitate LSI implementation as well.

According to the present invention, the data of a plurality of pixels at respective predetermined positions centered on each pixel of the pixels of the input image are input, and the respective predetermined values are set with respect to the values of the pixels at the respective predetermined positions. In a spatial filter circuit for obtaining a value corresponding to a sum of values multiplied by a constant value according to a position, a multiplexer is provided corresponding to each of the predetermined positions, and each predetermined position is provided on the input side of each multiplexer. A plurality of constant multiplying means for multiplying the value of the input pixel by multiplying the input pixel value by a preset constant by bit-shifting or bit-reversing the bit string indicating the value, Each of the multiplexers selects the output of any one of the plurality of constant multiplication means on the input side of the multiplexer according to a given control signal, or outputs zero or outputs the predetermined value. Rank There is provided a spatial filter circuit characterized by comprising addition means for calculating a sum of outputs of all multiplexers provided corresponding to each unit.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described by way of embodiments with reference to the accompanying drawings.

First, the arithmetic constants that are the subject of the present invention will be described with reference to FIG. FIG. 1 shows 3 × 3 neighboring pixels Fi _{−1 ,} j ₋₁ , Fi _, j
_-1,, Fi _{+1 ,} j _-1,, Fi _{-1 ,} j, Fi _, j, Fi _{+1 ,} j, Fi _{-1 ,} j ₊₁ , Fi _, j
₊₁ , Fi _{+1 and} j ₊₁ are shown. The numbers in parentheses are operation constants of each pixel. Only the center pixel Fi _, j is 0,2,4
And the other eight surrounding pixels are 0, +1 and -1.

An example of such a 3 × 3 image neighborhood calculation of each pixel and input data is shown in FIG. 2 corresponds to the calculation of the following equation. Hereinafter, from FIG. 2 to FIG. 2 correspond to the operations represented by the following equations. For example, or in FIG. 2 is a one-dimensional operation, and in FIG. 2 is a two-dimensional operation.

_{Gij = Fi +1, j-Fi} -1, j ...... Gij = - (Fi +1, j-Fi -1, j) ...... Gij = Fi, j +1 -Fi, j -1 ...... Gij = − (Fi _, j ₊₁ −Fi _, j ₊₁ ) ... Gij = Fi _{−1 ,} j ₊₁ −Fi _{+1 ,} j ₊₁ …… Gij = − (Fi _{−1 ,} j ₋₁ −Fi _{+1 ,} J ₊₁₎ ... Gij = Fi _{+1 ,} j _-1 -Fi _{-1 ,} j ₊₁ ... Gij =-(Fi _{+1 ,} j _-1 -Fi _{-1 ,} j ₊₁₎ ...... Gij = _{Fi -1, j -1 + Fi,} j -1 + Fi +1, j -1 -Fi -1, j +1 -Fi, j +1 -Fi +1, j +1 ...... Gij = - (Fi -1 _{, j -1 + Fi, j -1} + Fi +1, j -1 -Fi -1, j +1 -Fi, j +1 -Fi +1, j +1) ...... Gij = Fi -1, j -1 _{+ Fi +1, j + Fi -1} , j +1 -Fi +1, j -1 -Fi +1, j-Fi +1, j +1 ...... Gij = - (Fi -1, j -1 + Fi -1, _{j + Fi -1, j +1 -Fi} +1, j -1 -Fi +1, j-Fi +1, j +1) ...... Gij = 2Fi, j-Fi -1, j-Fi +1, j ... ... Gij = 2Fi _, j-Fi _, j _-1 -Fi _, j ₊₁ ... Gij = 2Fi _, j-Fi _{-1 ,} j _-1 -Fi _{+ 1 ,} j _{+ 1} ... Gij = 2Fi _, j-Fi _{+ 1 ,} j- ₁ -Fi- _{1 ,} j _{+ 1} ... Gij = 4Fi _, j-Fi _, j- ₁ -Fi- _{1 ,} j −Fi _, j ₊₁ −Fi _{+1 ,} j
_{...... Gij = 4Fi, j-Fi} -1, j -1 -Fi +1, j -1 -Fi -1, j +1 -Fi +1, as j ₊₁ ...... above, the present invention is extremely The image calculation process is performed for a constant that is frequently used, and is multiplied by a constant as shown in FIG. In the figure, the symbol 0 / + 1 / -1 indicates a constant multiple of 0 or +1 or -1 of the input data, and the symbol 0/2/4 indicates a constant multiple of 0 or 2 or 4.

FIG. 4 shows an arithmetic circuit according to the present invention for performing the above arithmetic operation.
It is a block diagram of 20. The arithmetic circuit 20 is a multiplexer circuit 20.
1, an adder circuit 202 and an absolute value circuit 203. The multiplexer circuit 201 has nine multiplexers MUX1, 2, ... 9 corresponding to 3 × 3 neighborhood operations. The multiplexer used in this embodiment has an input S (select signal for selecting 0 or 1) and an output gate signal G.
(Y = 0 when G = 0, Y = SAXS when G = 1
2to1 multiplexer consisting of B) (5th)
Figure).

The inputs of these multiplexers are either the input data itself or its inverted input data, that is, the two's complement representation, except for MUX5. For MUX5, 2Fi _, j
And 4Fi _, j. In this case, it is only necessary to connect the ones shifted left by 1 bit and the ones shifted left by 2 bits at the time of input, and it is not necessary to separately provide a multiplier. Therefore, for MUX1, Fi _{-1 ,} j _-1 and -Fi _{-1 ,} j _-1 , and for MUX2, Fi _{-1 ,} j _-1 and -Fi _,
j _-1, the MUX3 Fi _+1, j _-1 and -Fi _+1, j _-1, the MUX4 Fi _-1,
j and −Fi _{−1 ,} 2Fi _for j, MUX5 _, j and 4Fi _, Fi _{+1 for} j, MUX6
_, J and −Fi _{+1 and} j, MUX7 have Fi _{−1 ,} j ₊₁ and −Fi _{−1 ,} j ₊₁ , MUX
8 for Fi _, j ₊₁ and −Fi _, j ₊₁ for MUX9, Fi _{+1 for} j ₊₁ and −Fi _+1
, J ₊₁ are input respectively.

These inputs are processed by the multiplexer circuit 201 in accordance with the operation control logic shown in Table 1 and then summed by the adder circuit 202, and the absolute value is taken by the absolute value circuit 203 or summed to obtain a new value. The calculation result Gi _, j is obtained.

The columns next to Table 1 are the multiplexer MUs shown in FIG.
Shows the select signal S and gate signal G from X1 to 9,
The vertical columns indicate the types of calculation from the time shown in FIG.

For example, when performing the operation of FIG. 2, S = X, G = 0, MUX2 S = X, G = 0, MUX3 S = X, G = 0, MUX4 S = 1 G = 1, MUX5 S = X, G = 0, MUX6 S = 0, G = 1, MUX7 S = X, G = 0, MUX8 S = X, G = 0, MUX9 S = X, Set G = 0.

Here, S, G, and Y are signals having the meanings described in the margins of Table 1. That is, S is a select signal for inputting data directly if 0 and inverted for 1 and is X if S.
Don't care, that is, the data may be direct or inverted. If G is 0, Y = 0 without passing the input data
Is output, and if it is 1, the input data is passed and Y = SAVS
This is the output gate signal that performs the operation according to B. Incidentally, S =
When X, Y = 0 is inevitable.

Here, Y = SAVSB outputs A when S = 1 and S
If = 0, it means that B is output (FIG. 5).

Therefore, when G = 1, Y = A or Y = B and either one is output.

By the above logic, Gij = Fi _{+ 1 ,} j-Fi- _{1 ,} j or Gij = | Fi _{+ 1 ,} j-Fi- _{1 ,} j | is obtained (Fig. 4).

The other calculations from to in FIG. 2 are similarly performed.

FIG. 6 shows nine registers 11, 12, ... 19 corresponding to each window (FIG. 3) of the spatial filter and is shown by a chain line so that the arithmetic circuit of FIG. Two line buffers 2 and 3 are connected to the outside of the spatial filter circuit 1 of the present invention. The input data {Fij} corresponding to the first row of the spatial filter is input to the multiplexer circuit 201 via the registers 11, 12, and 13 as described above. At the same time, the one corresponding to the second row is input to the multiplexer circuit 201 via the register 11 and the line buffer 2 and the registers 14, 15, 16 of the second row. The input data corresponding to the third line is register 11, line buffer 2 register
It is input to the multiplexer circuit 201 via the registers 17, 18, and 19 via 14 and the line buffer 3.

In this way, the data accumulated for three rows is subjected to the arithmetic processing as described in FIG. 4, and the 3 × 3 local neighborhood arithmetic can be realized by only scanning the arithmetic target image once.

FIG. 7 shows a pin configuration when the circuit of the present invention is integrated into one chip. 8 pins are required for processing the input data, 16 pins are required for outputting the calculation result, and 1 pin is required for carrying up and down the computation. Further, 5 pins are required to give a switching command to the multiplexer, 1 pin is required for the clock signal, and 1 pin is required for performing the absolute value calculation. With this pin configuration, edge detection, dithering, etc. can be performed with one chip, and a multistage spatial filter etc. can be obtained by connecting in tandem. Further, double precision can be easily obtained by connecting in parallel. Can be calculated. In any of these cases, the reduction in speed has no effect.

EFFECTS OF THE INVENTION As described above, according to the present invention, an image neighborhood operation is simply performed by generating input data in the form of being multiplied by a constant, selecting the data multiplied by this constant by an operation instruction given from the outside, and adding the data. As a result, it is possible to perform high-speed image processing without using a multiplier as in the conventional case and to realize LSI.

[Brief description of drawings]

FIG. 1 is a diagram showing arithmetic constants used in the present invention, FIG. 2 is a diagram showing an arithmetic example according to the present invention, FIG. 3 is a diagram showing types of constant multiplication according to the present invention, and FIG. 4 is an arithmetic operation according to the present invention. FIG. 5 is a diagram for explaining the operation of the multiplexer used in the circuit of FIG. 4, FIG. 6 is a spatial filter circuit according to the present invention, and FIG. 7 is a pin configuration diagram of the circuit of the present invention. 1 ... Spatial filter circuit, 2, 3 ... Line buffer, 11,
12 ... 19 ... Register, 20 ... Arithmetic circuit, 201 ... Multiplexer circuit, 202 ... Adding circuit, 203 ... Absolute value circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-48-57562 (JP, A) JP-A-59-2164 (JP, A) JP-A-56-8140 (JP, A) JP-A-58- 222383 (JP, A)

Claims (1)

[Claims] 1. Data of a plurality of pixels at respective predetermined positions centered on the respective pixels of an input image are input, and values of the pixels at the respective predetermined positions are input according to the respective predetermined positions. In a spatial filter circuit that obtains a value corresponding to the sum of values multiplied by a constant value, a multiplexer is provided corresponding to each of the predetermined positions, and the input side of each multiplexer has the pixel at the predetermined position. A plurality of constant multiplication means for respectively inputting a value and multiplying the input pixel value by a preset constant by bit-shifting or bit-inverting a bit string indicating the value are provided, and each of the multiplexers is Depending on the given control signal,
Output of any one of the plurality of constant multiplication means on the input side of the multiplexer is selected, or zero is output, and outputs of all multiplexers provided corresponding to each of the predetermined positions. A spatial filter circuit characterized by comprising addition means for obtaining the sum of