JPS62139083A - Two-dimensional linear interpolation circuit - Google Patents

Abstract

PURPOSE:To obtain a two-dimensional linear interpolation circuit which eliminates the need for a large capacity of memory and is above to process a multi-gradation picture at a high speed by forming a circuit using three adder circuits. CONSTITUTION:Two picture element data V(A) and V(V) out of four original picture element data and a constant alpha are given to the first adder circuit 1-1. The adder circuit 1-1 calculates V(E) based on equation I. Also, the remaining picture element data V(C) and V(D) and the constant alpha are given to the second adder circuit 1-2, and the circuit calculates V(F) based on equation II. Next, V(E), V(F) and a constant beta are given to the third adder circuit 1-3, and the circuit calculates V(G) based on equation III. Thus, the two-dimensional linear interpolation circuit which eliminates the need for a large capacity of memory, and processes the multi-gradation image at a high speed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-dimensional linear interpolation circuit that realizes two-dimensional data interpolation when processing images such as image rotation, enlargement, reduction, and movement.

<Prior Art> Conventionally, this type of device has been considered to use a look-up table as shown in FIG. 2 or to use a multiplier. However, in the lookup table method, when the number of bits of input data is large, the table (
(memory) itself requires a huge capacity, and the operating speed of large-capacity memory is slower than that of logic gates, so processing multi-gradation images at high speed requires circuit size and operating speed. It was unsuitable. Furthermore, those configured using multipliers also have the problem of increasing the circuit scale.

OBJECTIVES> It is an object of the present invention to provide a two-dimensional linear interpolation circuit that eliminates the drawbacks of the conventional example described above, can process multi-gradation images at high speed, and has a configuration suitable for LSI implementation.

<Example> FIG. 3 is a diagram for explaining the concept of two-dimensional linear interpolation. 1, 4 to 6 show embodiments of the present invention, 1
is a one-dimensional linear interpolation circuit, 2 is a 6-time g that calculates 1-k from the distribution ratio k (0≦to≦1), 3 is an 801 circuit, 4 is a 4-man AND circuit, and 5 is a proportionally distributed value. This is a multiplication circuit.

The concept of two-dimensional linear interpolation will be explained below with reference to FIG. 3. Points A, B, C, and D in FIG. 3 each represent a point with respect to a plane, and each has a certain value. These will be expressed as V(A), V(B), V(C), and V(D), respectively. At that time, one point G on the plane (G is the line segment A
The points in the figure surrounded by B, BD, DC, and CA, and the values V (C), V (A), V (B).

Determined from V (C) and V (D). Here, line segments AB and CD are parallel to each other, and line segments AC and BD are also parallel to each other. At this time, consider a straight line that passes through point G and is parallel to line segment BD, and let the point where it intersects with line segment AB be E, and the point where it intersects with line segment CD as F.

If so.

becomes.

The value V (E) of point E (7) and the value V (F) of point F are expressed as V (
E) = (1-(X) V (A) +aV (B)
-------(1)V (F) -(1-a)V
(C) +αV (D) −−−−−−(2) Toshi, v(c)=(1−β)V(E)+βV(F)
−−−−−−(3), °, y (G) = (1
-a) (1-p)V (A) +a (1-β)V
(B)+(1-α)βV (C) +a/3V (D)
-------(4) Let V (G) be α, β,
Determination from V(A), V(B), V(C), and V(D) is called two-dimensional linear interpolation.

Next, an unembodied example will be explained with reference to FIGS. 1 and 4 to 6. .

FIG. 1 is a block diagram of a circuit that calculates equation (4).

1-1 is the first addition circuit that calculates equation (1), and 1-2 is (
2) a second addition circuit that calculates equation (3); 1-3 is a third addition circuit that calculates equation (3); Addition circuit 1-1.1-2.
1-3 all have the same configuration, which is shown in FIG. The adder circuit l has α or β (referred to as ffi, k
), V (A) or V (C), or V (E) (collectively written as V (X)), and V
Input (B) or V (D) or V (F) (collectively referred to as V (Y)),! -1,,(1-k
)V(X)+kV(Y) is output. 2 is l- than k
This is a circuit that calculates k. 5-1 is V(Y),! : is a circuit that calculates kv (y), and 5-2 is a circuit that calculates V (X) J: (1-k) V (X) for l- of the output of 2. FIG. 4 shows a circuit that calculates 1-k from k. is a number between O and 1 and is expressed in 4 bits. bitφ is the digit l (=20).

bit is 0.5 = (2-1), bit 2 is 0.25 = (2-2), bit 3 is 0.125-(2
-3) digits are shown respectively. 4 bits for 1- as well
It is output as . The output bit φ becomes 1 only when the input is φ. That is, when each bit of the input is all φ, it becomes l, so it is given as the logical product of the negation of each input bit. Further, output bitl to bit3 are given as complements of input bitl to bit3. Therefore, it is given by adding the same value as bit3 to the negation of each bitl-bit3 of the input.

Figure 6 depicts 5 in detail, where V(X) or v(y) is given as 8-bit data, of which the upper 7 bits, upper 6 bits, and upper 5 bits are input to separate gates. There is. Also k or l
-k is treated as 4-bit data, bitl is given to the gate of the first 7 bits, bit2 is given to the gate of the upper 6 bits, and bit3 is given to the gate of the upper 5 bits as a gate signal for each gate. Each gate outputs input data when the gate signal is φ and when φ is l. Also, bi on k or 1-
tφ is used as a selection signal to determine whether to select either the input data itself to 5 or the sum of all the outputs of the respective gates. This allows the selected signal to be output,
(1-k) Give V(X) or kV(Y).

In the above embodiment, when k is given, 1- is generated in the constituent circuit, but it is of course possible to configure so that both k and l-k are given as data from outside. .

Furthermore, it goes without saying that α given to 1-1, 1-2 in FIG. 1 may be given as different values. In this case, interpolation can be performed as shown in FIG. That is, EF is not parallel to BD.

Furthermore, as shown in FIG. 8, the figure formed by A, B, C, and D can be used even if it is not a parallelogram as described above.

Effects> As explained below, according to the present invention, a two-dimensional linear interpolation circuit that does not require a large amount of memory and can perform high-speed calculations can be constructed. It is also suitable for LSI integration, and has the effect of making the circuit size smaller than before.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of this embodiment, FIG. 2 is a diagram showing a conventional example, and FIG. 3 is an explanatory diagram showing the concept of two-dimensional linear interpolation.
Figure 4 is a conceptual diagram of a circuit that calculates 1-k using a distribution ratio, Figure 5 is a block diagram of a first-order linear interpolation circuit, and Figure 6 is a circuit that performs first-order linear interpolation, one of which is the distribution ratio and input data. 7 and 8 are diagrams showing other embodiments of the present invention.
-2.1-3 indicates an addition circuit, and 5-1.5-2 indicates a multiplication circuit.

Claims (2)

[Claims] (1) First and second addition means that add the data value itself or a shifted data value to each of two pieces of data of the four original pixel data; outputs of the first and second addition means; A two-dimensional linear interpolation circuit characterized by comprising a third addition means for adding. (2) A two-dimensional linear interpolation circuit characterized in that the shifted data value in the first term is a value obtained by extracting only the upper bits of the data value.