CN116227507B - A computing device for bilinear interpolation processing - Google Patents

Abstract

The present disclosure relates to the field of data processing, and discloses an arithmetic device for performing bilinear interpolation processing, including: the weight input module is used for determining weight input data corresponding to each multiplier by utilizing the first low-level data u and the second low-level data v, and inputting the weight input data into the corresponding multiplier; the multiplexer is used for respectively determining data to be operated corresponding to at least one multiplier according to the first interpolation weight U and the second interpolation weight V, and inputting the data to be operated into the corresponding multiplier; the multiplier is used for carrying out corresponding multiplication according to the data to be calculated and the weight input data and determining multiplication results; and the adder is used for carrying out summation operation on multiplication operation results corresponding to the multipliers and determining bilinear interpolation processing results corresponding to the data to be interpolated. According to the embodiment of the disclosure, the input bit width of the multiplier can be reduced, the circuit area of the device is reduced, and the hardware resource consumption for bilinear interpolation processing is saved.

Description

A computing device for bilinear interpolation processing

technical field

The disclosure relates to the field of data processing, and in particular to an arithmetic device for bilinear interpolation processing.

Background technique

Bilinear interpolation is a linear interpolation extension of the interpolation function with two variables, and its principle is to perform a linear interpolation in two directions respectively. As an interpolation algorithm in numerical analysis, bilinear interpolation is widely used in technical fields such as signal processing, digital image and video processing.

Contents of the invention

In view of this, the present disclosure proposes a technical solution of an arithmetic device for performing bilinear interpolation processing.

According to an aspect of the present disclosure, there is provided an arithmetic device for bilinear interpolation processing, including: a weight input module, a multiplexer, a plurality of multipliers, and an adder, wherein the input of the multiplier The bit width is m-1 bit; the weight input module is configured to use the first low-order data u and the second low-order data v to determine the weight input data corresponding to each of the multipliers, and input the weight input data to The corresponding multiplier, wherein, the first low-order data u is the low-order m-1 bit of the first interpolation weight U, and the second low-order data v is the low-order m-1 bit of the second interpolation weight V, and the The first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1, and m is the number of bits of the binary number corresponding to the first interpolation weight U and the second interpolation weight V ; The multiplexer is used to respectively determine at least one data to be operated corresponding to the multiplier according to the first interpolation weight U and the second interpolation weight V, and input the data to be operated to corresponding The multipliers, wherein, the data to be operated corresponding to each of the multipliers is one of a plurality of data to be interpolated that needs to be processed by the bilinear interpolation; the multiplier is used to The data to be calculated and the weight input data are used to perform corresponding multiplication operations to determine the multiplication results; the adder is used to sum the multiplication results corresponding to each of the multipliers to determine the multiplication results. Bilinear interpolation processing results corresponding to multiple data to be interpolated.

In a possible implementation manner, the multiple multipliers include: a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier, and the weight input data includes: first weight input data, The second weight input data, the third weight input data and the fourth weight input data; the first weight input data that the weight input module inputs to the first multiplier is 1-u and 1-v; the weight The second weight input data that the input module inputs to the second multiplier is u and 1-v; the third weight input data that the weight input module inputs to the third multiplier is 1-u and v ; The fourth weight input data input to the fourth multiplier by the weight input module is u and v.

In a possible implementation manner, the multiplexer is configured to determine, according to the highest bit of the first interpolation weight U and the second interpolation weight V, the relative The value change of the first interpolation weight U, and the value change of the second low-order data v relative to the second interpolation weight V; the multiplexer is used for relatively Determine at least one multiplier based on the value change of the first interpolation weight U, the value change of the second low-order data v relative to the second interpolation weight V, and the plurality of data to be interpolated The corresponding data to be calculated, wherein the plurality of data to be interpolated includes: first data to be interpolated, second data to be interpolated, third data to be interpolated, and fourth data to be interpolated.

In a possible implementation manner, the multiplexer is configured to determine the first low-order data u when the highest bits of the first interpolation weight U and the second interpolation weight V are both 0 The value of v is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer is configured to make the value of the first low-order data u unchanged relative to the value of the first interpolation weight U, and the second low-order When the value of the data v is unchanged relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the first data to be interpolated, and the second multiplier The corresponding data to be operated is the second data to be interpolated, and the data to be operated corresponding to the third multiplier is the third data to be interpolated.

In a possible implementation, the multiplexer is configured to determine the first interpolation weight U when the highest bit of the first interpolation weight U is 1 and the highest bit of the second interpolation weight V is 0. The value of a low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v does not change relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and the second low-order When the value of the data v is unchanged relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the second data to be interpolated, and the third multiplier The corresponding data to be operated is the fourth data to be interpolated.

In a possible implementation, the multiplexer is configured to determine the first interpolation weight U when the highest bit of the first interpolation weight U is 0 and the highest bit of the second interpolation weight V is 1. The value of a low bit data u is unchanged relative to the value of the first interpolation weight U, and the value of the second low bit data v is changed relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer is configured to make the value of the first low-order data u unchanged relative to the value of the first interpolation weight U, and the second low-order When the value of data v changes relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the third data to be interpolated, and the second multiplier The corresponding data to be operated is the fourth data to be interpolated.

In a possible implementation manner, the multiplexer is configured to determine the first low-order data u when the highest bit of the first interpolation weight U and the second interpolation weight V are both 1 The value of v changes relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and the second low-order When the value of data v changes relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the fourth data to be interpolated.

In a possible implementation manner, the plurality of data to be interpolated is four pixel data of a 2×2 structure in the target image that needs to be processed by bilinear interpolation.

In the arithmetic device for performing bilinear interpolation processing in the embodiment of the present disclosure, the weight input data corresponding to each multiplier is determined by using the first low-order data u and the second low-order data v through the weight input module, and the weight input The multiplier corresponding to the data input, wherein the first low-order data u is the low-order m-1 bit of the first interpolation weight U, the second low-order data v is the low-order m-1 bit of the second interpolation weight V, and the first interpolation weight U and the second interpolation weight V is m bit, and is greater than or equal to 0 and less than or equal to 1; the weight input data determined according to the first low-order data u and the second low-order data v of m-1 bit, the number of bits is also m-1 bit, so that the input bit width of the multiplier can be reduced from m bit to m-1 bit. Using the multiplexer, according to the values of the first interpolation weight U and the second interpolation weight V, the data to be calculated corresponding to at least one multiplier can be respectively determined, wherein the data to be calculated corresponding to each multiplier is the data to be calculated that needs to be double One of the plurality of data to be interpolated by linear interpolation is input to the corresponding multiplier, so that the multiplication result corresponding to the multiplier can be adjusted, thereby ensuring the accuracy of the bilinear interpolation processing result. Through the multiplier, the corresponding multiplication operation can be performed according to the data to be calculated and the weight input data, and the result of the multiplication operation can be determined, and then through the adder, the multiplication results corresponding to each multiplier can be summed to determine the bilinear interpolation process result. By reducing the input bit width of the multiplier and adjusting the logic of inputting data to be interpolated into the multiplier through the multiplexer, the overall circuit area of the device can be reduced, and the consumption of hardware resources for bilinear interpolation processing can be saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings here are incorporated into the description and constitute a part of the present description. These drawings show embodiments consistent with the present disclosure, and are used together with the description to explain the technical solution of the present disclosure.

FIG. 1 shows a schematic diagram of an arithmetic device for bilinear interpolation processing in the related art.

Fig. 2 shows a block diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure.

Detailed ways

Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements. While various aspects of the embodiments are shown in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations. In addition, the term "at least one" herein means any one of a variety or any combination of at least two of the more, for example, including at least one of A, B, and C, which may mean including from A, Any one or more elements selected from the set formed by B and C.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present disclosure may be practiced without some of the specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art have not been described in detail so as to obscure the gist of the present disclosure.

Bilinear interpolation is a linear interpolation extension of the interpolation function with two variables, and its principle is to perform a linear interpolation in two directions respectively. As an interpolation algorithm in numerical analysis, bilinear interpolation is widely used in technical fields such as signal processing, digital image and video processing.

An expression of bilinear interpolation can be expressed as the following formulas (1) to (3):

result_ab=a×(1-U)+b×U (1)

result_cd=c×(1-U)+d×U (2)

result_abcd=result_ab×(1-V)+result_cd×V (3)

Among them, a, b, c, d represent the four data to be interpolated that need to be processed by bilinear interpolation; result_ab represents the output result of linear interpolation in the first direction; result_cd represents the output result of linear interpolation in the first direction; result_abcd indicates the output result of linear interpolation in the second direction, that is, the output result of bilinear interpolation; U indicates the first interpolation weight corresponding to linear interpolation in the first direction, and V indicates the second interpolation corresponding to linear interpolation in the second direction. Interpolation weight, the value range of U and V is greater than or equal to 0 and less than or equal to 1.

One way in the related technology is to calculate the linear interpolation output results result_ab and result_cd in the first direction according to the above formulas (1) and (2), and then calculate the two output results in the second direction according to the above formula (3). The direction is linearly interpolated to determine the output result_abcd of the bilinear interpolation.

In another way in the related technology, according to the above formulas (1), (2) and (3), the output result_abcd of the bilinear interpolation is expressed as the following formula (4):

result_abcd= a×(1-U)(1-V)+b×U(1-V)+c×(1-U)V+d×UV (4)

According to the above formula (4), the output result_abcd of the bilinear interpolation can be directly determined.

The above two technical solutions directly perform bilinear interpolation processing according to the first interpolation weight U and the second interpolation weight V, without optimizing the first interpolation weight U and the second interpolation weight V. In the prior art, when performing bilinear interpolation processing, the first interpolation weight U and the second interpolation weight V need to be input to a multiplier for multiplication. The first interpolation weight U and the second interpolation weight V can be expressed as m-bit binary numbers, where m is the number of bits of the binary number corresponding to the first interpolation weight U and the second interpolation weight V, and correspondingly, the input of the multiplier The bit width is also m bit. Since the value range of the first interpolation weight U and the second interpolation weight V is greater than or equal to 0 and less than or equal to 1, when the accuracy of the first interpolation weight U and the second interpolation weight V is high, that is, when m is large, the multiplier The corresponding input bit width is also larger, and the hardware resources consumed will also be larger.

FIG. 1 shows a schematic diagram of an arithmetic device for bilinear interpolation processing in the related art. As shown in FIG. 1 , an apparatus 100 may be used for bilinear interpolation processing, and the apparatus 100 includes a multiplier 101 , a multiplier 102 , a multiplier 103 , and a multiplier 104 , and an adder 105 .

Based on the above formula (4), it can be known that the multiplier 101 can be used to determine the multiplication result corresponding to a×(1-U)(1-V), and the multiplier 102 can be used to determine the result corresponding to b×U(1-V). The multiplication result, the multiplier 103 can be used to determine the corresponding multiplication result of c×(1-U)V, the multiplier 104 can be used to determine the multiplication result corresponding to d×UV, and the adder 105 can be used for each multiplication The multiplication results corresponding to the devices are summed to determine the bilinear interpolation processing result.

Wherein, the first interpolation weight U and the second interpolation weight V may be represented by m-bit binary numbers. Correspondingly, the input bit width of the multiplier also needs to be m bits. Since the value range of the first interpolation weight U and the second interpolation weight V is greater than or equal to 0 and less than or equal to 1, when the precision of U and V is high, that is, when m is large, the input bit width of the multiplier is large, It requires a large consumption of hardware resources.

The present disclosure provides an arithmetic device for bilinear interpolation processing, which can save consumption of hardware resources. The calculation device for performing bilinear interpolation processing provided by the present disclosure will be described in detail below.

Fig. 2 shows a block diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure. As shown in FIG. 2 , the device 200 includes: a weight input module 201 , a multiplexer 202 , multiple multipliers 203 and an adder 204 , wherein the input bit width of the multiplier 203 is m-1 bit.

The weight input module 201 is configured to use the first low-order data u and the second low-order data v to determine the weight input data corresponding to each multiplier 203, and input the weight input data to the corresponding multiplier 203, wherein the first low-order data u is the low m-1 bit of the first interpolation weight U, the second low data v is the low m-1 bit of the second interpolation weight V, the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1, m is the number of bits of the binary number corresponding to the first interpolation weight U and the second interpolation weight V.

The multiplexer 202 is used to determine the data to be operated corresponding to each multiplier 203 according to the values of the first interpolation weight U and the second interpolation weight V, and input the data to be operated to the corresponding multiplier 203, wherein , the data to be operated corresponding to each multiplier 203 is one of multiple data to be interpolated that needs to be processed by bilinear interpolation.

The multiplier 203 is configured to perform a corresponding multiplication operation according to the data to be operated and the weight input data, and determine the result of the multiplication operation.

The adder 204 is configured to sum the multiplication results corresponding to each multiplier 203 to determine the bilinear interpolation processing results corresponding to the plurality of data to be interpolated.

Wherein, the first interpolation weight U and the second interpolation weight V corresponding to the bilinear interpolation process can be expressed as m-bit binary numbers, and the value range of U and V is greater than or equal to 0 and less than or equal to 1.

Through the weight input module 201, each multiplication can be determined according to the first low-order data u and the second low-order data v, that is, the low-order m-1 bit of the first interpolation weight U and the low-order m-1 bit of the second interpolation weight V. The weight input data corresponding to the multiplier 203, and input the weight input data to each multiplier 203 respectively. The specific structure of the weight input module 201 can be set according to actual usage requirements, which is not specifically limited in this disclosure.

In an example, a 9-bit binary number is used to represent the first interpolation weight U and the second interpolation weight V greater than or equal to 0 and less than or equal to 1. For example, the first interpolation weight U is expressed as: 011000000, and the second interpolation weight V is expressed as: 001110011. Correspondingly, it can be determined that the first low-order data u is expressed as: 11000000, and the second low-order data v is expressed as: 01110011.

In an example, a 9-bit binary number is used to represent the first interpolation weight U greater than or equal to 0 and less than or equal to 1. When the value of the first interpolation weight U is equal to 0, it can be expressed as 000000000; the first low-order data u is 00000000, and the value of the first low-order data u is 0; at this time, the value of the first low-order data u is relative to the value of the first low-order data u - The value of the interpolation weight U remains unchanged. When the value of the first interpolation weight U is equal to 1, it can be expressed as 100000000; the first low-order data u is 00000000, and the value of the first low-order data u is 0; at this time, the value of the first low-order data u is relative to the value of the first low-order data u - The value of the interpolation weight U changes. By analogy, the second interpolation weight V is also applicable, and details are not described here.

Since 0 and 1 are represented by m-bit binary numbers, the corresponding low m-1 bits of the two are the same. When the value of the first interpolation weight U and/or the second interpolation weight V is equal to 1, that is, when the highest bit of the first interpolation weight U and/or the second interpolation weight V is 1, the corresponding first low-order data u and /or the value of the second low-order data v is 0, that is, the value of the first low-order data u is relative to the value of the first interpolation weight U, and/or the value of the second low-order data v is relative to the second interpolation The value of the weight V changes. At this time, according to the first low-order data u and the second low-order data v, the weight input data corresponding to each multiplier 203 is determined. Compared with the weight input data determined directly according to the first interpolation weight U and the second interpolation weight V, the weight The value of the input data has changed, resulting in a change in the corresponding multiplication result, which may affect the output result of the device 200, that is, affect the accuracy of the bilinear interpolation processing result.

In an example, a 9-bit binary number is used to represent the first interpolation weight U and the second interpolation weight V greater than or equal to 0 and less than or equal to 1. For example, when the value of the first interpolation weight U is equal to 1, and the value of the second interpolation weight V is greater than 0 and less than 1, based on the above formula (4), it can be known that the bilinear interpolation result is b×(1-V )+d×V. It can be seen from the above description that at this time, the value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V. If the weight input data corresponding to each multiplier 203 is determined according to the first low-order data u and the second low-order data v, and the operation is performed based on the above formula (4), the corresponding operation result is a×(1-v)+c× v=a×(1-V)+c×V. That is to say, according to the first low-order data u and the second low-order data v, determining the weight input data corresponding to each multiplier 203 will cause the corresponding multiplication results to change, thereby affecting the accuracy of the bilinear interpolation processing results .

Therefore, in order to ensure the accuracy of the bilinear interpolation processing results, at least one multiplier can be determined among multiple data to be interpolated through the multiplexer 202 according to the values of the first interpolation weight U and the second interpolation weight V 203 corresponding to the data to be operated, so as to adjust the multiplication result corresponding to at least one multiplier 203 .

In the following, in combination with possible implementations of the present disclosure, the process of determining the data to be calculated corresponding to at least one multiplier 203 by the multiplexer 202 according to the values of the first interpolation weight U and the second interpolation weight V will be specifically described. description, and will not be repeated here.

The specific structure and quantity of the multiplexer 202 can be set according to actual usage requirements, which is not specifically limited in the present disclosure.

According to the data to be operated and the weight input data corresponding to each multiplier 203, a corresponding multiplication operation can be performed, so as to determine the multiplication operation result corresponding to each multiplier 203. The multiplier 203 and the corresponding multiplication operation will be specifically described later in combination with possible implementation manners of the present disclosure, and details are not repeated here.

The specific structure and quantity of the multiplier 203 can be set according to actual usage requirements, which is not specifically limited in the present disclosure.

The adder 204 can sum the multiplication results output by each multiplier 203, determine the sum result, and determine the sum result as a bilinear interpolation processing result corresponding to a plurality of data to be interpolated.

The specific structure of the adder 204 can be set according to actual usage requirements, which is not specifically limited in the present disclosure.

In the arithmetic device for performing bilinear interpolation processing in the embodiment of the present disclosure, the weight input data corresponding to each multiplier is determined by using the first low-order data u and the second low-order data v through the weight input module, and the weight input The multiplier corresponding to the data input, wherein the first low-order data u is the low-order m-1 bit of the first interpolation weight U, the second low-order data v is the low-order m-1 bit of the second interpolation weight V, and the first interpolation weight U and the second interpolation weight V is m bit, and is greater than or equal to 0 and less than or equal to 1; the weight input data determined according to the first low-order data u and the second low-order data v of m-1 bit, the number of bits is also m-1 bit, so that the input bit width of the multiplier can be reduced from m bit to m-1 bit. Using the multiplexer, according to the values of the first interpolation weight U and the second interpolation weight V, the data to be calculated corresponding to at least one multiplier can be respectively determined, wherein the data to be calculated corresponding to each multiplier is the data to be calculated that needs to be double One of the plurality of data to be interpolated by linear interpolation is input to the corresponding multiplier, so that the multiplication result corresponding to the multiplier can be adjusted, thereby ensuring the accuracy of the bilinear interpolation processing result. Through the multiplier, the corresponding multiplication operation can be performed according to the data to be calculated and the weight input data, and the result of the multiplication operation can be determined, and then through the adder, the multiplication results corresponding to each multiplier can be summed to determine the bilinear interpolation process result. By reducing the input bit width of the multiplier and adjusting the logic of inputting data to be interpolated into the multiplier through the multiplexer, the overall circuit area of the device can be reduced, and the consumption of hardware resources for bilinear interpolation processing can be saved.

In a possible implementation manner, the multiple multipliers 203 include: a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier, and the weight input data includes: the first weight input data, the second weight Input data, the third weight input book and the fourth weight input data; the weight input module inputs the first weight input data of the first multiplier to be 1-u and 1-v; the weight input module inputs the second weight of the second multiplier The input data are u and 1-v; the third weight input data input to the third multiplier by the weight input module are 1-u and v; the fourth weight input data input by the weight input module to the fourth multiplier are u and v.

Fig. 3 shows a schematic diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure. As shown in FIG. 3 , the multiplier 203 includes: a first multiplier 2031 , a second multiplier 2032 , a third multiplier 2033 and a fourth multiplier 2034 .

According to the above formula (4), it can be determined that: the multiplication item in the first multiplier 2031 and the data to be calculated is (1-U)(1-V), therefore, it can be determined that the weight input module inputs the first multiplier The first weight input data is 1-u and 1-v; The multiplication item that is multiplied with the data to be operated in the second multiplier 2032 is U (1-V), therefore, it can be determined that the weight input module is input to the second multiplier The second weight input data is u and 1-v; the multiplication item that is multiplied with the data to be operated in the third multiplier 2033 is (1-U)V, therefore, it can be determined that the weight input module inputs the third multiplier The third weight input data is 1-u and v; the multiplication item that is multiplied with the data to be operated in the fourth multiplier 2034 is UV, therefore, it can be determined that the fourth weight input data that the weight input module inputs into the fourth multiplier is u and v.

Through the multiplexer 202 , after determining the data to be operated corresponding to each multiplier 203 among the plurality of data to be interpolated, the data to be operated is input to the corresponding multiplier 203 . The multiplier 203 can determine the corresponding multiplication result according to the data to be operated and the multiplication item corresponding to the multiplier 203 .

In a possible implementation manner, the multiplexer 202 is configured to determine the value change of the first low-order data u relative to the first interpolation weight U according to the highest bit of the first interpolation weight U and the second interpolation weight V , and the value change of the second low-order data v relative to the second interpolation weight V; the multiplexer is used to change the value of the first low-order data u relative to the first interpolation weight U, and the second low-order data v relative to Based on the value change of the second interpolation weight V and a plurality of data to be interpolated, determine data to be operated corresponding to at least one multiplier, wherein the plurality of data to be interpolated includes: first data to be interpolated, second data to be interpolated, The third data to be interpolated and the fourth data to be interpolated.

The value change of the first low-order data u relative to the first interpolation weight U refers to the value indicated by the first low-order data u of m-1 bits, and the value indicated by the first interpolation weight U of m bits, whether changes; the value change of the second low-order data v relative to the second interpolation weight V refers to the value indicated by the second low-order data v of m-1 bit, and the value indicated by the second interpolation weight V of m bits value, whether it has changed.

As can be seen from the foregoing, when the value of the first interpolation weight U and/or the second interpolation weight V is equal to 1, the value of the first low-order data u and/or the second low-order data v is relative to the value of the first interpolation weight U and/or Or the value of the second interpolation weight V changes. When the first interpolation weight U and/or the second interpolation weight V is greater than or equal to 0 and less than 1, the value of the first low-order data u and/or the second low-order data v is relative to the first interpolation weight U and/or the second The value of the interpolation weight V remains unchanged.

Since the first interpolation weight U and the second interpolation weight V are m-bit binary numbers, and the value range is greater than or equal to 0 and less than or equal to 1. Therefore, it is possible to quickly determine whether the values of the first interpolation weight U and the second interpolation weight V are equal to 1 through the highest bit of the first interpolation weight U and the first interpolation weight V, thereby determining the relative value of the first low-order data u to the first The value of the interpolation weight U changes, and the value of the second low-order data v relative to the second interpolation weight V changes.

In order to ensure that the multiplication result corresponding to each multiplier 203 is correct, the multiplexer 202 can determine the first low-order data u relative to the first interpolation weight U according to the highest bit of the first interpolation weight U and the second interpolation weight V The value changes, and the value of the second low-order data v relative to the second interpolation weight V changes.

According to the value change of the first low-order data u relative to the first interpolation weight U, the value change of the second low-order data v relative to the second interpolation weight V, and a plurality of data to be interpolated, the multiplexer 202 can determine at least Data to be operated corresponding to a multiplier.

Wherein, the multiple data to be interpolated include: first data to be interpolated a, second data to be interpolated b, third data to be interpolated c, and fourth data to be interpolated d. Through the multiplexer 202, the first multiplier 2031, the second multiplier 2032 and the data to be operated corresponding to the third multiplier 2033.

Based on the above formula (4), it can be seen that the value of the first low-order data u changes relative to the value of the first interpolation weight U, and/or the value of the second low-order data v relative to the value of the second interpolation weight V When a change occurs, the weight input data determined according to the first low-order data u and the second low-order data v is input to the fourth multiplier 2034, and the corresponding multiplication results are all 0. Therefore, when the value of the first low-order data u is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V, the first It is sufficient to input the interpolation data d to the fourth multiplier 2034; while the value of the first low-order data u changes relative to the value of the first interpolation weight U, and/or the value of the second low-order data v is relatively When the value of the second interpolation weight V changes, the weight input data determined according to the first low-order data u and the second low-order data v is input to the fourth multiplier 2034, and the corresponding multiplication result of the fourth multiplier 2034 must be is 0, therefore, there is no need to set the multiplexer to select the corresponding data to be calculated.

In a possible implementation manner, the multiplexer 202 is configured to determine that the value of the first low-order data u is relative to the first The value of the interpolation weight U remains unchanged, and the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V.

When the highest bits of the first interpolation weight U and the second interpolation weight V are both 0, that is, the values of the first interpolation weight U and the second interpolation weight V are both greater than or equal to 0 and less than 1. At this time, the value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V.

In an example, a 9-bit binary number is used to represent the first interpolation weight U and the second interpolation weight V greater than or equal to 0 and less than or equal to 1. For example, when the value of the first interpolation weight U is equal to 0.75, it may be expressed as 011000000; when the value of the second interpolation weight V is equal to 0.45, it may be expressed as 001110011. The highest bits of the first interpolation weight U and the second interpolation weight V are both 0, that is, the values of the first interpolation weight U and the second interpolation weight V are both greater than or equal to 0 and less than 1. Correspondingly, the first low-order data u is represented as 11000000, and the value of the first low-order data u is equal to 0.75; the second low-order data v is represented as 01110011, and the value of the second low-order data v is equal to 0.45. At this time, the value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer 202 is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and the value of the second low-order data v relative to When the value of the second interpolation weight V is constant, it is determined that the data to be operated corresponding to the first multiplier 2031 is the first data to be interpolated, the data to be operated corresponding to the second multiplier 2032 is the second data to be interpolated, and the third multiplier The data to be calculated corresponding to the multiplier 2033 is the third data to be interpolated, and the data to be calculated corresponding to the fourth multiplier 2034 is the fourth data to be interpolated.

Taking the aforementioned FIG. 3 as an example, as shown in FIG. 3 , the multiplexer 202 includes: a first multiplexer 2021 , a second multiplexer 2022 and a third multiplexer 2023 .

The value of the first low-order data u is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V, that is, the first low-order The values of the data u and the second low-order data v may represent real values of the first interpolation weight U and the second interpolation weight V. Therefore, the weight input data determined according to the first low-order data u and the second low-order data v of m-1 bits are multiplied with the data to be operated, relative to the first interpolation weight U and the second interpolation weight according to m bits The weight input data determined by V is multiplied with the data to be operated, and the corresponding multiplication result remains unchanged.

When the values of the first interpolation weight U and the second interpolation weight V are greater than or equal to 0 and less than 1, according to the above formula (4), the bilinear interpolation processing result result_abcd=a×(1-U)(1- V)+b×U(1-V)+c×(1-U)V+d×UV. Since the values of the first interpolation weight U and the second interpolation weight V are greater than or equal to 0 and less than 1, the value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v The value is unchanged relative to the value of the second interpolation weight V. Therefore, it can be determined by the first multiplexer 2021 that the data to be operated corresponding to the first multiplier 2031 is the first data to be interpolated a, and the data to be operated corresponding to the second multiplier 2032 can be determined by the second multiplexer 2022 as The second data to be interpolated b is determined by the third multiplexer 2023 that the data to be operated corresponding to the third multiplier 2033 is the third data to be interpolated c, and the data to be operated corresponding to the fourth multiplier 2034 is determined to be the fourth data to be operated. Interpolated data d. At this time, it can be guaranteed that the bilinear interpolation processing result result_abcd=a×(1-u)(1-v)+b×u(1-v)+c×(1-u)v+d×uv=a× (1-U)(1-V)+b×U(1-V)+c×(1-U)V+d×UV.

In a possible implementation manner, the multiplexer 202 is configured to determine the value of the first low-order data u when the highest bit of the first interpolation weight U is 1 and the highest bit of the second interpolation weight V is 0 The value of the first interpolation weight U changes, and the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V.

When the highest bit of the first interpolation weight U is 1 and the highest bit of the second interpolation weight V is 0, that is, the value of the first interpolation weight U is equal to 1, and the value of the second interpolation weight V is greater than or equal to 0 and less than 1 . At this time, the value of the first low-order data u changes relative to the value of the first interpolation weight U, while the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V.

In an example, a 9-bit binary number is used to represent the first interpolation weight U and the second interpolation weight V greater than or equal to 0 and less than or equal to 1. When the value of the first interpolation weight U is equal to 1, it may be expressed as 00000000, and when the value of the second interpolation weight V is equal to 0.45, it may be expressed as 001110011. The highest bit of the first interpolation weight U is 1, and the highest bit of the second interpolation weight V is 0, that is, the value of the first interpolation weight U is equal to 1, and the value of the second interpolation weight V is greater than or equal to 0 and less than 1. Correspondingly, the first low-order data u is represented as 00000000, and the value of the first low-order data u is equal to 0; the second low-order data v is represented as 01110011, and the value of the second low-order data v is equal to 0.45. At this time, the value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer 202 is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and the value of the second low-order data v relative to When the value of the second interpolation weight V remains unchanged, it is determined that the data to be calculated corresponding to the first multiplier 2031 is the second data to be interpolated, and the data to be calculated corresponding to the third multiplier 2033 is determined to be the fourth data to be interpolated.

The value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v remains unchanged relative to the value of the second interpolation weight V, that is, the first low-order The value of the data u cannot represent the real value of the first interpolation weight U; the value of the second low-order data v can represent the real value of the second interpolation weight V. Therefore, the weight input data determined according to the first low-order data u of m-1 bits is multiplied with the data to be operated, and the weight input data determined according to the first interpolation weight U of m bits is multiplied with the data to be operated, Its corresponding multiplication result may change.

When the value of the first interpolation weight U is equal to 1, and the value of the second interpolation weight V is greater than or equal to 0 and less than 1, according to the above formula (4), the bilinear interpolation result result_abcd=b×(1- V)+d×V. Since the value of the first interpolation weight U is equal to 1, the value of the first low-order data u is equal to 0, which changes relative to the value of the first interpolation weight U; the value of the second interpolation weight V is greater than or equal to 0 and less than 1 , the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V. , Therefore, in order to ensure the accuracy of bilinear interpolation processing by the device 200, the data to be calculated corresponding to the first multiplier 2031 is determined by the first multiplexer 2021 to be the second data to be interpolated b, and the third multiplexer 2021 is used to determine The selector 2023 determines that the data to be operated corresponding to the third multiplier 2033 is the fourth data to be interpolated d. At this time, it can be guaranteed that the bilinear interpolation processing result result_abcd=b×(1-v)+d×v=b×(1-V)+d×V.

In a possible implementation, the multiplexer 202 is configured to determine the value of the first low-order data u when the highest bit of the first interpolation weight U is 0 and the highest bit of the second interpolation weight V is 1 Relative to the value of the first interpolation weight U, the value of the second low-order data v changes relative to the value of the second interpolation weight V.

When the highest bit of the first interpolation weight U is 0 and the highest bit of the second interpolation weight V is 1, that is, the value of the first interpolation weight U is greater than or equal to 0 and less than 1, and the value of the second interpolation weight V is equal to 1 . At this time, the value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U, while the value of the second low-order data v changes relative to the value of the second interpolation weight V.

In an example, a 9-bit binary number is used to represent the first interpolation weight U and the second interpolation weight V greater than or equal to 0 and less than or equal to 1. The value of the first interpolation weight U is equal to 0.75, which can be expressed as 011000000, and the value of the second interpolation weight V is equal to 1, which can be expressed as: 100000000. The highest bit of the first interpolation weight U is 0, the highest bit of the second interpolation weight V is 1, that is, the value of the first interpolation weight U is greater than or equal to 0 and less than 1, and the value of the second interpolation weight V is equal to 1. Correspondingly, the first low-order data u is represented as 11000000, and the value of the first low-order data u is equal to 0.75; the second low-order data v is represented as 00000000, and the value of the second low-order data v is equal to 0. Therefore, the value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V.

In a possible implementation manner, the multiplexer 202 is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and the value of the second low-order data v relative to When the value of the second interpolation weight V changes, it is determined that the data to be calculated corresponding to the first multiplier 2031 is the third data to be interpolated, and the data to be calculated corresponding to the second multiplier 2032 is determined to be the fourth data to be interpolated.

The value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V, that is, the first low-order The value of the data u can represent the real value of the first interpolation weight U; the value of the second low-order data v cannot represent the real value of the second interpolation weight V. Therefore, the weight input data determined according to the second low-order data v of m-1 bits is multiplied with the data to be operated, and the weight input data determined according to the second interpolation weight V of m bits is multiplied with the data to be operated, Its corresponding multiplication result may change.

When the value of the first interpolation weight U is greater than or equal to 0 and less than 1, and the value of the second interpolation weight V is equal to 1, according to the above formula (4), the bilinear interpolation processing result result_abcd=c×(1- U)+d×U. Since the value of the first interpolation weight U is greater than or equal to 0 and less than 1, the value of the first low-order data u remains unchanged relative to the value of the first interpolation weight U; the value of the second interpolation weight V is equal to 1, and the second The value of the low-order data v is equal to 0, which is changed relative to the value of the second interpolation weight V. Therefore, in order to ensure the accuracy of the bilinear interpolation process performed by the device 200, the data to be operated corresponding to the first multiplier 2031 is determined by the first multiplexer 2021 to be the third data to be interpolated c, and the second multiplexer selects The unit 2022 determines that the data to be operated corresponding to the second multiplier 2032 is the fourth data to be interpolated d. At this time, it can be guaranteed that the bilinear interpolation processing result result_abcd=c×(1-u)+d×u=c×(1-U)+d×U.

In a possible implementation manner, the multiplexer 202 is configured to determine that the value of the first low-order data u is relative to the first The value of the interpolation weight U changes, and the value of the second low-order data v changes relative to the value of the second interpolation weight V.

When the highest bits of the first interpolation weight U and the second interpolation weight V are both 1, that is, the values of the first interpolation weight U and the second interpolation weight V are both equal to 1. At this time, the value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V.

In an example, a 9-bit binary number is used to represent the first interpolation weight U and the second interpolation weight V greater than or equal to 0 and less than or equal to 1. The value of the first interpolation weight U is equal to 1, which can be expressed as 100000000; the value of the second interpolation weight V is equal to 1, which can be expressed as 100000000. The highest bits of the first interpolation weight U and the second interpolation weight V are both 1, that is, the values of the first interpolation weight U and the second interpolation weight V are both equal to 1. Correspondingly, the first low-order data u is represented as 00000000, and the value of the first low-order data u is equal to 0; the second low-order data v is represented as 00000000, and the value of the second low-order data v is equal to 0. At this time, the values of the first low-order data u and the second low-order data v both change relative to the values of the first interpolation weight U and the second interpolation weight V.

In a possible implementation manner, the multiplexer 202 is used to change the value of the first low-order data u relative to the value of the first interpolation weight U, and the value of the second low-order data v is relative to the value of the first interpolation weight U. When the value of the second interpolation weight V changes, it is determined that the data to be operated corresponding to the first multiplier 2031 is the fourth data to be interpolated.

The value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V, that is, the first low-order The values of the data u and the second low-order data v cannot represent the real values of the first interpolation weight U and the second interpolation weight V. Therefore, the weight input data determined according to the first low-order data u and the second low-order data v of m-1 bits are multiplied with the data to be operated, compared to the first interpolation weight U and the second interpolation weight V determined according to m bits The weight input data of is multiplied with the data to be operated, and the corresponding multiplication result may change.

When the values of the first interpolation weight and the second interpolation weight are both equal to 1, according to the above formula (4), the bilinear interpolation processing result result_abcd=d can be determined. Since the values of the first interpolation weight and the second interpolation weight are both equal to 1, the values of the first low-order data u and the second low-order data v are both equal to 0, and the value of the first low-order data u is relative to the first interpolation weight U The value of changes, and the value of the second low-order data v changes relative to the value of the second interpolation weight V. Therefore, in order to ensure the accuracy of the bilinear interpolation process performed by the apparatus 200, the data to be operated corresponding to the first multiplier 2031 is determined by the first multiplexer 2021 as the fourth data to be interpolated d. At this time, it can be guaranteed that the bilinear interpolation processing result result_abcd=d.

In a possible implementation manner, the plurality of data to be interpolated is four pixel data of a 2×2 structure in the target image that needs to be processed by bilinear interpolation.

The device 200 for performing bilinear difference can be applied to data filtering processing in a high-performance processor, for example, a texture unit unit in a graphics processing unit (graphics processing unit, GPU), or an arithmetic operation logic unit that requires filtering . Correspondingly, the plurality of data to be interpolated may be four pixel data of a 2×2 structure in the target image that needs to be processed by bilinear interpolation.

In an example, when the target image needs to be enlarged, each pixel on the target image needs to move in a specific direction according to a corresponding scale factor. When zooming in with a non-integer scale factor, there will be some pixel locations that do not have the appropriate pixel value, resulting in a hole. At this point, these holes need to be assigned appropriate RGB or grayscale values so that the output enlarged target image does not contain pixels without pixel values. With the hole as the center, the pixel data corresponding to the four pixel points of the 2×2 structure around the hole can be obtained, and then the pixel data can be input into the multiplier 203 as the data to be interpolated, and the bilinear interpolation process can be performed to determine the corresponding bilinear The result of the interpolation processing, that is, the pixel data corresponding to the hole, so that the corresponding RGB or gray value can be assigned to the hole.

In the arithmetic device for performing bilinear interpolation processing in the embodiment of the present disclosure, the weight input data corresponding to each multiplier is determined by using the first low-order data u and the second low-order data v through the weight input module, and the weight input The multiplier corresponding to the data input, wherein the first low-order data u is the low-order m-1 bit of the first interpolation weight U, the second low-order data v is the low-order m-1 bit of the second interpolation weight V, and the first interpolation weight U and the second interpolation weight V is m bit, and is greater than or equal to 0 and less than or equal to 1; the weight input data determined according to the first low-order data u and the second low-order data v of m-1 bit, the number of bits is also m-1 bit, so that the input bit width of the multiplier can be reduced from m bit to m-1 bit. Using the multiplexer, according to the values of the first interpolation weight U and the second interpolation weight V, the data to be calculated corresponding to at least one multiplier can be respectively determined, wherein the data to be calculated corresponding to each multiplier is the data to be calculated that needs to be double One of the plurality of data to be interpolated by linear interpolation is input to the corresponding multiplier, so that the multiplication result corresponding to the multiplier can be adjusted, thereby ensuring the accuracy of the bilinear interpolation processing result. Through the multiplier, the corresponding multiplication operation can be performed according to the data to be calculated and the weight input data, and the result of the multiplication operation can be determined, and then through the adder, the multiplication results corresponding to each multiplier can be summed to determine the bilinear interpolation process result. By reducing the input bit width of the multiplier and adjusting the logic of inputting data to be interpolated into the multiplier through the multiplexer, the overall circuit area of the device can be reduced, and the consumption of hardware resources for bilinear interpolation processing can be saved.

It should be noted that although FIG. 2 and FIG. 3 are used as examples to describe the circuit structure of the arithmetic device for bilinear interpolation processing as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly set the specific structure of the computing device used for bilinear interpolation processing according to personal preferences and/or actual application scenarios, and adaptively increase, decrease, and replace the circuits and electrical components in it, as long as they can be based on the above The process can be processed by bilinear interpolation.

Having described various embodiments of the present disclosure above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims (12)

1. A computing device for carrying out bilinear interpolation processing, characterized in that, comprising: a weight input module, a multiplexer, a plurality of multipliers and an adder, wherein the input bit width of the multiplier is m-1 bit; The weight input module is configured to use the first low-order data u and the second low-order data v to determine the weight input data corresponding to each of the multipliers, and input the weight input data to the corresponding multipliers, wherein , the first low-order data u is the low-order m-1 bit of the first interpolation weight U, the second low-order data v is the low-order m-1 bit of the second interpolation weight V, and the first interpolation weight U and the The second interpolation weight V is m bit, and is greater than or equal to 0 and less than or equal to 1, and m is the number of bits of the binary number corresponding to the first interpolation weight U and the second interpolation weight V; The multiplexer is configured to respectively determine data to be operated corresponding to at least one of the multipliers according to the first interpolation weight U and the second interpolation weight V, and input the data to be operated to corresponding The multiplier, wherein the data to be operated corresponding to each multiplier is one of a plurality of data to be interpolated that needs to be processed by bilinear interpolation; The multiplier is configured to perform a corresponding multiplication operation according to the data to be operated and the weight input data, and determine the result of the multiplication operation; The adder is configured to sum the multiplication results corresponding to each of the multipliers, and determine the bilinear interpolation processing results corresponding to the plurality of data to be interpolated; Wherein, the multiplexer is specifically configured to: according to the highest bit of the first interpolation weight U and the second interpolation weight V, determine the relative value of the first low-order data u relative to the first interpolation weight U value change, and the value change of the second low-order data v relative to the second interpolation weight V; according to the value change of the first low-order data u relative to the first interpolation weight U, the The value change of the second low-order data v relative to the second interpolation weight V and the plurality of data to be interpolated determine the data to be operated corresponding to at least one multiplier. 2. The device according to claim 1, wherein the plurality of multipliers comprises: a first multiplier, a second multiplier, a third multiplier and a fourth multiplier, and the weight input data comprises: first weight input data, second weight input data, third weight input data and fourth weight input data; The first weight input data input to the first multiplier by the weight input module is 1-u and 1-v; The second weight input data input to the second multiplier by the weight input module is u and 1-v; The third weight input data that the weight input module inputs to the third multiplier is 1-u and v; The fourth weight input data that the weight input module inputs to the fourth multiplier is u and v. 3. The device according to claim 2, wherein the plurality of data to be interpolated comprises: first data to be interpolated, second data to be interpolated, third data to be interpolated, and fourth data to be interpolated. 4. The device according to claim 3, wherein the multiplexer is configured to determine the highest bit of the first interpolation weight U and the second interpolation weight V when both are 0. The value of the first low-order data u is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V. 5. The device according to claim 4, wherein the multiplexer is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and when the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the first data to be interpolated, The data to be operated corresponding to the second multiplier is the second data to be interpolated, and the data to be operated corresponding to the third multiplier is the third data to be interpolated. 6. The device according to claim 3, wherein the multiplexer is configured to set the highest bit of the first interpolation weight U to 1, and the highest bit of the second interpolation weight V to be 0 , it is determined that the value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V The value does not change. 7. The device according to claim 6, wherein the multiplexer is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and when the value of the second low-order data v is unchanged relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the second data to be interpolated, The data to be operated corresponding to the third multiplier is the fourth data to be interpolated. 8. The device according to claim 3, wherein the multiplexer is configured to set the highest bit of the first interpolation weight U to 0, and the highest bit of the second interpolation weight V to be 1 , it is determined that the value of the first low-order data u is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data v is relative to the value of the second interpolation weight V The value changes. 9. The device according to claim 8, wherein the multiplexer is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, and when the value of the second low-order data v changes relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the third data to be interpolated, The data to be operated corresponding to the second multiplier is the fourth data to be interpolated. 10. The apparatus according to claim 3, wherein the multiplexer is configured to determine the The value of the first low-order data u changes relative to the value of the first interpolation weight U, and the value of the second low-order data v changes relative to the value of the second interpolation weight V. 11. The device according to claim 10, wherein the multiplexer is configured to change the value of the first low-order data u relative to the value of the first interpolation weight U, And when the value of the second low-order data v changes relative to the value of the second interpolation weight V, it is determined that the data to be operated corresponding to the first multiplier is the fourth data to be interpolated. 12. The device according to any one of claims 1 to 11, wherein the plurality of data to be interpolated is four pixel data of a 2×2 structure in the target image that needs to be processed by bilinear interpolation.

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