WO2023124371A1

WO2023124371A1 - Data processing apparatus and method, and chip, computer device and storage medium

Info

Publication number: WO2023124371A1
Application number: PCT/CN2022/124516
Authority: WO
Inventors: 霍冠廷; 王文强; 徐宁仪
Original assignee: 上海商汤智能科技有限公司
Priority date: 2021-12-31
Filing date: 2022-10-11
Publication date: 2023-07-06
Also published as: CN114329330A

Abstract

Provided in the present disclosure are a data processing apparatus and method, and a chip, a computer device and a storage medium. The data processing apparatus comprises: a data conversion circuit, which is used for receiving data to be processed, and converting, into first symbol data and absolute value data, the data to be processed, wherein the first symbol data represents that corresponding data to be processed is a positive value or a negative value; and a calculation circuit, which is used for acquiring the first symbol data and the absolute value data that are generated by the data conversion circuit, performing first operation processing on the absolute value data, so as to obtain a first intermediate calculation result, determining second symbol data of the first intermediate calculation result on the basis of the first symbol data, and performing second operation processing on the basis of the second symbol data and the first intermediate calculation result, so as to obtain a target processing result of the data to be processed.

Description

Data processing device, method, chip, computer equipment and storage medium

cross-reference statement

This application claims the priority of Chinese Patent Application No. 202111666460.4 filed with the China Patent Office on December 31, 2021, the entire contents of which are incorporated herein by reference.

technical field

The present disclosure relates to the field of computer technology, and in particular, to a data processing device, method, chip, computer equipment, and computer-readable storage medium.

Background technique

Matrix multiplication is one of the most important operations in data calculations performed by artificial intelligence (AI) chips. For example, in the implementation of convolutional neural networks, convolution calculations can be converted into matrix multiplication calculations. There is a problem of high power consumption in the current matrix multiplication calculation.

Contents of the invention

Embodiments of the present disclosure at least provide a data processing device, method, chip, computer equipment, and computer-readable storage medium.

In a first aspect, an embodiment of the present disclosure provides a data processing device, including a data conversion circuit and a calculation circuit. The data conversion circuit is used to receive the data to be processed, and convert the data to be processed into first symbol data and absolute value data; transmit the first symbol data and the absolute value data to the calculation circuit. Wherein, the first sign data indicates that the corresponding data to be processed is a positive value or a negative value. The calculation circuit is used to obtain the first symbol data and the absolute value data generated by the data conversion circuit, perform a first operation on the absolute value data, and obtain a first intermediate calculation result; and based on the The first symbol data determines the second symbol data of the first intermediate calculation result; and performs a second operation process based on the second symbol data and the first intermediate calculation result to obtain a target processing result of the data to be processed.

In a second aspect, an embodiment of the present disclosure further provides a data processing method applied to a data processing device, where the data processing device includes a data conversion circuit and a calculation circuit. The method includes: the data conversion circuit receives the data to be processed, and converts the data to be processed into first symbol data and absolute value data; the data conversion circuit transmits the first symbol data to the calculation circuit And the absolute value data, wherein the first symbol data indicates that the corresponding data to be processed is a positive value or a negative value; the calculation circuit obtains the first symbol data generated by the data conversion circuit and the The absolute value data, performing first arithmetic processing on the absolute value data to obtain a first intermediate calculation result; the calculation circuit determines second sign data of the first intermediate calculation result based on the first sign data; and The calculation circuit performs a second calculation process based on the second symbol data and the first intermediate calculation result to obtain a processing result of the data to be processed.

In a third aspect, an optional implementation manner of the present disclosure further provides a chip, including the data processing device as described in the first aspect or any embodiment of the first aspect.

In a fourth aspect, an optional implementation manner of the present disclosure further provides a computer device, including a memory and the data processing apparatus as described in the first aspect or any embodiment of the first aspect.

In a fifth aspect, an optional implementation manner of the present disclosure further provides a computer device, including the chip described in the third aspect above.

In the fifth aspect, an optional implementation manner of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a computer device, the computer device executes the above-mentioned second aspect The steps of the data processing method.

For the effect description of the above data processing method, chip, computer equipment, and computer-readable storage medium, please refer to the description of the above data processing device, which will not be repeated here.

In order to make the above-mentioned objects, features and advantages of the present disclosure more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required in the embodiments. These drawings show embodiments consistent with the present disclosure, and are used together with the description to explain the technical solution of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as limiting the scope. For those skilled in the art, they can also make From these drawings other related drawings are obtained.

FIG. 1 shows a schematic diagram of a data processing device provided by an embodiment of the present disclosure;

Fig. 2a shows a schematic structural diagram of a specific example when the data processing apparatus provided by an embodiment of the present disclosure processes data to be processed;

Fig. 2b shows a schematic structural diagram of another specific example of processing data to be processed by a data processing device provided by an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of another data processing device provided by an embodiment of the present disclosure;

Fig. 4a shows a schematic structural diagram of a specific example of another data processing apparatus provided by an embodiment of the present disclosure when processing data to be processed;

Fig. 4b shows a schematic structural diagram of another specific example of another data processing apparatus provided by an embodiment of the present disclosure when processing data to be processed;

FIG. 5 shows a specific circuit structure diagram of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 6 shows a specific circuit structure diagram of another data conversion circuit provided by an embodiment of the present disclosure;

FIG. 7 shows a schematic structural diagram of a second numerical operation circuit provided by an embodiment of the present disclosure;

FIG. 8 shows a schematic structural diagram of a data processing device for multiplying the first matrix C to be processed and the second matrix D to be processed provided by an embodiment of the present disclosure;

Fig. 9 shows a schematic flowchart of a data processing method provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. The described embodiments are only some of the embodiments of the present disclosure, not all of them. The components of the disclosed embodiments generally described and illustrated herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of embodiments of the present disclosure is not intended to limit the scope of the claimed disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort shall fall within the protection scope of the present disclosure.

Matrix multiplication is one of the most important operations in the data calculation of AI chips. For example, in the implementation process of convolutional neural network, the convolution calculation can be converted into matrix multiplication calculation; the calculation rule of matrix multiplication calculation is, as the multiplier The matrix elements in the i-th row of the matrix are multiplied by the corresponding matrix elements in the corresponding position of the j-th column as the multiplicand, and then the product results are added to obtain the position in the i-th row and j-th column in the result matrix matrix elements. In order to realize the multiplication operation between matrices, in the AI chip, it is necessary to deploy a circuit that realizes matrix operation, and the circuit that realizes matrix operation usually occupies a large amount of chip space and consumes most of the power consumption. The power consumption is usually positively correlated with the bit width of the data to be processed; the current matrix operation circuit directly processes the signed data, and because the bit width occupied by the signed data is large, it needs to consume a lot of power during the matrix multiplication operation. power consumption.

Based on the above research, the present disclosure provides a data processing device, method, chip, computer equipment, and computer-readable storage medium, by converting the multiplication between signed data to be processed into the multiplication between unsigned data to be processed The multiplication operation can reduce the data bit width during the multiplication operation, and reduce the chip volume and power consumption required for the matrix multiplication calculation.

The defects in the existing solutions and the solutions proposed by the present disclosure are the results obtained by the inventor after practice and careful research. The solution should be the inventor's contribution to the disclosure during the disclosure process.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

The connection described in the embodiments of the present disclosure refers to the connection between hardware circuits, such as connecting different circuit modules (such as data conversion circuits and computing circuits) through lines. To facilitate the understanding of this embodiment, first implement the present disclosure A data processing device disclosed in this example is introduced in detail, taking the application of the data processing device provided by the embodiment of the present disclosure in matrix operation as an example.

Referring to FIG. 1 , it is a schematic diagram of a data processing device 10 provided by an embodiment of the present disclosure. The data processing device 10 includes a data conversion circuit 11 and a calculation circuit 12 .

The data conversion circuit 11 is used to receive data to be processed, and convert the data to be processed into first symbol data and absolute value data; transmit the first symbol data and the absolute value data to the calculation circuit 12 ; Wherein, the first sign data indicates that the corresponding data to be processed is a positive value or a negative value.

The calculation circuit 12 is used to obtain the first symbol data and the absolute value data generated by the data conversion circuit 11, and perform a first calculation process on the absolute value data to obtain a first intermediate calculation result; based on the The first symbol data determines the second symbol data of the first intermediate calculation result; and performs a second operation process based on the second symbol data and the first intermediate calculation result to obtain a processing result of the data to be processed.

In a specific implementation, the input end of the data conversion circuit 11 can be connected to the output end of other processing circuits or registers to receive the data to be processed transmitted by other processing circuits, or to read the data to be processed from the register to convert the data to be processed converted into first symbol data and absolute value data.

The output terminal of the data conversion circuit 11 can be connected with the input terminal of the calculation circuit 12, and the data conversion circuit 11 can directly transmit the first symbol data and the absolute value data obtained after data conversion to the data to be processed to the calculation circuit 12; the calculation circuit 12 , for receiving the first sign data and absolute value data transmitted by the data conversion circuit 11 when acquiring the first sign data and absolute value data generated by the data conversion circuit 11 .

In a possible implementation manner, when the data to be processed includes multiple data, for example, the data to be processed includes first data to be processed and second data to be processed; the first data to be processed includes a plurality of first sub-data The second data to be processed includes a plurality of second sub-data; then a data conversion circuit 11 can be used to receive the first data to be processed and the second data to be processed respectively, and convert a plurality of first sub-data in the first data to be processed converting the sub-data into first symbol data and absolute value data corresponding to each first sub-data; and converting a plurality of second sub-data in the second data to be processed into corresponding to each second sub-data Second sign data and absolute value data.

Exemplarily, the data processing device 10 provided by the embodiment of the present disclosure can be applied in matrix multiplication operations. The data to be processed includes, for example, matrix A and matrix B to be multiplied, and the matrix elements in matrix A and matrix B are both Signed value; matrix A and matrix B are both 3*3 matrices, and the number system is int8, the first sub-data includes the matrix elements of each row in matrix A, and the second sub-data includes the matrix elements of each column in matrix B; Each matrix element in the matrix A and the matrix B with a relatively wide bit width can be converted into a symbol matrix and an absolute value matrix with a relatively small bit width through the data conversion circuit 11;

Among them, the matrix A satisfies

Matrix B satisfies

The symbol matrix corresponding to matrix A is

The symbol matrix includes first symbol data corresponding to each matrix element of matrix A;

The symbol matrix corresponding to matrix B is

The symbol matrix includes first symbol data corresponding to each matrix element of matrix B;

In addition, the absolute value matrix corresponding to matrix A is

The absolute value matrix includes absolute value data corresponding to each matrix element of matrix A;

The absolute value matrix corresponding to matrix B is

The absolute value matrix includes absolute value data corresponding to each matrix element of the matrix B.

In another possible implementation manner, when there are multiple pieces of data to be processed, data conversion can be performed on the corresponding data to be processed through the data conversion circuits 11 having the same quantity as the data to be processed. Exemplarily, the data to be processed includes first data to be processed and second data to be processed; the first data to be processed includes a plurality of first sub-data; the second data to be processed includes a plurality of second sub-data; the data conversion circuit 11 It includes a first data conversion circuit 11-1 and a second data conversion circuit 11-2; wherein, the first data conversion circuit 11-1 is used to receive the first data to be processed, and convert multiple first data in the first data to be processed A sub-data is respectively converted into first symbol data and absolute value data corresponding to each first sub-data; the second data conversion circuit 11-2 is used to receive the second data to be processed, and convert the data in the second data to be processed The plurality of second sub-data are respectively converted into first sign data and absolute value data corresponding to each second sub-data.

Exemplarily, the data processing device 10 provided by the embodiment of the present disclosure can be applied in matrix multiplication operations, and the data to be processed includes matrix A and matrix B, where both matrix A and matrix B are 3*3 int8 matrices, and the first One sub-data includes each matrix element in the matrix A, and the second sub-data includes each matrix element in the matrix B; through the first data conversion circuit 11-1, each of the matrix A that occupies a relatively wide bit width The matrix elements are respectively converted into the first symbol data and absolute value data occupying a relatively small bit width; through the second data conversion circuit 11-2, each matrix element in the matrix B occupying a relatively wide bit width is respectively It is transformed into first symbol data and absolute value data occupying a relatively small bit width.

Data conversion circuit 11 converts each matrix element in matrix A into corresponding first symbol matrix and absolute value data; and after converting each matrix element in matrix B into corresponding first symbol matrix and absolute value data, it can be sent to Calculation circuit 12 transmits the first symbol matrix and absolute value data.

Since the rule of matrix operation is that each matrix element in the i-th row of the matrix as a multiplier is multiplied by the matrix element in the corresponding position of the j-th column of the matrix as a multiplicand, and then the products are added together as the result matrix The matrix element located at the i-th row and the jth column position, therefore, the data processing device 10 may include a plurality of calculation circuits 12, wherein the number of calculation circuits 12 is related to the number of rows and columns of the matrix involved in the matrix multiplication operation, For example, if two 3*3 (that is, 3 rows and 3 columns) matrices are multiplied, 9 computing circuits are required to calculate each matrix element in the result matrix. For example, a 5*4 (that is, 5 rows and 4 columns ) matrix and a matrix of 4*6 (that is, 4 rows and 6 columns) are multiplied, and 30 calculation circuits are needed to calculate each matrix element in the result matrix; wherein, each calculation circuit 12 is used to receive the matrix The first symbol data and absolute value data corresponding to each matrix element in the i-th row of A and the first symbol data and absolute value data corresponding to each matrix element in the j-th column of matrix B respectively, and the absolute value data performing a first calculation process to obtain a first intermediate calculation result; and determining second symbol data of the first intermediate calculation result based on the first symbol data, and performing a second calculation process based on the second symbol data and the first intermediate calculation result to obtain The processing result of the data to be processed, that is, after multiplying matrix A and matrix B, the matrix element in the position of row i and column j in the obtained result matrix; where, i∈[1,3]; j∈[1 ,3].

Specifically, FIG. 2a shows a schematic structural diagram of a specific example of using a data conversion circuit 11 to process data to be processed in the data processing device 10 of the embodiment of the present disclosure. Comprise data conversion circuit 11 and a plurality of calculation circuits 12 in this data processing device 10, here, because be to carry out multiplication operation to matrix A and matrix B, so the quantity of calculation circuit 12 is 9 (namely calculation circuit 12-1, calculating circuit 12-2, calculation circuit 12-3, ..., calculation circuit 12-9); wherein, data conversion circuit 11 is used to receive matrix A and matrix B, and each matrix element in matrix A and matrix B Each matrix element in is converted into first symbol data and absolute value data respectively; Data conversion circuit 11 transmits the first symbol data and absolute value data corresponding to each matrix element in matrix A and each matrix element in matrix B to corresponding computing circuit Corresponding first sign data and absolute value data; Wherein, data conversion circuit 11 will be positioned at the first sign data and absolute value data (namely a_sign ₀₀ , a_sign ₀₁ , a_sign ₀₂ respectively corresponding to each matrix element in the first row in matrix A and a_cvt ₀₀ , a_cvt ₀₁ , a_cvt ₀₂ ) and the first sign data and absolute value data corresponding to each matrix element in the first column in matrix B (ie b_sign ₀₀ , b_sign ₁₀ , b_sign ₂₀ and b_cvt ₀₀ , b_cvt ₁₀ , b_cvt ₂₀ ) is transmitted to the calculation circuit 12-1 to calculate the matrix elements at the position of the first row and the first column in the result matrix; similarly, the data conversion circuit 11 converts each matrix element at the first row in the matrix A to The corresponding first sign data and absolute value data (that is, a_sign ₀₀ , a_sign ₀₁ , a_sign ₀₂ and a_cvt ₀₀ , a_cvt ₀₁ , a_cvt ₀₂ ) and the matrix elements in the second column in matrix B respectively correspond to the first sign data and Absolute value data (ie b_sign ₀₁ , b_sign ₁₁ , b_sign ₂₁ and b_cvt ₀₁ , b_cvt ₁₁ , b_cvt ₂₁ ) are transmitted to the calculation circuit 12-2 to calculate the matrix element at the position of the first row and second column in the result matrix ; By analogy, the data conversion circuit 11 is positioned at the first symbol data and the absolute value data corresponding to each matrix element of the third row in the matrix A (i.e. a_sign ₂₀ , a_sign ₂₁ , a_sign ₂₂ and a_cvt ₂₀ , a_cvt ₂₁ , a_cvt ₂₂ ) and the first sign data and absolute value data (ie b_sign ₀₂ , b_sign ₁₂ , b_sign ₂₂ and b_cvt ₀₂ , b_cvt ₁₂ , b_cvt ₂₂ ) corresponding to each matrix element in the third column of the matrix B are transmitted to the calculation circuit 12 -9, to calculate the matrix element at the position of the third row and third column in the result matrix.

Fig. 2b shows a schematic structural diagram of a specific example of using two data conversion circuits 11 (ie, a first data conversion circuit 11-1 and a second data conversion circuit 11-2) to respectively process corresponding data to be processed. The data processing device 10 includes a first data conversion circuit 11-1, a second data conversion circuit 11-2, and a plurality of calculation circuits 12; here, since matrix A and matrix B are multiplied, the calculation circuit 12 Quantity is 9 (namely calculation circuit 12-1, calculation circuit 12-2, calculation circuit 12-3, ..., calculation circuit 12-9); Wherein, the first data conversion circuit 11-1 is used for receiving matrix A, and convert each matrix element in the matrix A into the first symbol data and absolute value data respectively; the second data conversion circuit 11-2 is used to receive the matrix B, and convert each matrix element in the matrix B into the first symbol data respectively A symbol data and absolute value data; the first data conversion circuit 11-1 transmits the first symbol data and absolute value data corresponding to each matrix element in the matrix A to the corresponding computing circuit, and the second data conversion circuit 11-2 sends the corresponding calculation circuit The calculation circuit transfers the first symbol data and absolute value data corresponding to each matrix element in the matrix B; wherein, the first data conversion circuit 11-1 converts the first symbol data and the absolute value data corresponding to each matrix element in the first row in the matrix A respectively Absolute value data (that is, a_sign ₀₀ , a_sign ₀₁ , a_sign ₀₂ and a_cvt ₀₀ , a_cvt ₀₁ , a_cvt ₀₂ ) are transmitted to the calculation circuit 12-1, and the second data conversion circuit 11-2 converts each matrix in the first column of the matrix B to The first sign data and absolute value data corresponding to the elements (ie b_sign ₀₀ , b_sign ₁₀ , b_sign ₂₀ and b_cvt ₀₀ , b_cvt ₁₀ , b_cvt ₂₀ ) are transmitted to the calculation circuit 12-1, so that the calculation circuit 12-1 calculates the result Matrix elements at the first row and first column position in the matrix; similarly, the first data conversion circuit 11-1 converts the first symbol data and absolute value data corresponding to each matrix element at the first row in the matrix A ( That is, a_sign ₀₀ , a_sign ₀₁ , a_sign ₀₂ and a_cvt ₀₀ , a_cvt ₀₁ , a_cvt ₀₂ ) are transmitted to the calculation circuit 12-2, and the second data conversion circuit 11-2 converts the matrix elements in the second column in the matrix B to corresponding The first sign data and absolute value data (that is, b_sign ₀₁ , b_sign ₁₁ , b_sign ₂₁ and b_cvt ₀₁ , b_cvt ₁₁ , b_cvt ₂₁ ) are transmitted to the calculation circuit 12-2, so that the calculation circuit 12-2 calculates the position in the result matrix The matrix element at the second column position of a row; By analogy, the first data conversion circuit 11-1 is positioned at the first sign data and the absolute value data corresponding to each matrix element in the third row in matrix A respectively (being a_sign ₂₀ , a_sign ₂₁ , a_sign ₂₂ and a_cvt ₂₀ , a_cvt ₂₁ , a_cvt ₂₂ ) are transmitted to the calculation circuit 12-9, and the second data conversion circuit 11-2 converts the first symbols corresponding to the matrix elements in the third column in the matrix B Data and absolute value data (that is, b_sign ₀₂ , b_sign ₁₂ , b_sign ₂₂ and b_cvt ₀₂ , b_cvt ₁₂ , b_cvt ₂₂ ) are transmitted to the calculation circuit 12-9, so that the calculation circuit 12-9 calculates the result matrix located in the third row No. Matrix elements at three column positions.

In a possible implementation manner, FIG. 3 provides a schematic diagram of another data processing apparatus 10 for the embodiment of the present disclosure. The data processing device 10 also includes a first register 13 and a second register 14 , wherein both the first register 13 and the second register 14 are connected to the output end of the data conversion circuit 11 and the input end of the calculation circuit 12 .

The data conversion circuit 11 is also used to store the first sign data into the first register 13 and store the absolute value data into the second register 14 .

The calculation circuit 12 is used to read the first sign data from the first register 13 and the absolute value data from the second register 14 when acquiring the first sign data and absolute value data generated by the data conversion circuit 11 .

Exemplarily, the data processing device 10 provided by the embodiment of the present disclosure further includes a first register 13 for storing first sign data and a second register 14 for storing absolute value data. Taking the data to be processed including matrix A and matrix B as an example, the data conversion circuit 11 transmits each matrix element of matrix A to the first register 13-1 after converting the data to be processed into first symbol data and absolute value data The corresponding first symbol data, the first symbol data corresponding to each matrix element of matrix B is transmitted to the first register 13-2, and the absolute value data corresponding to each matrix element of matrix A is transmitted to the second register 14-1, And the absolute value data corresponding to each matrix element of the matrix B is transmitted to the second register 14-2; or, the first data conversion circuit 11-1 converts each first data in the first data to be processed (ie matrix A) After the sub-data (i.e. matrix elements) are converted into corresponding first symbol data and absolute value data, the first symbol data corresponding to each matrix element of matrix A is transmitted to the first register 13-1, and sent to the second register 14 -1 The absolute value data corresponding to each matrix element of the transmission matrix A; the second data conversion circuit 11-2 converts each second sub-data (ie matrix element) in the second data to be processed (ie matrix B) After the corresponding first symbol data and absolute value data, the first symbol data corresponding to each matrix element of matrix B is transmitted to the first register 13-2, and each matrix of matrix B is transmitted to the second register 14-2 The absolute value data corresponding to the element.

The first register 13-1 and the first register 13-2 respectively store the obtained first symbol data, and the second register 14-1 and the second register 14-2 respectively store the obtained absolute value data.

The data processing device 10 includes a plurality of calculation circuits 12, and each calculation circuit 12 can read from the first register 13-1 that each matrix element in the i-th row in the matrix A corresponds to The first symbol data, read from the second register 14-1 the absolute value data corresponding to the matrix elements in the i-th row in the matrix A, and read the j-th column in the matrix B from the first register 13-2 The first symbol data respectively corresponding to the matrix elements of the matrix B and the absolute value data corresponding to the matrix elements in the jth column in the matrix B read from the second register 14-2, and the first operation is performed on the absolute value data to obtain a first intermediate calculation result; and determining second symbol data of the first intermediate calculation result based on the first symbol data, and performing a second operation process based on the second symbol data and the first intermediate calculation result to obtain a processing result of the data to be processed, That is, after matrix A is multiplied by matrix B, the matrix element at the i-th row and j-th column in the resulting matrix is obtained.

Specifically, FIG. 4a shows a schematic diagram of another specific example when a data conversion circuit 11 is used to process data to be processed in the data processing device 10 of the embodiment of the present disclosure. The data processing device 10 includes a data conversion circuit 11 , a first register 13 , a second register 14 and a plurality of calculation circuits 12 . Here, since matrix A and matrix B are multiplied, therefore, the number of calculation circuits 12 is 9 (i.e. calculation circuit 12-1, calculation circuit 12-2, calculation circuit 12-3, ..., calculation Circuit 12-9); wherein, the data conversion circuit 11 is used to receive the matrix A and the matrix B, and convert each matrix element in the matrix A and each matrix element in the matrix B into first symbol data and absolute value data respectively; The data conversion circuit 11 transmits to the first register 13 the first symbol data corresponding to each matrix element in the matrix A and the first symbol data corresponding to each matrix element in the matrix B, so that the first register 13 stores the corresponding matrix elements in the matrix A. The first symbol data corresponding to each matrix element in matrix B and the first symbol data corresponding to each matrix element in matrix B; the data conversion circuit 11 transmits to the second register 14 the absolute value data corresponding to each matrix element in matrix A and the absolute Value data, so that the second register 14 stores the absolute value data corresponding to each matrix element in matrix A and the absolute value data corresponding to each matrix element in matrix B.

After the calculation circuit 12-1 receives the enable signal, it obtains the first sign data (ie, a_sign ₀₀ , a_sign ₀₁ a_sign ₀₂ ) and matrix Each matrix element in the first column in B corresponds to the first symbol data (ie b_sign ₀₀ , b_sign ₁₀ , b_sign ₂₀ ), and obtains from the second register 14 the matrix elements in the first row in matrix A corresponding to Absolute value data (ie a_cvt ₀₀ , a_cvt ₀₁ , a_cvt ₀₂ ) and the absolute value data corresponding to each matrix element in the first column of matrix B (ie b_cvt ₀₀ , b_cvt ₁₀ , b_cvt ₂₀ ), to calculate the result matrix The matrix element at the first row and first column position in .

Similarly, after receiving the enable signal, the calculation circuit 12-2 obtains the first symbol data corresponding to each matrix element in the first row in the matrix A (that is, a_sign ₀₀ , a_sign ₀₁ a_sign _{02 ,} respectively) from the first register 13 ) and the first symbol data corresponding to each matrix element in the second column in matrix B (ie b_sign ₀₁ , b_sign ₁₁ , b_sign ₂₁ ), and obtain each matrix in the first row in matrix A from the second register 14 The absolute value data corresponding to the elements (ie a_cvt ₀₀ , a_cvt ₀₁ , a_cvt ₀₂ ) and the absolute value data corresponding to each matrix element in the second column in matrix B (ie b_cvt ₀₁ , b_cvt ₁₁ , b_cvt ₂₁ ), to calculate Get the matrix element at the position of the first row and second column in the result matrix.

By analogy, after the calculation circuit 12-9 receives the enable signal, it obtains the first sign data corresponding to each matrix element in the third row in the matrix A (that is, a_sign ₂₀ , a_sign ₂₁ , a_sign ₂₂ ) and the first sign data (ie b_sign ₀₂ , b_sign ₁₂ , b_sign ₂₂ ) corresponding to each matrix element in the third column in matrix B, and obtain the data in the third row in matrix A from the second register 14 The absolute value data corresponding to each matrix element (ie a_cvt ₂₀ , a_cvt ₂₁ , a_cvt ₂₂ ) and the absolute value data corresponding to each matrix element in the third column in matrix B (ie b_cvt ₀₂ , b_cvt ₁₂ , b_cvt ₂₂ ), To calculate the matrix element at the position of the third row and third column in the result matrix.

Fig. 4b shows a schematic diagram of another specific example of using two data conversion circuits 11 (ie, a first data conversion circuit 11-1 and a second data conversion circuit 11-2) to respectively process corresponding data to be processed. In addition to the calculation circuits 12, the first register 13 and the second register 14 in FIG. 4a, FIG. 4b also includes a first data conversion circuit 11-1 and a second data conversion circuit 11-2. The first data conversion circuit 11-1 is used to receive the matrix A, and convert each matrix element in the matrix A into the first symbol data and absolute value data respectively; the second data conversion circuit 11-2 is used to receive the matrix B, and Each matrix element in the matrix B is respectively converted into first symbol data and absolute value data; the first data conversion circuit 11-1 transmits the first symbol data corresponding to each matrix element in the matrix A to the first register 13, and sends the first symbol data to the first register 13 The absolute value data corresponding to each matrix element in the second register 14 transfer matrix A; The second data conversion circuit 11-2 transfers the first symbol data corresponding to each matrix element in the matrix B to the first register 13, and sends to the second register 14 Absolute value data corresponding to each matrix element in the transfer matrix B. The functions and data processing flow of each calculation circuit 12 in FIG. 4b are similar to the specific implementation manner shown in FIG. 4a, and repeated descriptions will not be repeated.

In a specific implementation, the data conversion circuit 11 includes a first conversion circuit and a second conversion circuit; wherein, the first conversion circuit is used to receive the first numerical value of the preset first bit in the data to be processed; the received first The value is used as the first symbol data; and the first value is transmitted to the second conversion circuit; the second conversion circuit is used to receive the second value of the preset second bit in the data to be processed, and based on the first value transmitted by the first conversion circuit Value, convert the second value to obtain absolute value data.

Wherein, the preset first bit represents the sign bit, for example, the bit width of each matrix element in the matrix is n, then the preset first bit can be, for example, the n-1th bit; the preset second bit represents the value bit , for example, bits 0 to n-2 in a matrix element with a bit width of n; for example, the first value of the preset first bit may include 0 and 1, where 0 means positive, that is, the value of the data to be processed When the first value of the preset first bit includes 0, the data to be processed is a positive value; 1 means negative, that is, when the first value of the preset first bit of the data to be processed includes 1, the data to be processed is a negative value .

Specifically, when the data conversion circuit 11 converts the data to be processed into the first symbol data and absolute value data, in order to ensure that the values of the data to be processed before and after data conversion are not changed, it is necessary to pre-set The second numerical value of the second bit is set to be converted into absolute value data; the second conversion circuit includes a first adder, a first negation circuit and a first selector connected in sequence; the input terminal of the first selector is connected to the first The output end of the conversion circuit is connected to the output end of the first inversion circuit; the input end of the first inversion circuit is connected to the output end of the first adder.

Wherein, the first adder is used to respond to receiving the second value of the preset second bit in the data to be processed, sum the second value and the preset value to obtain the first intermediate value; transmit to the first negation circuit first intermediate value.

Wherein, the preset numerical value may include 1 or -1, for example. In the embodiment of the present disclosure, when the preset value includes -1, the complement of the second value is calculated by first adding the second value to the preset value, and then inverting the addition result bit by bit. ; In the case that the preset value includes 1, use the method of inverting the second value by bit first, and then add it to the preset value to find the complement of the second value; the above two methods can be calculated to obtain the first The absolute value of the binary value, the specific implementation method can be selected according to the actual circuit design requirements, so as to achieve the relevant purpose. The above two methods of calculating the complement of the second value, that is, calculating the absolute value of the second value, will be described in detail below.

In the case where the preset value includes -1, the first inverting circuit is configured to perform a bitwise inversion operation on the first intermediate value in response to receiving the first intermediate value transmitted by the first adder to obtain a second intermediate value ;Transfer the second intermediate value to the first selector.

The first selector is used to convert the first value to the first value in response to receiving the second value of the preset second bit in the data to be processed, the second intermediate value transmitted by the first negation circuit, and the first value transmitted by the first conversion circuit As the selection control signal, it controls to output the second numerical value as absolute value data, or controls to output the second intermediate numerical value as absolute value data. Specifically, when the first numerical value is 0, the control outputs the second numerical value as absolute value data; when the first numerical value is 1, the control outputs the second intermediate numerical value as absolute value data.

Exemplarily, a specific circuit structure diagram of the data conversion circuit 11 can be shown in FIG. An inverse circuit and a first selector; the first conversion circuit is used to receive the first value of the n-1th bit in the data to be processed (ie val[n-1], where n represents the bit width occupied by the data to be processed), Output the first numerical value of the n-1th bit as the first symbol data (i.e. sign), and transmit the first numerical value to the first selector in the second conversion circuit; the first adder in the second conversion circuit is used for Receive the second value (ie val[n-1:0]) of the n-2th to the 0th bit in the data to be processed, and add the second value and the preset value (for example, -1) and sum them, Obtain the first intermediate value; transmit the first intermediate value to the first negation circuit in the second conversion circuit and transmit the second value to the first selector; the first negation circuit bitwise Inverting to obtain the second intermediate value, and transmitting the second intermediate value to the first selector; the first selector is used to use the first value as Select the control signal to control the output of the second value as absolute value data (ie abs), or to control the output of the second intermediate value as absolute value data (ie abs).

Exemplarily, the specific process of converting the data to be processed by the data _conversion circuit 11 shown in FIG. Receive the first value 0 of the seventh bit in a ₀₀ , use the received first value as the first symbol data, and transmit the first value to the second conversion circuit.

The first adder in the second conversion circuit responds to receiving the second value 1000101 of the 6th to 0th bits in a ₀₀ , sums the second value and the preset value -1 to obtain the first intermediate value 1000100; The first inverting circuit in the second conversion circuit transmits the first intermediate value.

In response to receiving the first intermediate value, the first inversion circuit performs a bitwise inversion operation on the first intermediate value to obtain a second intermediate value 0111011; and transmits the second intermediate value to the first selector.

In response to receiving the first value 0, the second value 1000101, and the second intermediate value 0111011, the first selector uses the first value 0 as a selection control signal. Since the first value is 0, the data to be processed itself is a positive value. Then, the second numerical value of the preset second bit itself is an absolute value, therefore, the control outputs the second numerical value 1000101 as absolute value data.

In addition, if the data to be processed includes the matrix element a ₀₁ =11000101 in the matrix A, the first conversion circuit in the data conversion circuit 11 receives the first numerical value 1 of the 7th bit in a ₀₁ , and uses the received first numerical value as The first symbol data, and transmit the first value to the second conversion circuit.

The first adder in the second conversion circuit responds to receiving the second value 1000101 of the 6th to 0th bits in _a01 , sums the second value and the preset value -1 to obtain the first intermediate value 1000100; The first inverting circuit in the second conversion circuit transmits the first intermediate value.

In response to receiving the first value 1, the second value 1000101 and the second intermediate value 0111011, the first selector uses the first value 1 as a selection control signal. Since the first value is 1, the data to be processed itself is a negative value. Therefore, the control outputs the second intermediate value 0111011 as absolute value data.

In another possible implementation manner, when the preset value includes 1, the second conversion circuit may further include a first negation circuit, a first adder, and a first selector connected in sequence; wherein, the first The output end of the negation circuit is connected to the input end of the first adder, and the output end of the first adder is connected to the input end of the first selector.

The first inversion circuit is configured to perform a bitwise inversion operation on the second value to obtain a first intermediate value in response to receiving a second value preset in a second bit in the data to be processed; and transmit the second value to the first adder. an intermediate value.

The first adder is used for receiving the first intermediate value transmitted by the first negation circuit, summing the first intermediate value and the preset value 1 to obtain a second intermediate value; and transmitting the second intermediate value to the first selector.

The first selector is configured to take the first value as The control signal is selected to control the output of the second value as absolute value data, or to control the output of the second intermediate value as absolute value data. Specifically, when the first numerical value is 0, the control outputs the second numerical value as absolute value data; when the first numerical value is 1, the control outputs the second intermediate numerical value as absolute value data.

Exemplarily, the specific circuit structure diagram of the data conversion circuit 11 can be shown in Figure 6, the data conversion circuit 11 includes a first conversion circuit and a second conversion circuit, and the second conversion circuit includes sequentially connecting the first inverting circuit, the first An adder and a first selector; the first conversion circuit is used to receive the first numerical value of the n-1th bit in the data to be processed (ie val[n-1], wherein n represents the bit width occupied by the data to be processed), Output the first numerical value of the n-1th bit as the first symbol data (i.e. sign), and transmit the first numerical value to the first selector in the second conversion circuit; the first negation circuit in the second conversion circuit Receive the second numerical value (ie val[n-1:0]) of the n-2th bit to the 0th bit in the data to be processed, and perform bitwise inversion on the second numerical value to obtain the first intermediate value; The adder transmits the first intermediate value and transmits the second value to the first selector; after the first adder receives the first intermediate value, it adds and sums the first intermediate value and a preset value (for example: 1), Obtain the second intermediate value; transmit the second intermediate value to the first selector; the first selector is used to use the first value as a selection control signal after receiving the first value, the second value and the second intermediate value, and the control will The second numerical value is output as absolute value data (ie, abs), or the second intermediate value is output as absolute value data (ie, abs).

The concrete process that data conversion circuit 11 converts data to be processed is as follows: if data to be processed comprises matrix element _a00 =01000101 in matrix A, the first conversion circuit in data conversion circuit 11 receives the 7th bit in _a00 A value of 0, the received first value is used as the first symbol data, and the first value is transmitted to the second conversion circuit.

The first inversion circuit in the second conversion circuit, in response to receiving the second value 1000101 of the 6th to 0th bits in a ₀₀ , performs a bitwise inversion operation on the second value to obtain the first intermediate value 0111010; The first adder in the second conversion circuit transmits the first intermediate value.

In response to receiving the first intermediate value, the first adder adds the first intermediate value to a preset value 1 to obtain a second intermediate value 0111011; transmits the second intermediate value to the first selector.

The first selector, in response to receiving the first value 0, the second value 1000101 and the second intermediate value 0111011, uses the first value 0 as a selection control signal, because when the first value is 0, the data to be processed itself is a positive value , then the second value of the preset second bit itself is an absolute value, therefore, the control outputs the second value 1000101 as absolute value data.

In addition, if the data to be processed includes the matrix element a ₀₁ =11000101 in the matrix A, the first conversion circuit in the data conversion circuit 11 receives the first numerical value 1 of the 7th bit in a ₀₁ , and uses the received first numerical value as The first symbol data, and transmit the first value to the second converting circuit.

The first inversion circuit in the second conversion circuit responds to receiving the second value 1000101 of the 6th to 0th bits in a ₀₁ , and performs a bitwise inversion operation on the second value to obtain the first intermediate value 0111010; The first adder in the conversion circuit transmits the first intermediate value.

The first selector, in response to receiving the first value 1, the second value 1000101 and the second intermediate value 0111011, uses the first value 1 as a selection control signal, because when the first value is 1, the data to be processed itself is a negative value , therefore, the control outputs the second intermediate value 0111011 as absolute value data.

In a specific implementation, after the data conversion circuit 11 converts the data to be processed into first sign data and absolute value data, the first sign data and absolute value data may be transmitted to the calculation circuit 12 for processing the data to be processed.

Specifically, the calculation circuit 12 may include a symbolic operation circuit, a first numerical operation circuit, and a second numerical operation circuit; wherein, the output terminal of the symbolic operation circuit is connected to the input end of the second numerical operation circuit; the output of the first numerical operation circuit The terminal is connected to the input terminal of the second numerical operation circuit; the symbolic operation circuit is used to respond to the acquisition of the first symbolic data, and based on the first symbolic data, determine the second symbolic data of the first intermediate calculation result; The operation circuit transmits the second symbol data.

The first numerical operation circuit is used for performing first operation processing on the absolute value data in response to the acquired absolute value data to obtain a first intermediate calculation result; and transmitting the first intermediate calculation result to the second numerical operation circuit.

The second numerical operation circuit is configured to perform a second operation based on the second symbolic data and the first intermediate calculation result in response to receiving the second symbol data transmitted by the symbol operation circuit and the first intermediate calculation result transmitted by the first numerical operation circuit Processing to obtain the target processing result of the data to be processed.

Wherein, the first operation processing includes multiplication processing; the second operation processing includes addition processing; the data to be processed includes first data to be processed and second data to be processed; the first data to be processed includes a plurality of first sub-data; The processed data includes a plurality of second sub-data respectively corresponding to the first sub-data; the first symbol data includes first symbol data of the first sub-data and first symbol data of the second sub-data respectively corresponding to the first sub-data .

The symbol operation circuit includes an XOR gate circuit; the XOR gate circuit is used for performing exclusive OR gates on the first symbol data of each first sub-data and the first symbol data of the corresponding second sub-data for each first sub-data. or processing to obtain the second sign data of the first intermediate calculation result obtained by multiplying each first sub-data and the corresponding second sub-data.

Exemplarily, the first data to be processed includes matrix

Wherein the first sub-data includes each matrix element in matrix A, namely a ₀₀ , a ₀₁ , a ₀₂ , a ₁₀ , a ₁₁ , a ₁₂ , a ₂₀ , a ₂₁ , a ₂₂ ; The sign data includes a_sign ₀₀ , a_sign ₀₁ , a_sign ₀₂ , a_sign ₁₀ , a_sign ₁₁ , a_sign ₁₂ , a_sign ₂₀ , a_sign ₂₁ , a_sign ₂₂ .

The second pending data includes matrix

Wherein, the second sub-data includes each matrix element in the matrix B, namely b ₀₀ , b ₀₁ , b ₀₂ , b ₁₀ , b ₁₁ , b ₁₂ , b ₂₀ , b ₂₁ , b ₂₂ ; the multiple first sub-data are respectively The corresponding first sign data of each second sub-data is b_sign ₀₀ , b_sign ₀₁ , b_sign ₀₂ , b_sign ₁₀ , b_sign ₁₁ , b_sign ₁₂ , b_sign ₂₀ , b_sign ₂₁ , b_sign ₂₂ .

The embodiment of the present disclosure is applied to perform matrix multiplication operation on matrix A and matrix B. During the operation process, the XOR gate circuit in the symbol operation circuit is used to, for each first sub-data in matrix A, convert the first The first symbol data of the sub-data and the first symbol data of the second sub-data multiplied by the first sub-data in matrix B are subjected to XOR processing to obtain the first sub-data and the corresponding second sub-data The second sign data of the first intermediate calculation result obtained after the multiplication process.

For example, during the matrix multiplication operation, the symbol operation circuit can combine the first symbol data of each first sub-data in the first row in matrix A with the corresponding second sub-data in the first column in matrix B Exclusive OR processing is performed on the second symbol data to obtain the second symbol data of the first intermediate calculation result obtained after the first sub-data and the corresponding second sub-data are multiplied;

Determined as the second symbol data of the first intermediate calculation result obtained after multiplication of a ₀₀ and b ₀₀ ;

Determined as the second symbol data of the first intermediate calculation result obtained after multiplication of a ₀₁ and b ₁₀ ;

It is determined as the second sign data of the first intermediate calculation result obtained by multiplying a ₀₂ and b ₂₀ .

In a specific implementation, when the data to be processed includes the first data to be processed and the second data to be processed, the absolute value data includes the first absolute value data corresponding to each first sub-data in the first data to be processed and the first absolute value data corresponding to the second Second absolute value data corresponding to the second sub-data corresponding to each first sub-data in the data to be processed; the first numerical operation circuit includes a multiplier, and the multiplier is used for each first sub-data, each A product operation is performed on the first absolute value data of the first sub-data and the second absolute value data corresponding to the second sub-data to obtain a first intermediate calculation result corresponding to each first sub-data.

Exemplarily, the first data to be processed includes matrix

Wherein the first sub-data includes each matrix element in the matrix A, namely

The first absolute value data _of each first sub-data includes a_ctv ₀₀ , a_ctv ₀₁ , a_ctv ₀₂ , a_ctv ₁₀ , a_ctv 11 , a_ctv ₁₂ , a_ctv ₂₀ , a_ctv ₂₁ , a_ctv ₂₂ .

The second pending data includes matrix

Wherein, the second sub-data includes each matrix element in the matrix B, namely b ₀₀ , b ₀₁ , b ₀₂ , b ₁₀ , b ₁₁ , b ₁₂ , b ₂₀ , b ₂₁ , b ₂₂ ; The two absolute value data include b_ctv ₀₀ , b_ctv ₀₁ , b_ctv ₀₂ , b_ctv ₁₀ , b_ctv ₁₁ , b_ctv ₁₂ , b_ctv ₂₀ , b_ctv ₂₁ , b_ctv ₂₂ .

The embodiment of the present disclosure is applied to perform matrix multiplication operation on matrix A and matrix B. During the operation, the multiplier in the first numerical operation circuit is used for each first sub-data in matrix A, and the first sub-data The first absolute value data of the matrix B is multiplied with the second absolute value data of the second sub-data multiplied by the first sub-data to obtain the multiplication process of the first sub-data and the corresponding second sub-data The first intermediate calculation result obtained after.

For example, in the process of matrix multiplication, the multiplier in the first numerical operation circuit can be used to combine the first absolute value data of each first sub-data in the first row in matrix A with the first absolute value data in the first column in matrix B The second absolute value data of the corresponding second sub-data is multiplied to obtain the first intermediate calculation result obtained after the first sub-data and the corresponding second sub-data are multiplied; that is, a_ctv ₀₀ × b_ctv ₀₀ is determined as The first intermediate calculation result after multiplying a ₀₀ and b ₀₀ ; determine a_ctv ₀₁ × b_ctv ₁₀ as the first intermediate calculation result after multiplying a ₀₁ and b ₁₀ ; set a_ctv ₀₂ × b_ctv ₂₀ It is determined as the first intermediate calculation result obtained after multiplying a ₀₂ and b ₂₀ .

In a specific implementation, the second numerical operation circuit includes a second negation circuit, a second selector, a second adder, and a third adder; wherein, the input terminal of the second inversion circuit is connected to the output of the first numerical operation circuit The input end of the second selector is respectively connected with the output end of the second negation circuit, the output end of the sign operation circuit and the output end of the first numerical operation circuit; the input end of the second adder is connected with the output end of the sign operation circuit The output terminal is connected; the input terminal of the third adder is respectively connected with the output terminal of the second selector and the output terminal of the second adder.

Wherein, the second negation circuit is used to receive the first intermediate calculation result corresponding to each first sub-data transmitted by the first numerical operation circuit, and perform bitwise fetching on the first intermediate calculation result corresponding to each first sub-data The reverse operation is performed to obtain the second intermediate calculation result corresponding to each first sub-data, and transmit the second intermediate calculation result corresponding to each first sub-data to the second selector.

The second selector is used to respond to receiving the second symbol data of the first intermediate calculation result corresponding to each first sub-data transmitted by the symbol operation circuit, and the second symbol data corresponding to each first sub-data transmitted by the second negation circuit. The intermediate calculation results and the first intermediate calculation results corresponding to each first sub-data transmitted by the first numerical operation circuit use the second symbol data as a selection control signal to control the first intermediate calculation results corresponding to each first sub-data Output as the third intermediate calculation result corresponding to the first sub-data, or control to output the second intermediate calculation result corresponding to each first sub-data as the third intermediate calculation result corresponding to the first sub-data; to the third The adder transmits the third intermediate calculation result corresponding to each first sub-data. Specifically, when the second symbol data is 0, the control outputs the first intermediate calculation result corresponding to each first sub-data as the third intermediate calculation result corresponding to the first sub-data; when the second symbol data is In the case of 1, the control outputs the second intermediate calculation result corresponding to each first sub-data as the third intermediate calculation result corresponding to the first sub-data.

The second adder is configured to respond to the second symbol data of the first intermediate calculation result corresponding to each first sub-data transmitted by the receiving symbol operation circuit, and calculate the second symbol of the first intermediate calculation result corresponding to each first sub-data The data are summed to obtain a fourth intermediate calculation result; and the fourth intermediate calculation result is transmitted to the third adder.

The third adder is configured to calculate the third intermediate calculation result and the fourth intermediate calculation result corresponding to each first sub-data in response to receiving the third intermediate calculation result and the fourth intermediate calculation result corresponding to each first sub-data. And, get the target processing result.

In this way, there is no need to perform addition processing operations between the negative calculation results obtained after multiplying each first sub-data and the corresponding second sub-data and the preset value (ie 1), only by multiplying each Add the second symbol data corresponding to the first intermediate calculation result obtained after multiplying the first sub-data and the corresponding second sub-data to obtain the fourth intermediate calculation result; and combine the fourth intermediate calculation result with each of the first intermediate calculation results The third intermediate calculation result obtained after the multiplication of the first sub-data and the corresponding second sub-data is added, and the target processing result of the data to be processed can be obtained; it can be seen that this process reduces the number of addition operations and reduces the number of calculations in the circuit. The deployment of the adder further simplifies the circuit structure, thereby reducing the space occupied by the matrix multiplication operation circuit in the chip.

Exemplarily, a schematic structural diagram of the second numerical operation circuit may be shown in FIG. 7 . The second numerical operation circuit includes a second adder, a second inverting circuit, a second selector, and a third adder; wherein, the second adder is used to receive each first sub-data and the corresponding The second sign data (i.e. res_sign) of the first intermediate calculation result obtained after the second sub-data is multiplied, for example, may include res_sign0, res_sign1, ..., res_signm, where m represents the result matrix in the matrix multiplication operation process The number of matrix elements in the middle), and the second symbol data corresponding to each matrix element in the i-th row in the matrix as the multiplier is added to obtain the fourth intermediate calculation result (i.e. add_sign); transmit this to the third adder The fourth intermediate calculation result; the second negation circuit is used to receive the first intermediate calculation obtained by multiplying each first sub-data and the corresponding second sub-data transmitted by the first numerical operation circuit (such as a multiplier) Result (that is, res_val, such as may include res_val0, res_val1, ..., res_valm, wherein m represents the number of matrix elements in the result matrix during the matrix multiplication operation), and perform bitwise fetching of the first intermediate calculation result On the contrary, the second intermediate calculation result is obtained; the second intermediate calculation result is transmitted to the second selector; after the second selector receives the second symbol data, the first intermediate calculation result and the second intermediate calculation result, the second symbol The data is used as a selection control signal to control the output of the first intermediate calculation result or the second intermediate calculation result as the third intermediate calculation result; transmit the third intermediate calculation result to the third adder; the third adder receives the third intermediate calculation result After the calculation result and the fourth intermediate calculation result, add the third intermediate calculation result and the fourth intermediate calculation result to obtain the matrix elements in the result matrix (ie mul_val, for example, may include mul_val00, mul_val01, ..., mul_valNM, where , N represents the number of rows of the matrix as the multiplier during the matrix multiplication operation, and M represents the number of columns of the matrix as the multiplicand during the matrix multiplication operation).

Exemplarily, the specific numerical operation process of the second numerical operation circuit can be shown as follows: take the first data to be processed as matrix A and the second data to be processed as matrix B, calculate the matrix A in the first row Each matrix element of is multiplied with each corresponding matrix element in the first column in the corresponding matrix B to obtain the operation process of the matrix element at the first row and first column position in the result matrix as an example; if through the multiplier, After the determined a ₀₀ and b ₀₀ are multiplied, the first intermediate calculation result obtained is 1000111, and the second inversion circuit performs a bitwise inversion operation on the first intermediate calculation result after receiving the first intermediate calculation result , to obtain the second intermediate calculation result 0111000 corresponding to a ₀₀ ; if through the multiplier, the first intermediate calculation result obtained after the multiplication of a ₀₁ and b ₁₀ determined is 0100011, the second negation circuit receives the first After the intermediate calculation result, the bitwise inversion operation is performed on the first intermediate calculation result to obtain the second intermediate calculation result 1011100 corresponding to a ₀₁ ; if the multiplier is used, the determined a ₀₂ and b ₂₀ are multiplied to obtain the first An intermediate calculation result is 0100011. After receiving the first intermediate calculation result, the second inversion circuit performs a bitwise inversion operation on the first intermediate calculation result to obtain a second intermediate calculation result 1011100 corresponding to a ₀₂ .

If the first sign data corresponding to the sign bit of a ₀₀ includes 0, the first sign data corresponding to the sign bit of a ₀₁ includes 1, the first sign data corresponding to the sign bit of a ₀₂ includes 0; the sign bit of b ₀₀ corresponds to The first sign data includes 1, the first sign data corresponding to the sign bit of b ₁₀ includes 1, and the first sign data corresponding to the sign bit of b ₂₀ includes 0.

The sign operation circuit performs XOR processing on the first sign data of a ₀₀ and the first sign data of b ₀₀ to obtain the second sign data 1 of the first intermediate calculation result obtained by multiplying a ₀₀ and the corresponding b ₀₀ ; Similarly, the sign operation circuit performs XOR processing on the first sign data of a ₀₁ and the first sign data of b ₁₀ , and obtains the first intermediate calculation result obtained after multiplying a ₀₁ and the corresponding b ₁₀ Two symbol data 0; similarly, the symbol operation circuit performs XOR processing on the first symbol data of a ₀₂ and the first symbol data of b ₂₀ , and obtains the first intermediate calculation result obtained after the multiplication processing of a ₀₂ and b ₂₀ The second sign data 0; the sign operation circuit transmits the second sign data respectively corresponding to the three first intermediate calculation results to the second adder and the second selector.

The second selector receives the first intermediate calculation result 1000111 obtained after multiplying a ₀₀ and b ₀₀ , the second intermediate calculation result 0111000 obtained after bitwise inversion of the first intermediate calculation result, and a ₀₀ and the corresponding b ₀₀ are multiplied by the second symbol data 1 of the first intermediate calculation result, and the second symbol data 1 is used as the selection control signal. Since the second symbol data is 1, the representation will be a ₀₀ and The first intermediate calculation result obtained after the multiplication of b ₀₀ is a negative value, therefore, the control outputs the second intermediate calculation result 0111000 obtained after bitwise inversion of the first intermediate result as the third intermediate calculation result.

Similarly, the second selector receives the first intermediate calculation result 0100011 obtained after multiplying a ₀₁ and b ₁₀ , and the second intermediate calculation result 1011100 obtained after bitwise inversion of the first intermediate calculation result And after the second sign data 0 of the first intermediate calculation result obtained after multiplying a ₀₁ and the corresponding b ₁₀ , the second sign data 0 is used as the selection control signal, because when the second sign data is 0, the representation will be The first intermediate calculation result obtained after the multiplication of a ₀₁ and b ₁₀ is a positive value, therefore, the control outputs the first intermediate calculation result 0100011 as the third intermediate result.

Similarly, the second selector receives the first intermediate calculation result 0100011 obtained after multiplying a ₀₂ and b ₂₀ , and the second intermediate calculation result 1011100 obtained after bitwise inversion of the first intermediate calculation result And after the second symbol data 0 of the first intermediate calculation result obtained after the multiplication of a ₀₂ and b ₂₀ , the second symbol data 0 is used as the selection control information, because when the second symbol data is 0, the representation will be a ₀₂ The first intermediate calculation result obtained after multiplication with b ₂₀ is a positive value, therefore, the control outputs the first intermediate calculation result 0100011 as the third intermediate result.

The second selector transmits the third intermediate calculation result to the third adder.

The second adder receives the second symbol data 1 of the first intermediate calculation result obtained after multiplying a ₀₀ and the corresponding b ₀₀ , and the first intermediate calculation result obtained after multiplying a ₀₁ and the corresponding b ₁₀ After the second symbol data 0 of the calculation result and the second symbol data 0 of the first intermediate calculation result obtained after multiplying a ₀₂ and b ₂₀ , the above three second symbol data are added and summed to obtain the fourth an intermediate calculation result 1; and transmitting the fourth intermediate calculation result to the third adder.

After receiving the third intermediate calculation result and the fourth intermediate calculation result transmitted by the second selector, the third adder adds and sums the third intermediate calculation result and the fourth intermediate calculation result to obtain the target processing of the data to be processed As a result, add 0111000, 0100011, 0100011, and 1 to obtain the first row of the matrix obtained by multiplying each matrix element in the first row of matrix A by the corresponding matrix element in the first column of matrix B. A column of matrix elements.

The data processing device provided by the present disclosure can be applied in the process of multiplication of signed matrices with multiple N rows and M columns. Taking the application in two signed matrix multiplication operations as an example, the first data to be processed includes The first matrix to be processed, the second data to be processed includes the second matrix to be processed; a plurality of first sub-data in the first data to be processed includes a plurality of matrix elements located in row i in the first matrix to be processed; a plurality of The second sub-data includes a plurality of matrix elements positioned at the jth column in the second matrix to be processed; i∈[1, N], N is a positive integer greater than or equal to 2, representing the total number of rows of the first matrix to be processed; j∈ [1, M], M is a positive integer greater than or equal to 2, indicating the total number of columns of the second matrix to be processed.

Exemplarily, taking the application of the data processing device provided by the present disclosure in multiplying two signed matrices as an example, if the first data to be processed includes the first matrix to be processed

And since the type of each matrix element in the first matrix C to be processed is int type and occupies 8-bit space, then

The second data to be processed includes the second matrix to be processed

And since the type of each matrix element in the second matrix D to be processed is an int type and occupies 8 bits of space, then

Next, the process of multiplying the first matrix C to be processed by the second matrix D to be processed by the data processing device as follows will be introduced:

Utilize the first data conversion circuit 11-1 to receive the first matrix C to be processed, and convert each matrix element (ie c ₀₀ , c ₀₁ , c ₁₀ , c ₁₁ ) in the first matrix C to be processed into the first Symbolic data as well as absolute value data.

Specifically, the first conversion circuit in the first data conversion circuit 11-1 receives the n-1th bit corresponding to each matrix element in the first matrix C to be processed (because each matrix element is int8, it occupies 8 bits of space , ie n=8, so the n-1th (i.e. the 7th) characterizes the first numerical value of the sign bit of the matrix element), and uses the first numerical value as the first sign data of each matrix element, that is, receives c ₀₀ The first value 1 of the 7th bit of c 01, the first value 1 is used as the first symbol data of c ₀₀ ; and the first value 1 of the 7th bit of c ₀₁ is received, and the first value 1 is used as the first symbol data of c ₀₁ data; and receive the first numerical value 0 of the 7th bit of c ₁₀ , and use the first numerical value 0 as the first symbol data of c ₁₀ ; and receive the first numerical value 0 of the 7th bit of c ₁₁ , and use the first numerical value 0 as the first symbol data for c ₁₁ .

The first conversion circuit in the first data conversion circuit 11-1, after receiving the first value corresponding to each matrix element in the first data to be processed, can transmit the first value corresponding to each matrix element to the first data conversion circuit The second selector in the second conversion circuit in 11-1.

In addition, the second conversion circuit in the first data conversion circuit 11-1 receives the n-2th to 0th bits corresponding to each matrix element in the first matrix C to be processed (because each matrix element is int8, that is, it occupies 8-bit space, that is, n=8, so the n-2th bit to the 0th bit (ie the 6th bit to the 0th bit) represents the second value of the value of the matrix element), and based on receiving the corresponding value of each matrix element The first numerical value is converted to the second numerical value corresponding to the matrix element to obtain the absolute value data corresponding to the matrix element.

Specifically, the second conversion circuit includes a first adder, a first inverting circuit, and a first selector connected in sequence; wherein, the first adder receives the second value 1111110 of the 6th to 0th bits of c ₀₀ , the second value and the preset value (-1) are summed to obtain the first intermediate value 1111101 corresponding to c ₀₀ ; and the first intermediate value is transmitted to the first inverting circuit; the first inverting circuit receives the first After the intermediate value, perform bitwise inversion on the first intermediate value to obtain the second intermediate value 0000010 corresponding to c ₀₀ ; transmit the second intermediate value to the first selector; the first selector receives the second intermediate value corresponding to c ₀₀ value, the second intermediate value corresponding to c ₀₀ , and the first value corresponding to c ₀₀ (that is, the first symbol data corresponding to c ₀₀ ), the first value is used as the selection control signal, since the first value is 1, that is, c ₀₀ itself is a negative value, therefore, the second intermediate value 0000010 corresponding to c ₀₀ needs to be output as the absolute value data corresponding to c ₀₀ .

Similarly, the first adder receives the second value 1111010 of the 6th to 0th digits of c ₀₁ , and sums the second value with the preset value (-1) to obtain the first intermediate value 1111001 corresponding to c ₀₁ ; and transmit the first intermediate value to the first inversion circuit; after the first inversion circuit receives the first intermediate value, the first intermediate value is bitwise inverted to obtain the second intermediate value 0000110 corresponding to c ₀₁ ; The first selector transmits the second intermediate value; the first selector receives the second value corresponding to c ₀₁ , the second intermediate value corresponding to c ₀₁ , and the first value corresponding to c ₀₁ (that is, the first symbol corresponding to c ₀₁ data), the first value is used as the selection control signal, since the first value is 1, that is, c ₀₁ itself is a negative value, therefore, the second intermediate value 0000110 corresponding to c ₀₁ needs to be output as the absolute value data corresponding to c ₀₁ .

Similarly, the first adder receives the second value 0000001 of the 6th to 0th digits of c ₁₀ , sums the second value with the preset value (-1), and obtains the first intermediate value 0000000 corresponding to c ₁₀ ; and transmit the first intermediate value to the first inverting circuit; after the first inverting circuit receives the first intermediate value, the first intermediate value is bitwise inverted to obtain the second intermediate value 1111111 corresponding to c ₁₀ ; The first selector transmits the second intermediate value; the first selector receives the second value corresponding to c ₁₀ , the second intermediate value corresponding to c ₁₀ , and the first value corresponding to c ₁₀ (that is, the first symbol corresponding to c ₁₀ data), the first value is used as the selection control signal, since the first value is 0, that is, _c10 itself is a positive value, therefore, the second value 0000001 corresponding to _c10 can be output as the absolute value data corresponding to _c10 .

Similarly, the first adder receives the second value 0000000 from the 6th bit to the 0th bit of c ₁₁ , sums the second value with the preset value (-1), and obtains the first intermediate value 10000001 corresponding to c ₁₁ ; and transmit the first intermediate value to the first inverting circuit; after the first inverting circuit receives the first intermediate value, the first intermediate value is bitwise inverted to obtain the second intermediate value 01111110 corresponding to c ₁₁ ; The first selector transmits the second intermediate value; the first selector receives the second value corresponding to c ₁₁ , the second intermediate value corresponding to c ₁₁ and the first value corresponding to c ₁₁ (that is, the first symbol corresponding to c ₁₁ data), the first numerical value is used as the selection control signal, since the first numerical value is 0, that is, c ₁₁ itself is a positive value, therefore, the second numerical value 0000000 corresponding to c ₁₁ can be output as the absolute value data corresponding to c ₁₁ .

In addition, the second data conversion circuit 11-2 is used to receive the second matrix D to be processed, and convert each matrix element (that is, d ₀₀ , d ₁₀ ) in the second matrix D to be processed into the first symbol data and the absolute value data.

Specifically, the first conversion circuit in the second data conversion circuit 11-2 receives the n-1th bit corresponding to each matrix element in the second to-be-processed column D (because each matrix element is int8, it occupies 8 bits space, i.e. n=8, therefore, the n-1th (i.e. the 7th bit) characterizes the first numerical value of the sign bit of the matrix element), and the first numerical value is used as the first sign data of each matrix element, that is, receiving The first value 0 of the 7th bit of d ₀₀ is 0, and the first value 0 is used as the first symbol data of d ₀₀ ; and the first value 0 of the 7th bit of d ₁₀ is received, and the first value 0 is used as the first symbol data of d ₁₀ A symbolic data.

The first conversion circuit in the second data conversion circuit 11-2, after receiving the first value corresponding to each matrix element in the second data to be processed, can transmit the first value corresponding to each matrix element to the second data conversion circuit The second selector in the second conversion circuit in 11-2.

In addition, the second conversion circuit in the second data conversion circuit 11-2 receives the n-2th to 0th bits corresponding to each matrix element in the second to-be-processed matrix D (because each matrix element is int8, i.e. occupies 8-bit space, that is, n=8, so the n-2th bit to the 0th bit (ie the 6th bit to the 0th bit) represents the second value of the value of the matrix element), and based on receiving the corresponding value of each matrix element The first numerical value is converted to the second numerical value corresponding to the matrix element to obtain the absolute value data corresponding to the matrix element.

Specifically, the second conversion circuit includes a first adder, a first inverting circuit, and a first selector connected in sequence; wherein, the first adder receives the second value 0000001 of the 6th to 0th bits of d ₀₀ , sum the second value with the preset value (-1) to obtain the first intermediate value 0000000 corresponding to d ₀₀ ; and transmit the first intermediate value to the first negation circuit; the first negation circuit receives the first After the intermediate value, perform bitwise inversion on the first intermediate value to obtain the second intermediate value 1111111 corresponding to d ₀₀ ; transmit the second intermediate value to the first selector; the first selector receives the second intermediate value corresponding to d ₀₀ value, the second intermediate value corresponding to d ₀₀ , and the first value corresponding to d ₀₀ (that is, the first symbol data corresponding to d ₀₀ ), the first value is used as the selection control signal, since the first value is 0, that is, d ₀₀ itself is a positive value, therefore, the second value 0000001 corresponding to d ₀₀ can be output as the absolute value data corresponding to d ₀₀ .

Similarly, the first adder receives the second value 0000010 of the 6th to 0th digit of d ₁₀ , sums the second value with the preset value (-1), and obtains the first intermediate value 0000001 corresponding to d ₁₀ ; and transmit the first intermediate value to the first inverting circuit; after the first inverting circuit receives the first intermediate value, the first intermediate value is bitwise inverted to obtain the second intermediate value 1111110 corresponding to d ₁₀ ; The first selector transmits the second intermediate value; the first selector receives the second value corresponding to d ₁₀ , the second intermediate value corresponding to d ₁₀ , and the first value corresponding to d ₁₀ (that is, the first symbol corresponding to d ₁₀ data), the first numerical value is used as the selection control signal, since the first numerical value is 0, that is, _d10 itself is a positive value, therefore, the second numerical value 0000010 corresponding to _d10 can be output as the absolute value data corresponding to _d10 .

Since the multiplication operation of matrix C and matrix D is essentially to multiply the matrix elements in the first row of matrix C and the corresponding matrix elements in the first column of matrix D, and sum them up to obtain The matrix elements of the first row and the first column of the result matrix E, that is, e ₀₀ =c ₀₀ ×d ₀₀ +c ₀₁ ×d ₁₀ of the result matrix E; The matrix elements corresponding to the first column in E are multiplied and summed to obtain the matrix elements located in the first column of the second row in the result matrix E, that is, e ₁₀ =c ₁₀ ×d ₀₀ of the result matrix E c ₁₁ ×d ₁₀ ; therefore, two calculation circuits, ie, the calculation circuit 12-1 and the calculation circuit 12-2, are required to calculate and obtain each matrix element in the result matrix E respectively.

In the first data conversion circuit 11-1, each matrix element in the first matrix C to be processed is converted into corresponding first sign data and absolute value data and the second data conversion circuit 11-2 converts the second matrix D to be processed After each matrix element in is converted into the corresponding first symbol data and absolute value data, the first data conversion circuit 11-1 can convert the matrix elements in the first row in the first matrix C to be processed (i.e. c ₀₀ , c ₀₁ ) respectively corresponding to the first sign data and absolute value data are transmitted to the calculation circuit 12-1, and at the same time, the second data conversion circuit 11-2 can convert the matrix elements (ie, d ₀₀ , d ₁₀ ) respectively corresponding to the first symbol data and absolute value data are transmitted to the calculation circuit 12-1, so that the calculation circuit 12-1, based on the first symbols corresponding to c ₀₀ , c ₀₁ , d ₀₀ , d ₁₀ data and absolute value data, and calculate e ₀₀ in the result matrix E; similarly, the first data conversion circuit 11-1 can convert the matrix elements (ie, c ₁₀ , c ₁₁ ) respectively corresponding to the first sign data and absolute value data to the calculation circuit 12-2, and at the same time, the second data conversion circuit 11-2 can place the matrix elements in the first column in the second matrix D to be processed (ie d ₀₀ , d ₁₀ ) respectively corresponding first sign data and absolute value data are transmitted to the calculation circuit 12-2, so that the calculation circuit 12-2, based on the first sign data corresponding to c ₀₀ , c ₀₁ , d ₀₀ , d ₁₀ respectively and the absolute value data, and calculate e ₁₀ in the result matrix E.

In a specific implementation, the calculation circuit 12-1 includes a symbol operation circuit, a first value operation circuit, and a second value operation circuit; wherein, the sign operation circuit includes an exclusive OR gate circuit for receiving the first symbol data corresponding to c ₀₀ , The first symbol data corresponding to c ₀₁ , the first symbol data corresponding to d ₀₀ , and the first symbol data corresponding to d ₁₀ ; and the first symbol data corresponding to c ₀₀ and the first symbol data corresponding to d ₀₀ are subjected to XOR processing , obtain the second symbol data (that is, 1^0=1) of the first intermediate calculation result obtained after c ₀₀ and the corresponding d ₀₀ are multiplied; and the first symbol data corresponding to c ₀₁ and the corresponding d ₁₀ Exclusive OR processing is performed on the first symbol data to obtain the second symbol data (that is, 1^0=1) of the first intermediate calculation result obtained by multiplying c ₀₁ and the corresponding d ₁₀ .

The exclusive OR gate circuit in the calculation circuit 12-1 multiplies c ₀₀ and the corresponding d ₀₀ to obtain the second symbol data 1 of the first intermediate calculation result, and multiplies c ₀₁ and the corresponding d ₁₀ to obtain The second sign data 1 of the first intermediate calculation result is transmitted to the second selector and the second adder in the second numerical operation circuit in the calculation circuit 12-1 respectively.

The first numerical calculation circuit in the calculation circuit 12-1 includes a multiplier for receiving absolute value data corresponding to c ₀₀ , absolute value data corresponding to c ₀₁ , absolute value data corresponding to d ₀₀ , and absolute value data corresponding to d ₁₀ ; and multiply the absolute value data corresponding to c ₀₀ and the absolute value data corresponding to d ₀₀ to obtain the first intermediate calculation result 0000010 obtained after multiplying c ₀₀ and the corresponding d ₀₀ ; and the absolute value data corresponding to c ₀₁ The value data and the absolute value data corresponding to d ₁₀ are multiplied to obtain the first intermediate calculation result 0001100 obtained by multiplying c ₀₁ and the corresponding d ₁₀ .

The multiplier in the calculation circuit 12-1 multiplies c ₀₀ and the corresponding d ₀₀ to obtain the first intermediate calculation result 0000010, and c ₀₁ and the corresponding d ₁₀ to obtain the first intermediate calculation result 0001100 , respectively transmitted to the second selector and the second negation circuit in the second numerical operation circuit in the calculation circuit 12-1.

The second numerical calculation circuit in the calculation circuit 12-1 includes a second inversion circuit, a second selector, a second adder and a third adder, wherein the second inversion circuit is used to receive c ₀₀ and the corresponding The first intermediate calculation result obtained after the multiplication of d ₀₀ is 0000010, and the bitwise inversion operation is performed on the first intermediate calculation result to obtain the second intermediate calculation result 1111101; the second intermediate calculation result is transmitted to the second selector ; The second selector is used to receive the second symbol data 1 of the first intermediate calculation result obtained after multiplying c ₀₀ and the corresponding d ₀₀ , and the first intermediate calculation result obtained after multiplying c ₀₀ and the corresponding d ₀₀ The intermediate calculation result 0000010 and the second intermediate calculation result 1111101, and the second symbol data 1 of the first intermediate calculation result obtained after multiplying c ₀₀ and the corresponding d ₀₀ as the selection control signal, because the second symbol data is 1 , then the second intermediate calculation result 1111101 after bitwise inversion of the first intermediate calculation result needs to be used as the third intermediate calculation result.

In addition, the second inversion circuit is also used to receive the first intermediate calculation result 0001100 obtained after multiplying c ₀₁ and the corresponding d ₁₀ , and perform a bitwise inversion operation on the first intermediate calculation result to obtain the second Intermediate calculation result: 1110011; transmit the second intermediate calculation result to the second selector; the second selector is also used to receive the first intermediate calculation result obtained after multiplying c ₀₁ and corresponding d ₁₀ Two-symbol data 1, the first intermediate calculation result 0001100 obtained after multiplying c ₀₁ and the corresponding d ₁₀ and the second intermediate calculation result 1110011, the first intermediate calculation result obtained after multiplying c ₀₁ and the corresponding d ₁₀ The second symbol data 1 of the intermediate calculation result is used as the selection control signal. Since the second symbol data is 1, the second intermediate calculation result 1110011 after bitwise inversion of the first intermediate calculation result needs to be used as the third intermediate calculation result .

After the second selector in the calculation circuit 12-1 determines each third intermediate calculation result, the third intermediate calculation result may be transmitted to the third adder in the calculation circuit 12-1. The second adder in the calculation circuit 12-1 is used to receive the second symbol data 1 of the first intermediate calculation result obtained after multiplying c ₀₀ and the corresponding d ₀₀ , and multiply c ₀₁ and the corresponding d ₁₀ Then obtain the second symbol data 1 of the first intermediate calculation result, and calculate its sum value to obtain the fourth intermediate calculation result, namely 2 (ie 00000010).

The third adder in the calculation circuit 12-1 is used to receive the above-mentioned third intermediate calculation results and the fourth intermediate calculation results, and sum them to obtain e ₀₀ in the result matrix E (that is, to sum 1111101, 1110011, 00000010 , to get 11110010).

Similarly, the calculation circuit 12-2 includes a symbol operation circuit, a first value operation circuit and a second value operation circuit; wherein, the sign operation circuit includes an exclusive OR gate circuit for receiving the first symbol data corresponding to _c10 , _c11 The corresponding first symbol data, the first symbol data corresponding to d ₀₀ , and the first symbol data corresponding to d ₁₀ ; and the first symbol data corresponding to c ₁₀ and the first symbol data corresponding to d ₀₀ are subjected to XOR processing to obtain The second symbol data (ie 0^0=0) of the first intermediate calculation result obtained after multiplying c ₁₀ and the corresponding d ₀₀ ; and the first symbol data corresponding to c ₁₁ and the first symbol data corresponding to d ₁₀ Exclusive OR processing is performed on the sign data to obtain the second sign data (that is, 0^0=1) of the first intermediate calculation result obtained by multiplying c ₀₁ and the corresponding d ₁₀ .

The exclusive OR gate circuit in the calculation circuit 12-2 multiplies c ₁₀ and the corresponding d ₀₀ to obtain the second symbol data 0 of the first intermediate calculation result, and multiplies c ₁₁ and the corresponding d ₁₀ to obtain The second sign data 0 of the first intermediate calculation result is transmitted to the second selector and the second adder in the second numerical operation circuit in the calculation circuit 12-2 respectively.

The first numerical operation circuit in the calculation circuit 12-2 includes a multiplier for receiving absolute value data corresponding to c ₁₀ , absolute value data corresponding to c ₁₁ , absolute value data corresponding to d ₀₀ , and absolute value data corresponding to d ₁₀ ; and The absolute value data corresponding to c ₁₀ and the absolute value data corresponding to d ₀₀ are multiplied to obtain the first intermediate calculation result 0000001 obtained after multiplying c ₁₀ and the corresponding d ₀₀ ; and the absolute value data corresponding to c ₁₁ and the absolute value data corresponding to d ₁₀ are multiplied to obtain the first intermediate calculation result 0000000 obtained by multiplying c ₁₁ and the corresponding d ₁₀ .

The multiplier in the calculation circuit 12-2 multiplies c ₁₀ and the corresponding d ₀₀ to obtain the first intermediate calculation result 0000001 and c ₁₁ and the corresponding d ₁₀ to obtain the first intermediate calculation result 0000000 , respectively transmitted to the second selector and the second negation circuit in the second numerical operation circuit in the calculation circuit 12-2.

The second numerical calculation circuit in the calculation circuit 12-2 includes a second negation circuit, a second selector, a second adder, and a third adder, wherein the second negation circuit is used to receive c ₁₀ and the corresponding The first intermediate calculation result obtained after the multiplication of d ₀₀ is 0000001, and the bitwise inversion operation is performed on the first intermediate calculation result to obtain the second intermediate calculation result 1111110; the second intermediate calculation result is transmitted to the second selector ; The second selector is used to receive the second symbol data 0 of the first intermediate calculation result obtained after multiplying c ₁₀ and the corresponding d ₀₀ , obtained after multiplying c ₁₀ and the corresponding d ₀₀ The first intermediate calculation result 0000001 and the second intermediate calculation result 1111110, and the second symbol data 0 of the first intermediate calculation result obtained after multiplying c ₁₀ and the corresponding d ₀₀ as the selection control signal, because the second symbol data is 0, the first intermediate calculation result 0000001 can be used as the third intermediate calculation result.

In addition, the second inversion circuit is also used to receive the first intermediate calculation result 0000000 obtained after multiplying c ₁₁ and the corresponding d ₁₀ , and perform a bitwise inversion operation on the first intermediate calculation result to obtain the second The intermediate calculation result 1111111; transmit the second intermediate calculation result to the second selector; the second selector is also used for receiving the second intermediate calculation result of the first intermediate calculation result obtained after multiplying c ₁₁ and the corresponding d ₁₀ Symbol data 0, the first intermediate calculation result 0000000 obtained by multiplying c ₁₁ and the corresponding d ₁₀ , and the second intermediate calculation result 1111111, the first intermediate obtained by multiplying c ₁₁ and the corresponding d ₁₀ The second symbol data 0 of the calculation result is used as the selection control signal, and since the second symbol data is 0, the first intermediate calculation result 0000000 can be used as the third intermediate calculation result.

After the second selector in the calculation circuit 12-2 determines each third intermediate calculation result, the third intermediate calculation result may be transmitted to the third adder in the calculation circuit 12-2.

The second adder in the calculation circuit 12-2 is used to receive the second symbol data 0 of the first intermediate calculation result obtained after multiplying c ₁₀ and the corresponding d ₀₀ and multiply c ₁₁ and the corresponding d ₁₀ Then obtain the second symbol data 0 of the first intermediate calculation result, and calculate its sum value to obtain the fourth intermediate calculation result, namely 0 (ie 00000000).

The third adder in the calculation circuit 12-2 is used to receive the above-mentioned third intermediate calculation results and the fourth intermediate calculation results, and sum them to obtain e ₁₀ in the result matrix E (to sum 0000001, 0000000, 00000000 to obtain 00000001).

A specific structural diagram of a data processing device for performing multiplication operations on the first matrix C to be processed and the second matrix D to be processed may be shown in FIG. 8 .

In the embodiment of the present disclosure, through the cooperative work of the data conversion circuit and the calculation circuit in the data processing device, the multiplication operation between the signed data to be processed is converted into the multiplication operation between the unsigned data to be processed, which can reduce the multiplication rate. The data bit width during operation reduces the chip size and power consumption required for matrix multiplication calculations.

In addition, in the process of performing multiplication and addition operations by the calculation circuit, the layout of the adder in the data processing device is reduced, the structure of the data processing device is simplified, and the volume of the data processing device can be effectively reduced, thereby reducing the number of components of the data processing device in the AI chip. The occupied space can reduce the volume of the AI chip and increase the application range of the AI chip, that is, the AI chip can be applied to scenarios with limited volume.

Those skilled in the art can understand that in the above-mentioned device in the specific implementation mode, the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process. The specific execution order of each step should be based on its function and possible The inner logic is OK.

Based on the same inventive concept, the embodiments of the present disclosure also provide a data processing method corresponding to the data processing device. Since the problem-solving principle of the method in the embodiments of the present disclosure is similar to that of the above-mentioned data processing device in the embodiments of the present disclosure, the implementation of the method Reference can be made to the implementation of the device, and repeated descriptions will not be repeated.

The execution subject of the data processing method provided by the embodiments of the present disclosure is generally a computer device with a certain computing capability, and the computer device includes, for example, a data processing device, a server, or other processing devices. In some possible implementation manners, the data processing method may be implemented by a processor invoking computer-readable instructions stored in a memory.

Referring to FIG. 9 , it is a schematic flowchart of a data processing method provided by an embodiment of the present disclosure. The method is applied to a data processing device, and the data processing device includes a data conversion circuit and a calculation circuit; the method includes:

S901. The data conversion circuit receives the data to be processed, and converts the data to be processed into first symbol data and absolute value data; transmits the first symbol data and absolute value data to the calculation circuit; wherein, the first symbol data represents the corresponding to-be-processed data Data is positive or negative.

S902. The calculation circuit acquires the first symbol data and the absolute value data generated by the data conversion circuit, and performs a first calculation process on the absolute value data to obtain a first intermediate calculation result; determine a second value of the first intermediate calculation result based on the first symbol data Symbolic data: performing a second calculation process based on the second symbolic data and the first intermediate calculation result to obtain a processing result of the data to be processed.

In an optional implementation manner, the data conversion circuit transmits the first symbol data and the absolute value data to the input terminal of the calculation circuit through its output terminal.

In an optional implementation manner, the data processing device further includes a first register and a second register. Correspondingly, the method further includes: the data conversion circuit storing the first symbol data into the first register, and storing the absolute value data into the second register; reading the first sign data from the first register, and reading the absolute value data from the second register.

In an optional implementation manner, the data conversion circuit includes a first conversion circuit and a second conversion circuit, and the method further includes: the first conversion circuit receives a preset first bit in the data to be processed The first value of the bit, using the received first value as the first symbol data and transmitting the first value to the second conversion circuit; the second conversion circuit receives the data to be processed A second value of the second bit is preset, and based on the first value transmitted by the first conversion circuit, the second value is converted to obtain the absolute value data.

In an optional implementation manner, the second conversion circuit includes a first adder, a first negation circuit, and a first selector connected in sequence, and the method further includes: the first adder responds to receiving the second value of the preset second bit in the data to be processed, summing the second value and the preset value to obtain a first intermediate value; transmitting the first intermediate value to the first inverting circuit an intermediate value; the first inversion circuit responds to receiving the first intermediate value transmitted by the first adder, and performs a bitwise inversion operation on the first intermediate value to obtain a second intermediate value, transmit the second intermediate value to the first selector; the first selector responds to receiving the second value of the preset second bit in the data to be processed, and the first inverting circuit transmits The second intermediate value and the first value transmitted by the first conversion circuit, using the first value as a selection control signal, control the output of the second value as the absolute value data, or control The second intermediate value is output as the absolute value data.

In an optional implementation manner, the data to be processed includes first data to be processed and second data to be processed; the first data to be processed includes a plurality of first sub-data; the second data to be processed It includes a plurality of second sub-data; the data conversion circuit includes a first data conversion circuit and a second data conversion circuit. Correspondingly, the method further includes: the first data conversion circuit receives the first data to be processed, and converts a plurality of first sub-data in the first data to be processed into The first symbol data and absolute value data corresponding to the first sub-data; the second data conversion circuit receives the second data to be processed, and converts a plurality of second sub-data in the second data to be processed respectively are first sign data and absolute value data corresponding to each of the second sub-data.

In an optional implementation manner, the calculation circuit includes a symbolic operation circuit, a first numerical operation circuit and a second numerical operation circuit. Correspondingly, the method further includes: the symbolic operation circuit responds to the acquisition of the first symbolic data, and based on the first symbolic data, determines the second symbolic data of the first intermediate calculation result, and sends to the The second numerical operation circuit transmits the second symbol data; the first numerical operation circuit performs a first operation on the absolute value data in response to obtaining the absolute value data to obtain the first intermediate calculation Result; transmit the first intermediate calculation result to the second numerical operation circuit; the second numerical operation circuit responds to receiving the second symbol data transmitted by the symbol operation circuit and the first numerical operation The first intermediate calculation result transmitted by the circuit, based on the second symbol data and the first intermediate calculation result, performs a second calculation process to obtain a target processing result of the data to be processed.

In an optional implementation manner, the first operation processing includes multiplication processing; the second operation processing includes addition processing; the data to be processed includes first data to be processed and second data to be processed; The first data to be processed includes a plurality of first sub-data; the second data to be processed includes a plurality of second sub-data respectively corresponding to the first sub-data; the first symbol data includes the first The first symbol data of the sub-data and the first symbol data of the second sub-data respectively corresponding to the first sub-data; the symbol operation circuit includes an exclusive OR gate circuit. Correspondingly, the method further includes: for each of the first sub-data, the XOR gate circuit combines the first symbol data of each of the first sub-data with the first symbol data of the corresponding second sub-data Exclusive OR processing is performed to obtain second sign data of the first intermediate calculation result obtained by multiplying each of the first sub-data and the corresponding second sub-data.

In an optional implementation manner, the absolute value data includes the first absolute value data corresponding to each of the first sub-data and the first absolute value data corresponding to each of the first sub-data The second absolute value data; the first numerical operation circuit includes a multiplier. Correspondingly, the method further includes: for each of the first sub-data, the multiplier combines the first absolute value data of each of the first sub-data with the second absolute value data of the corresponding second sub-data Performing a product operation to obtain a first intermediate calculation result corresponding to each of the first sub-data.

In an optional implementation manner, the second numerical operation circuit includes a second negation circuit, a second selector, a second adder, and a third adder. Wherein, the second negation circuit receives the first intermediate calculation result corresponding to each of the first sub-data transmitted by the first numerical operation circuit, and calculates the first intermediate calculation result corresponding to each of the first sub-data performing a bitwise inversion operation on the calculation result to obtain a second intermediate calculation result corresponding to each of the first sub-data, and transmitting the second intermediate calculation result corresponding to each of the first sub-data to the second selector . The second selector responds to receiving the second symbol data of the first intermediate calculation result corresponding to each of the first sub-data transmitted by the symbol operation circuit, and each of the first intermediate calculation results transmitted by the second negation circuit. The second intermediate calculation result corresponding to the first sub-data and the first intermediate calculation result corresponding to each of the first sub-data transmitted by the first numerical operation circuit, using the second symbol data as a selection control signal , control to output the first intermediate calculation result corresponding to each of the first sub-data as the third intermediate calculation result corresponding to the first sub-data, or control to output the second intermediate calculation result corresponding to each of the first sub-data The result is output as a third intermediate calculation result corresponding to the first sub-data; and the third intermediate calculation result corresponding to each of the first sub-data is transmitted to the third adder. The second adder responds to receiving the second symbol data of the first intermediate calculation result corresponding to each of the first sub-data transmitted by the symbol operation circuit, and for each of the first sub-data corresponding to Summing the second sign data of the first intermediate calculation result to obtain a fourth intermediate calculation result; transmitting the fourth intermediate calculation result to the third adder. In response to receiving the third intermediate calculation result and the fourth intermediate calculation result corresponding to each of the first sub-data, the third adder calculates the third intermediate calculation result corresponding to each of the first sub-data summing the fourth intermediate calculation result to obtain the target processing result.

In an optional implementation manner, the first data to be processed includes a first matrix to be processed; the second data to be processed includes a second matrix to be processed; the plurality of first sub-data includes the first A plurality of matrix elements located in row i in a matrix to be processed; a plurality of the second sub-data includes a plurality of matrix elements located in column j in the second matrix to be processed; i∈[1,N], N is a positive integer greater than or equal to 2, representing the total number of rows of the first matrix to be processed; j∈[1, M], M being a positive integer greater than or equal to 2, representing the total number of columns of the second matrix to be processed.

Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to the relevant description in the embodiment of the data processing device corresponding to the embodiment of the present disclosure, the implementation of the method can refer to the implementation of the above-mentioned data processing device, repeat The place will not be repeated.

Those skilled in the art can understand that in the above method of specific implementation, the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process. The specific execution order of each step should be based on its function and possible The inner logic is OK.

The embodiment of the present disclosure also provides a chip, including the data processing device as provided in the embodiment of the present disclosure.

The embodiment of the present disclosure also provides a computer device, including: a memory and the data processing apparatus provided in the embodiment of the present disclosure.

The embodiment of the present disclosure also provides a computer device, including a chip.

The data processing apparatus provided by the embodiments of the present disclosure may include a chip, an AI chip, and the like. The computer device provided in the embodiment of the present disclosure may include a smart terminal such as a mobile phone, or may also be other devices, servers, etc. that can be used for data processing, which is not limited here.

Embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a computer device, the computer device executes the data processing described in the foregoing method embodiments. method steps. Wherein, the storage medium may be a volatile or non-volatile computer-readable storage medium.

Embodiments of the present disclosure also provide a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the data processing method described in the above method embodiment, for details, please refer to the above method The embodiment will not be repeated here.

Wherein, the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. wait. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described system and device can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned storage medium includes various media that can store program codes such as U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk.

Finally, it should be noted that the above-described embodiments are only specific implementations of the present disclosure, and are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto, although referring to the aforementioned The embodiments have described the present disclosure in detail, and those skilled in the art should understand that any person familiar with the technical field can still modify the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present disclosure Changes can be easily imagined, or equivalent replacements can be made to some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in this disclosure. within the scope of protection. Therefore, the protection scope of the present disclosure should be defined by the protection scope of the claims.

Claims

A data processing device, characterized in that it comprises:

A data conversion circuit, configured to receive data to be processed, and convert the data to be processed into first symbol data and absolute value data, wherein the first symbol data indicates that the corresponding data to be processed is positive or negative value;

Calculation circuit for:

Acquiring the first symbol data and the absolute value data generated by the data conversion circuit;

performing a first calculation process on the absolute value data to obtain a first intermediate calculation result;

determining second sign data of the first intermediate calculation result based on the first sign data;

Performing a second calculation process based on the second symbol data and the first intermediate calculation result to obtain a target processing result of the data to be processed.
The device according to claim 1, characterized in that,

The output end of the data conversion circuit is connected to the input end of the calculation circuit;

The data conversion circuit is further configured to transmit the first symbol data and the absolute value data to the input terminal of the calculation circuit through the output terminal of the data conversion circuit.
The device according to claim 1, characterized in that,

The device also includes a first register and a second register;

The data conversion circuit is further configured to store the first sign data into the first register, and store the absolute value data into the second register;

The calculation circuit is also used to read the first sign data from the first register, and read the absolute value data from the second register.
The device according to any one of claims 1-3, wherein the data conversion circuit comprises:

A first conversion circuit, configured to receive a first numerical value of a preset first bit in the data to be processed, and use the received first numerical value as the first symbol data;

A second conversion circuit, configured to receive a second value preset in a second bit in the data to be processed, and perform conversion processing on the second value based on the first value transmitted by the first conversion circuit , to obtain the absolute value data.
The device according to claim 4, wherein the second converting circuit comprises:

A first adder, configured to sum the second value and the preset value to obtain a first intermediate value in response to receiving a second value of a preset second bit in the data to be processed;

A first inversion circuit, the input end of the first inversion circuit is connected to the output end of the first adder, and is used for responding to receiving the first intermediate value transmitted by the first adder, for performing a bitwise inversion operation on the first intermediate value to obtain a second intermediate value;

A first selector, the input end of the first selector is connected to the output end of the first conversion circuit and the output end of the first inverting circuit, and is used for responding to receiving the preset in the data to be processed Set the second value of the second bit, the second intermediate value transmitted by the first negation circuit, and the first value transmitted by the first conversion circuit, and use the first value as a selection control signal, control to output the second value as the absolute value data, or control to output the second intermediate value as the absolute value data.
The device according to any one of claims 1-5, wherein the data to be processed includes first data to be processed and second data to be processed; the first data to be processed includes a plurality of first sub-data ; The second data to be processed includes a plurality of second sub-data; the data conversion circuit includes:

A first data conversion circuit, configured to receive the first data to be processed, and convert a plurality of first sub-data in the first data to be processed into first data corresponding to each of the first sub-data symbolic data as well as absolute value data;

The second data conversion circuit is configured to receive the second data to be processed, and convert a plurality of second sub-data in the second data to be processed into first data corresponding to each of the second sub-data Symbolic data as well as absolute value data.
The device according to any one of claims 1-6, wherein the computing circuit comprises:

a sign operation circuit, configured to determine second sign data of the first intermediate calculation result based on the first sign data in response to acquiring the first sign data;

A first numerical operation circuit, configured to, in response to acquiring the absolute value data, perform a first operation on the absolute value data to obtain the first intermediate calculation result;

The second numerical operation circuit, the input end of the second numerical operation circuit is connected to the output end of the symbolic operation circuit and the output end of the first numerical operation circuit, and is used to respond to receiving the transmission from the symbolic operation circuit The second symbol data and the first intermediate calculation result transmitted by the first numerical operation circuit, based on the second symbol data and the first intermediate calculation result, a second calculation process is performed to obtain the The target processing result for the data to be processed.
The device according to claim 7, characterized in that,

The first arithmetic processing includes multiplication processing;

The second arithmetic processing includes addition processing;

The data to be processed includes first data to be processed and second data to be processed;

The first data to be processed includes a plurality of first sub-data;

The second data to be processed includes a plurality of second sub-data respectively corresponding to the first sub-data;

The first symbol data includes first symbol data of the first sub-data and first symbol data of the second sub-data respectively corresponding to the first sub-data;

The symbol operation circuit includes an exclusive OR gate circuit;

The XOR gate circuit is used to perform XOR processing on the first symbol data of each of the first sub-data and the first symbol data corresponding to the second sub-data for each of the first sub-data, to obtain The second symbol data of the first intermediate calculation result obtained after each of the first sub-data and the corresponding second sub-data is multiplied.
The device according to claim 8, wherein the absolute value data includes first absolute value data corresponding to each of the first sub-data and the second sub-data corresponding to each of the first sub-data The second absolute value data corresponding to the data;

The first numerical operation circuit includes a multiplier;

The multiplier is configured to, for each of the first sub-data, perform a product operation on the first absolute value data of each of the first sub-data and the second absolute value data corresponding to the second sub-data to obtain each of the first sub-data The first intermediate calculation result corresponding to the first sub-data.
The device according to claim 8 or 9, wherein the second numerical operation circuit comprises:

A second inversion circuit, the input end of the second inversion circuit is connected to the output end of the first numerical operation circuit, and is used to receive each of the first sub-data corresponding to the transmission of the first numerical operation circuit and performing a bitwise inversion operation on the first intermediate calculation result corresponding to each of the first sub-data to obtain a second intermediate calculation result corresponding to each of the first sub-data;

a second selector, the input end of the second selector is respectively connected to the output end of the second negation circuit, the output end of the symbol operation circuit, and the output end of the first numerical operation circuit, In response to receiving the second symbol data of the first intermediate calculation result corresponding to each of the first sub-data transmitted by the symbol operation circuit, each of the first sub-data transmitted by the second inverting circuit The second intermediate calculation result corresponding to the sub-data, and the first intermediate calculation result corresponding to each of the first sub-data transmitted by the first numerical operation circuit, the second symbol data is used as a selection control signal, and the control will The first intermediate calculation result corresponding to each of the first sub-data is output as the third intermediate calculation result corresponding to the first sub-data, or control the second intermediate calculation result corresponding to each of the first sub-data as the output outputting the third intermediate calculation result corresponding to the first sub-data;

The second adder, the input terminal of the second adder is connected to the output terminal of the symbol operation circuit, and is used to respond to receiving the first intermediate corresponding to each of the first sub-data transmitted by the symbol operation circuit For the second symbol data of the calculation result, sum the second symbol data of the first intermediate calculation result corresponding to each of the first sub-data to obtain a fourth intermediate calculation result;

A third adder, the input end of the third adder is respectively connected to the output end of the second selector and the output end of the second adder, for responding to receiving each of the first The third intermediate calculation result corresponding to the sub-data and the fourth intermediate calculation result are summed to the third intermediate calculation result corresponding to each of the first sub-data and the fourth intermediate calculation result to obtain the Target processing result.
The device according to any one of claims 8-10, characterized in that,

The first data to be processed includes a first matrix to be processed;

The second data to be processed includes a second matrix to be processed;

The plurality of first sub-data includes a plurality of matrix elements located in row i in the first matrix to be processed, i∈[1,N];

The plurality of second sub-data includes a plurality of matrix elements located in column j in the second matrix to be processed, j∈[1,M];

N is a positive integer greater than or equal to 2, representing the total number of rows of the first matrix to be processed;

M is a positive integer greater than or equal to 2, and represents the total number of columns of the second matrix to be processed.
A data processing method, characterized in that it is applied to a data processing device, and the data processing device includes a data conversion circuit and a calculation circuit; the method includes:

The data conversion circuit receives the data to be processed, and converts the data to be processed into first symbol data and absolute value data;

The data conversion circuit transmits the first symbol data and the absolute value data to the calculation circuit; wherein, the first symbol data indicates that the corresponding data to be processed is a positive value or a negative value;

The calculation circuit acquires the first symbol data and the absolute value data generated by the data conversion circuit, performs a first calculation process on the absolute value data, and obtains a first intermediate calculation result;

the calculation circuit determines second sign data of the first intermediate calculation result based on the first sign data;

The calculation circuit performs a second calculation process based on the second symbol data and the first intermediate calculation result to obtain a processing result of the data to be processed.
A chip, characterized by comprising the data processing device according to any one of claims 1-11.
A computer device, characterized in that it includes:

memory; and

The data processing device according to any one of claims 1-11.
A computer device, characterized by comprising the chip as claimed in claim 13.
A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is run by a computer device, the computer device executes the data processing method according to claim 12 A step of.