JP2005128618A - Divider, exposure control device, and division method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a small and high speed divider without causing a system complication and a circuit scale increase. <P>SOLUTION: The divider 1 processes an operation of dividing a dividend X by a divisor K as an addition of given elements that are the dividend X multiplied by powers of two (2<SP>N</SP>) according to an approximation depending on the divisor K (refer to formula (8)). The approximation corresponds with given limited values that are each a possible input as the divisor K, and has the sufficient accuracy of the integral part of each element added. The division can be performed simply by bit shifts and additions to realize a small and high speed divider. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a division circuit, an exposure control device, and a division method for performing a division operation.

Conventionally, a divider is used to perform a division operation in an information processing apparatus.
In such a divider, when the divisor is B, the dividend is A, and A / B is calculated as the division result Y, the divisor B is subtracted from the dividend A, the remainder C is stored in a register, and the remainder C is divisored again. Usually, the operation of pulling B is repeated.

FIG. 8 is a block diagram showing a schematic configuration of a conventional divider.
In FIG. 8, the dividend A is input to the shifter 201, and the divisor B is input to the subtracter 203 and the division controller 205. Then, the dividend A is bit-shifted by the shifter 201 in accordance with the number of bits D having a preset calculation accuracy.
The multiplexer 202 selects the dividend A shifted by the shifter 201 and inputs the selected dividend A to the subtracter 203.

The subtractor 203 subtracts the divisor B from the dividend A, and outputs the remainder C to the register 204 and the division controller 205.
When the first division cycle ends, the division controller 205 outputs a control signal CS for storing the remainder C to the register 204. When the register 204 receives the control signal CS from the division controller 205, the remainder C Is stored.

Then, after the next cycle, the division controller 205 switches the output from the multiplexer 202 to the subtracter 203 from the shifter 201 side to the register 204, so that the remainder C stored in the register 204 via the multiplexer 202 is obtained. Input to the subtractor 203.
When the remainder C is input to the subtractor 203, the subtractor 203 subtracts the divisor B from the remainder C, and the remainder C at that time is output to the register 204 and the division controller 205.
When the above operation is repeated and the remainder C becomes smaller than the divisor B, the division controller 205 ends the calculation, calculates the division result Y according to the calculation accuracy, and outputs it to the outside.
Such a division method is well known, and is described in, for example, Japanese Patent Application Laid-Open No. 2002-175178.
JP 2002-175178 A

However, the conventional divider has a problem that depending on the dividend A and the divisor B, the number of division calculation cycles is different and may require 100 to 1000 cycles or more, which hinders a high-speed division operation. In addition, it is conceivable to speed up the operation by using such a divider together with a plurality of comparators and multipliers. However, there is a problem that the system becomes complicated and the circuit scale increases. It was.
An object of the present invention is to realize a small and high-speed divider.

In order to solve the above problems, the present invention provides:
An divider ^M for calculating a result of dividing the dividend X by a divisor K, and approximating an integer part of 2 ^L / K (L is an integer) by a sum of addition elements 2 ^N (N is a positive integer) Based on the above, the division result is calculated by performing an operation of X × (M / 2 ^L ).
Here, the power of 2 ^L is a value that defines the accuracy of division, and can be arbitrarily set as required.

With such a configuration, division can be performed only by bit shift and addition, so that a small and high-speed divider can be realized.
Moreover, since the approximate value M is prepared according to the divisor K, it is possible to ensure sufficient accuracy as the division result.
For each integer up to N determined by the divisor K, bit shift value output means for outputting the M / 2 ^N bit shift values of the dividend X (for example, the shifter 21 in FIG. 6 and the wiring processing for bit shifting the output) Part), a selection unit (for example, the control unit 10 in FIG. 4 and the MUXs 22a to 22i in FIG. 6) for selecting the predetermined M / 2 ^N- bit shift value corresponding to the divisor K, and the selection unit And adding means (for example, adders 23a to 23h in FIG. 6) for adding each of the selected M / 2 ^N- bit shift values.

With such a configuration, since the output of the bit shift value output means can be selected by the selection means and then added by the addition means, it is possible to cope with division by different divisors K.
The selection means stores selection information (for example, the LUT in FIG. 5) indicating which of the M / 2 ^N- bit shift values of the dividend X is selected for a plurality of the divisors K. Each of the M / 2 ^N- bit shift values corresponding to the inputted divisor K is selected based on the selection information.

With this configuration, the divisor K and the M / 2 ^N- bit shift value to be selected can be easily associated with each other, so the value of the divisor K or the number of divisors K that may be input is changed. Even in this case, it is possible to easily cope with the divisor K after the change.
The present invention also provides:
A luminance is calculated by performing division by using any of the above-mentioned dividers and dividing the integrated value obtained by integrating the pixel values of the video as the dividend X and the number of pixels related to the integrated value as the divisor K. The exposure control device is configured to perform exposure control of the video based on the above.

That is, in the calculation of the luminance level, the process of dividing the luminance value accumulated for a large number of pixels by the number of the large number of pixels is repeated, so that the high-speed feature of the divider according to the present invention is further effective. It will be a thing. Further, since the divider according to the present invention is small, the manufacturing cost is low, the power consumption is low, and the divider is more suitable for exposure control.
The present invention also provides:
A division method for calculating a result of dividing a dividend X by a divisor K, in which an integer part of 2 ^L / K (L is an integer) is approximated by a sum of addition elements 2 ^N (N is a positive integer) Based on the value M, a division result is calculated by performing an operation of X × (M / 2 ^L ).
With this method, a small and high-speed divider can be realized.

Embodiments of a divider according to the present invention will be described below with reference to the drawings.
First, the division method in the present invention will be described.
In the present invention, it is assumed that the divisor is fixed to some extent, such as luminance value averaging processing for exposure control in the imaging apparatus. For example, in an image having a size of QVGA (Quarter Video Graphics Array), CIF (Common Intermediate Format), VGA (Video Graphics Array), SVGA (Super Video Graphics Array), XGA (eXtended Graphics Array), or SXGA () SupereXtended Graphics Array When calculating the average value of luminance (the integrated value of the luminance of each pixel / the total number of pixels), the divisor becomes a fixed value because the number of pixels of a block that is a processing unit in each image is determined. .

In such a case, if a general-purpose divider that can divide by an arbitrary divisor is used, a redundant circuit configuration is obtained. Therefore, the function is optimized, and the circuit scale is reduced and the operation speed is increased.
That is, an object of the division method according to the present invention is to divide an input X (integer) by a divisor K (integer) to obtain an output Y including a decimal part. That is,
Y = X × (1 / K) (1)
Here, the expression (1) is expressed as the following expressions (2) and (3).
Y≈X × (M / 2 ²⁰ ) (2)
1 / K≈M / 2 ²⁰ (3)
Here, M is an integer, and 2 ²⁰ is a value that defines the precision in division.

Then, from equation (3)
M = int (2 ²⁰ /K+0.5) (4)
Here, “int” represents a function that outputs only the integer part of the argument in parentheses. Further, by adding “0.5”, the equation (4) means rounding off.
Next, the meaning of the integer M will be described.

In the following description, it is assumed that K = 3072 (the total number of pixels of QVGA). At this time, the equation (1) is
Y = X × (1/3072) (5)
Thus, according to equation (4), M = 341. As a result, the equation (2) is expressed as the following equation.
Y≈X × (341/2 ²⁰ ) (6)
Furthermore, equation (5) can be expressed as:
Y≈Y ′ = X × ((256 + 64 + 16 + 4 + 1) / 2 ²⁰ ) (7)
That is,
Y ′ = X × (1/2 ¹² +1/2 ¹⁴ +1/2 ¹⁶ +1/2 ¹⁸ +1/2 ²⁰ ) (8)
Since the coefficient (7) or (8) is expressed by a power of 2, it is easy to configure a digital circuit.

That is, since the calculation of X / 2 ^N (N is a natural number) can be executed by bit shifting, when executing the expression (7) or (8), the input X is 20 bits, 18 bits, 16 bits, respectively. The output Y ′ (division result) can be obtained by calculating a value shifted by 14 bits and 12 bits and adding the calculated results.
Therefore, by converting the expression (1) into an operation like the expression (7) or the expression (8), the division process can be realized by a shifter and an adder.

According to the above-described method, for example, in the case of each image format described above, the value of “M” can be grasped in advance.
FIG. 1 is a diagram showing the divisor K in each image format in the present embodiment.
In FIG. 1, for each type of image, the total number of pixels, the size of a block serving as a processing unit, and the total number of pixels of the block are defined. In this embodiment, as shown in FIG. 2, one image is divided into 25 (5 × 5) equal sizes, but the block sizes do not have to be equal, and the total number of pixels of the block is defined in advance. It only has to be done.

FIG. 3 is a diagram showing divisors K, 2 ²⁰ / K, M, and values M representing values of powers of 2 for the respective image formats.
In FIG. 3, the coefficient of X expressed as a power of 2 is defined as a fixed value corresponding to the divisor K of each image format.
Therefore, a value obtained by shifting the input X by a predetermined bit is calculated by a shifter that bit-shifts the input X by a bit corresponding to each power-of-two term, and among these, a value corresponding to each image format is selected. Thus, the output Y is obtained.

Hereinafter, a divider to which the present method is applied will be described.
First, the configuration will be described.
FIG. 4 is a diagram illustrating a functional configuration of the divider 1 according to the present embodiment.
In FIG. 4, the divider 1 includes a control unit 10 and a calculation unit 20.
The control unit 10 stores a lookup table (LUT) in which the value of each divisor K in FIG. 3 that may be input as the divisor K is associated with the coefficient of X expressed as a power of 2. ing. More specifically, the LUT is a code in which an image format (divisor K) is associated with an X coefficient. When the code that gives the divisor K is input, the control unit 10 outputs the selection signals SEL-MUX0 to 8 to the calculation unit 20 according to the corresponding power-of-two element (X / 2 ^N ). . Specifically, selection signals SEL-MUX0 to 8 indicating whether or not the input X selects each value shifted by a predetermined bit are output to the arithmetic unit 20. (Refer to the description of the arithmetic unit 20 in FIG. 6).

The arithmetic unit 20 calculates a value obtained by shifting the input X by a predetermined bit, and calculates and outputs an output Y by selecting and adding these values according to a selection signal input from the control unit 10. Here, the input X is an unsigned 26-bit integer value.
FIG. 5 is a diagram showing the contents of the LUT stored in the control unit 10.
In FIG. 5, the LUT stores for each image format whether or not each of the outputs shifted to the left by 0 to 8 bits in the description of the arithmetic unit 20 in FIG. 6 is selected, and “0” is not selected. “1” indicates selection.

FIG. 6 is a diagram illustrating a circuit configuration example of the arithmetic unit 20.
In FIG. 6, the arithmetic unit 20 includes a shifter 21, multiplexers (MUX) 22a to 22i, and adders 23a to 23h.
In FIG. 6, the shifter 21 shifts the input X to the right by 20 bits and outputs it to the MUXs 22a to 22j. Note that the process of shifting the input X to the right by 20 bits corresponds to 1/2 ²⁰ of the expression (7).

  The output of the shifter 21 is input to each multiplexer as a value shifted by a predetermined bit by wiring processing. This processing corresponds to, for example, multiplication processing corresponding to each addition element of (256 + 64 + 16 + 4 + 1) in Expression (7). Specifically, the output of the shifter 21 is input to the MUX 22a with the output shifted to the left by 8 bits. Similarly, the output of the shifter 21 is input to the MUXs 22b to 22i with the output of the shifter 21 shifted by 7 to 0 bits, respectively. Is done.

As described above, the MUXs 22a to 22i are each input with a value obtained by shifting the output of the shifter 21 by a predetermined bit to the left by the wiring process, and each of the MUXs 22a to 22i receives selection signals SEL-MUX0 to 8 input from the control unit 10. Thus, either the output of the bit-shifted shifter 21 or “0” is selected and output.
The adders 23a to 23h add the values input to the adders and output the result. Then, when the adders 23a to 23h sequentially add, the output Y (quotient) is finally output by the adder 23h. This addition process corresponds to the process of (256 + 64 + 16 + 4 + 1) in Expression (7).

6 shows a configuration in which the value shifted 20 bits to the right by the shifter 21 is further shifted to the left by a predetermined bit by the wiring process. However, the bit shift result obtained by collecting these bit shifts is converted into the MUX 21a˜ It is good also as inputting into 21i.
FIG. 7 is a diagram illustrating a circuit configuration example of the arithmetic unit 20 when the bit shifts in FIG. 6 are combined.

In FIG. 7, as a result of collecting the bit shifts, the shifter 21 is unnecessary.
7 does not affect the pattern in which the control unit 10 selects the MUXs 22a to 22i, so that the selection signals SEL-MUX0 to 8 described above according to the divisor K. The same selection signal may be input.

Next, the operation will be described.
In FIG. 1, a code that gives a divisor K and a dividend X are input to the divider 1, and a code that gives the divisor K is passed to the control unit 10, and the dividend X is passed to the calculation unit 20.
When a code giving the divisor K is input, the control unit 10 refers to the LUT to select one of the inputs of the MUXs 22a to 22i (the output of the shifter 21 shifted to the left or “0”). The selection signals SEL-MUX0 to 8 are output to the MUXs 22a to 22i.

In addition, in the arithmetic unit 20, the shifter 21 shifts the input divisor X by 20 bits to the right, and the output is input to each of the MUXs 22a to 22i through the left shift by the wiring process.
Then, each of the MUXs 22a to 22i selects and outputs either the output of the shifter 21 shifted to the left or “0” in accordance with the selection signals SEL-MUX0 to 8 input thereto.

For example, in the case of a QVGA image, from FIG. 5, a selection signal for selecting the output of the shifter 21 shifted to the left is input to the MUXs 22a, 22c, 22e, 22g, and 22i. A selection signal for selecting 0 ″ is input.
The outputs of the MUXs 22a to 22i are sequentially added by the adders 23a to 22h, and the output of the adder 23h is output as a quotient obtained by dividing the dividend X by the divisor K.

As described above, the divider 1 according to the present embodiment has a predetermined value obtained by multiplying the dividend X by a power of 2 (2 ^N ) based on the approximation according to the divisor K for dividing the dividend X by the divisor K. Processed as addition of elements (see equation (8)). The approximation performed at this time corresponds to a limited predetermined value that may be input as the divisor K, and has sufficient accuracy for the integer part of each element to be added.

Therefore, since division can be performed only by bit shift and addition, a small and high-speed divider can be realized.
In addition, even if the value or number that can be input as the divisor K is changed, it can be dealt with only by changing the contents of the LUT, so that versatility can be ensured.

  Further, when the divider 1 according to the present embodiment is used for exposure control of an electronic camera or the like, in the calculation of the luminance level, a process of dividing the luminance value accumulated for a large number of pixels by the large number of pixels. Since it is repeated, the feature of high speed becomes more effective. Further, since the divider 1 according to the present invention is small, the manufacturing cost is low, the power consumption is low, and the divider 1 is more suitable for exposure control of an electronic camera or the like.

  In the present embodiment, the input X is an unsigned 26-bit integer, which is shifted 20 bits to the right by the shifter and further left-shifted by a maximum of 8 bits, so (26-20) + 8 = 14-bit integer part. However, a 1-bit code bit is added for the subsequent addition process, and finally an integer part of 15 bits is obtained. In this case, an operation having a 35-bit dynamic range is performed together with the 20-bit decimal part generated by the 20-bit shift.

On the other hand, if lower calculation accuracy is sufficient, for example, the integer part can be made into a dynamic range of 15 bits with no sign and the fractional part can be made into a fixed 19-bit dynamic range of 4 bits. Can be handled by changing the input dynamic range of the adders 23a to 23h.
Further, in the present embodiment, as shown in the equation (4), it is described that “M” is rounded off after the decimal point. However, by rounding down or rounding up the decimal point, It is possible to ensure almost the same calculation accuracy.

It is a figure which shows the divisor K in each image format. It is a figure which shows the area | region division of the image used as the background of the divisor prescribed | regulated in embodiment. It is a figure which shows the value which represented the divisor K in the case of each image format, 2 < ²⁰ > / K, M, and the value M by the power of 2, respectively. It is a figure which shows the function structure of the divider 1 which concerns on this Embodiment. It is a figure which shows the content of LUT which the control part 10 has memorize | stored. 3 is a diagram illustrating a circuit configuration example of a calculation unit 20. FIG. It is a figure which shows the circuit structural example of the calculating part 20 at the time of putting together the bit shift in FIG. It is a block diagram which shows schematic structure of the conventional divider.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Divider, 10 Control part, 20 Operation part, 21,201 Shifter, 22a-22i, 202 Multiplexer (MUX), 23a-23h Adder, 203 Subtractor, 204 Register, 205 Division controller

Claims (5)

A divider for calculating a result of dividing a dividend X by a divisor K;
By performing an operation of X × (M / 2 ^L ) based on an approximate value M obtained by approximating the integer part of 2 ^L / K (L is an integer) by the sum of addition elements 2 ^N (N is a positive integer) A divider characterized by calculating a division result. Bit shift value output means for outputting M / 2 ^N bit shift values of the dividend X for each integer up to N determined by the divisor K;
Selecting means for selecting the predetermined M / 2 ^N- bit shift value corresponding to the divisor K;
Adding means for adding each of the M / 2 ^N- bit shift values selected by the selecting means;
The divider according to claim 1, comprising: The selection means stores selection information indicating which of the M / 2 ^N- bit shift values of the dividend X is to be selected for a plurality of the divisor K, and is input based on the selection information 3. The divider according to claim 2, wherein each of the M / 2 ^N- bit shift values corresponding to the divisor K is selected. A divider according to any one of claims 1 to 3,
The luminance is calculated by dividing the integrated value obtained by integrating the pixel values of the video as the dividend X and the number of pixels related to the integrated value as the divisor K, and based on the luminance, exposure control of the video is performed. An exposure control device characterized in that: A division method for calculating a result of dividing a dividend X by a divisor K,
By performing an operation of X × (M / 2 ^L ) based on an approximate value M obtained by approximating the integer part of 2 ^L / K (L is an integer) by the sum of addition elements 2 ^N (N is a positive integer) A division method characterized by calculating a division result.

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