JPH0457112A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain the arithmetic unit which can execute a data processing at a high speed without bringing about a remarkable increase of a circuit scale by providing a look-up table means constituted by using a storage element having plural ports. CONSTITUTION:A look-up table 10 has two ports, and an output from the port for inputting input data A as an address, and an output from the port for inputting input data B as an address correspond to output data D and output data E respectively. That is, in this case, as a result, operations of D = 15 X A and E = 15 X B are executed in parallel. Two operations are independent except a fact that a coefficient 15 is common, and by executing them in parallel, a processing speed becomes two folds. In such a way, by executing a look-up operation by using a table which uses a storage element having plural ports, the circuit scale can be suppressed to a small increase, comparing with a linear increase of an arithmetic speed caused by an increase of the number of ports.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus that performs arithmetic processing such as multiplication and division in digital signal processing, and particularly relates to an arithmetic apparatus that performs high-speed signal processing.

[Conventional technology]

FIG. 4 shows an example of a data calculation method using a conventional table lookup type calculation device disclosed in, for example, Japanese Unexamined Patent Publication No. 53-47739. In this way, the data calculation method using the table lookup method is used for multiplication and division in digital signal processing, derivation of trigonometric functions, and the like. Here, explanation will be given by taking as an example the multiplication of a constant coefficient and a variable.

In the figure, 1 is a lookup table, which is generally a ROM (
It is composed of a read-only memory (read-only memory), etc., and its contents are written at each address as a calculation result determined from coefficient constants and variables input at the address. For example, if the input data A4 to A are integers (any of 0 to 15) expressed in 4-bit natural binary numbers, and the coefficient is 15 (1111 expressed in natural binary numbers), the output data D8 ~D, are as shown in Table 1 below.

Table 1 Therefore, the input data A4 to A are assigned to each memory address determined as an address input, and the corresponding output data D8 to
Write the value of D in advance and enter the input data A4.
This table lookup method reads out the calculation result written in advance when ~A1 is given as an address input. In this case, for example, data 1001 (1
If 9) is given in base 0, the multiplication result is 100
0111 (135 in decimal) is read from the table.

In this case, the capacity of the ROM required for the table is 24-16 words, the number of words determined by the number of bits of input data, and the number of bits is 8, which is the number of bits of output data D8 to D1.

[Problem to be solved by the invention]

Since the conventional table lookup type arithmetic device is configured as described above, the circuit scale is determined by the capacity of the table (ROM) which depends on the number of bits of input data and output data. In particular, it has been pointed out that as the number of bits of input data increases, the capacity of the table increases exponentially, resulting in an increase in circuit scale.

Also, when performing high-speed data processing such as image processing, it is necessary to shorten the table (ROM) access time or
It is necessary to use a speed-up method such as performing parallel processing using multiple tables. However, ROM access time is generally not that high, and if the latter method is used, multiple tables with circuit sizes determined by the number of bits of the data and output data described above are required, which inevitably increases the circuit size significantly. Causes problems. This increase in circuit size leads to an increase in the number of parts, or in the case of LSI, an increase in the area occupied by the circuit (.

This invention was made in order to solve the above-mentioned problems, and it is an arithmetic operation that can perform high-speed data processing without significantly increasing the circuit scale in an arithmetic device using a table lookup method. The purpose is to obtain equipment.

[Means to solve the problem]

The arithmetic device according to the present invention is configured to perform the same operation as when using a lookup table using a memory element having a plurality of ports.

[Effect]

Since the table lookup type arithmetic device according to the present invention uses a memory element having multiple ports as a table, it is possible to extract multiple outputs in parallel by addressing multiple ports independently. Become. Therefore, it is possible to obtain the same effect on speeding up data processing as the method using a table using a plurality of storage elements shown in the conventional example.

Furthermore, compared to the case where a plurality of memory elements are generally used, the use of a memory element having a plurality of ports has the advantage that the increase in circuit scale can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an arithmetic unit according to an embodiment of the present invention. In the figure, reference numeral 10 denotes a look-up table, which is composed of a memory element having a plurality of ports. Here, a case where the number of ports is two will be explained. A is the first input data and is expressed as a 4-bit binary number (A 4. A 3. A 2°A,). B is the second input, (B
,,B3. The same (B,,B,) is expressed as a 4-bit binary number.D is the first output data, and (DIl~
D,) is an 8-bit binary number, E is the second output data, and (E.

~E, ) is expressed as an 8-bit binary number.

The operation will be explained below. It is assumed that the contents of the lookup table are as shown in Table 1, as in the conventional example. The lookup table 10 has two boats, and the output from the boat that takes input data A as an address input corresponds to output data D, and the output from the boat that takes input data B as an address input corresponds to output data E. That is, in this case, the following calculations are executed in parallel: D=15XA...Equation (]) E=15XB...Equation (2). The processing of equations (1) and (2) are independent except for the common coefficient 15, and assuming that the time required for one operation (table access time) is equal, the processing can be performed by executing them in parallel. The speed will be doubled.

In this way, when a lookup table is constructed using a memory element with multiple ports, the circuit scale is larger than that of a normal memory element with a single port. It gets bigger by that amount.

FIG. 2 shows a schematic configuration diagram of a memory element having two ports. In the figure, 2 is a memory cell array section, 3a and 3b are first
．． Second address decoder, 4a.

4b is the first. This is a second readout circuit. Compared to a storage element with a single port, a storage element with two ports has an additional pair of address decoders and readout circuits, but it is not necessary to have two memory cell arrays. Since the memory cell array section of a typical semiconductor memory element occupies most of the circuit scale, the number of ports can be increased by performing lookup operations using a table using a memory element with multiple ports. Compared to the linear increase in calculation speed that accompanies this, the circuit size can be suppressed to a slight increase.

To perform calculations using the table lookup method, it is possible to use a single ROM as the table and configure it by combining parts such as semiconductor elements, but it is possible to configure the table and its surroundings by incorporating them all into one semiconductor integrated circuit. A very efficient computing device can be constructed.

FIG. 3 is a schematic diagram showing an example of the configuration of a semiconductor integrated circuit for performing table lookup operations using a memory element having a plurality of ports. In the figure, 5 indicates an input circuit, and 6 indicates an output circuit. 7 is an input signal, and 8 is an output signal. The input circuit 5 receives the input signal 7, performs preprocessing such as changing the data order, and then stores data A4 to A4 in the lookup table 10.
A + , and 84 to B are output. Data D8 ~ subjected to calculation processing by the lookup table 10
DI, Ell to E are subjected to post-processing such as changing the order of data and changing the word length by the output circuit 6, and are outputted as an output signal 8. Although the input circuit 5 and the output circuit 6 are shown separately in FIG. 3, they may of course be combined as an input/output circuit.

In the above description of the embodiment, an example has been described in which a memory element with two boats is used in the lookup table, but it is also possible to use a memory element with three or more boats. Not even.

Although FIG. 2 shows an example of a read-only memory element, it goes without saying that a writable memory element may also be used when implementing the present invention.

〔Effect of the invention〕

As described above, according to the arithmetic device according to the present invention, the function of a plurality of lookup tables is realized using a memory element having a plurality of ports, so that table lookup can be performed without significantly increasing the circuit scale. It becomes possible to perform high-speed data processing using this method. In other words, there is an effect that a high-speed table lookup type arithmetic device can be realized with a small number of parts at low cost, or in the case of LSI, with a small area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a table lookup type arithmetic device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a semiconductor integrated circuit equipped with a lookup type arithmetic function, and FIG. The figure is a schematic diagram showing an example of the configuration of a semiconductor integrated circuit for performing table lookup operations using memory elements having multiple ports, and FIG. 4 is a diagram showing an example of a conventional table lookup type arithmetic device. be. In the figure, 1.10 is a lookup table, AA4 to A,
is the first input data, B, 84 to B1 are the second input data, D, D8 to D1 are the first output data, B, EII
~E, is the second output data, 2 is the memory cell array, 3
a and 3b are address decoders, 4a and 4b are readout circuits, 5 is an input circuit, 6 is an output circuit, 7 is an input signal, and 8 is an output signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A table lookup type arithmetic device, characterized by comprising lookup table means configured using a storage element having a plurality of ports.