JPS5819760Y2 - semiconductor storage device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a semiconductor memory device, and particularly relates to an insulated gate field effect transistor (Insulated Gate Field Effect Transistor).
The present invention relates to a semiconductor memory device suitable for forming a memory circuit by integrating field effect transistors (abbreviated as IGFETs or MOSFETs) on the same silicon wafer.

There are two types of semiconductor memory devices: dynamic type circuits and static type circuits.The former is called dynamic type memory, and the latter is called static type memory, and various circuit systems are used for each. There is.

FIG. 1 shows an example of the configuration of a memory array and a sense circuit of a commonly used static type memory.

Here it is. ,Lo. . . . Ln and Ln are the input/output line of each row of the memory array, the input/output line (input line and complement relationship), and l Ot t 1 , respectively.

...tm is a row address line.

Therefore, in this example, since the matrix has m columns and n rows, an mXn focusing configuration is shown.

As the sense circuits ■□, ■2゜...In, a complementary clocked inverter as shown in Fig. 2 at or b is used, and as each memory cell C, a complementary type IG as shown in Fig. 3 is used. -Uses FET circuit.

One voltage sensing circuit may be provided in each row of the memory array, or one voltage sensing circuit may be provided for the entire memory array. FIG. 1 shows an example of the former, with one clocked inverter ( sense circuit) is provided.

Cronked inverter entry method A. . Alt...An is
In this case, this signal selects a row, and this signal selects the clocked inverters ①o to ①.

Only one of them is activated, and only the read data of the column of the memory array is transferred to the sense output line So and taken out as the output signal Dont via the output circuit OL.

By the way, in the case of semiconductor memory, the time required to read data is called the access time tA.In recent years, there has been a trend towards memory capable of high-speed operation, and the access time tA
One of the important points in memory circuits is how to shorten Oc.

This access time tAo can be shortened by shortening the delay time of all circuits that operate when reading data, but in particular, the information read out to the data input/output lines Lo, L1, etc. is processed as quickly as possible. An important point is the characteristics of the sense circuit for transmitting information to the output circuit OL.

In the conventional method shown in Fig. 1, the outputs of n sense circuits are commonly connected and read out to the common sense output line So, but the sense circuit output inevitably has parasitic capacitance. Therefore, as in the conventional method, nflfffi
When all the sense outputs of
It is clear that the ability of one selected sense circuit out of n to drive the common output line So decreases in proportion to the value of n.

In recent years, semiconductor memories are aiming for multi-pin points, and the value of n is often several tens or more. In such cases, all sense circuits are connected to a common sense output line S.

The method of connecting to the sense circuit is the reading time t ACC of the sense circuit.
However, if we increase the size of the 2000s, we may end up going against the trend of shortening them.

In order to eliminate this time, it is possible to design the drive capability of each sense circuit to be as small as possible, but as is well known, the conductance gm of the sense circuit and its pattern area are approximately proportional to each other, so it is necessary to The chip area must be increased.

The present invention was developed in view of the above-mentioned circumstances.The sense circuit that detects the voltage of each output line of the memory array is divided into multiple sets, and the sense circuit output is commonly connected for each set. By selectively obtaining the output), the data access time tAC can be reduced even when the number of columns in the memory array increases.
It is an object of the present invention to provide a semiconductor memory device that allows a multi-pint memory to be designed without increasing C and without increasing the semiconductor chip area.

An embodiment of the present invention will be described below with reference to the drawings.

Since this embodiment shown in FIG. 4 corresponds to that shown in FIG. 1, the same reference numerals are used for corresponding parts, and only the differences will be explained.

That is, the feature of this embodiment is that the column system is divided into two, the sense circuit outputs of n/2 columns are commonly connected by the output line Sol, and the remaining n
The sense circuit outputs of the 72 columns are commonly connected to an output line So2, and this common output line S is connected.

1802 is a binary signal N, H that divides the column into two.
Selection circuit C of clocked inverter configuration clocked by C■1. Connected to C■20 input section.

The binary signal N is, for example, tt Ijj while selecting the n/2 columns, and drives the selection circuit CI□, and the binary signal N is, for example, 1'' while selecting the remaining n/2 columns.
By driving the selection circuit C2, the selection circuit C
■1. C■ This eliminates the influence of the two outputs on each other.

And commonly connected selection circuit C■1. The output of C2 is connected to the output circuit OL.

With the circuit configuration as described above, the output lines So1. Only half of the parasitic capacitance attached to the output line So shown in Figure 1 is attached to So2, and even if the sense output line is divided into two as shown in Figure 4, the area increase due to this is almost negligible. Cronked inverter C that is suppressed to a negligible extent and added 1. The output load capacitance of C2 is very small compared to the output capacitance of the sense circuit, and the clocked inverters CI□ and C2 do not require a particularly large side.

Therefore, when comparing the conventional circuit of FIG. 1 with the same sense circuit, the one of FIG. 4 can shorten the readout time in the sense circuit to about 172 without increasing the area.

In the above embodiment, a case has been described in which the sense circuit output line is divided into two, but it may be divided into three, four, etc., and the number of selection circuits in each set may be increased accordingly.

Furthermore, in the embodiment, a complementary semiconductor memory using different channel IGFETs has been explained, but a single channel type IGFET has been described.
It can also be applied to semiconductor memory using T.

As an example of this case, FIG. 5 shows a circuit diagram of a memory cell using only a P-channel type IGFET, and FIG. 6 shows a basic diagram of a sense circuit or selection circuit.

Furthermore, although the embodiments have been described with respect to static type semiconductor memories, the present invention can also be applied to dynamic type memories.

As explained above, according to the present invention, since the sense output lines are divided into a plurality of groups, it is possible to provide a semiconductor memory device that can shorten data access time without increasing the area occupied by the semiconductor chip.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of a conventional memory array and sense circuit; Figures 2a and b are specific examples of the same sense circuit;
The figure is a specific circuit diagram of the memory cell shown in Figure 1, Figure 4 is a circuit diagram showing one embodiment of the present invention, and Figures 5 and 6 are diagrams of main parts of other embodiments of the present invention. FIG. L□, L□"Ln, Ln...input/output line,
C: Memory cell, I□, In: Sense circuit, CI□,, CI2: Selection circuit.

Claims (1)

[Scope of utility model registration request] A memory array arranged in a matrix, a plurality of data lines connected to this memory array, a plurality of first selection circuits that also serve as sense circuits connected to these data lines, and these first selection circuits. means for dividing the circuit output into a plurality of blocks, and for each of these blocks, dividing the first selection circuit output into one output line; and a second selection circuit connected to each of the divided output lines. , means for consolidating the outputs of these second selection circuits into one, and an output circuit connected to this means.