JP3531402B2 - Square circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a squaring circuit that outputs the square of the numerical value of input data.

[0002]

2. Description of the Related Art A square operation can be regarded as a multiplication in which a multiplier and a multiplicand are the same. Regarding the conventional squaring circuit, the method for deriving the squaring value in a digital circuit is described in, for example, the document “Knowledge of Hardware” (Setsuo Osuka, Hideaki Chikaya, Ohmsha).
Describes a digital circuit multiplication method. The basic rule of multiplication in a digital circuit is that the multiplicand is multiplied by each digit of the multiplier, and this is moved to the left by the number of digits corresponding to each digit of the multiplier (bit shift) to obtain the partial product. The result of multiplication is obtained by adding the partial products of. That is, (1) If the digit of the multiplier is 0, multiply the multiplicand by 0, and (2) If the digit of the multiplier is 1, multiply the multiplicand by 1 and shift the multiplicand to the left by an amount equal to the digit of the multiplied multiplier. Then, the multiplication result can be obtained.

This derivation method is similar to the case of decimal numbers. For example, a calculation method in a digital circuit of 6 × 5 in decimal will be described as an example. When expressed in binary numbers, 6 can be expressed as 110 and 5 can be expressed as 101. In the following, decimal numbers will be written in parentheses after being expressed in binary numbers. That is, they are represented as 110 (6) and 101 (5). 110
The calculation of (6) × 101 (5) is as follows.

[0004]

[Equation 1]

That is, of each digit of the multiplier 101 (5), 0 is digitized for a digit which is 0 and multiplicand 110 (6) is digitized for a digit which is 1, and a partial product is obtained by bit-shifting that digit. The multiplication result can be obtained by adding all the partial products.

By the way, the square can be considered as a multiplication in which the multiplier and the multiplicand are the same. Therefore, for example, in the conventional squaring circuit, the square of 1011 (11) is obtained as follows according to the conventional method described above.

[0007]

[Equation 2]

The conventional 2 for determining such a squared value
The squaring circuit will be specifically described. A squaring circuit that outputs a squared value of input data by a conventional method can be realized by using a logical product gate and an adder in a circuit using a logic element such as a gate array or an IC. As an example, when the input data of the squaring circuit is 4 bits, the conventional 2
Figure a block diagram showing a specific hardware configuration of the circuit multiply
Shown in 17 . Next, the operation of the conventional squaring circuit with reference to FIG 7. In FIG. 17 , 1701 and 17
02, 1703, 1704 are AND gates, 1705,
1706 and 1707 are adders.

Next, the operation of the circuit will be described. FIG. 17
In the above, 4-bit data input to the squaring circuit is set to D ₀ , D ₁ , D ₂ , and D _{3 in} order from the lower bit. At this time, D _i (i: non-negative integer) is 0 or 1. That is, D _i
Ε {0, 1}. The 4-bit digital data input to the squaring circuit is input to the AND gate 1701. The AND gate 1701 has inputs D ₀ and D ₀ , D ₁ ,
The logical product of D ₂ and D ₃ is calculated and output to the adder 1705. That is, the AND gate 1701 outputs 0 if D ₀ is 0, the input data if D ₀ is 1, and the adder 1705
Output to.

The 4-bit data input to the squaring circuit is similarly AND gate 1702 and AND gate 170.
3, input to the AND gate 1704. Then, the logical product gate 1702 calculates the logical product of D ₁ and D ₀ , D ₁ , D ₂ , and D ₃ and outputs the logical product to the adder 1705. The logical product gate 1703 takes the logical product of D ₂ and D ₀ , D ₁ , D ₂ , and D ₃ and outputs the logical product to the adder 1706. Further, the logical product gate 1704 calculates the logical product of D ₃ and D ₀ , D ₁ , D ₂ , and D ₃ and outputs the logical product to the adder 1707. That is, AND gate 1702, a 0, D ₁ is 0, D ₁ is a 1, then the input data, and outputs to the adder 1705. Moreover, AND gate 1703, a D ₂ are 0, 0, D ₂ is a 1, then the input data, and outputs to the adder 1706. Similarly, AND gate 1704, a D ₃ is 0, 0, D ₃ is a 1, then the input data, and outputs to the adder 1707.

The operation of the adder 1705 will be described. The adder 1705 adds the value output from the logical product gate 1701 and the value output from the logical product gate 1702 by 1-bit left bit shift, and outputs the addition result. That is, the adder 1705 outputs the addition result obtained by adding the least significant digit of the input data of the squaring circuit and the multiplication result of the second digit from the bottom.

Next, the operation of the adder 1706 will be described.
The adder 1706 adds the output of the adder 1705 and the value obtained by shifting the output of the AND gate 1703 by 2 bits to the left, and outputs the addition result. That is, the adder 1
706 is the least significant digit of the input data of the squaring circuit and 2 from the bottom
The addition result of adding the multiplication result of the second digit from the first digit is output.

Next, the operation of the adder 1707 will be described.
The adder 1707 adds the output of the adder 1706 and the value obtained by shifting the output of the AND gate 1704 by 3 bits to the left, and outputs the addition result. That is, the adder 1
Reference numeral 707 outputs the addition result obtained by adding the multiplication result of each digit of the input data of the squaring circuit.

As described above, when the value to be squared, that is, the value to be squared is 4 bits, a numerical value of at least 4 bits or more is 3
It is necessary to add times. However, when the squaring circuit is required to operate at high speed, the delay due to the adder becomes a problem. For example, the delay of the 1-bit adder on the gate array is described in the document "A.
According to "SIC Data Book TC180G / E Series Macrocell" (Toshiba), it is about 1.2 ns. Therefore, the delay of the 4-bit adder is 4.8 ns, which is 16 times the delay of 0.3 ns of the AND cell. Since the delay when performing 4-bit addition three times is 4.8 × 3 = 14.4 ns, a signal of 1 / 14.4 ns = about 70 MHz or more causes a delay of 1 clock or more in output, and pipeline processing Since it is necessary, there is a problem that the timing control becomes complicated and the circuit scale also increases.

In order to reduce the delay until the squared value is output after the input data is input to the squaring circuit, it is general to reduce the output bit. Bit reduction can not only reduce the delay but also the circuit scale. For example, when the number of input bits is 7 bits, a circuit diagram showing a circuit configuration of the conventional squaring circuit in which no bits are reduced is shown in FIG .
In 8 (a), shows a configuration diagram showing a circuit configuration in a case where the bit reduction in FIG. 18 (b).

The circuit shown in FIG . 18A is a block diagram of a conventional squaring circuit in the case where the number of input bits is 7 bits. The operation of the circuit is shown in FIG. Since it is similar to the case, the description of the circuit operation is omitted. Next, the operation of the circuit when the number of bits is reduced is shown in FIG.
Will be explained. In FIG. 18B, 1801,
1802 and 1803 are AND gates, 1804 and 180
5 is an adder.

Next, the operation of the circuit will be described. FIG.
In (b), 7-bit data input to the squaring circuit is D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , in order from the lower bit.
Let them be D ₅ and D ₆ . At this time, D _i (i: non-negative integer) is 0 or 1. That is, D _i ε {0,1}. The 7-bit digital data input to the squaring circuit is input to the AND gate 1801. AND gate 1801
Takes the logical product of the input D ₄ and D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ and D ₆ and outputs it to the adder 1804. That is,
The AND gate 1801 outputs 0 when D ₄ is 0 and D ₀ is 1
If so, the input data is output to the adder 1804.

The 7-bit data input to the squaring circuit is similarly AND gate 1802 and AND gate 180.
Input to 3. Then, in the AND gate 1802, D ₅
And D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , and D ₆ are ANDed and output to the adder 1804. AND gate 18
In 03, the logical product of D ₆ and D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ and D ₆ is calculated and output to the adder 1805. That is,
The AND gate 1802, D ₅ is 0, 0, D ₅ 1
If so, the input data is output to the adder 1804. Further, the AND gate 1803, 0, D ₆ is 0, D ₆
If is 1, the input data is output to the adder 1805.

The operation of the adder 1804 will be described. The adder 1804 adds the value output from the AND gate 1801 by 4 bits and the value output from the AND gate 1802 by 5 bits, and outputs the addition result. That is, the adder 1804 outputs the addition result obtained by adding the multiplication result of the second digit from the top of the input data of the squaring circuit and the multiplication result of the third digit from the top.

Next, the operation of the adder 1805 will be described.
The adder 1805 adds the output of the adder 1804 and the value obtained by shifting the value output from the AND gate 1803 by 6 bits, and outputs the addition result. That is, the adder 1805 outputs the addition result obtained by adding the most significant digit of the input data of the squaring circuit, the second digit from the top, and the third digit from the top.

In this way, when the input is 7 bits, if the bit reduction is not performed, the number of additions is required to be 7-1 = 6 times as shown in FIG. The number of additions can be reduced by adopting a configuration in which multiplication with lower bits is not performed. For example, if the circuit shown in FIG. 18B is configured to perform multiplication only up to 3 bits, the number of additions can be reduced to two.

When bits are reduced to eliminate the contribution of lower bits to the output of the squaring circuit, the number of additions is reduced, the delay is reduced, and the circuit scale can be reduced, while the output of the squaring circuit is reduced. There is a problem that an error from the true square value is generated. Figure a graph of input-output characteristics of the conventional squaring circuit, for example that the bit reduction mentioned 7-bit input on
19 shows. In FIG. 19 , the dotted line shows the input / output characteristics of the squaring circuit in the ideal case without bit reduction and the solid line with the bit reduction. As can be seen from FIG. 19, there is a problem that the error from the solid line becomes large by reducing the bits.

[0023]

As described above, in the conventional squaring circuit, the adder adds the partial products of the number corresponding to the digit of the input data and outputs the squared value. It was Therefore, as the number of bits of the input data of the squaring circuit increases, the number of additions of the adder increases. Therefore, when a high-speed circuit operation speed is required, a delay of several clocks may occur to output the squared value, which requires pipeline processing to complicate timing control. There was a problem that the scale increased. Further, when the number of adders is reduced to reduce the delay due to repeated addition and the lower bits of the output are reduced, an error occurs in the output value of the squaring circuit, and an accurate square value is obtained. There was a problem that it was not output. The present invention has been made to solve such a problem, and an object of the present invention is to obtain a square circuit that can handle high-speed operation with a simple AND circuit configuration.

[0024]

The squaring circuit according to the present invention is an MSB value extracting circuit for extracting the MSB value of the input of the squaring circuit and an output of the MSB value extracting circuit from the input of the squaring circuit. An adder for subtracting the MSB value to obtain the LSP value at the input of the squaring circuit; a left bit shift circuit for left bit shifting the MSB value output from the MSB value extraction circuit;
A left bit shift circuit for left bit shifting the LSP value which is the output of the adder, and an adder for adding the outputs of the two left bit shift circuits and outputting the squared result are provided. .

Further, the squaring circuit according to the present invention uses the input M
A plurality of AND gates that operate as an MSB value extraction circuit that extracts the SB value and that outputs a logical product of the most significant bit of the input and all bits, and the most significant bit of the input that makes the addition output high impedance by the enable input Is provided as one input, a logical product element that outputs 1 when the input of the squaring circuit is 0, a logical sum element, and a 3-state output buffer.

Further, the squaring circuit according to the present invention uses the input M
A plurality of AND gates that output the logical product of the most significant bit of the input and all bits, and a plurality of three-state output buffer gates that make the output high impedance by the enable input, operating as an MSB value extraction circuit that extracts the SB value And an AND element which outputs 1 when the input of the squaring circuit is 0, an OR element, a 3-state output buffer, and an addition which outputs a squared result in which the most significant bit of the input is one input It is equipped with a container.

Further, the squaring circuit according to the present invention is an MSB value extracting circuit for extracting the MSB value of the input of the squaring circuit and an output of the MSB value extracting circuit from the input of the squaring circuit.
An adder that subtracts the B value to obtain the LSP value of the input of the squaring circuit, a left bit shift circuit that left-shifts the MSB value that is the output of the MSB value extraction circuit, and an LSP that is the output of the adder. A left bit shift circuit that shifts the value to the left, an MSB value extraction circuit that extracts the MSB value of the LSP value that is the output of the adder, and an output of the MSB value extraction circuit from the LSP value that is the output of the adder Is LS
An adder that subtracts the MSB value of the P value to obtain the LSP value of the LSP value of the input of the squaring circuit, a left bit shift circuit that left-shifts the MSB value that is the output of the MSB value extraction circuit, and the addition A left bit shift circuit for left-shifting the LSP value, which is the output of the converter, and an adder for adding the outputs of the four left bit shift circuits and outputting the squared result are provided.

Further, the squaring circuit according to the present invention is an MSB value extracting circuit for extracting the MSB value of the input of the squaring circuit and an output of the MSB value extracting circuit from the input of the squaring circuit.
An adder that subtracts the B value to obtain the LSP value of the input of the squaring circuit, a decoder that decodes the MSB value that is the output of the MSB value extraction circuit, and a left bit shift circuit that shifts the decoder output to the left. , The left bit shift circuit for left bit shifting the LSP value output from the adder and the outputs from the two left bit shift circuits are added to obtain 2
And an adder for outputting a multiplication result.

Further, the squaring circuit according to the present invention uses the input M
A plurality of AND gates that operate as an MSB value extraction circuit that extracts the SB value and that outputs a logical product of the most significant bit of the input and all bits; and a plurality of adders that make the addition output high impedance by the enable input, This is provided with a logical product element that outputs 1 when the input of the squaring circuit is 0, an OR element, and a 3-state output buffer.

Further, the squaring circuit according to the present invention uses the input M
A plurality of AND gates that output the logical product of the most significant bit of the input and all bits, and a plurality of three-state output buffer gates that make the output high impedance by the enable input, operating as an MSB value extraction circuit that extracts the SB value And an AND element that outputs 1 when the input of the squaring circuit is 0, an OR element, a 3-state output buffer, and 2
And an adder for outputting a multiplication result.

Further, the squaring circuit according to the present invention uses the input M
A plurality of AND gates that operate as an MSB value extraction circuit that extracts SB values, that outputs a logical product of the most significant bit of the input and all bits, and an AND element and an inverter that operate as a decoder that decodes the input of the adder And a plurality of adders that make the addition output high impedance by the enable input, a logical product element that outputs 1 when the input of the squaring circuit is 0, a logical sum element, and a 3-state output buffer. It was done.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a configuration diagram showing a configuration of a squaring circuit according to the first embodiment. In FIG. 1, 101 is an MSB value extraction circuit, 102 is a left bit shift circuit, 103 is an adder, 1
Reference numeral 04 is a left bit shift circuit, and 105 is an adder. The value obtained by the squaring circuit in the present embodiment will be described. The squaring circuit is a circuit that outputs the numerical data of the square of the input data. When the input data is x and the output data is y, the relationship between x and y can be expressed by the following equation. y = x ² (1) In the above equation, x is represented by the sum of x ₁ and x ₂ . That is, x = x ₁ + x ₂ (2). By substituting the equation (2), the equation (1) can be expressed as follows. y = (x ₁ + x ₂ ) ² = x ₁ ² + 2x ₁ x ₂ + x ₂ ² (3) If x ₁ > x ₂ holds, squared x ₁ ² and x ₂ ^{2 respectively} . The following relationships are established for. x ₁ ² >> x ₂ ² (4) Using the relationship of the expression (4), the expression (3) can be transformed as follows. _{^{y = x 1 2 + 2x 1}} x 2 + x 2 2 ≒ x 1 2 + 2x 1 x 2 (5) In other words, choose the x ₁ and x ₂ as x _1> x ₂ holds, for squaring circuit output data y The contribution of x ₂ ² can be ignored. In the first embodiment, the right side of equation (5) is obtained as the output of the squaring circuit.

The operation will be described below with reference to the drawings.
In FIG. 1, when digital input data, which is a binary signal, is input to the squaring circuit, it is input to the MSB value extraction circuit 101 to extract the MSB value. Here, the MSB is the most significant digit which becomes 1 when the input data is expressed in binary. The value of the input data x of the squaring circuit is 2 ^m ≤x
If ≦ 2 ^{m + 1} −1 (m is a non-negative integer),
The m-th bit is the MSB. In this case, the MSB value is 2 ^m
Is. Further, hereinafter, a plurality of bits representing a value x-2 ^m obtained by subtracting the MSB value 2 ^m from the input data x, that is, a plurality of bits lower than the MSB are set as LSP, and x-2 ^m is set as an LSP value. The MSB value extraction circuit 101 extracts and outputs 2 ^{m in} which the m-th bit is 1. Below, MSB of input data x
The value 2 ^m is x ₁ , and the MSB value 2 ^m is subtracted from x-x _1.
That is, the LSP value is set to x ₂ . Therefore, x, x ₁ , x ₂
The following relationships are established between the two. x = x ₁ + x ₂ (2)

As an example, consider the case of input data x = 11. When expressed in a binary number, 11 is 1011. After that,
Numerical values shall be written in decimal numbers in parentheses after being written in binary numbers. That is, it is expressed as 1011 (11). x is the MSB value 1000 (8) and the input data 1011
It can be divided into LSP value 11 (3) obtained by subtracting MSB value 1000 (8) from (11). MSB value extraction circuit 1
01 extracts and outputs 1000 (8) in which the third bit is 1. Since m is a non-negative integer, the least significant bit is the 0th bit.

The MSB value extraction circuit 101 outputs x ₁ which is the MSB value of the input data x, that is, 2 ^m . The x ₁ output from the MSB value extraction circuit 101 is input to the left bit shift circuit 102. Further, x ₁ is also input to the shift input S of the left bit shift circuit 102. The x ₁ input to the left bit shift circuit 102 is left bit-shifted by the digit designated by the shift input S. M for shift input S
Since x ₁ of which the 1st bit is 1 is input, x ₁ is left-shifted by m bits to output x ₁ ′. Here, x ₁ 'is a value obtained by shifting 2 ^m by m bits, so 2 ^2m
be equivalent to. That is, x ₁ ′ = x ₁ ² . The left bit shift circuit 102 squares x ₁ or 2 ^m and outputs x ₁ ² or 2 ^2m to the adder 105.

The operation of the left bit shift circuit 102 when the input data x = 11 will be described. MSB value extraction circuit 10
10 which is the MSB value of the input data x output from 1
00 (8) is left bit-shifted by 3 bits in the left bit shift circuit 102. Where 1000 (8) is 3
Since only the 1st bit is 1, a 3-bit shift of 1000 (8) is equivalent to a square operation. Bit-shifted value 1
000000 (64) is input to the adder 105 as the output of the left bit shift circuit 102.

The MSB value x ₁ or 2 ^m of the input data x output from the MSB value extraction circuit 101 is also input to the adder 103. The adder 103 subtracts x ₁ from the input data x and outputs x−x _1, that is, the LSP value x ₂ to the left bit shift circuit 104.

Adder 103 when input data x = 11
The operation of will be described. The adder 103 is 1 which is the MSB value of the input data x output from the MSB value extraction circuit 101.
000 (8) is subtracted from the input data x = 1011 (11), and the LSP value of the input data x, 11 (3), is output to the left bit shift circuit 104.

The left bit shift circuit 104 includes an adder 1
The LSP value x ₂ of the input data x, which is the output of 03, is input. In addition, the shift input S of the left bit shift circuit 104
X ₁ which is the MSB value of the input data x output from the MSB value extraction circuit 101 is input to the. The x ₂ input to the left bit shift circuit 104 is left bit-shifted by a digit obtained by adding 1 to the value designated by the shift input S. Since x ₁ with the m-th bit being 1 is input to the shift input S, x ₂ is shifted to the left by (m + 1) bits. The left m-bit shift corresponds to x ₁ times, and the left 1-bit shift corresponds to 2 times. That is, the left (m + 1) bit shift of x ₂ in the left bit shift circuit 104 is equivalent to the operation of deriving 2x ₁ x ₂ . The left bit shift circuit 104 outputs ₂ × ₁ × ₂ to the adder 105.

The operation of the left bit shift circuit 104 when the input data x = 11 will be described. 11 (3), which is the LSP value of the input data x output from the adder 103, is 3
The bit is shifted left by + 1 = 4 bits. Here, the left 4-bit shift is equivalent to the operation of 2 ⁴ = 16 times, 2 × x ₁
(8) × x ₂ (3) = 48 is derived. The bit-shifted value is 110000 (48), which is output to the adder 105 as the output of the left bit shift circuit 104.

In the adder 105, the left bit shift circuit 1
And x ₁ ² output from 02, the left bit shift circuit 104
2 x ₁ x ₂ output from the above are added and output as the output of the squaring circuit. When input x = 11, 1000000 (6
4) and 110000 (48) are added, 11100
00 (112) is output.

As described above, the input data of the squaring circuit is M
The SB value and the LSP value are divided, a constant left bit shift operation is performed on each of them, a partial product is obtained, and two partial products are added to obtain a squared value. The number can be reduced to obtain a squaring circuit with less delay.

Embodiment 2. Although the operation of the squaring circuit has been described using the block diagram in the first embodiment, the squaring circuit can be configured using an actual logic circuit. In the second embodiment, processing in bit units when an actual digital signal is input to the squaring circuit will be described using a logic circuit.

[0044] Even the second embodiment, by placing the Form 1 in the same manner as y = x ² embodiment _{x = x 1 + x 2,} y ≒ x 1 2
+ 2x ₁ x ₂ and obtaining the value approximating. Hereinafter, as an example, a case where the number of input bits is 4 bits will be described with reference to the drawings. FIG. 2 is a configuration diagram showing the configuration of the squaring circuit according to the second embodiment.
02 and 203 are AND gates, and 204, 205 and 206
Is an adder, 207 is a 3-state output buffer, 208 is an AND element, and 209 is an OR element.

Next, the operation of the circuit will be described. In FIG. 2, 4-bit data input to the squaring circuit is D ₀ , D ₁ , D ₂ and D _{3 in} order from the lower bit. At this time D
_i (i: non-negative integer) is 0 or 1. That is, D _i ∈
It is {0,1}. First, a case where the data input to the squaring circuit is not 0 will be described. That is, if the logical product symbol is &, then D ₀ & D ₁ & D ₂ & D ₃ ≠ 0. Of the 4-bit digital signal input to the squaring circuit, D
3 is input to the enable E of the adder 204. If E = 1, the adder 204 adds the inputs A and B of the adder 204 and outputs the addition result, and if E = 0, the output becomes high impedance and the addition result is not output. Therefore D ₃ =
If it is 1, the adder 204 adds using the inputs D ₀ , D ₁ , D ₂ , and D ₃ and outputs the addition result. On the other hand, D ₃
If = 0, the output of the adder 204 becomes high impedance and the addition result is not output.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since a D ₃ = 1, the enable E of the adder 204 is 1, the adder 204 outputs the addition result by adding the inputs A and B.

The input 4-bit digital signal is also input to the AND gate 201. D ₃ goes to C of the AND gate 201, and D ₀ , D ₁ and D _{2 go} to the AND gate 20.
1 is input to I ₀ , I ₁ , and I ₂ , respectively. In the AND gate 201, the inversion of D ₃ and the lower 3 bits D ₀ , D
The logical product of ₁ and D ₂ is calculated and output to the adder 205 and the logical product gate 202. That is, the AND gate 201 is
If D ₃ = 0, then O ₀ , O ₁ and O ₂ are respectively changed to D ₀ ,
D ₁ and D ₂ are output, and if D ₃ = 1 then O ₀ , O ₁ and O ₂ to 0 are output to the adder 205 and the AND gate 202.

This will be described with reference to the drawings. Figure 3
(A) is a block diagram showing the structure of the AND gate 201, where 301 is an inverter, and 302, 303, 304 are AND elements. C of the AND gate 201 is connected to the inverter 301. Therefore, the inverter 301
D ₃ of the inverting ↓ D ₃ (hereinafter, the inverted signal is down arrow ↓
Is added to B of the logical product elements 302, 303, 304.

I ₀ , I ₁ , and I ₂ of the AND gate 201 are
They are connected to A of the logical product elements 304, 303 and 302, respectively. Further, the logical product outputs of the logical product elements 304, 303 and 302 are connected to O ₀ , O ₁ and O ₂ , respectively. The logical product elements 302, 303, 304 output the logical product of the inputs A and B, respectively. Therefore, if D ₃ = 0, the inverted D ₃ (the inverted signal is indicated by the downward arrow ↓).
Subjecting) is AND gate becomes ↓ D ₃ = 1 302,30
Since 1 is input to B of 3, 304, the logical product element 3
The outputs of 04, 303 and 302 are D ₀ , D ₁ and D _{2 respectively.}
And O ₀ , O ₁ and O ₂ respectively represent D ₀ , D ₁ and D ₂
Is output. On the other hand, if D ₃ = 1 then ↓ D ₃ = 0 and 0 is input to B of the logical product elements 302, 303, 304, so the outputs of the logical product elements 304, 303, 302 all become 0, 0 is output from O ₀ , O ₁ and O ₂ .
An input / output table of the AND gate 201 is shown together with FIG.

The output of the AND gate 201 is the adder 20.
5 and the AND gate 202. The signals output from O ₀ , O ₁ and O _{2 of the} AND gate 201 are D ₀ ′, D ₁ ′ and D ₂ ′, respectively. If D ₃ = 0, then D ₂ '
= D ₂ , D ₁ ′ = D ₁ , D ₀ ′ = D ₀ . Of the outputs of the AND gate 201, D ₂ 'is input to the enable E of the adder 205. Similar to the adder 204, the adder 205 adds the inputs A and B of the adder 205 and outputs the addition result when E = 1, and outputs the high impedance when E = 0 and outputs the addition result. do not do. Therefore, D ₂ '= 1
, Ie, if the MSB of the input is D ₂ , then adder 205 adds using inputs D ₀ ′, D ₁ ′, D ₂ ′,
Output the addition result. On the other hand, if D ₂ '= 0, the output of the adder 205 becomes high impedance and the addition result is not output.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₃ = 1, AND gate 201 D ₀ ', D _1', outputs the all D ₂ '0. Then, since D ₂ '= 0 is input to the enable E of the adder 205, the output of the adder 205 becomes high impedance and the addition result is not output.

D ₀ ′, D ₁ ′ and D ₂ ′ output from the AND gate 201 are also input to the AND gate 202. D ₂ ′ is input to C of the AND gate 202, and D ₀ ′ and D ₁ ′ are input to I ₀ and I ₁ of the AND gate 202, respectively. Similarly to the AND gate 201, the AND gate 202 also takes the logical product of the inversion of D ₂ ′ and the lower 2 bits D ₀ ′ and D ₁ ′, and outputs it to the adder 206 and the AND gate 203. That is, the AND gate 20
2, 'if = 0, O _0, respectively, from _{O 1 D 0' D 2,} D 1 ' , and also D _2' if = a 1, O _0, from O ₁ 0 adders 206 and Output to the AND gate 203.

This will be described with reference to the drawings. Figure 3
(B) is a configuration diagram showing a configuration of the AND gate 202, in which 305 is an inverter, and 306 and 307 are AND elements. The C of the AND gate 202 is connected to the inverter 305. Thus, inverter 305 outputs a 'inversion ↓ D ₂ of' D ₂ to B of AND gate 306 and 307.

I ₀ and I ₁ of the logical product gate 202 are connected to A of the logical product elements 307 and 306, respectively. Further, the logical product outputs of the logical product elements 307 and 306 are connected to O ₀ and O ₁ , respectively. AND elements 306, 30
7 outputs a logical product of inputs A and B, respectively. Therefore, if D ₂ '= 0, then ↓ D ₂ ' = 1 and the logical product element 3
Since the 06,307 of B 1 is inputted, respectively output D ₀ of AND gate 307 and 306 ', D _1' coincides with, O _0, respectively, from O ₁ is D ₀ ', D _1' Is output. On the contrary, if D ₂ '= 1, then ↓ D ₂ ' = 0 and 0 is input to B of the logical product elements 306 and 307, so that the outputs of the logical product elements 306 and 307 are all 0 and O ₀ , O ₁
Will output 0. An input / output table of the AND gate 202 is shown together with FIG.

The output of the AND gate 202 is the adder 20.
6 and the AND gate 203. The signals output from O ₀ and O ₁ of the AND gate 202 are D ₀ ″ and D ₁ ″, respectively. If D ₃ = 0 and D ₂ = 0,
D ₁ ″ = D ₁ and D ₀ ″ = D ₀ . AND gate 20
Of the two outputs, D ₁ ″ is input to the enable E of the adder 206. Similar to the adder 204 and the adder 205, the adder 206 adds the inputs A and B of the adder 206 and outputs the addition result when E = 1, and the output becomes high impedance when E = 0. Do not output the addition result. Therefore, if D ₁ ″ = 1, that is, if the input MSB is D ₁ , the adder 206 performs addition using the inputs D ₀ ″ and D ₁ ″, and outputs the addition result. On the other hand, D ₁ ″ =
If it is 0, the output of the adder 206 becomes high impedance and the addition result is not output.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₃ = 1, AND gate 201 D ₀ ', D _1', outputs the all D ₂ '0. Since D ₂ '= 0, the AND gate 202 outputs D ₀ ' and D ₁ 'as they are. That is, both D ₀ ″ and D ₁ ″ are 0. Then D ₁ ″ = 0
Is input to the enable E of the adder 206, the output of the adder 206 becomes high impedance and the addition result is not output.

The D ₀ ″ and D ₁ ″ output from the AND gate 202 are also input to the AND gate 203. D ₁ ″ goes to C of the AND gate 203, and D ₀ ″
Are input to I _{0 of the} AND gate 203, respectively.
Similarly to the logical product gates 201 and 202, the logical product gate 203 takes the logical product of the inversion of D ₁ ″ and the lower 1 bit D ₀ ″ and outputs the logical product to the 3-state output buffer 207 and the logical sum element 209. To do. That is, the AND gate 203
Outputs D ₀ ″ from O ₀ if D ₁ ″ = 0,
If D ₁ ″ = 1, O ₀ to 0 are output to the 3-state output buffer 207 and the OR element 209.

This will be described with reference to the drawings. Figure 3
(C) is a block diagram showing the configuration of the AND gate 203, where 308 is an inverter and 309 is an AND element.
C of the AND gate 203 is connected to the inverter 308. Thus, inverter 308 outputs D ₁ '' inverted ↓ D ₁ 'of the' to B of AND gate 309.

I _{0 of the} AND gate 203 is connected to A of the AND element 309. The logical product output of the logical product element 309 is connected to O ₀ . AND element 3
09 outputs the logical product of the inputs A and B. Therefore,
If D ₁ ″ = 0, ↓ D ₁ ″ = 1, and AND element 3
Since the 09 B 1 is inputted, the output of AND gate 309 'coincides with, from O ₀ D _0' D ₀ 'is output'. On the other hand, if D ₁ ″ = 1, ↓ D ₁ ″ = 0 and 0 is input to B of the logical product element 309, so the output of the logical product element 309 becomes 0, and ₀ from O 0. Is output. An input / output table of the AND gate 203 is shown together with FIG.

The output of the AND gate 203 is input to the 3-state output buffer 207 and the input a of the OR element 209. The signal output from O _{0 of the} AND gate 203 is D ₀ ′ ″. D ₃ = 0 and D ₂ = 0 and D ₁ = 0
Then, D ₀ ′ ″ = D ₀ . By the way, since the input data of the squaring circuit is not 0, the logical product element 208 outputs 0, and 0 is input to the input b of the logical sum element 209. Since the logical sum element 209 outputs the logical sum of the input a and the input b, the value output from the logical sum element 209 is the input a.
That is, it is equal to D ₀ '''. That is, if D ₀ ″ ″ = 0, 0 is output, and if D ₀ ″ ″ = 1, 1 is output. The output of the logical sum element 209 is the 3-state output buffer 20.
7 is input to enable E. The 3-state output buffer 207 outputs D ₀ ″ ″ which is an input when E = 1, and when E = 0, the output becomes high impedance and does not output the input. Therefore, if D ₀ ′ ″ = 1, that is, if the input MSB is D ₁ , then E = 1 and 3
The state output buffer 207 outputs 1 and D ₀ '''
= 0, that is, when the MSB of the input is other than D ₁ , E = 0 and the output of the 3-state output buffer 207 becomes high impedance and the input is not output.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₃ = 1, AND gate 201 D ₀ ', D _1', outputs the all D ₂ '0. Since D ₂ '= 0, the AND gate 202 outputs D ₀ ' and D ₁ 'as they are. That is, both D ₀ ″ and D ₁ ″ are 0. 'Since = 0, the AND gate 203 D _0' D ₁ 'outputs "as is, i.e. as D _0' '' = 0. Further, since the input of the squaring circuit is not 0, the logical product element 208 outputs 0. The logical sum element 209 is a logical product element 2 with D ₀ ″ ″ = 0.
The output of 08, that is, 0 which is the logical sum of 0 is output. Therefore, the enable E of the 3-state output buffer 207 becomes 0, the output becomes high impedance, and the input D ₀ ′ ″ is not output.

Next, the case where the input data of the squaring circuit is 0 will be described. That is, if the logical sum symbol is #,
D ₀ #D ₁ #D ₂ #D ₃ = 0. At this time, the logical product element 208 outputs 1 to the input b of the logical sum element 209. Further, since the enable E of each of the adders 204, 205, and 206 is 0, all outputs become high impedance and the addition result is not output. Further, since the output D ₀ ′ ″ = 0 of the AND gate 203, the inputs a of the 3-state output buffer 207 and the OR element 209 are both 0.

The logical sum element 209 calculates the logical sum of the output D ₀ ′ ″ of the logical product gate 203 input to the input a and the output of the logical product element 208 input to the input b. Input to enable E of 207. now,
Since the logical product element 208 outputs 1, the logical sum element 20
9 outputs 1 regardless of whether the output D ₀ ′ ″ of the AND gate 203 is 0 or 1 and outputs the 3-state output buffer 207.
1 is input to the enable E of the. Therefore, the 3-state output buffer 207 outputs the input D ₀ ″ ″ = 0 as the output of the squaring circuit.

As described above, if the MSB in the input data of the squaring circuit is D ₃ , that is, if D ₃ = 1 then only the adder 204 performs addition. If the MSB is D ₂ , that is, D ₃ = 0 and D ₂ = 1 then the adder 2
Only 05 adds. Similarly, if the MSB is D ₁ , ie, D ₃ = 0, D ₂ = 0 and D ₁ = 1 then only adder 206 will perform the addition. If the MSB is D ₀ , that is, D ₃ = 0, D ₂ = 0, D ₁ = 0 and D ₀ = 1 and the 3-state output buffer 207 is 1
Is output. That is, the AND gates 201, 202, 2
The 03 and 3-state output buffers 207 are input MSs.
It operates as a B value extraction circuit. If the input data of the squaring circuit is 0, the 3-state output buffer 207 outputs 0.

Next, the operation of the adder 204 when the MSB of the input of the squaring circuit is D ₃ , that is, D ₃ = 1 will be described with reference to the drawings. Since D ₃ = 1, the numerical value of the input data of the squaring circuit is 8 or more and 15 or less, and only the adder 204 outputs the addition result. FIG. 4A is a configuration diagram showing the configuration of the adder 204. As shown in FIG. 4A, the adder 204 is a 7-bit adder, and the input A has seven inputs A ₀ to A ₆ (A ₀ is the least significant digit). Similarly, input B is 7 inputs from B ₀ to B ₆ (B ₀ is the least significant digit)
There is.

As shown in FIG. 4A, D ₃ = 1 is input to A ₆ to the input A of the adder 204, and 0 is input to the 6 inputs A ₀ to A _5. It That is, the adder 2
To the input A of 04, the MSB value of 8 square = 64 is input. On the other hand, the input B of the adder 204 has B ₆ ,
D ₂ , D ₁ , and D ₀ are input to B ₅ and B ₄ , respectively, and ₀ is input to the four inputs B ₀ to B ₃ . That is,
A value obtained by subtracting the MSB value of 8 from the input data of the squaring circuit by 2 × 8 = 16 is input to the input B of the adder 204. 64 input to the input A in the adder 204
And 16 times the value obtained by subtracting 8 from the input data input to the input B are added and output as the output of the squaring circuit. Therefore, the output y of the squaring circuit is the MSB value x of the input x of the squaring circuit.
_1, expressed as follows by using the LSP value x ₂ minus x ₁ from x. y = x ₁ ² + 2x ₁ x ₂ (6)

The operation of the adder 205 when the MSB of the input of the squaring circuit is D ₂ , that is, D ₃ = 0 and D ₂ = 1 will be described with reference to the drawings. Since D ₃ = 0 and D ₂ = 1 are satisfied, the numerical value of the input data of the squaring circuit is 4 or more and 7 or less, and the adder 2
Only 05 outputs the addition result. FIG. 4B shows an adder 2
It is a block diagram which shows the structure of 05. As shown in FIG. 4B, the adder 205 is a 5-bit adder, and the input A has five inputs A ₀ to A ₄ (A ₀ is the least significant digit). Similarly, input B is five inputs B ₀ to B ₄ (B
₀ is the least significant digit).

As shown in FIG. 4B, D ₂ = 1 is input to A ₄ to the input A of the adder 205, and 0 is input to the four inputs A ₀ to A _3. It That is, the adder 2
To the input A of 05, the MSB value of 4 squared = 16 is input. On the other hand, the input B of the adder 205 has B ₄ and B ₃
D ₁ and D ₀ are input to each of them, and ₀ is input to the three inputs B ₀ to B ₂ . That is, the input B of the adder 205 receives a value obtained by subtracting the MSB value of 4 from the input data of the squaring circuit, which is 2 × 4 = 8 times. In the adder 205, 16 input to the input A and 8 times the value obtained by subtracting 4 from the input data input to the input B are added, and 2 is added.
It outputs as the output of the squaring circuit. Therefore, the output y of the squaring circuit
Can be expressed as follows using the MSB value x ₁ of the input x of the squaring circuit and the LSP value x ₂ obtained by subtracting x ₁ from x. y = x ₁ ² + 2x ₁ x ₂ (6)

The adder 206 when the MSB of the input of the squaring circuit is D ₁ , that is, D ₃ = 0, D ₂ = 0 and D ₁ = 1
The operation of will be described with reference to the drawings. Since D ₃ = 0, D ₂ = 0 and D ₁ = 1 are given, the numerical value of the input data of the squaring circuit is 2 or 3, and only the adder 206 outputs the addition result. FIG. 4C is a configuration diagram showing the configuration of the adder 206. As shown in FIG. 4C, the adder 206 is a 3-bit adder, and the input A has three inputs A ₀ to A ₂ (A ₀ is the least significant digit). Similarly, inputs B are B ₀ to B
_There are 3 inputs up to ₂ (B ₀ is the least significant digit).

As shown in FIG. 4C, D ₁ = 1 is input to A ₂ to the input A of the adder 206, and ₀ is input to A ₀ and A _1.
Is entered. That is, the input A of the adder 206 is
The MSB value 2 squared = 4 is input. On the other hand, to the input B of the adder 206, D ₀ is input to B ₂ and B ₀ and B ₁
Is input to 0. That is, the input B of the adder 206
A value obtained by subtracting 2 which is the MSB value from the input data of the squaring circuit is multiplied by 2 × 2 = 4 is input to the. Adder 20
In 6, the 4 input to the input A and 4 times the value obtained by subtracting 2 from the input data input to the input B are added and output as the output of the squaring circuit. Therefore, the output y of the squaring circuit is the LSB obtained by subtracting x ₁ from the MSB value x ₁ of the input x of the squaring circuit.
It can be expressed as follows using the P value x ₂ . y = x ₁ ² + 2x ₁ x ₂ (6)

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. In this case, since D ₃ = 1, only the adder 204 outputs the addition result. 8 ² = 64 is input to the input A of the adder 204. Also, the input B of the adder 204 is 16 times 11-8 = 3,
That is, 48 is input. Therefore, the adder 204 has 64
+ 48 = 112 is output as the output of the squaring circuit.

As described above, M of the input data of the squaring circuit is
The SB value is extracted, and the square of the MSB value and the multiple of the lower bits according to the MSB value are added by an adder to obtain the square value. Can be obtained.

Third Embodiment In the second embodiment, an adder is provided for each input of the AND gate that operates as the MSB value extraction circuit, and any one adder or three-state output buffer outputs the squared result for one input data. Although configured, this is not necessary. For example, as shown in FIG. 5, a configuration may be used in which a 3-state output buffer gate is used for the input of the adder. Generally, the number of gates in the three-state buffer is smaller than that in the adder. Therefore, the circuit scale can be reduced by using the three-state buffer gate instead of the adder.

Also in the third embodiment, as in the first embodiment, by setting y = x ² to x = x ₁ + x ₂ , y≈x ₁ ²
+ 2x ₁ x ₂ and obtaining the value approximating. Hereinafter, as an example, a case where the number of input bits is 4 bits will be described with reference to the drawings. FIG. 5 is a configuration diagram showing the configuration of the squaring circuit according to the third embodiment.
02, 503, and 504 are 3-state output buffer gates, and 505 is an adder. It should be noted that the same or corresponding parts as those in FIG.

Next, the operation of the circuit will be described. As in the case of the second embodiment, in FIG. 5, the 4-bit signal input to the squaring circuit is D ₀ , D ₁ , D ₂ , in order from the lower bit.
Let it be D ₃ . At this time, D _i ε {0,1}. First, 2
A case where the data input to the squaring circuit is not 0 will be described.

As in the second embodiment, the 4-bit digital signal input to the squaring circuit is input to the AND gate 201. In the AND gate 201, the inversion of D ₃
The logical product with the lower 3 bits is calculated, and the logical product gate 202
Output to. In the logical product gate 202, the logical product of the inversion of D ₂ 'and the lower 2 bits is calculated, and the logical product gate 2
Output to 03. The logical product gate 203 takes the logical product of the inversion of D ₁ ″ and D ₀ and outputs the logical product to the 3-state output buffer gate 304. That is, as in the second embodiment, the AND gates 201, 202 and 203 operate as an MSB value extraction circuit for squaring circuit input data.

The operation of the 3-state output buffer gate 501 will be described. The input data of the squaring circuit is input to the 3-state output buffer gate 501 as well as the AND gate 201. D ₀ , D ₁ , D ₂ , and D ₃ are input to I ₀ , I ₁ , I ₂ , and I ₃ of the 3-state output buffer gate 501, respectively. The 3-state output buffer gate 501 has
A 0 is input to input G ₁ to zero the unused input of adder 505. Specifically, G ₁ is grounded. In addition, D ₃ of the input 4-bit input data is 3
It is also input to the enable E of the state output buffer gate 501. The 3-state output buffer gate 501 is E
= D ₃ = 1, the input is output as it is, and E = D ₃ = 0, the output is high impedance and the input is not output. Therefore, the 3-state output buffer gate 501 is
_{If 3} is 1, D ₀ , D ₁ , D ₂ , D ₃ , and G ₁ (= 0) are output to the adder 505, and if D ₃ is 0, the output becomes high impedance and the input D ₀ , D ₁ , D ₂ , D ₃ , G ₁
(= 0) is not output to the adder 505.

This will be described with reference to the drawings. Figure 6
(A) is a configuration diagram showing a configuration of a 3-state output buffer gate 501, which includes 601, 602, 603, 604,
Reference numeral 605 is a 3-state output buffer. E of the 3-state output buffer gate 501 is connected to the enable E of the 3-state output buffers 601, 602, 603, 604, 605. 3-state output buffer gate 50
G ₁ , I ₀ , I ₁ , I ₂ , and I ₃ of ₁ are 3-state output buffers 605, 604, 603, 602, and 601 respectively.
It is connected to the. Therefore 605, 604, 603, 6
02, 601, 0, D ₀ , D ₁ , D ₂ , D ₃ are input, respectively. The three-state output buffers 605, 604, and 60 are provided for O _g , O ₀ , O ₁ , O ₂ , and O ₃ , respectively.
The outputs of 3, 602 and 601 are connected.

Three-state output buffers 601, 602,
D ₃ is input to the enable E of 603, 604 and 605, and if E = D ₃ = 1 then the 3-state output buffer 60
5, 604, 603, 602 and 601 are each G ₁
(= 0), D ₀ , D ₁ , D ₂ , D ₃ are output, and E = D ₃ = 0
If so, 3-state output buffers 605, 604, 60
All the outputs of 3, 602, and 601 become high impedance and do not output a signal. 3-state output buffer 5
The input / output table of 01 is shown together with FIG.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₃ = 1, the 3-state output buffer gate 501 has D ₀ , D ₁ ,
D ₂ , D ₃ , and G ₁ (= 0) are output to the adder 505.

Next, the 3-state output buffer gate 50
The operation of No. 2 will be described. D ₀ ′, D ₁ ′ and D ₂ ′ output from the logical product gate 201 are the logical product gate 202,
It is also input to the 3-state output buffer gate 502.
D ₀ ′, D ₁ ′ and D ₂ ′ are input to I ₀ , I ₁ and I ₂ of the 3-state output buffer gate 502, respectively. To the 3-state output buffer gate 502, 0 is input to the input G ₂ in order to set the unused input of the adder 505 to 0. Specifically, G ₂ is grounded. D ₂ 'of the inputs of the 3-state output buffer gate 502 is also input to the enable E of the 3-state output buffer gate 502. The 3-state output buffer gate 502 is E =
If D ₂ '= 1, the input is output as it is, E = D ₂ ' = 0
Then, the output becomes high impedance and the input is not output. Therefore, the 3-state output buffer gate 502 is
If D ₂ ′ is 1, D ₀ ′, D ₁ ′, D ₂ ′ and G ₂ (= 0) are output to the adder 505, and if D ₂ ′ is 0, the output becomes high impedance and the input D ₀ , D ₁ , D ₂ ,
G ₂ (= 0) is not output to the adder 505.

This will be described with reference to the drawings. Figure 6
(B) is a configuration diagram showing a configuration of the 3-state output buffer gate 502, and 606, 607, 608, 609 are 3-state output buffers. E of the 3-state output buffer gate 502 is a 3-state output buffer 60.
Connected to enable E of 6, 607, 608, 609. G ₂ , I _{0 of} the 3-state output buffer gate 502,
I ₁ and I ₂ are 3-state output buffers 609 and
It is connected to 608, 607, and 606. Therefore 60
9, 608, 607, and 606 have 0,
D ₀ ′, D ₁ ′ and D ₂ ′ are input. Also, O _g , O ₀ ,
A 3-state output buffer 60 is provided for each of O ₁ and O _2.
The outputs of 9, 608, 607, and 606 are connected.

Three-state output buffers 606, 607,
D ₂ 'is input to enable E of 608 and 609,
If E = D ₂ '= 1, 3-state output buffer 609,
608, 607 and 606 are G ₂ (= 0) and
Outputs D ₀ ', D ₁ ' and D ₂ 'and 3 if E = D ₂ ' = 0
State output buffers 609, 608, 607, 606
Outputs of all become high impedance and do not output signals. Input / output table of 3-state output buffer 502
It shows with FIG.6 (b).

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₃ = 1, AND gate 201 D ₀ ', D _1', outputs the all D ₂ '0. Since D ₂ '= 0, 0 is input to the enable E of the 3-state output buffer gate 502. Therefore, the output of the 3-state output buffer gate 502 becomes high impedance, and the inputs D ₀ ′, D ₁ ′, D ₂ ′ and G ₂ (= 0) are not output to the adder 505.

Next, the 3-state output buffer gate 50
The operation of No. 3 will be described. D ₀ ″ and D ₁ ″ output from the AND gate 202 are input to the 3-state output buffer gate 503 as well as the AND gate 203.
D ₀ ″ and D ₁ ″ are 3-state output buffer gates 50
3 are input to I ₀ and I ₁ , respectively. To the 3-state output buffer gate 503, 0 is input to the input G ₃ in order to set the unused input of the adder 505 to 0. Specifically, G ₃ is grounded. Further, D ₁ ″ of the inputs of the 3-state output buffer gate 503 is also input to the enable E of the 3-state output buffer gate 503. The 3-state output buffer gate 503 has E =
If D ₁ ″ = 1, the input is output as it is, E = D ₁ ″
If = 0, the output becomes high impedance and the input is not output. Therefore, the 3-state output buffer gate 503
Is, D ₁ '' is 1 if _{D 0 '', D 1 '} ', G 3 (= 0)
Is output to the adder 505, and if D ₁ ″ is 0, the output becomes high impedance and the input D ₀ ″,
D ₁ ″ and G ₃ (= 0) are not output to the adder 505.

This will be described with reference to the drawings. Figure 6
FIG. 6C is a configuration diagram showing the configuration of the 3-state output buffer gate 503, and 610, 611, and 612 are 3-state output buffers. E of the 3-state output buffer gate 503 is a 3-state output buffer 610, 61.
Connected to enable E of 1,612. G ₃ , I ₀ , and I ₁ of the 3-state output buffer gate 503 are connected to the 3-state output buffers 612, 611, and 610, respectively. Therefore, 0, D ₀ ″, and D ₁ ″ are input to 612, 611, and 610, respectively. Also, O _g ,
A three-state output buffer 61 is provided for each of O ₀ and O _1.
The outputs of 2, 611 and 610 are connected.

Three-state output buffers 610 and 611,
D ₁ ″ is input to the enable E of 612, and E =
If D ₁ ″ = 1, 3-state output buffers 612, 6
11, 610 are G ₃ (= 0), D ₀ ″,
D ₁ ″ is output, and if E = D ₁ ″ = 0, the outputs of the three-state output buffers 610, 611, and 612 all become high impedance and no signal is output. An input / output table of the 3-state output buffer 503 is shown with FIG.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₃ = 1, AND gate 201 D ₀ ', D _1', outputs the all D ₂ '0. 'Because it is = 0, the AND gate 202 D _0' D _2, 'as it is, i.e. D _0' D ₁ ', and it outputs the 0 both D _1' '. D ₁ ″ =
Since it is 0, 0 is input to the enable E of the 3-state output buffer gate 503. Therefore, the output of the 3-state output buffer gate 503 becomes high impedance, and the inputs D ₀ ″, D ₁ ″ and G ₃ (= 0) are not output to the adder 505.

Next, the 3-state output buffer gate 50
The operation of No. 4 will be described. D ₀ ′ ″ output from the AND gate 203 is a 3-state output buffer gate 504.
Entered in. D ₀ ″ ″ is input to I ₀ of the 3-state output buffer gate 504. The 3-state output buffer gate 504 has an input 0 input to G ₄ to zero the unused input of adder 505. Specifically grounds the G _4. Further, D ₀ ″ ″ input to the 3-state output buffer gate 504 is the OR element 20.
It is also input to the input a of 9. By the way, since the input of the squaring circuit is not 0, the logical product element 208 outputs 0, and 0 is input to the input b of the logical sum element 209. Since the logical sum element 209 outputs the logical sum of the input a and the input b, the value output from the logical sum element 209 is equal to D ₀ ″ ″. That is, if D ₀ ′ ″ = 0, 0 is output, and D ₀ =
If it is 1, 1 is output. The output of the logical sum element 209 is 3
It is input to the enable E of the state output buffer gate 504. The 3-state output buffer gate 504 is E =
If it is 1, the input is output as it is, and if E = 0, the output becomes high impedance and the input is not output. Therefore,
The 3-state output buffer gate 504 has D ₀ ′ ″ =
If 1, D ₀ ″ ″, G ₄ (= 0) is output to the adder 505, and if D ₀ ″ ″ = 0, the output becomes high impedance and the input D ₀ , G ₄ ( ₀ = 0) is added to the adder 505
Do not output to.

This will be described with reference to the drawings. Figure 6
FIG. 6D is a configuration diagram showing the configuration of the 3-state output buffer gate 504, and 613 and 614 are 3-state output buffers. E of the 3-state output buffer gate 504 is connected to the enable E of the 3-state output buffers 613 and 614. 3-state output buffer gate 5
G ₄ and I ₀ of 04 are 3-state output buffers 6 respectively.
14 and 613. Therefore, 614 and 613
0 and D ₀ ′ ″ are input to the respective terminals. Also,
A three-state output buffer 61 is provided for each of O _g and O _0.
The outputs of 4, 613 are connected.

The output of the logical sum element 209 is input to the enable E of the three-state output buffers 613 and 614,
If E = 1, 3-state output buffers 614 and 613
Outputs G ₄ (= 0) and D ₀ ''', respectively, and E = 0
In that case, all outputs of the three-state output buffers 613 and 614 become high impedance and no signal is output.
The input / output table of the 3-state output buffer 504 is shown in FIG.
Shown with (d).

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since a D ₃ = 1, the AND gate 201 is outputted as 0 all the _{D 0, D 1, D 2} , Therefore since it is D ₂ = 0, the AND gate 202 as the D _0, D ₁ That is, both D ₀ and D ₁ are output as 0. Since addition is D ₁ = 0, the AND gate 203 outputs a D ₀ as is, i.e. as D ₀ = 0. Then, 0 is input to the input a of the logical sum element 209. At this time, the logical sum element 209 is a logical sum of D ₀ = 0 and 0 input from the logical product element 208, that is, 0.
Is input to the enable E of the 3-state output buffer gate 504. Therefore, 3-state output buffer gate 5
The output of 04 becomes high impedance, and the inputs D ₀ and G ₄ (= 0) are not output to the adder 505.

Next, the operation of the adder 505 will be described with reference to the drawings. FIG. 7 shows a 3-state output buffer gate 50.
FIG. 6 is a diagram for explaining the connection between 1, 502, 503, 504 and the adder 505, and the 3-state output buffer gates 501, 502, 503, 504 and the adder 505 in FIG.
FIG. 3 is a diagram showing in detail, including input / output connections. As shown in FIG. 7, the adder 505 is a 7-bit adder, and the input A is seven inputs A ₀ to A ₆ (A ₀ is the least significant digit).
There is. Similarly, the input B has seven inputs B ₀ to B ₆ (B ₀ is the least significant digit). Of the input A, A ₅ , A ₃ , A ₁
Is always 0. Specifically, A ₅ , A ₃ , and A ₁ are grounded. Similarly, of inputs B, the inputs of B ₁ and B ₀ are always 0
And Specifically, B ₁ and B ₀ are grounded.

Three-state output buffer gates 501, 5
The connections of the outputs of 02, 503, and 504 and the adder 505 will be described. Of the outputs of the 3-state output buffer gate 501, O ₃ is connected to A _{6 of the} adder 505. Also O ₂
Is connected to B ₆ , O ₁ is connected to B ₅ , and O ₀ is connected to B ₄ . Further, the O _g of the 3-state output buffer gate 501 is connected to the input of the other adder 505. Next, of the outputs of the 3-state output buffer gate 502, O ₂ is connected to A _{4 of the} adder 505. O ₁ is connected to B ₄ , and O ₀ is connected to B ₃ . Also, other adders 5
The O _g of the 3-state output buffer gate 502 is connected to the input of 05. Next, of the outputs of the 3-state output buffer gate 503, O ₁ is connected to A _{2 of the} adder 505. Also, O ₀ is connected to B ₂ . Further, the O _g of the 3-state output buffer gate 503 is connected to the input of the other adder 505. Next, of the outputs of the 3-state output buffer gate 504, O ₀ is connected to A _{0 of the} adder 505. Further, O _g of the 3-state output buffer gate 504 is connected to the input of the other adder 505.

Next, the operation of the adder 505 when the MSB of the input of the squaring circuit is D ₃ , that is, D ₃ = 1 will be described. At this time, the numerical value of the input data of the squaring circuit is 8 or more and 15
Below, only the 3-state output buffer gate 501 outputs its input to the adder 505. To the input A of the adder 505, D ₃ output from the 3-state output buffer gate 501 is input to A ₆ . A ₁ , A ₃ , and A ₅ are grounded, and the input is 0. The A _0, since the G ₁ of A _2, A ₄ is 3-state output buffer gate 501 (= 0) is input, the input is zero. That is, the adder 505
8 ² = 64 is input to the input A of. On the other hand, the input B of the adder 505 is connected to B ₆ , B ₅ , and B ₄ by D ₂ and D, respectively.
₁ and D ₀ are input. B ₀ and B ₁ are grounded and the input is 0. Further, since the output G ₁ (= 0) of the 3-state output buffer gate 501 is input to B ₂ and B ₃ , the input is 0. That is, since B ₀ , B ₁ , B ₂ and B ₃ are 0, 8 is subtracted from the input data of the square circuit represented by D ₂ , D ₁ and D ₀ to the input B of the adder 505. Value of 16
Double is entered. The adder 505 is input to the input A 6
4 and 16 times the value obtained by subtracting 8 from the input data input to the input B are added and output as the output of the squaring circuit.

Next, the operation of the adder 505 when the MSB of the input of the squaring circuit is D ₂ , that is, D ₃ = 0 and D ₂ = 1 will be described. At this time, the numerical value of the input data of the squaring circuit is 4
The above is 7 or less, and the 3-state output buffer gate 50
Only 2 outputs its input to the adder 505. Adder 505
Input A has a 3-state output buffer gate 5 on A ₄
D ₂ output from 02 is input. A ₁ , A ₃ , and A ₅ are grounded, and the input is 0. Also, A ₀ , A ₂ , A ₆
Is the output G ₂ of the 3-state output buffer gate 502 (=
0) is input, so the input is 0. That is, 4 ² = 16 is input to the input A of the adder 505. On the other hand, the input B of the adder 505 has B ₄ and B ₃ respectively having D
₁ and D ₀ are input. B ₀ and B ₁ are grounded and the input is 0. Further, since the output G ₂ (= 0) of the 3-state output buffer gate 502 is input to B ₂ , B ₅ , and B ₆ , the input is 0. That is, since B ₀ , B ₁ and B ₂ are 0, the input B of the adder 505 is 8 times the value obtained by subtracting 4 from the input data of the squaring circuit represented by D ₁ and D _0. Is entered. The adder 505 is input to the input A 16
And 8 times the value obtained by subtracting 4 from the input data input to the input B are added and output as the output of the squaring circuit.

Next, the operation of the adder 505 when the MSB of the input of the squaring circuit is D ₁ , that is, D ₃ = 0, D ₂ = 0 and D ₁ = 1 will be described. At this time, the numerical value of the input data of the squaring circuit is 2 or 3, and only the 3-state output buffer gate 503 outputs the input to the adder 505.
To the input A of the adder 505, D ₁ output from the 3-state output buffer gate 503 is input to A ₂ .
A ₁ , A ₃ , and A ₅ are grounded, and the input is 0. A ₀ , A ₄ , and A ₆ are 3-state output buffer gates 50.
Since the output G ₃ (= 0) of ₃ is input, the input is 0. That is, 2 ² = 4 is input to the input A of the adder 505. On the other hand, to the input B of the adder 505, D ₀ is input to B ₂ . B ₀ and B ₁ are grounded and the input is 0. Further, since the output G ₃ (= 0) of the 3-state output buffer gate 503 is input to B ₃ , B ₄ , B ₅ , and B ₆ , the input is 0. That is, since B ₀ and B ₁ are 0, four times the value obtained by subtracting 2 from the input data of the squaring circuit represented by D ₀ is input to the input B of the adder 505. The adder 505 adds 4 input to the input A and 4 times the value obtained by subtracting 2 from the input data input to the input B, and outputs the result as the output of the squaring circuit.

As an example, the input of the squaring circuit is 1011.
The case of (11) will be described. Since D ₀ = 1 in this case, only the 3-state output buffer gate 501 inputs to the adder 505. The input A of the adder 505 is
8 ² = 64 is input. Also, the input B of the adder 505
Is input 16 times 11-8 = 3, that is, 48. Therefore, the adder 505 outputs 64 + 48 = 112 as the output of the squaring circuit.

As described above, M of the input data of the squaring circuit is
It is possible to reduce the number of adders by extracting SB and calculating the square value by adding the square of MSB and the multiple of the lower bit according to MSB by the adder. Furthermore, by reducing the number of adders by using the 3-state output buffer gate, it is possible to obtain a square circuit having a small circuit scale.

Fourth Embodiment In the first embodiment, the MSB value of the input data is obtained using the MSB value extraction circuit, and the input data is divided into the MSB value and the LSP value to perform the calculation. In the fourth embodiment, the MSB value is further extracted from the LSP value and the MSB value is extracted.
Value and LSP value are divided and calculated and added,
Reduce the output error.

The value obtained by the squaring circuit in the fourth embodiment will be described. The square circuit is the numerical value 2 of the input data.
This is a circuit that outputs the data of the power value. When the input data is x and the output data is y, the relationship between x and y can be expressed by the following equation. y = x ² (1) In the above equation, x is represented by the sum of x ₁ and x ₂ . That is, x = x ₁ + x ₂ (2) holds. By substituting the equation (2), the equation (1) can be expressed as follows. y = (x ₁ + x ₂ ) ² = x ₁ ² + 2x ₁ x ₂ + x ₂ ² (3) In the first embodiment, x _{1 and} x ₂ are satisfied so that x ₁ > x _2.
By selecting, the value ignoring x ₂ ² in the formula (3) was obtained. In the fourth embodiment, x ₁ so that x ₁ > x ₂ holds.
Select ₁ and x _2, further denote the x ₂ by the sum of x ₃ and x _4. That is, x ₂ = x ₃ + x ₄ (7) holds. By substituting the equation (7), the equation (3) can be expressed as follows. y = x ₁ ² + 2x ₁ x ₂ + x ₂ ² = x ₁ ² + 2x ₁ x ₂ + x ₃ ² + 2x ₃ x ₄ + x ₄ ² (3) 'Here, if x ₃ > x ₄ holds, then 2 The following relation holds between the multiplied x ₃ ² and x ₄ ² . x ₃ ² >> x ₄ ² (8) Using the relationship of the expression (8), the expression (3) ′ can be transformed as follows. _{^{y = x 1 2 + 2x 1}} x 2 + x 3 2 + 2x 3 x 4 + x 4 2 ≒ x 1 2 + 2x 1 x 2 + x 3 2 + 2x 3 x 4 (9) i.e., x _3> x ₄ so holds x ₃ And x ₄ are selected, the contribution of x ₄ ² to the squared output data y can be ignored. In the fourth embodiment, the right side of equation (9) is obtained as the output of the squaring circuit. The fourth embodiment will be described below with reference to the drawings. FIG. 8 is a configuration diagram showing the configuration of the squaring circuit according to the fourth embodiment. In FIG. 8, 801 is an MS.
A B value extraction circuit, 802 is a left bit shift circuit, 803 is an adder, 804 is a left bit shift circuit, and 805 is an adder. Further, the same or corresponding portions as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Next, the operation of the circuit will be described. In FIG. 8, as in the first embodiment, when digital input data is input to the squaring circuit, it is input to the MSB value extraction circuit 101 and the MSB value is extracted. The numerical value of the input data x of the squaring circuit is 2 ^m ≤x≤2 ^{m + 1} -1 (m is a non-negative integer)
, The m-th bit is the MSB. In this case, the MSB value extraction circuit 101 outputs 2 where the m-th bit is 1.
Extract and output ^m . Hereinafter, 2 ^m that is the MSB value of the input x is x ₁ , and the LSP value x−2 ^{m obtained} by subtracting 2 ^m from x, that is, x−x ₁ is x ₂ . That is, the following relationship holds between x, x ₁ and x ₂ . x = x ₁ + x ₂ (6)

As an example, consider the case of input data x = 14. When expressed in binary, 14 is 1110 (14). x is the MSB 1000 (8) and the input data 1
L obtained by subtracting the MSB value of 1000 (8) from 110 (14)
The SP value can be divided into 110 (6). The MSB value extraction circuit 101 extracts and outputs 1000 (8) in which the third bit is 1.

The MSB value extraction circuit 101 outputs x ₁ that is the MSB value of the input data x, that is, 2 ^m . The x ₁ output from the MSB value extraction circuit 101 is input to the left bit shift circuit 102. Further, x ₁ is also input to the shift input S of the left bit shift circuit 102. The x ₁ input to the left bit shift circuit 102 is left bit-shifted by the digit designated by the shift input S. M for shift input S
Since x ₁ of which the 1st bit is 1 is input, x ₁ is left-shifted by m bits to output x ₁ ′. Here, x ₁ 'is a value obtained by shifting 2 ^m by m bits, so 2 ^2m
be equivalent to. That is, x ₁ ′ = x ₁ ² . The left bit shift circuit 102 squares x ₁ or 2 ^m and outputs x ₁ ² or 2 ^2m to the adder 805.

The operation of the left bit shift circuit 102 when the input data x = 14 will be described. MSB value extraction circuit 10
10 which is the MSB value of the input data x output from 1
00 (8) is left bit-shifted by 3 bits in the left bit shift circuit 102. Where 1000 (8) is 3
Since only the 1st bit is 1, a 3-bit shift of 1000 (8) is equivalent to a square operation. Bit-shifted value 1
000000 (64) is input to the adder 805 as the output of the left bit shift circuit 102.

The MSB value x _{1 of the} input data x output from the MSB value extraction circuit 101, that is, 2 ^m, is also input to the adder 103. The adder 103 subtracts x ₁ from the input data x and outputs x−x _1, that is, the LSP value x ₂ to the left bit shift circuit 104.

Adder 103 when input data x = 14
The operation of will be described. The adder 103 is 1 which is the MSB value of the input data x output from the MSB value extraction circuit 101.
000 (8) is subtracted from the input data x = 1110 (14), and 110 (6), which is the LSP value of the input data x, is output to the left bit shift circuit 104.

The left bit shift circuit 104 includes an adder 1
The LSP value x ₂ of the input data x, which is the output of 03, is input. In addition, the shift input S of the left bit shift circuit 104
X ₁ which is the MSB value of the input data x output from the MSB value extraction circuit 101 is input to the. The x ₂ input to the left bit shift circuit 104 is left bit-shifted by a digit obtained by adding 1 to the value designated by the shift input S. Since x ₁ with the m-th bit being 1 is input to the shift input S, x ₂ is shifted to the left by (m + 1) bits. Here, a left m-bit shift corresponds to x ₁ times, and a 1-bit shift corresponds to 2 times. That is, the left (m + 1) bit shift of x2 in the left bit shift circuit 104 is equivalent to the operation of deriving 2x ₁ x ₂ . The left bit shift circuit 104 outputs ₂ × ₁ × ₂ to the adder 805.

The operation of the left bit shift circuit 104 when the input data x = 14 will be described. 110 (6), which is the LSP value of the input data x output from the adder 103, is
It is bit-shifted by 3 + 1 = 4 bits. Where 4
Bit shift is equal to 24 = 16 times operation, 2 × x ₁
(8) × x ₂ (6) = 96 is derived. The bit-shifted value is 1100000 (96), which is output to the adder 105 as the output of the left bit shift circuit 104.

Input data x output from the adder 103
The LSP value x _{2 of} is also input to the MSB value extraction circuit 801, and the MSB value is extracted. LSP value x of input data x
₂ numbers are ^{2 n ≦ x ≦ 2 n +} 1 -1 (n is a nonnegative integer, m
> N), the nth bit is the MSB.
In this case, the MSB value extraction circuit 801 extracts and outputs 2 ^{n in} which the nth bit is 1. Below, L of input data x
SP value is a MSB value of x ₂ and 2 ⁿ to x _3, x having from x ₂ minus 2 ⁿ ₂ -2 ⁿ other words x ₂ -x ₃ and x _4. That is, the following relationship holds among x ₂ , x ₃ , and x ₄ . x ₂ = x ₃ + x ₄ (7)

The operation of the MSB value extraction circuit 801 when the input data x = 14 will be described. The LSP value 110 (6) of the input data x is the MSB value 100 (4).
And LSP value 1 obtained by subtracting 100 (4) from 110 (6)
It can be divided into 0 (2). MSB value extraction circuit 80
1 outputs 100 (4) in which the second bit is 1 and outputs it.

The MSB value extraction circuit 801 outputs x ₃ which is the MSB value of x ₂ , that is, 2 ⁿ . MSB value extraction circuit 8
The x ₃ output from 01 is input to the left bit shift circuit 802. Further, x ₃ is also input to the shift input S of the left bit shift circuit 802. Left bit shift circuit 80
The x ₃ input to 2 is left bit-shifted by the digit specified by the shift input S. Since x ₃ having the n-th bit of 1 is input to the shift input S, x ₃ is left-bit shifted by n bits and outputs x ₃ ′. Here, x ₃ 'is equal to 2 ^{2n because} it is a value obtained by shifting 2 ⁿ left n bits. I.e. x ₃ '= x ₃ 2. The left bit shift circuit 802 squares x ₃ or 2 ⁿ to obtain x ₃ ² or 2 ²ⁿ
Is output to the adder 805.

The operation of the left bit shift circuit 802 when the input data x = 14 will be described. MSB value extraction circuit 80
MS of LSP value x ₂ of input data x output from 1
The B value 100 (4) is the left bit shift circuit 802.
Is shifted left by 2 bits. Where 100
In (4), only the second bit is 1, so 100 (4)
The left 2 bit shift of is equal to the square operation. The bit-shifted output 10000 (16) is input to the adder 805 as the output of the left bit shift circuit 802.

X output from the MSB value extraction circuit 801
The MSB value of ₂ that is x _3, that is, 2 ^n, is also input to the adder 803. The adder 803 the x ₃ subtracts from the LSP value x ₂ of the input data x, and outputs a x ₂ -x ₃ i.e. x ₄ left bit shift circuit 804.

Adder 803 when input data x = 14
The operation of will be described. The adder 803 outputs the MSB value of x ₂ output from the MSB value extraction circuit 801, which is 100.
(4) is subtracted from 110 (6) which is the input of the adder 603, and 10 (2) which is the LSP value of x ₂ is output to the left bit shift circuit 804.

The left bit shift circuit 804 includes an adder 8
The LSP value x _{4 of} x ₂ which is the output of 03 is input. Further, the shift input S of the left bit shift circuit 804 has M
X ₃ which is the MSB value of x ₂ output from the SB value extraction circuit 801 is input. The x ₄ input to the left bit shift circuit 804 is left bit shifted by a digit obtained by adding 1 to the value designated by the shift input S. N for shift input S
Since x ₃ of which the 1st bit is 1 is input, x ₄ is (n +
1) Left bit is shifted by 1 bit. The left n-bit shift corresponds to x ₃ times, and the 1-bit shift corresponds to 2 times. That is, the (n + 1) -bit shift of x ₄ in the left bit shift circuit 804 is equivalent to the operation of deriving 2x ₃ x ₄ . Left bit shift circuit 804, 2x ₃ x ₄
Is output to the adder 805.

The operation of the left bit shift circuit 804 when the input data x = 14 will be described. 10 (2), which is the LSP value of x ₂ output from the adder 803, is 2 + 1 = 3.
Only bits are bit-shifted. Here, 3-bit shift is equivalent to 2 ³ = 8 times operation, 2 × x ₃ (4) × x
₄ (2) = 16 is derived. The value left-shifted is 10000 (16), and the left-bit shift circuit 80
4 is output to the adder 805.

In the adder 805, the left bit shift circuit 1
The x ₁ ² and 2x ₁ x ₂ and 2x ₃ x ₄ output from x ₃ ² and the left bit shift circuit 804 which is output from the left bit shift circuit 802 which is output from the left bit shift circuit 104 which is output from the 02 Add and output as the output of the squaring circuit. When input data x = 14, 1000000 (6
4), 1100000 (96), 10000 (16) and 10000 (16) are added to obtain 11,000,000
(192) is output.

FIG . 20 shows a graph of the input / output of the squaring circuit. The dotted line is the ideal value, the solid line is the input / output of the squaring circuit in the fourth embodiment, and the alternate long and short dash line is the input / output of the squaring circuit in the first embodiment. It can be seen that the fourth embodiment has smaller output approximation error.

As described above, the input data of the squaring circuit is M
The SB value and the LSP value are divided, a predetermined left bit shift operation is performed for each to obtain a partial product, and the MSP value and the LSP value are similarly calculated for the LSP value.
By dividing into values, performing a predetermined left bit shift operation for each to obtain partial products, and adding these four partial products to obtain the squared value, the number of adders can be made smaller than before. By reducing the number, it is possible to obtain a squaring circuit with a small delay. Further, by further dividing the LSP value, performing the bit shift operation and adding the result, a square circuit with less error can be obtained.

Embodiment 5. FIG. In the first embodiment, input data is divided into an MSB value and an LSP value, a predetermined left bit shift operation is performed on each of them to obtain a partial product, and two partial products are added to obtain a squared value. It was configured. In the fifth embodiment,
The operation is described as a configuration in which data input to the left bit shift circuit is decoded by a decoder, the decoder output is left bit shifted by the left bit shift circuit to obtain a partial product, and two partial products are added to obtain a squared value. To do.

In the first embodiment, y = x ² is replaced by x = x ₁ + x
_{It was set to 2} and approximated as y≈x ₁ ² + 2x ₁ x ₂ . in this case,
Approximation error is x _{² 2.} When the numerical value of the input data x of the squaring circuit is in the range of 2 ^m ≦ x ≦ 2 ^{m + 1} −1 (m is a non-negative integer), the m-th bit is the MSB. Here as in the first embodiment, if the x ₁ and MSB value of x, the most significant bits of the value of x _2, the value of the approximation error x ₂ ² varies.

For example, if the most significant bit of x ₂ , that is, the (m-1) th bit is 0, x ₂ is smaller than x _1/2 . The ratio of the approximation error when x ₂ = x _1/2 , that is, x ₂ ² / y is calculated as follows. ^{_{x 2 2 / y = (x}} 1/2) 2 / (3x 1/2) 2 = 1/9 (10) hence (m-1) if bit is 0, the ratio of the approximation error than 1/9 Get smaller.

However, if the most significant bit of x ₂ ,
That is, if the (m−1) th bit is 1, x ₂ is smaller than x ₁ . The ratio of the approximation error when x ₂ = x ₁ , that is, x ₂ ² / y is obtained as follows. x ₂ ² / y = x ₁ ² / (2x ₁ ) ² = 1/4 (11) Therefore, when the (m−1) th bit is 1, the approximation error ratio can take a large value of about 1/4. .

In the fifth embodiment, first, y = x ^{2 is changed} to x = x ₁
+ By placing a x _2, to approximate _{^{y ≒ x 1 2 + 2x 1}} x 2. Furthermore the numeric value represented by the most significant bit of x ₂ x ₅ Distant, the _{^{x 1 2 (x 1 + x}} 5/2) by decoding the × x _1, the output value y of the square circuit as follows Represent. In _{^{y = x 1 2 + 2x 1}} x 2 + x 1 x 5/2 (12) according to the present embodiment 5 obtains the right side of equation (12) as an output of the squaring circuit. According to equation (12), when the most significant bit of x ₂ is 0, the third term on the right side of equation (12) becomes 0 from x ₅ = 0, which is in agreement with the value obtained in the first embodiment. , X ₂
If the most significant bit of is 2 then the value of the third term on the right ^- hand side, 2 ^{2 (m-1),} is added to the output from x ₅ = 2 ^m-1 to reduce the approximation error compared to the first embodiment. You can Embodiment 5 will be described below with reference to the drawings. FIG. 9 is a configuration diagram showing the configuration of the squaring circuit according to the fifth embodiment, and in FIG. 9, reference numeral 901 is a decoder. Further, the same or corresponding portions as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Next, the operation of the circuit will be described. In FIG. 9, when digital input data which is a binary signal is input to the squaring circuit, it is input to the MSB value extraction circuit 101 and the MSB value is extracted. When the numerical value of the input data x of the squaring circuit is in the range of 2 ^m ≦ x ≦ 2 ^{m + 1} −1 (m is a non-negative integer), the m-th bit is the MSB. In this case, M
The SB value extraction circuit 101 extracts and outputs 2 ^{m in} which the m-th bit is 1. Hereinafter, a 2 ^m is the MSB value of the input data x x _1, the x-2 ^m i.e. LSP values minus 2 ^m from x to x-x ₁ and x _2. Therefore, the following relationship holds between x, x ₁ and x ₂ . x = x ₁ + x ₂ (6)

As an example, consider the case of input data x = 14. When expressed in binary, 14 is 1110 (14). x can be divided into 1000 (8) which is the MSB value and LSP value 110 (6) obtained by subtracting the MSB value 1000 (8) from the input data 1110 (14). In the MSB value extraction circuit 101, the third bit is 1 (1000 (8))
Is extracted and output.

The MSB value extraction circuit 101 outputs x ₁ that is the MSB value of the input data x, that is, 2 ^m . The x ₁ output from the MSB value extraction circuit 101 is input to the decoder 901 and also to the adder 103. The adder 103 subtracts x ₁ from the input data x and outputs x−x _1, that is, x ₂ to the decoder 901.

Adder 103 when input data x = 14
The operation of will be described. The adder 103 is 1 which is the MSB value of the input data x output from the MSB value extraction circuit 101.
000 (8) is the input data x, 1110 (14)
110 which is the LSP value of the input data x
(6) is output to the decoder 901.

[0130] and x ₁ i.e. 2 ^m is MSB value of the input data x output from the MSB value extraction circuit 101, x ₂ which is the output of the adder 103 is decoded is input to the decoder 901. This will be described with reference to the drawings. FIG. 10 is a block diagram showing the structure of the decoder 901.
01 is the most significant bit extraction circuit, 1002 is a right bit shift circuit, and 1003 is an adder.

The x ₂ input to the decoder 901 is input to the most significant bit extraction circuit 1001 and the most significant bit is extracted. Since the MSB of x is the mth bit, the most significant bit of x ₂ , which is the LSP value of x, is the (m-1) th bit. (M-1) the long bit is 0 MSB extraction circuit 1001 x ₅ = 0, also (m-1) most significant if bit is 1 bit extraction circuit 1001 x ₅
= 2 ^m-1 is output to the right bit shift circuit 1002.

The x ₅ output from the most significant bit extraction circuit 1001 is input to the right bit shift circuit 1002 and right bit shifted by 1 bit. Therefore, the value x _5/2 which is output from the right bit shift circuit 1002, the input x
0 or 2 depending on whether the (m-1) th bit of is 0 or 1.
It becomes ^m-2 . X _5/2 which is output from the right bit shift circuit 1002 is added is input x ₁ and the adder 1003. Therefore, the value output from the adder 1003 (x ₁ +
x _5/2) is the input x (m-1) th bit is 0 or 1 Kaniyori becomes 2 ^m or ^{2 m} +2 ^m-2. Adder 100
The output of 3 is input to the left bit shift circuit 102 as the output of the decoder 901.

Decoder 90 for input data x = 14
The operation of No. 1 will be described. 1 which is the LSP value of input data x
The most significant bit of 10 (6) is 1. The most significant bit value extraction circuit 1001 has a second bit of 1 100 (4)
Is extracted and output to the right bit shift circuit 1002.
In the right bit shift circuit 1002, the second bit output from the most significant bit extraction circuit 1001 is 100.
(4) is shifted right by 1 bit and 10 (2) is output to the adder 1003. The adder 1003 adds 1000 (8) output from the MSB value extraction circuit 101 and 10 (2) output from the right bit shift circuit 1002, and outputs an addition result 1010 (10) as an output of the decoder 901. Output to the left bit shift circuit 102.

(X ₁ + x ₅ output from the decoder 901)
/ 2) is input to the left bit shift circuit 102. Further, x ₁ output from the MSB value extraction circuit 101 is also input to the shift input S of the left bit shift circuit 102. (X ₁ + x ₅ input to the left bit shift circuit 102
/ 2) is bit-shifted to the left by the digit specified by the shift input S. Since the shift input S m-th bit is input x ₁ of _{1, (x 1 + x 5} /2) is bit-shifted to the left by m bits, and outputs a x ₁ '. Where x ₁ '
It is because a value of 2 ^m or 2 ^m +2 ^m-2 and m-bit shift, equal to 2 ^2m or ^{2 2m} +2 ^2m-2. That x ₁ 'is ^{_{= (x 1 2 + x 1}} x 5/2). Left bit shift circuit 102 outputs a x ₁ ² Namely 2 ^2m, the sum of x ₁ x _5/2 i.e. 0 or ^{2 m} 2 ^m-2 in the adder 105.

The operation of the bit shift circuit 102 when the input data x = 14 will be described. 1000 (8) which is the MSB value of the input data x output from the decoder 901
And 1010 (10), which is the sum of 10 (2) obtained by right-shifting the most significant bit of the LSP value by 1 bit, is left-bit-shifted by 3 bits in the left-bit shift circuit 102.
The left bit-shifted value 1010000 (80) is input to the adder 105 as the output of the left bit shift circuit 102.

Input data x output from the adder 103
The LSP value x _{2 of} is input to the decoder 901 and the left bit shift circuit 104. Further, the shift input S of the left bit shift circuit 104 is input with x ₁ which is the MSB value of the input data x output from the MSB value extraction circuit 101. The x ₂ input to the left bit shift circuit 104 is left bit-shifted by a digit obtained by adding 1 to the value designated by the shift input S. Since x ₁ whose m-th bit is 1 is input to the shift input S, x ₂ is (m +
1) Left bit is shifted by 1 bit. The left m-bit shift corresponds to x ₁ times, and the left 1-bit shift corresponds to 2 times. That is, the left (m + 1) bit shift of x ₂ in the left bit shift circuit 104 is equivalent to the operation of deriving 2x ₁ x ₂ . The left bit shift circuit 104 is 2x
₁ × ₂ is output to the adder 105.

The operation of the left bit shift circuit 104 when the input data x = 14 will be described. 110 (6), which is the LSP value of the input data x output from the adder 103, is
The bits are left-shifted by 3 + 1 = 4 bits. here,
Left 4 bit shift is equivalent to 2 ⁴ = 16 times operation, 2 ×
x ₁ (8) × x ₂ (6) = 96 is derived. The bit-shifted value is 110000 (96), which is output to the adder 105 as the output of the bit shift circuit 104.

In the adder 105, the left bit shift circuit 1
And ^{_{x 1 2 + x 1 x 5}} /2 which is output from the 02 adds 2x ₁ x ₂ output from the left bit shift circuit 104 as the output of the squaring circuit. 101 if input x = 14
0000 (80) and 110000 (96) are added and 110000 (176) is output.

As described above, the input data of the square circuit is M
It is divided into SB value and LSP value, and the MSB value is decoded using the most significant bit of the LSP value.
A predetermined left shift operation is performed on each of the values to obtain a partial product, and two partial products are added to obtain a square value. Fewer square circuits can be obtained with less error.

Sixth Embodiment In the fifth embodiment, the operation of the squaring circuit has been described using the block having the arithmetic function. In the sixth embodiment, processing in bit units when an actual digital signal is input to the squaring circuit will be described using a logic circuit.

Also in the sixth embodiment, as in the fifth embodiment, by setting y = x ² to x = x ₁ + x ₂ , y≈x ₁ ²
+ Approximate to the 2x ₁ x _2. Furthermore the numeric value represented by the most significant bit of x ₂ x ₅ Distant, the _{^{x 1 2 (x 1 + x}} 5/2)
By decoding into × x ₁ , eventually y = x ₁ ² + 2x ₁ x ₂
+ Request x ₁ x _5/2 as an output of the squaring circuit. Hereinafter, as an example, a case where the number of input bits is 4 will be described with reference to the drawings. FIG. 11 is a configuration diagram showing the configuration of the squaring circuit in the sixth embodiment, and 1101, 1102, and 1103 are adders. Further, the same or corresponding parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

As in the second embodiment, the 4-bit digital signal input to the squaring circuit is input to the AND gate 201. In the AND gate 201, the inversion of D ₃
The logical product with the lower 3 bits is calculated, and the logical product gate 202
Output to. In the logical product gate 202, the logical product of the inversion of D ₂ 'and the lower 2 bits is calculated, and the logical product gate 2
Output to 03. The logical product gate 203 takes the logical product of the inversion of D ₁ ″ and D ₀ and outputs the logical product to the 3-state output buffer gate 304. That is, as in the second embodiment, the AND gates 201, 202 and 203 operate as an MSB value extraction circuit for squaring circuit input data.

Of the 4-bit data input to the squaring circuit, D ₃ is input to the enable E of the adder 1101. When E = 1, the adder 1101 adds the inputs of the adder and outputs the addition result. When E = 0, the output becomes high impedance and the addition result is not output. Therefore D ₃ =
If 1, the adder 1101 inputs D ₀ , D ₁ , D ₂ , D ₃
To add and output the addition result. On the other hand, D
_{If 3} = 0, the output of the adder 1101 becomes high impedance and the addition result is not output.

As an example, the input of the squaring circuit is 1110.
The case of (14) will be described. Since a D ₃ = 1, the enable E of the adder 1101 is 1, the adder 1101 outputs the addition result.

Of the outputs of the AND gate 201, D ₂ is input to the enable E of the adder 1102. Adder 1
Similarly to the adder 1101, the reference numeral 102 adds the inputs when E = 1 and outputs the addition result, and the output becomes high impedance when E = 0 and does not output the addition result. Therefore D
_{If 2} = 1, the adder 1102 adds using the inputs D ₀ , D ₁ , and D ₂ and outputs the addition result. On the other hand, D ₂
If = 0, the output of the adder 1102 becomes high impedance and the addition result is not output.

Of the outputs of the AND gate 202, D ₁ is input to the enable E of the adder 1103. Adder 1
Similarly to the adders 1101 and 1102, 103 adds the inputs and outputs the addition result when E = 1, and outputs the high impedance when E = 0 and does not output the addition result. Therefore, if D ₁ = 1, the adder 1103 adds using the inputs D ₀ and D ₁ and outputs the addition result. On the other hand, if D ₁ = 0, the output of the adder 1103 becomes high impedance and the addition result is not output.

Next, the operation of the adder 1101 when the MSB of the input of the squaring circuit is D ₃ , that is, D ₃ = 1 will be described with reference to the drawings. Since D ₃ = 1, the numerical value of the input data of the squaring circuit is 8 or more and 15 or less, and only the adder 1101 outputs the addition result. FIG. 12A shows an adder 1101.
It is a block diagram which shows the structure of. As shown in FIG. 12A, the adder 1101 is a 7-bit adder, and the input A has seven inputs A ₀ to A ₆ (A ₀ is the least significant digit). Similarly, input B is seven inputs B ₀ to B ₆ (B
₀ is the least significant digit).

As shown in FIG. 12A, the adder 110
To the input A of 1, D ₃ = 1 and D ₂ are input to A ₆ and A ₄ , respectively, and 0 is input to the five inputs A ₀ to A ₃ and A ₅ . That is, the input A of the adder 1101 is connected to the MS
The sum of the square of 8 = 64 which is the B value and the value obtained by right-shifting the most significant bit of the LSP value by 1 bit is input. On the other hand, to the input B of the adder 1101, D ₂ , D ₁ , and D ₀ are input to B ₆ , B ₅ , and B ₄ , respectively, and 4 from B ₀ to B ₃ are input.
0 is input to each input. That is, the adder 110
A value obtained by subtracting 8 which is the MSB value from the input data of the squaring circuit is multiplied by 2 × 8 = 16 is input to the input B of 1. The adder 1101 adds the inputs A and B and outputs the result as the output of the squaring circuit.

The operation of the adder 1102 when the MSB of the input of the squaring circuit is D ₂ , that is, D ₃ = 0 and D ₂ = 1 will be described with reference to the drawings. Since D ₂ = 1, the value of the input data of the squaring circuit is 4 or more and 7 or less, and the adder 110
Only 2 outputs the addition result. FIG. 12B shows an adder 1
2 is a configuration diagram showing the configuration of 102. FIG. As shown in FIG. 12B, the adder 1102 is a 5-bit adder, and the input A is five inputs A ₀ to A ₄ (A ₀ is the least significant digit).
There is. Similarly, the input B has five inputs B ₀ to B ₄ (B ₀ is the least significant digit).

As shown in FIG. 12B, the adder 110
To the second input A, D ₂ and D ₁ are input to A ₄ and A ₂ , respectively, and 0 is input to the three inputs A ₀ , A ₁ and A ₃ .
That is, to the input A of the adder 1102, the sum of 4 squared = 16, which is the MSB value, and the value obtained by right-shifting the most significant bit of the LSP value by 1 bit are input. On the other hand, the input B of the adder 1102 is connected to B ₄ and B ₃ by D ₁ and D ₀ , respectively.
Is input, and 0 is input to the three inputs B ₀ to B ₂ . That is, for the input B of the adder 1102, the value obtained by subtracting the MSB value of 4 from the input data of the squaring circuit is 2
The value multiplied by × 4 is input. Input A at adder 1102
And B are added and output as the output of the squaring circuit.

The operation of the adder 1103 when the MSB of the input of the squaring circuit is D ₁ , that is, D ₃ = 0, D ₂ = 0 and D ₁ = 1 will be described with reference to the drawings. Since D ₁ = 1, the numerical value of the input data of the squaring circuit is 2 or 3,
Only the adder 1103 outputs the addition result. 12
FIG. 7C is a configuration diagram showing a configuration of the adder 1103. As shown in FIG. 12C, the adder 1103 is a 3-bit adder, and the input A has three inputs A ₀ to A ₂ (A ₀ is the least significant digit). Similarly, inputs B are B ₀ to B
_There are 3 inputs up to ₂ (B ₀ is the least significant digit).

As shown in FIG. 12C, the adder 110
The third input A, is D _1, D ₀ is input to the A _2, A _0, A ₁
Is input to 0. That is, to the input A of the adder 1103, the sum of the MSB value of 2 squared = 4 and the value obtained by right-shifting the most significant bit of the LSP value by 1 bit is input. On the other hand, the input B of the adder 1103 is B ₂ to D _0.
Is input, and 0 is input to B ₀ and B ₁ . That is,
To the input B of the adder 1103, a value obtained by subtracting 2 which is the MSB value from the input data of the squaring circuit is multiplied by 2 × 2 is input. The adder 1103 adds the input A and the input B and outputs the result as the output of the squaring circuit.

As an example, the input of the squaring circuit is 1110.
The case of (14) will be described. In this case, since D ₃ = 1, only the adder 1101 outputs the addition result.
8 × (8 + 2) = 80 is input to the input A of the adder 1101. Further, the input B of the adder 1101 has a value of 14-
16 times 8 = 6, that is, 96 is input. Therefore, the adder 1101 outputs 80 + 96 = 176 as the output of the squaring circuit.

As described above, the input data of the squaring circuit is M
Divide into SB value and LSP value, decode using the most significant bit of MSB value and LSP value, and decode output and LSP
By performing a left bit shift operation according to the MSB value for each value and adding the results of the left bit shift operation to obtain a squared value, the number of adders is reduced and the delay is smaller than in the conventional case. The squaring circuit can be obtained with a small error.

FIG. 13 shows a graph of input / output of the squaring circuit. The dotted line is the ideal value, the solid line is the input / output of the squaring circuit in the sixth embodiment, and the alternate long and short dash line is the input / output of the squaring circuit in the first embodiment. It can be seen from FIG. 13 that the sixth embodiment has a smaller output approximation error.

Seventh Embodiment

In the sixth embodiment, the output of the AND gate is used as the output of the adder. However, this is not always necessary, and the output of the AND gate is not required as in the third embodiment.
It is configured as the input of 3-state output buffer gate,
The output of the 3-state output buffer gate may be added by an adder.

The configuration diagram of the squaring circuit in this case is, for example, 2
When the input of the squaring circuit is 4 bits, the configuration is the same as in FIG. Taking the case where the input of the squaring circuit is 4 bits as an example, the configuration of the squaring circuit in the seventh embodiment will be described below with reference to FIG. Third Embodiment in Third Embodiment
Is different from the 3-state output buffer gates 501 and 5
02 and 503 and the adder 505 are connected.

The connection between the 3-state output buffer gates 501, 502 and 503 and the adder 505 in the seventh embodiment will be described with reference to the drawings. FIG. 14 is a diagram for explaining the connection between the 3-state output buffer gates 501, 502, 503 and the adder 505. The 3-state output buffer gates 501, 502, 503, 504 and the adder 505 in FIG. It is the figure which described in detail including connection. As shown in FIG. 14, the adder 505 is a 7-bit adder, and the input A has seven inputs A ₀ to A ₆ (A ₀
Is the least significant digit). Similarly, the input B has seven inputs B ₀ to B ₆ (B ₀ is the least significant digit). Of the inputs A, the inputs A ₅ , A ₃ , and A ₁ are always 0. Specifically, A ₅ ,
Ground A ₃ and A ₁ . Similarly, of the inputs B, the inputs of B ₁ and B ₀ are always 0. Specifically, B ₁ and B ₀ are grounded.

3-state output buffer gates 501 and 5
The connections of the outputs of 02, 503, and 504 and the adder 505 will be described. Of the outputs of the 3-state output buffer gate 501, O ₃ and O ₂ are connected to A ₆ and A ₄ of the adder 505, respectively. O ₂ is also connected to B ₆ , and O ₁ is B ₅ , O _0.
Are respectively connected to B ₄ . In addition, the input of the other adder 505 is the 3-state output buffer gate 501.
O _{g of} is connected. Next, of the outputs of the 3-state output buffer gate 502, O ₂ and O ₁ are respectively added by the adder 5
05 is connected to A ₄ and A ₂ . O ₁ is also connected to B ₄ , and O ₀ is connected to B ₃ . Also, other adders 5
The O _g of the 3-state output buffer gate 502 is connected to the input of 05. Next, of the outputs of the 3-state output buffer gate 503, O ₁ and O ₀ are connected to A ₂ and A ₀ of the adder 505. O ₀ is also connected to B ₂ .
Further, the O _g of the 3-state output buffer gate 503 is connected to the input of the other adder 505. Then 3
Of the outputs of the state output buffer gate 504, O ₀
Is connected to A ₀ of the adder 505. Further, O _g of the 3-state output buffer gate 504 is connected to the input of the other adder 505.

Next, the operation of the adder 505 when the MSB of the input of the squaring circuit is D ₃ , that is, D ₃ = 1 will be described. At this time, the numerical value of the input data of the squaring circuit is 8 or more and 15
Below, only the 3-state output buffer gate 501 outputs its input to the adder 505. The input A of the adder 505 has three-state output buffer gates 50 at A ₆ and A _4.
D ₃ and D ₂ output from 1 are input. A ₁ , A ₃ , A
₅ is grounded and the input is 0. Further, since A ₁ and A ₂ are input to G ₁ (= 0) of the 3-state output buffer gate 501, the input is 0. That is, the adder 5
In input A of 05, the MSB value 8 squared = 64,
The sum of the values obtained by shifting the most significant bit of the LSP value by 1 bit to the right is input. On the other hand, to the input B of the adder 505, D ₂ , D ₁ and D ₀ are input to B ₆ , B ₅ and B ₄ , respectively. B ₀ and B ₁ are grounded and the input is 0. Further, since the output G ₁ (= 0) of the 3-state output buffer gate 501 is input to B ₂ and B ₃ , the input is 0. That is, a value obtained by subtracting the MSB value of 8 from the input data of the squaring circuit is multiplied by 2 × 8 = 16 is input to the input B of the adder 505. The adder 505 adds the input A and the input B and outputs the result as the output of the squaring circuit.

Next, the operation of the adder 505 when the MSB of the input of the squaring circuit is D ₂ , that is, D ₃ = 0 and D ₂ = 1 will be described. At this time, the numerical value of the input data of the squaring circuit is 4
The above is 7 or less, and the 3-state output buffer gate 50
Only 2 outputs its input to the adder 505. Adder 505
The input A is supplied with A ₄ , A ₂ and D ₂ , D ₁ output from the 3-state output buffer gate 502. A ₁ ,
A ₃ and A ₅ are grounded and the input is 0. Further, since the output G ₂ (= 0) of the 3-state output buffer gate 502 is input to A ₀ and A ₆ , the input is 0. That is, to the input A of the adder 505, the sum of 4 squared = 16, which is the MSB value, and the value obtained by right-shifting the most significant bit of the LSP value by 1 bit are input. On the other hand, the adder 50
To the input B of 5, D ₁ and D ₀ are input to B ₄ and B ₃ , respectively. B ₀ and B ₁ are grounded and the input is 0. B ₂ , B ₅ , and B ₆ are 3-state output buffer gates 50.
Since the output G ₂ (= 0) of ₂ is input, the input is 0. That is, for the input B of the adder 505, the value obtained by subtracting the MSB value of 4 from the input data of the squaring circuit is 2 × 4 =
The value multiplied by 8 is input. The adder 505 adds the input A and the input B and outputs the result as the output of the squaring circuit.

Next, the operation of the adder 505 when the MSB of the input of the squaring circuit is D ₁ , that is, D ₃ = 0, D ₂ = 0 and D ₁ = 1 will be described. At this time, the numerical value of the input data of the squaring circuit is 2 or 3, and only the 3-state output buffer gate 503 outputs the input to the adder 505.
To the input A of the adder 505, D ₂ , D ₀ output from the 3-state output buffer gate 503 are input to A ₂ , A ₀ . A ₁ , A ₃ , and A ₅ are grounded, and the input is 0. A ₄ and A ₆ are 3-state output buffer gates 50.
Since the output G ₃ (= 0) of ₃ is input, the input is 0. That is, to the input A of the adder 505, the sum of the MSB value of 2 squared = 4 and the value obtained by right-shifting the most significant bit of the LSP value by 1 bit is input. On the other hand, to the input B of the adder 505, D ₀ is input to B ₂ . B ₀ ,
B ₁ is grounded and the input is 0. Also B ₃ ,
B ₄ , B ₅ , and B ₆ are 3-state output buffer gates 503
Since the output G ₃ (= 0) of is input, the input is 0. That is, for the input B of the adder 505, the value obtained by subtracting the MSB value of 2 from the input data of the squaring circuit is 2 × 2 =
The value multiplied by 4 is input. The adder 505 adds the input A and the input B and outputs the result as the output of the squaring circuit.

As an example, the input of the squaring circuit is 1110.
The case of (14) will be described. Since D ₀ = 1 in this case, only the 3-state output buffer gate 501 inputs to the adder 505. The input A of the adder 505 is
8 × (8 + 2) = 80 is input. Also, the adder 50
For input B of 5, 16 times 14-8 = 6, or 96
Is entered. Therefore, the adder 505 is 80 + 96 = 17
6 is output as the output of the squaring circuit.

As described above, the input data of the squaring circuit is M
Divide into SB value and LSP value, decode using the most significant bit of MSB value and LSP value, and decode output and LSP
By performing the left bit shift operation according to the MSB value for each value and adding the result of the left bit shift operation to obtain the squared value, the number of adders can be reduced and the delay can be reduced as compared with the conventional case. Further, the square circuit can be obtained with a small error by reducing the number of adders by using the 3-state output buffer gate.

Eighth Embodiment In the sixth embodiment, as a decoding method, a method of right-shifting the most significant bit of the LSP value of the input data by 1 bit and adding it to the MSB value has been described in the case of using an actual logic circuit. The decoding method is not always necessary. For example, the squaring circuit may be configured as shown in FIG. FIG. 15 is a block diagram of the squaring circuit in the eighth embodiment, and 1501 is a decoder. The operation of the squaring circuit according to the eighth embodiment will be described with reference to FIG. Note that the same or corresponding portions as those in FIG. 2 in the second embodiment and FIG. 11 in the sixth embodiment are denoted by the same reference numerals and the description thereof will be omitted.

The difference between the eighth embodiment and the sixth embodiment is that, as shown in FIG. 15, the input of the adder 1101 is
That is, the decoder 1501 is inserted. Also in the eighth embodiment, as in the sixth embodiment, the adder 11 is used only when the MSB of the input of the squaring circuit is D ₃ , that is, D ₃ = 1.
01 works. Since D ₃ = 1, the numerical value of the input data of the squaring circuit is 8 or more and 15 or less, and only the adder 1101 outputs the addition result. The input data is input to the AND gate 201 and the adder 1101 and also to the decoder 1501.

FIG . 21 is a block diagram showing the structure of the decoder 1501, and shows the connection between the decoder 1501 and the adder 1101 at the same time. In FIG. 21 , reference numeral 2101 is a logical product element, and 2102 is an inverter. As shown in FIG. 21 , D ₁ and D ₂ of the inputs of the adder 1101 are input to the logical product element 2101. The logical product element 2101 is the input D
The logical product of ₁ and D ₂ is calculated and input to A _{5 of the} adder 1101. Further, D ₁ is also input to the inverter 2102.
The inverter 2102 inputs the inversion of D ₁ into A _{4 of the} adder 1101. To the input A of the other adder 1101, D ₃ = 1 is input to A ₆ , and 0 is input to the four inputs A ₀ to A ₃ . On the other hand, to the input B of the adder 1101, D ₂ , D ₁ and D ₀ are input to B ₆ , B ₅ and B ₄ , respectively, and ₀ is input to the four inputs B ₀ to B _3. R.
The adder 1101 adds the input A and the input B and outputs the result as the output of the squaring circuit.

FIG. 16 shows a graph of input / output of the squaring circuit. The dotted line is the ideal value, the solid line is the input / output of the squaring circuit in the eighth embodiment, and the alternate long and short dash line is the input / output of the squaring circuit in the sixth embodiment. When the input data is large, the decoder according to the eighth embodiment is used, whereby the sixth embodiment is realized.
The approximation error can be smaller than that of the square circuit in.

[0170]

Since the present invention is constructed as described above, it has the following effects.

In the first embodiment, the MS of the input of the squaring circuit is
Extract the B value. The MSB value is subtracted from the input of the squaring circuit to obtain the LSP value of the input of the squaring circuit. The MSB value is bit-shifted to the left. Bit shift the LSP value to the left. By adding the values bit-shifted to the left and outputting the squared result, the number of additions by the calculator is reduced and
A squaring circuit can be realized.

Further, in the second embodiment, a plurality of AND gates output a plurality of ANDs. Addition is performed by a plurality of adders using a plurality of AND gate outputs. Outputs the logical product of the inputs. Outputs the logical sum of the logical product output and the logical product gate output. By outputting the input by the logical sum output, it is possible to reduce the number of additions by the adder and realize a square circuit having a small circuit scale.

Further, in the third embodiment, a plurality of AND gates output a plurality of ANDs. The input is output according to the most significant bit of the outputs of the AND gates. Outputs the logical product of the inputs. Outputs the logical sum of the logical product output and the logical product gate output. Input is output by OR output. By adding with the adder and outputting the squared result, the number of additions by the adder can be reduced and a square circuit with a small circuit scale can be realized.

Also, in the fourth embodiment, the MSB value of the input of the squaring circuit is extracted. The MSB value is subtracted from the input of the squaring circuit to obtain the LSP value of the input of the squaring circuit. The MSB value is bit-shifted to the left. Bit shift the LSP value to the left. The MSB value of the LSP value at the input of the squaring circuit is extracted.
The MSB value of the LSP value is subtracted from the LSP value of the input of the squaring circuit to obtain the LSP value of the LSP value of the input of the squaring circuit.
The MSB value of the LSP value is left bit-shifted. The LSP value of the LSP value is bit-shifted to the left. By adding the values bit-shifted to the left and outputting the squared result, the number of times of addition by the adder can be reduced, and a square circuit with a small circuit scale and a small output error can be realized.

Also, in the fifth embodiment, the MSB value of the input of the squaring circuit is extracted. The MSB value is subtracted from the input of the squaring circuit to obtain the LSP value of the input of the squaring circuit. Decode the MSB value using the LSP value. The decoding result is bit-shifted to the left. Bit shift the LSP value to the left. By adding the values bit-shifted to the left and outputting the squared result, the number of times of addition by the adder can be reduced, and a square circuit with a small circuit scale and a small output error can be realized.

Further, in the sixth embodiment, a plurality of AND gates output a plurality of ANDs. Addition is performed by a plurality of adders using a plurality of AND gate outputs. Outputs the logical product of the inputs. Outputs the logical sum of the logical product output and the logical product gate output. By outputting the input by the logical sum output, it is possible to reduce the number of additions by the adder and realize a squaring circuit having a small circuit scale and a small output error.

Further, in the seventh embodiment, a plurality of AND gates output a plurality of ANDs. The input is output according to the most significant bit of the outputs of the AND gates. Outputs the logical product of multiple logical product gate inputs. Outputs the logical sum of the logical product output and the logical product gate output. Input is output by OR output. By performing addition by the adder and outputting the squared result, it is possible to reduce the number of additions by the adder and realize a squaring circuit having a small circuit scale and a small output error.

Also, in the eighth embodiment, a plurality of AND gates output a plurality of ANDs. The input is output according to the most significant bit of the outputs of the AND gates. Outputs the logical product of multiple logical product gate inputs. Outputs the logical sum of the logical product output and the logical product gate output. Input is output by OR output. Outputs the logical product of the adder inputs. Outputs the inverse of the adder input. By performing addition by the adder and outputting the squared result, it is possible to reduce the number of additions by the adder and realize a squaring circuit having a small circuit scale and a small output error.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a squaring circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a squaring circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a configuration of an AND gate according to a second embodiment of the present invention and a diagram showing its input / output.

FIG. 4 is a configuration diagram of an adder according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a squaring circuit according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a 3-state output buffer gate according to a third embodiment of the present invention and a diagram showing its input / output.

FIG. 7 is a connection diagram showing a connection between a 3-state output buffer gate and an adder according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a squaring circuit according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a squaring circuit according to a fifth embodiment of the present invention.

FIG. 10 is a configuration diagram of a decoder according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of a squaring circuit according to a sixth embodiment of the present invention.

FIG. 12 is a configuration diagram of an adder according to a sixth embodiment of the present invention.

FIG. 13 is an input / output characteristic diagram of the squaring circuit according to the sixth embodiment of the present invention.

FIG. 14 is a connection diagram showing a connection between a 3-state output buffer gate and an adder according to a seventh embodiment of the present invention.

FIG. 15 is a configuration diagram of a squaring circuit according to an eighth embodiment of the present invention.

FIG. 16 is an input / output characteristic diagram of the squaring circuit according to the eighth embodiment of the present invention.

FIG. 17 is an input / output characteristic diagram of the squaring circuit according to the fourth embodiment of the present invention.

FIG. 18 is a configuration diagram showing configurations of a decoder and an adder according to an eighth embodiment of the present invention.

FIG. 19 is a configuration diagram showing a configuration of a conventional squaring circuit.

FIG. 20 is a configuration diagram showing a configuration of a conventional squaring circuit and a configuration of a conventional squaring circuit for performing bit reduction.

FIG. 21 is an input / output characteristic diagram of a conventional square circuit that reduces bits.

[Explanation of symbols]

101 MSB value extraction circuit 102, 104 left bit shift circuit 103, 105 adder 201, 202, 203 AND gate 204, 205, 206 adder 207 3-state output buffer 208 AND element 209 OR element 301, 305, 308 Inverters 302, 303, 304, 306, 307, 309 AND elements 501, 502, 503, 504 3-state output buffer gate 505 Adders 601-614 3-state output buffer 801 MSB value extraction circuits 802, 804 Left bit shift circuit 803 , 805 Adder 901 Decoder 1001 Most significant bit extraction circuit 1002 Right bit shift circuit 1003 Adder 1101, 1102, 1103 Adder 1501 Decoder 1701, 1702, 1703, 1704 AND gate 17 5,1706,1707 adder 1801, 1802 and 1803 AND gates 1804 and 1805 adder 2101 AND gate 2102 inverter.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-2-22734 (JP, A) JP-A 48-63652 (JP, A) JP-A 64-57332 (JP, A) JP-A 57- 168342 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/552

Claims (8)

(57) [Claims] 1. An MSB value extraction circuit for extracting an MSB value of an input, a left bit shift circuit for left bit shifting an output of the MSB value extraction circuit, and an LSP by subtracting an output of the MSB value extraction circuit from an input. It is provided with an adder for outputting a value, a left bit shift circuit for left bit shifting the LSP value output from the adder, and an adder for adding the outputs of the two left bit shift circuits. Square circuit. 2. A plurality of AND gates, which operate as an MSB value extraction circuit for extracting an MSB value of an input, output a logical product of the most significant bit of the input and all the bits of the input, and the plurality of AND gates. Of the AND gate, one of which is the most significant bit of the AND gate, and one of which is output when the input of the squaring circuit is 0 And a three-state output buffer that outputs the input by the output of the logical sum element, and the output of the logical sum gate and the output of the logical product gate circuit. 3. A plurality of AND gates, which operate as an MSB value extraction circuit for extracting the MSB value of the input, output a logical product of the most significant bit of the input and all the bits of the input, and the plurality of AND gates. Of the three-state output buffer gates, which outputs the inputs by the enable inputs, an AND element that outputs 1 when the input of the squaring circuit is 0, and an AND of the outputs of the OR elements. An OR element having the output of the gate as an input and the outputs of the plurality of three-state output buffer gates as the inputs, and particularly the most significant bit of the three-state output buffer gates as one input,
A squaring circuit comprising: an adder that outputs an addition result. 4. An MSB value extracting circuit for extracting an MSB value of an input, a left bit shift circuit for left bit shifting an output of the MSB value extracting circuit, and an LSP by subtracting an output of the MSB value extracting circuit from an input. An adder that outputs a value, a left bit shift circuit that left-shifts the LSP value output from the adder, an MSB value extraction circuit that extracts the MSB value of the LSP value, and an output of the MSB value extraction circuit A left bit shift circuit for left bit shifting the MSB value of the LSP value and an addition for outputting the LSP value of the LSP value by subtracting the MSB value of the LSP value output from the MSB value extraction circuit from the input LSP value. And a left bit shift circuit for left bit shifting the LSP value of the LSP value output from the adder, and an adder for adding the outputs of the four left bit shift circuits. A squaring circuit characterized in that 5. An MSB value extraction circuit for extracting an input MSB value, an adder for subtracting an output of the MSB value extraction circuit from an input to output an LSP value, an output of the MSB value extraction circuit and the addition Decoder that receives the LSP value that is the output of the adder, a left bit shift circuit that shifts the output of the decoder to the left bit, and an LSP that is the output of the adder
A left bit shift circuit for shifting the value to the left by a bit;
A squaring circuit comprising an adder for adding the outputs of two left bit shift circuits. 6. A plurality of logical product gates, which operate as an MSB value extraction circuit for extracting an input MSB value, which outputs a logical product of the most significant bit of the input and all the bits of the input, and the plurality of logical product gates. , The output of which is an input, and the adder which makes the addition output high impedance by the enable input, the AND element which outputs 1 when the input of the square circuit is 0, the output of the OR element and the AND gate 2. A squaring circuit comprising: a logical sum element having an output of the input as an input and a three-state output buffer outputting an input by the output of the logical sum element. 7. A plurality of AND gates, which operate as an MSB value extraction circuit for extracting an MSB value of an input, output a logical product of the most significant bit of the input and all the bits of the input, and the plurality of AND gates. 3-state output buffer gates that take the output of the input as an input and that output by the enable input, an AND element that outputs 1 when the input of the squaring circuit is 0, an output of the OR element and an AND gate 2. A squaring circuit comprising: a logical sum element having the output of the input as an input and an adder having the outputs of a plurality of three-state output buffer gates as the input and outputting the addition result. 8. A plurality of AND gates, which operate as an MSB value extraction circuit for extracting the MSB value of the input, output a logical product of the most significant bit of the input and all the bits of the input, and decode the input of the adder. A logical product element that operates as a decoder and an inverter, a plurality of adders that take the outputs of the plurality of logical product gates, the output of the logical product element and the output of the inverter as inputs, and that make the addition output high impedance by the enable input, An AND element that outputs 1 when the input of the squaring circuit is 0, an OR element that receives the output of the OR element and the output of the AND gate, and an input that outputs the output of the OR element 3 A squaring circuit having a state output buffer.