JP2511979Y2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2511979Y2 JP2511979Y2 JP983988U JP983988U JP2511979Y2 JP 2511979 Y2 JP2511979 Y2 JP 2511979Y2 JP 983988 U JP983988 U JP 983988U JP 983988 U JP983988 U JP 983988U JP 2511979 Y2 JP2511979 Y2 JP 2511979Y2
- Authority
- JP
- Japan
- Prior art keywords
- control element
- semiconductor device
- filler
- heat
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【考案の詳細な説明】 〈産業上の利用分野〉 本考案は、制御素子と電力素子とを組み合せた複合素
子を有する半導体装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a structure of a semiconductor device having a composite element in which a control element and a power element are combined.
〈従来技術〉 従来、集積回路（以下ICという）を含む半導体制御素
子と半導体電力素子とを組み合せた複合素子を有する半
導体装置は、第４図の如く、基板１に制御素子２と電力
素子（ヒートスプレツター３、パワーチツプ４）が、ト
ランスフアーモールド、粉体塗装の方法を主に用いて、
シリカ及びアルミナ等の熱伝導媒体（フイラー）６を含
有する高熱伝導性の絶縁封止材（エポキシ樹脂）５を注
入することにより、絶縁封止されている。<Prior Art> Conventionally, a semiconductor device having a composite element in which a semiconductor control element including an integrated circuit (hereinafter referred to as an IC) and a semiconductor power element are combined has a control element 2 and a power element (substrate) on a substrate 1 as shown in FIG. The heat spreader 3 and power chip 4) mainly use the transfer mold and powder coating methods.
It is insulated and sealed by injecting a highly heat conductive insulating sealant (epoxy resin) 5 containing a heat conductive medium (filler) 6 such as silica and alumina.
なお、図中７はアルミニウム線、８は半導体受動素
子、９はリード端子である 〈考案が解決しようとする問題点〉 しかし、このようなICを含む制御素子と電力素子とを
組み合せた半導体装置の絶縁封止法は、トランスフアー
モールド、粉体塗装が主に用いられており、いずれの方
法においても電力素子の熱放射性を主眼としているた
め、高熱伝導性のエポキシ樹脂が使用される。また、両
封止法とも、ゲル化時間が非常に短いため、樹脂硬化
後、熱伝導媒体（フイラー）は第４図の如く、樹脂全体
に一様に分布し熱伝導性が均一となる。この場合、ICを
含む制御素子と電力素子との許容接合温度は、制御素子
の方が低く、複合素子である半導体装置としての使用温
度範囲は制御素子側で規制されてしまう。また、均一の
熱伝導を持つ材料で封止された場合、電力素子の許容接
合温度が制御素子の許容接合温度に等しくなり、半導体
装置としての使用温度範囲が狭くなるという問題点があ
る。In the figure, 7 is an aluminum wire, 8 is a semiconductor passive element, and 9 is a lead terminal. <Problems to be solved by the invention> However, a semiconductor device in which a control element including such an IC and a power element are combined. In the insulation and sealing method of (1), transfer molding and powder coating are mainly used, and since heat radiation of the power element is the main object in either method, an epoxy resin having high thermal conductivity is used. Further, in both sealing methods, the gelation time is very short, so that after the resin is cured, the heat conductive medium (filer) is uniformly distributed throughout the resin as shown in FIG. 4, and the heat conductivity becomes uniform. In this case, the allowable junction temperature between the control element including the IC and the power element is lower in the control element, and the operating temperature range of the semiconductor device, which is a composite element, is restricted on the control element side. In addition, when it is sealed with a material having uniform heat conduction, the allowable junction temperature of the power element becomes equal to the allowable junction temperature of the control element, which causes a problem that the operating temperature range of the semiconductor device is narrowed.
本考案は、上記問題点を考慮してなされたもので、電
力素子と制御素子との熱分離が有効に行い得、使用温度
を広範囲とし得る半導体装置の提供を目的とする。The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a semiconductor device that can effectively perform heat separation between a power element and a control element and can have a wide operating temperature range.
〈問題点を解決するための手段〉 上記目的を達成するために本考案は、同一基板上に制
御素子と電力素子とが搭載され、且つ前記両素子が前記
基板とともにフィラーを含有する絶縁封止材によって一
体的に封止されてなる半導体装置において、前記電力素
子の周辺の前記絶縁封止材に、フィラーが含有された高
熱伝熱部が形成されるとともに、前記制御素子の周辺の
前記絶縁封止材にはフィラーがほとんど含有されない低
熱伝導部が形成されてなることを特徴とする。<Means for Solving the Problems> In order to achieve the above object, the present invention provides an insulating encapsulation in which a control element and a power element are mounted on the same substrate, and both elements include a filler together with the substrate. In a semiconductor device integrally sealed with a material, a high-heat heat transfer part containing a filler is formed in the insulating sealing material around the power element, and the insulating around the control element is formed. It is characterized in that the sealing material is formed with a low heat conduction part containing almost no filler.
〈作用〉 上記問題点解決手段において、電力素子13,14の周辺
に絶縁封止材15にフイラー16を含有させた高熱伝導部17
が形成されると共に制御素子12の周辺に低熱伝導部18が
形成されているので、絶縁封止材15による同一パツケー
ジ内で熱勾配を有することになり、電力素子13,14から
発生する熱が、制御素子12に伝達されにくくなり、半導
体装置としての使用温度範囲の設定を電力素子13,14側
の広い許容接合温度範囲内にすることができる。<Operation> In the means for solving the above problems, the high thermal conductive part 17 in which the filler 16 is contained in the insulating sealing material 15 around the power elements 13 and 14 is provided.
Since the low heat conducting portion 18 is formed around the control element 12 with the formation of the heat insulating material, there is a thermal gradient within the same package due to the insulating sealing material 15, and the heat generated from the power elements 13 and 14 is generated. As a result, it is less likely to be transmitted to the control element 12, and the operating temperature range of the semiconductor device can be set within a wide allowable junction temperature range on the power element 13, 14 side.
〈実施例〉 以下、本考案の実施例を図面に基づいて詳述する。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本考案の第一実施例を示す半導体装置の断面
図である。図示の如く、この半導体装置は、ICを含む制
御素子12と電力素子13,14とを組み合せた複合素子を有
し、該複合素子が絶縁封止材15でキヤステイング法によ
り一体的に封止され、該絶縁封止材15に熱伝導媒体（フ
イラー）16が含有され、前記電力素子13,14の周辺に熱
伝導媒体（フイラー）16が凝集する高熱伝導部17と、前
記制御素子12の周辺に熱伝導媒体（フイラー）をほとん
ど分布させない低熱伝導部18が形成されているものであ
る。FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention. As shown in the figure, this semiconductor device has a composite element in which a control element 12 including an IC and power elements 13 and 14 are combined, and the composite element is integrally sealed by an insulating sealing material 15 by a casting method. The insulating sealing material 15 contains a heat conducting medium (filler) 16, and the high heat conducting portion 17 in which the heat conducting medium (filler) 16 aggregates around the power elements 13 and 14, and the control element 12 are provided. A low heat conductive portion 18 in which a heat conductive medium (filler) is hardly distributed is formed in the periphery.
前記制御素子12は、基板11の一側部に実装され、前記
電力素子は、基板11の他側部に実装される。電力素子と
しては、ヒートスプレツター13およびパワーチツプ14が
ある。制御素子12の両端には、半導体受動素子20（例え
ばコンデンサーや抵抗等）が対応するように載置され、
電力素子13,14のパワーチツプ14の上面よりアルミニウ
ム線21にて基板11に接続される。また、前記基板11の一
側部にはリード端子22が取り付けられる。そして、該リ
ード端子22が絶縁封止材15から突出されている。絶縁封
止材15は、シリカおよびアルミナ等の熱伝導媒体（フイ
ラー）16を含有するもので、ゲル化時間の長いエポキシ
樹脂が使用され、前記制御素子12および電力素子13,14
の複合素子が一体となるよう箱状（パツケージ）に形成
される。The control element 12 is mounted on one side of the board 11, and the power element is mounted on the other side of the board 11. The power element includes a heat spreader 13 and a power chip 14. A semiconductor passive element 20 (for example, a capacitor or a resistor) is mounted on both ends of the control element 12 so as to correspond to each other,
The upper surface of the power chip 14 of the power elements 13 and 14 is connected to the substrate 11 by an aluminum wire 21. A lead terminal 22 is attached to one side of the substrate 11. Then, the lead terminal 22 is projected from the insulating sealing material 15. The insulating encapsulant 15 contains a heat conductive medium (filler) 16 such as silica and alumina, epoxy resin having a long gelation time is used, and the control element 12 and the power elements 13, 14 are used.
The composite element is formed in a box shape (package) so as to be integrated.
次に上記半導体装置の成形方法について説明する。ま
ず、第１図の如く、電力素子13,14の発熱量は高いの
で、リード端子22から離れた位置で基板11に実装する。
また、制御素子12の発熱量は電力素子13,14に比べて低
いので、リード端子22側に実装する。そして、リード端
子22を上側にして、キヤステイング法で絶縁封止する。
このとき、絶縁封止材15は、ゲル化時間の長い絶縁封止
材（エポキシ樹脂）15を使用し、熱伝導媒体16を含有し
ておく。そうすると、ゲル化までの間に絶縁封止材（エ
ポキシ樹脂）15より比重の大きい熱伝導媒体（フイラ
ー）16が下部に沈降し、基板11下部に実装された電力素
子13周辺に凝集し、高熱伝導部17となる。一方、基板11
の上部は、熱伝導媒体16の沈降により制御素子12の周辺
には熱伝導媒体（フイラー）16がほとんど分布しない低
熱伝導部18となる。Next, a method of molding the above semiconductor device will be described. First, as shown in FIG. 1, since the power elements 13 and 14 generate a large amount of heat, they are mounted on the substrate 11 at positions away from the lead terminals 22.
Further, since the heat generation amount of the control element 12 is lower than that of the power elements 13 and 14, the control element 12 is mounted on the lead terminal 22 side. Then, the lead terminal 22 is placed on the upper side, and insulation is sealed by the casting method.
At this time, as the insulating sealing material 15, the insulating sealing material (epoxy resin) 15 having a long gelation time is used, and the heat conduction medium 16 is contained therein. Then, the heat conductive medium (filler) 16 having a larger specific gravity than the insulating encapsulant (epoxy resin) 15 settles down to the bottom until it gels, and it condenses around the power element 13 mounted on the bottom of the board 11 to generate high heat. It becomes the conduction part 17. On the other hand, the substrate 11
At the upper part of the heat conducting medium 16 is set a low heat conducting portion 18 in which the heat conducting medium (filler) 16 is hardly distributed around the control element 12 due to the sedimentation of the heat conducting medium 16.
その結果、構成部品が一体となつた同一パツケージ内
においては、電力素子13,14を封止する部分に高熱伝導
部17となり、制御素子12を封止する部分に低熱伝伝導部
18となるので、同一パツケージ内に熱勾配をもたせるこ
とができ、電力素子13,14から発生する熱が、制御素子1
2部に伝達しにくくなり、半導体装置としては使用温度
範囲の設定を電力素子13,14側の許容接合温度範囲内で
使用できる様になる。As a result, in the same package in which the components are integrated, a high heat conduction part 17 is formed in the part that seals the power elements 13 and 14, and a low heat conduction part is formed in the part that seals the control element 12.
18, the heat gradient can be provided in the same package, and the heat generated from the power elements 13 and 14 is controlled by the control element 1.
It becomes difficult to transmit to the two parts, and the semiconductor device can be used within the allowable junction temperature range on the power element 13, 14 side.
このように、高熱伝導部17と低熱伝導部18の形成によ
り、電力素子13,14と制御素子12との熱分離が有効に行
い得、使用温度範囲の広い半導体装置を提供できる。As described above, by forming the high heat conducting portion 17 and the low heat conducting portion 18, heat separation between the power elements 13 and 14 and the control element 12 can be effectively performed, and a semiconductor device having a wide operating temperature range can be provided.
第２図は本考案の第二実施例を示すもので、これは、
ケース23を利用したポツテイング法で絶縁封止した場合
を示している。他の構成は上記第一実施例と同様であ
り、本例においても上記と同様の作用効果を奏する。FIG. 2 shows a second embodiment of the present invention.
The figure shows a case where the case 23 is used for insulation and sealing by a potting method. The other structure is the same as that of the first embodiment, and this embodiment also has the same effect as the above.
なお、本考案は、上記実施例に限定されるものではな
く、本考案の範囲内で上記実施例に多くの修正および変
更を加え得ることは勿論である。It should be noted that the present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.
例えば上記実施例における熱伝導媒体（フイラー）
は、注入時に含有させず、予め熱伝導媒体（フイラー）
を電力素子周辺に凝集させておき、その後絶縁封止材を
注入する。For example, the heat transfer medium (filler) in the above embodiment
Is not included at the time of injection, and is a heat conduction medium (filler) in advance.
Are agglomerated around the power device, and then an insulating sealant is injected.
また、第３図（ａ）の如く、予め制御素子と電力素子
の許容温度範囲に合せて熱伝導媒体（フイラー）の含有
量を調整した絶縁封止材を別々に注入凝固させる方法
や、また許容温度範囲の異なる半導体素子が３個以上あ
る場合でも、第３図（ｂ）の如く、予め各々の素子の許
容温度範囲に合せて熱伝導媒体（フイラー）の含有量を
調整した熱伝導の異なる絶縁封止材を夫々別々に注入凝
固させ、中熱伝導部25を形成することにより、上記と同
様な作用効果を奏し得る。Further, as shown in FIG. 3 (a), a method of separately injecting and coagulating an insulating encapsulating material in which the content of the heat conducting medium (filler) is adjusted in advance according to the allowable temperature range of the control element and the power element, or Even when there are three or more semiconductor elements having different allowable temperature ranges, as shown in FIG. 3 (b), the heat conduction medium (filler) content is adjusted in advance according to the allowable temperature range of each element. The different insulating sealing materials are separately injected and solidified to form the intermediate heat conducting portion 25, and thereby the same operational effect as described above can be obtained.
また、上記実施例では電力用の半導体装置について説
明したが、電力用以外の用途のものも同様に構成でき
る。Further, in the above-mentioned embodiment, the semiconductor device for electric power is explained, but the one for use other than electric power can be constructed in the same manner.
〈考案の効果〉 以上の説明から明らかな通り、本考案によると、電力
素子の周辺に絶縁封止材にフイラーを含有させた高熱伝
導部が形成されると共に制御素子の周辺に低熱伝導部が
形成されているので、絶縁封止材による同一パツケージ
内で熱勾配を有することになり、電力素子から発生する
熱が制御素子に伝達されにくくなり、電力素子と制御素
子との熱分離を確実に行える。<Effect of the Invention> As is clear from the above description, according to the present invention, the high heat conduction part containing the filler in the insulating sealing material is formed around the power element, and the low heat conduction part is formed around the control element. Since it is formed, it has a thermal gradient in the same package by the insulating encapsulant, the heat generated from the power element is less likely to be transferred to the control element, and the heat separation between the power element and the control element is ensured. You can do it.
したがつて、半導体装置としての使用温度範囲を制御
素子側より高温まで許容できる電力素子側の広い許容接
合温度範囲内に設定して使用できるといつた優れた効果
がある。Therefore, if the semiconductor device can be used by setting the operating temperature range within a wide allowable junction temperature range on the power element side that can tolerate a higher temperature than the control element side, it has an excellent effect.
第１図は本考案の第一実施例を示すキヤステイング法で
絶縁封止された半導体装置の断面図、第２図は本考案の
第二実施例を示すポツテイング法で絶縁封止された場合
の半導体装置の断面図、第３図（ａ）（ｂ）は夫々本考
案の他の実施例を示す断面図、第４図は従来の半導体装
置の断面図である。 12:制御素子、13,14:電力素子、15:絶縁封止材、16:熱
伝導媒体（フイラー）、17:高熱伝導部、18:低熱伝導
部、20:半導体受動素子、21:アルミニウム線、22:リー
ド端子、23:ケース。FIG. 1 is a sectional view of a semiconductor device insulation-sealed by the casting method according to the first embodiment of the present invention, and FIG. 2 is a semiconductor device insulation-sealed by the potting method according to the second embodiment of the present invention. 3A and 3B are sectional views showing another embodiment of the present invention, and FIG. 4 is a sectional view of a conventional semiconductor device. 12: Control element, 13, 14: Power element, 15: Insulation encapsulant, 16: Thermal conductive medium (filler), 17: High thermal conductive section, 18: Low thermal conductive section, 20: Semiconductor passive element, 21: Aluminum wire , 22: Lead terminal, 23: Case.
フロントページの続き (72)考案者 藤原 亨 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (56)参考文献 特開 昭57−40966（ＪＰ，Ａ) 実開 昭60−37248（ＪＰ，Ｕ)Continuation of the front page (72) Inventor Toru Fujiwara 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP 57-40966 (JP, A) Actual 60-37248 (JP) , U)
Claims (1)
され、且つ前記両素子が前記基板とともにフィラーを含
有する絶縁封止材によって一体的に封止されてなる半導
体装置において、 前記電力素子の周辺の前記絶縁封止材に、フィラーが含
有された高熱伝熱部が形成されるとともに、前記制御素
子の周辺の前記絶縁封止材にはフィラーがほとんど含有
されない低熱伝導部が形成されてなることを特徴とする
半導体装置。1. A semiconductor device in which a control element and a power element are mounted on the same substrate, and the both elements are integrally sealed together with the substrate by an insulating sealing material containing a filler. A high heat transfer part containing a filler is formed in the insulating encapsulant around the element, and a low heat conductive part containing almost no filler is formed in the insulating encapsulant around the control element. A semiconductor device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP983988U JP2511979Y2 (en) | 1988-01-27 | 1988-01-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP983988U JP2511979Y2 (en) | 1988-01-27 | 1988-01-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01115255U JPH01115255U (en) | 1989-08-03 |
| JP2511979Y2 true JP2511979Y2 (en) | 1996-09-25 |
Family
ID=31216938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP983988U Expired - Lifetime JP2511979Y2 (en) | 1988-01-27 | 1988-01-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2511979Y2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002373929A (en) * | 2001-06-14 | 2002-12-26 | Tokyo Electron Ltd | Wafer support |
| JP5120032B2 (en) * | 2008-04-03 | 2013-01-16 | 株式会社デンソー | Electronic equipment |
| CN110914977A (en) | 2017-07-21 | 2020-03-24 | 株式会社村田制作所 | Electronic component |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5740966A (en) * | 1980-08-25 | 1982-03-06 | Hitachi Ltd | Semiconductor device |
| JPS6037248U (en) * | 1983-08-19 | 1985-03-14 | 富士電機株式会社 | hybrid integrated circuit |
-
1988
- 1988-01-27 JP JP983988U patent/JP2511979Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01115255U (en) | 1989-08-03 |
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