JPH0713984B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0713984B2
JPH0713984B2 JP16792989A JP16792989A JPH0713984B2 JP H0713984 B2 JPH0713984 B2 JP H0713984B2 JP 16792989 A JP16792989 A JP 16792989A JP 16792989 A JP16792989 A JP 16792989A JP H0713984 B2 JPH0713984 B2 JP H0713984B2
Authority
JP
Japan
Prior art keywords
semiconductor device
control element
heat
sealing material
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16792989A
Other languages
Japanese (ja)
Other versions
JPH0332032A (en
Inventor
秀行 今中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16792989A priority Critical patent/JPH0713984B2/en
Publication of JPH0332032A publication Critical patent/JPH0332032A/en
Publication of JPH0713984B2 publication Critical patent/JPH0713984B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、制御素子と電力素子とを組み合わせた複合素
子を有する電力半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a power semiconductor device having a composite element in which a control element and a power element are combined.

〈従来技術〉 従来、集積回路(以下、ICという)を含む半導体制御素
子と半導体電力素子とを組み合わせた複合素子を有する
電力半導体装置は、第3図の如く、基板1に制御素子2
と電力素子(ヒートスプレツター3、パワーチツプ4)
とを組み合わせた複合素子を搭載し、これらをトランス
フアーモールド、粉体塗装、キヤステイング法あるいは
ポツテイング法を用いてシリカおよびアルミナ等の熱伝
導媒体(フイラー)6を含有する高熱伝導性の絶縁封止
材(エポキシ樹脂)5を注入することにより絶縁封止さ
れている。
<Prior Art> Conventionally, a power semiconductor device having a composite element in which a semiconductor control element including an integrated circuit (hereinafter referred to as an IC) and a semiconductor power element are combined has a control element 2 on a substrate 1 as shown in FIG.
And power device (heat spreader 3, power chip 4)
And a composite element that is a combination of the above and a transfer element, powder coating, casting method or potting method, and these are used to provide a high thermal conductivity insulation seal containing a heat conductive medium (filler) 6 such as silica and alumina. By injecting a stopper material (epoxy resin) 5, the material is insulated and sealed.

なお、図中、7はアルミニウム線等のボンデイングワイ
ヤー、8は半導体受動素子、9はリード端子である 〈発明が解決しようとする問題点〉 しかし、このようなICを含む制御素子と電力素子とを組
み合わせた複合素子を有する電力半導体装置の絶縁封止
法は、トランスフアーモールド、粉体塗装、キヤステイ
ング法、ポツテイング法があり、いずれの方法において
も電力素子の熱放散性を主眼としているため、高熱伝導
性のエポキシ樹脂が使用される。
In the figure, 7 is a bonding wire such as an aluminum wire, 8 is a semiconductor passive element, and 9 is a lead terminal. <Problems to be solved by the invention> However, a control element including such an IC and a power element There are transfer mold, powder coating, casting method, and potting method as the insulation sealing method of the power semiconductor device having the composite element in which the power element heat dissipation is the main focus. , High thermal conductivity epoxy resin is used.

ここで、トランスフアーモールド、粉体塗装ではゲル化
時間が非常に短いため、樹脂硬化後、熱伝導媒体は、第
3図の如く、樹脂全体に一様に分布し熱伝導性が均一と
なる。この場合、ICを含む制御素子と電力素子との許容
接合温度は、制御素子の方が低く、複合素子である半導
体装置としての使用温度範囲は制御素子側で規制されて
しまう。
Here, in the transfer mold and powder coating, the gelation time is very short, and therefore, after the resin is cured, the heat conduction medium is evenly distributed throughout the resin as shown in FIG. 3, and the heat conductivity becomes uniform. . In this case, the allowable junction temperature between the control element including the IC and the power element is lower in the control element, and the operating temperature range of the semiconductor device, which is a composite element, is restricted on the control element side.

また、均一の熱伝導を持つ材料で封止された場合、電力
素子の許容接合温度が制御素子の許容接合温度に等しく
なり、半導体装置としての使用温度範囲が狭くなる。
Further, when the material is sealed with a material having uniform heat conduction, the allowable junction temperature of the power element becomes equal to the allowable junction temperature of the control element, and the operating temperature range of the semiconductor device is narrowed.

上記に対応する手段として、キヤステイング法あるいは
ポツテイング法により制御素子と電力素子とを組み合わ
せた複合素子を絶縁封止材で一体的で封止する際に、絶
縁封止材は電力素子の周辺に高熱伝導部が形成されると
共に制御素子の周辺に低熱伝導部を形成するような方法
の提案もある。
As a means corresponding to the above, when a composite element combining a control element and a power element is integrally sealed with an insulating sealing material by a casting method or a potting method, the insulating sealing material is provided around the power element. There is also a proposal of a method of forming a high heat conduction part and a low heat conduction part around the control element.

しかし、この方法においても、絶縁封止材はシリカおよ
びアルミナ等の熱伝導媒体を含有するもので、ゲル化時
間の長いエポキシ樹脂を使用するか、もしくは熱伝導媒
体を含まないエポキシ樹脂を併用する必要があり、工程
数が増える。
However, also in this method, the insulating encapsulant contains a heat conductive medium such as silica and alumina, and an epoxy resin having a long gelation time is used or an epoxy resin containing no heat conductive medium is used in combination. It is necessary and the number of processes increases.

そこで、本発明は、上記課題に鑑み、一工程で電力素子
(高熱伝導部)と制御素子(低熱伝導部)との熱分離が
有効に行い得、使用温度を広範囲とし得る半導体装置の
製造方法の提供を目的とする。
Therefore, in view of the above problems, the present invention is a method for manufacturing a semiconductor device, which can effectively perform heat separation between a power element (high heat conduction section) and a control element (low heat conduction section) in one step, and can be used in a wide temperature range. For the purpose of providing.

〈課題を解決するための手段〉 本発明による課題解決手段は、第1,2図の如く、基板11
上に制御素子12と電力素子13,14とを組み合わせた複合
素子を搭載し、これらを熱伝導媒体16を含有する絶縁封
止材15で一体的に封止する半導体装置の製造方法におい
て、絶縁封止材15の注型作業前に前処理として絶縁封止
材15を高温で連続的に撹拌し、注型作業途中においても
絶縁封止材15を高温保持してその粘度を低下させること
により熱伝導媒体16の沈降速度を大にし、電力素子13,1
4の周辺に高熱伝導部17を形成すると共に制御素子12の
周辺に低熱伝導部18を形成して高熱伝導部17と低熱伝導
部18との二層に分離するものである。
<Means for Solving the Problems> The means for solving the problems according to the present invention is as shown in FIGS.
In the method for manufacturing a semiconductor device, which mounts a composite element in which the control element 12 and the power elements 13 and 14 are combined on the above, and integrally seals these with the insulating encapsulant 15 containing the heat conductive medium 16, By continuously stirring the insulating encapsulant 15 at a high temperature as a pretreatment before the casting operation of the encapsulant 15, and keeping the insulating encapsulant 15 at a high temperature even during the casting operation to reduce its viscosity. The sedimentation velocity of the heat transfer medium 16 is increased, and the power elements 13,1
A high heat conductive portion 17 is formed around the periphery of the control element 4 and a low heat conductive portion 18 is formed around the control element 12 to separate the high heat conductive portion 17 and the low heat conductive portion 18 into two layers.

〈作用〉 上記課題解決手段において、絶縁封止材15の注型作業前
に前処理として絶縁封止材15を高温で連続的に撹拌し、
注型作業途中においても絶縁封止材15を高温保持してそ
の粘度を低下させることにより熱伝導媒体16の沈降速度
を大にしているので、一工程で電力素子13,14を封止す
る高熱伝導部17と、制御素子12を封止する低熱伝導部18
との熱分離が有効に行い得る。
<Operation> In the above means for solving problems, the insulating sealing material 15 is continuously stirred at a high temperature as a pretreatment before the casting operation of the insulating sealing material 15,
Even during the casting operation, the insulating sealing material 15 is kept at a high temperature and its viscosity is lowered to increase the sedimentation speed of the heat conduction medium 16, so that the high heat for sealing the power elements 13 and 14 in one step is used. Conducting part 17 and low heat conducting part 18 for sealing the control element 12
The heat separation with can be effectively performed.

また、これにより、同一パツケージ内に熱匂配をもたせ
ることができ、電子素子13,14の発熱する熱が制御素子1
2に伝達しにくくなり、半導体装置としては使用温度範
囲の設定を電子素子13,14側の許容接合温度範囲内で使
用できる様になるので、使用温度範囲の広い半導体装置
を提供できる。
Further, this makes it possible to provide a thermal odor in the same package, and the heat generated by the electronic elements 13 and 14 is controlled by the control element 1.
2 is difficult to transmit, and the setting of the operating temperature range of the semiconductor device can be used within the allowable junction temperature range on the electronic element 13, 14 side, so that a semiconductor device having a wide operating temperature range can be provided.

〈実施例〉 以下、本発明の一実施例を第1図に基づいて詳述する。
第1図は本発明の一実施例を示すポツテイング法で絶縁
封止された半導体装置の断面図である。
<Example> Hereinafter, an example of the present invention will be described in detail with reference to FIG.
FIG. 1 is a cross-sectional view of a semiconductor device insulation-sealed by the potting method showing an embodiment of the present invention.

図示の如く、本実施例の半導体装置は、基板11上にICを
含む制御素子12と電力素子(ヒートスプレツター13,パ
ワーチツプ14)とを組み合わせた複合素子が搭載され、
該複合素子が熱伝導媒体(フイラー)16が含有された絶
縁封止材15でポツテイング法により一体的に封止され、
前記電力素子13,14の周辺に熱伝導媒体16が凝集する高
熱伝導部17と、前記制御素子12の周辺に熱伝導媒体16を
ほとんど分布させない低熱伝導部18が形成されたもので
ある。
As shown in the figure, the semiconductor device of the present embodiment has a composite element in which a control element 12 including an IC and a power element (heat spreader 13, power chip 14) are combined on a substrate 11,
The composite element is integrally sealed by an potting method with an insulating sealing material 15 containing a heat conductive medium (filler) 16,
A high heat conduction part 17 in which a heat conduction medium 16 is aggregated around the power elements 13 and 14, and a low heat conduction part 18 in which the heat conduction medium 16 is hardly distributed are formed around the control element 12.

前記制御素子12は、基板11の一側部に搭載されており、
該制御素子12の両端には、半導体受動素子20(例えば、
コンデンサーや抵抗等)が対向するように載置されてい
る。
The control element 12 is mounted on one side of the substrate 11,
At both ends of the control element 12, a semiconductor passive element 20 (for example,
Capacitors, resistors, etc.) are placed so as to face each other.

前記電力素子13,14は、基板11の他側部に搭載されてい
る。該パワーチツプ14は、ヒートスプレツタ13上に載置
されており、その上面よりアルミニウム線等のボンデイ
ングワイヤー21にて基板11に接続されている。
The power elements 13 and 14 are mounted on the other side of the substrate 11. The power chip 14 is mounted on the heat spreader 13 and is connected to the substrate 11 from the upper surface thereof by a bonding wire 21 such as an aluminum wire.

前記基板11の一側部には、リード端子22が取り付けられ
ており、該リード端子22の一部が絶縁封止材15から突出
している。
A lead terminal 22 is attached to one side of the substrate 11, and a part of the lead terminal 22 projects from the insulating encapsulant 15.

前記絶縁封止材15は、熱伝導媒体16の沈降を防止するた
め超微粉シリカおよびアルミナ等を含有する熱硬化タイ
プの2液混合型エポキシ樹脂が使用されている。該制御
素子12および電力素子13,14が一体となるよう箱状(パ
ツケージ)に形成されている。
The insulating sealing material 15 is a thermosetting type two-component mixed epoxy resin containing ultrafine silica and alumina in order to prevent the heat conducting medium 16 from settling. The control element 12 and the power elements 13 and 14 are formed in a box shape (package) so as to be integrated.

次に、上記半導体装置の製造方法について説明する。Next, a method of manufacturing the semiconductor device will be described.

まず、電力素子13,14の発熱量は高いので、電力素子13,
14をリード端子22から離れた位置で基板11に搭載し、制
御素子12の発熱量は電力素子13,14に比べて低いので、
制御素子12をリード端子22側に搭載する。そして、リー
ド端子22を上側にして熱伝導媒体16を含有する絶縁封止
材15を用いてポツテイング法で絶縁封止する。
First, since the heat generation amount of the power elements 13 and 14 is high,
14 is mounted on the substrate 11 at a position away from the lead terminals 22, and the heat generation amount of the control element 12 is lower than that of the power elements 13 and 14,
The control element 12 is mounted on the lead terminal 22 side. Then, the lead terminal 22 is placed on the upper side, and the insulating sealing material 15 containing the heat conductive medium 16 is used to perform the insulating sealing by the potting method.

このとき使用する絶縁封止材15は、主剤と硬化剤とが別
々になつている2液混合熱硬化タイプのエポキシ樹脂で
あり、主剤および硬化剤に夫々熱伝導媒体16を含有して
おく。そして、主剤と硬化剤とを夫々別々に、その樹脂
が硬化することなく粘度が最小となる温度(例えば、80
℃)で1時間放置する。次に、主剤と硬化剤とを60℃に
保温された別々の撹拌用ステンレス製容器に移し連続的
に撹拌を続ける。この攪拌を続けながら、その一方で一
台の半導体装置の注入充填に必要な量を取り出し主剤と
硬化剤とを混合し、箱(ケース)23内に注入する。この
とき、箱23も40〜60℃に加熱保温しておく。注入後は、
そのエポキシ樹脂の所定の硬化温度で加熱し硬化させ
る。
The insulating sealing material 15 used at this time is a two-liquid mixed thermosetting type epoxy resin in which the main agent and the curing agent are separately provided, and the heat conduction medium 16 is contained in each of the main agent and the curing agent. Then, the main agent and the curing agent are separately separated from each other at a temperature (for example, 80
Left for 1 hour. Next, the main agent and the curing agent are transferred to separate stirring stainless steel containers kept at 60 ° C. and continuously stirred. While continuing this agitation, on the other hand, the amount necessary for the injection filling of one semiconductor device is taken out, the main agent and the curing agent are mixed, and the mixture is injected into the box (case) 23. At this time, the box 23 is also heated and kept at 40 to 60 ° C. After injection,
The epoxy resin is heated and cured at a predetermined curing temperature.

このようにすると、そのエポキシ樹脂に対する所定の時
間条件内で、熱伝導媒体16をエポキシ層の下部に沈降さ
せることができ、電力素子13,14の周辺に高熱伝導部17
と制御素子12の周辺に低熱伝導部18との2層を一工程で
形成することができる。
By doing so, the heat transfer medium 16 can be settled under the epoxy layer within a predetermined time condition for the epoxy resin, and the high heat transfer part 17 can be provided around the power elements 13 and 14.
In addition, it is possible to form two layers of the low thermal conductive portion 18 around the control element 12 in one step.

ここで、熱伝導媒体16の沈降について説明する。Here, sedimentation of the heat transfer medium 16 will be described.

液状エポキシ樹脂は非ニユートン流体であるが、高温に
して粘度を下げた状態では、ニユートン流体に対するス
トークスの法則を適用できると考える。すなわち、沈降
速度は、熱伝導媒体16の粒子半径の2乗に正比例し、粒
子と液体の密度差とに比例し、液体の粘度に逆比例す
る。
Liquid epoxy resin is a non-Newtonian fluid, but it is considered that Stokes' law for Newtonian fluid can be applied when the viscosity is lowered at high temperature. That is, the sedimentation velocity is directly proportional to the square of the particle radius of the heat transfer medium 16, proportional to the density difference between the particles and the liquid, and inversely proportional to the viscosity of the liquid.

したがつて、樹脂を高温にして粘度を下げれば熱伝導媒
体16の沈降は大きくなる。
Therefore, if the temperature of the resin is raised to lower the viscosity, the sedimentation of the heat transfer medium 16 increases.

また、エポキシ樹脂には熱伝導媒体16の沈降を防止する
ため超微粒シリカを含有している。この超微粒シリカ
は、多くのSi-OH基を有しており、シラノール基と水素
結合を起こして3次元の網の目構造を形成し熱伝導媒体
16の沈降を防止している。したがつて、絶縁封止材15を
高温で連続的に撹拌することによつて、この3次元の網
の目構造を分断し熱伝導媒体16を容易に沈降させること
になる。
Further, the epoxy resin contains ultrafine silica in order to prevent sedimentation of the heat transfer medium 16. This ultrafine silica has many Si-OH groups and forms hydrogen bonds with silanol groups to form a three-dimensional network structure, which is a heat transfer medium.
Prevents sedimentation of 16. Therefore, by continuously stirring the insulating sealing material 15 at a high temperature, the three-dimensional mesh structure is divided and the heat transfer medium 16 is easily settled.

以上のように、構成部品が一体となつた同一パツケージ
内において、絶縁封止材15の注型作業前に前処理として
絶縁封止材15を高温で連続的に撹拌し、注型作業途中に
おいても絶縁封止材15を高温保持してその粘度を低下さ
せることにより熱伝導媒体16の沈降速度を大にしている
ので、一工程で電力素子13,14を封止する高熱伝導部17
と、制御素子12を封止する低熱伝導部18との熱分離が有
効に行い得る。
As described above, in the same package in which the components are integrated, the insulating sealing material 15 is continuously stirred at a high temperature as a pretreatment before the casting operation of the insulating sealing material 15, and in the middle of the casting operation. Since the insulating sealing material 15 is kept at a high temperature and its viscosity is lowered to increase the sedimentation speed of the heat conducting medium 16, the high heat conducting portion 17 that seals the power elements 13 and 14 in one step.
And the low heat conductive portion 18 that seals the control element 12 can be effectively thermally separated.

また、これにより、同一パツケージ内に熱匂配をもたせ
ることができ、電子素子13,14の発熱する熱が制御素子1
2に伝達しにくくなり、半導体装置としては使用温度範
囲の設定を電力素子13,14側の許容接合温度範囲内で使
用できる様になるので、使用温度範囲の広い半導体装置
を提供できる。
Further, this makes it possible to provide a thermal odor in the same package, and the heat generated by the electronic elements 13 and 14 is controlled by the control element 1.
2 is difficult to transmit, and the setting of the operating temperature range of the semiconductor device can be used within the allowable junction temperature range on the side of the power elements 13 and 14, so that a semiconductor device having a wide operating temperature range can be provided.

なお、本発明は、上記実施例に限定されるものではな
く、本発明の範囲内で上記実施例に多くの修正および変
更を加え得ることは勿論である。
The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.

例えば、エポキシ樹脂の初期加熱速度、混合時の保温温
度を調整することにより熱伝導媒体の密度分布を変える
ことができるので、内蔵される半導体素子の許容温度に
最適の絶縁封止をつくることができる。
For example, since the density distribution of the heat conductive medium can be changed by adjusting the initial heating rate of the epoxy resin and the heat retention temperature at the time of mixing, it is possible to create the optimum insulating seal for the allowable temperature of the built-in semiconductor element. it can.

また、上記実施例ではポツテイング法で説明したが、第
2図に示すようにキヤステイング法でも同様な効果を得
ることができる。
Although the potting method has been described in the above embodiment, the casting method can also obtain the same effect as shown in FIG.

〈発明の効果〉 以上の説明から明らかな通り、本発明によると、絶縁封
止材の注型作業前に前処理として絶縁封止材を高温で連
続的に撹拌し、注型作業途中においても絶縁封止材を高
温保持してその粘度を低下させることにより熱伝導媒体
の沈降速度を大にしているので、一工程で電力素子を封
止する高熱伝導部と、制御素子を封止する低熱伝導部と
の熱分離が有効に行い得る。
<Effects of the Invention> As is apparent from the above description, according to the present invention, the insulating sealing material is continuously stirred at a high temperature as a pretreatment before the casting operation of the insulating sealing material, and even during the casting operation. By keeping the insulating encapsulant at a high temperature and decreasing its viscosity, the sedimentation speed of the heat-conducting medium is increased. The heat separation from the conductive portion can be effectively performed.

また、これにより、同一パツケージ内に熱匂配をもたせ
ることができ、電子素子の発熱する熱が制御素子に伝達
しにくくなり、半導体装置としては使用温度範囲の設定
を電力素子側の許容接合温度範囲内で使用できる様にな
るので、使用温度範囲の広い半導体装置を提供できる。
Further, this makes it possible to have a thermal gradient in the same package, and it becomes difficult for the heat generated by the electronic element to be transmitted to the control element, and the setting of the operating temperature range for the semiconductor device is set to the allowable junction temperature on the power element side. Since it can be used within the range, it is possible to provide a semiconductor device having a wide operating temperature range.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示すポツテイング法で絶縁
封止された半導体装置の断面図、第2図は本発明の他の
実施例を示すキヤステイング法で絶縁封止された場合の
半導体装置の断面図、第3図は従来の半導体装置の断面
図である。 11:基板、12:制御素子、13,14:電力素子、15:絶縁封止
材、16:熱伝導媒体(フイラー)、17:高熱伝導部、18:
低熱伝導部。
FIG. 1 is a sectional view of a semiconductor device which is insulation-sealed by a potting method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device which is insulation-sealed by a casting method according to another embodiment of the present invention. FIG. 3 is a sectional view of a semiconductor device, and FIG. 3 is a sectional view of a conventional semiconductor device. 11: Substrate, 12: Control element, 13, 14: Power element, 15: Insulation sealing material, 16: Thermal conductive medium (filler), 17: High thermal conductive part, 18:
Low heat conduction part.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/31 25/04 25/16 A 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 23/31 25/04 25/16 A 25/18

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板上に制御素子と電力素子とを組み合わ
せた複合素子を搭載し、これらを熱伝導媒体を含有する
絶縁封止材で一体的に封止する半導体装置の製造方法に
おいて、絶縁封止材の注型作業前に前処理として絶縁封
止材を高温で連続的に撹拌し、注型作業途中においても
絶縁封止材を高温保持してその粘度を低下させることに
より熱伝導媒体の沈降速度を大にし、電力素子の周辺に
高熱伝導部を形成すると共に制御素子の周辺に低熱伝導
部を形成して高熱伝導部と低熱伝導部との二層に分離す
ることを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising: mounting a composite element, which is a combination of a control element and a power element, on a substrate; and integrally sealing these elements with an insulating encapsulant containing a heat transfer medium. As a pretreatment before casting the sealing material, the insulating sealing material is continuously stirred at a high temperature, and the insulating sealing material is kept at a high temperature even during the casting operation to reduce the viscosity of the insulating material and thereby achieve a heat transfer medium. The high settling velocity of the power element is increased to form a high heat conductive part around the power element and a low heat conductive part around the control element to separate the high heat conductive part and the low heat conductive part into two layers. Manufacturing method of semiconductor device.
JP16792989A 1989-06-28 1989-06-28 Method for manufacturing semiconductor device Expired - Fee Related JPH0713984B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16792989A JPH0713984B2 (en) 1989-06-28 1989-06-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16792989A JPH0713984B2 (en) 1989-06-28 1989-06-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0332032A JPH0332032A (en) 1991-02-12
JPH0713984B2 true JPH0713984B2 (en) 1995-02-15

Family

ID=15858676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16792989A Expired - Fee Related JPH0713984B2 (en) 1989-06-28 1989-06-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0713984B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69637809D1 (en) * 1996-11-28 2009-02-26 Mitsubishi Electric Corp SEMICONDUCTOR DEVICE
JP2010199152A (en) * 2009-02-23 2010-09-09 Denso Corp Mold sealing method of electronic component and electronic component made by the same

Also Published As

Publication number Publication date
JPH0332032A (en) 1991-02-12

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