JP2506948B2 - Time axis correction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device for correcting time axis fluctuation of a reproduction signal in a signal reproduction device such as a video tape recorder (VTR).

2. Description of the Related Art In recent years, in a signal reproducing apparatus such as a VTR for broadcasting, a digital type time axis correcting apparatus is widely used to correct a time axis fluctuation of a reproduced signal.

An example of the conventional time axis correction device described above will be described below with reference to the drawings.

FIG. 6 is a schematic configuration diagram of a conventional time axis correction device. A signal including time axis fluctuation is input from the input terminal 1. The write clock generation circuit 2 generates a clock that follows the fluctuation of the input signal on the time axis and supplies it to the AD converter 3, the memory control circuit 5, and the like. In AD converter 3, input terminal 1
The input signal from is sampled by a clock that follows the time-axis fluctuation of the input signal generated by the write clock generation circuit 2, converted into a digital signal, and temporarily stored in the memory 4. On the other hand, the read clock generation circuit 7 generates a fixed clock that does not fluctuate on the time axis, reads the signal stored in the memory 4 in synchronization with this fixed clock, converts it into an analog signal again with the DA converter 6, and outputs it. Output from 8. The memory control circuit 5 uses two asynchronous clock signals, a write clock and a read clock, to control the memory such that writing and reading are apparently independent and in parallel.

Next, the principle of correcting the time base fluctuation will be described on the time base with reference to FIG. FIG. 7 (a) is an original signal with no time-axis fluctuation, and the signal recorded / reproduced from this signal has time-axis fluctuation as shown in FIG. 7 (b), which is the input terminal 1 of FIG. Entered in. The AD converter 3 samples points 160 to 172 (indicated by ●) in FIG. 7 (b) with a clock that follows the time-axis fluctuation and once stores it in the memory. Then, this is fixed clock without time-axis fluctuation. By reading out in step (c), it is possible to obtain a signal whose time axis fluctuation has been corrected, as shown in FIG. 7 (c). (For example, “VTR Technology” edited by the Japan Broadcasting Corporation, (Showa 57.10.20), Japan Broadcast Publishing Association, P. 118) Problems to be Solved by the Invention However, in the above configuration, the time-axis fluctuation of the input signal is An analog means is needed to generate the tracked clock. Therefore, the accuracy of the time axis correction is affected by variations in the analog circuit elements and temperature changes. Moreover, it becomes an obstacle when the whole device is made into a semiconductor. Further, since it is controlled by the two asynchronous clock signals of the write clock and the read clock, it interferes with the coupling with other digital processing circuits. Besides,
It is necessary to control the memory so that writing and reading are apparently independent and performed in parallel with two asynchronous clock signals, which complicates the memory configuration and memory control, and causes a large-scale circuit. Had a point.

The present invention focuses on the above problems, and an object thereof is to provide a time axis correction device capable of performing stable and highly accurate time axis correction without being affected by variations in circuit elements or temperature changes. Another object of the present invention is to provide a time axis correction apparatus which can be made into a semiconductor as a whole and which operates only with one system of clocks without time axis fluctuation.

Means for Solving the Problems In order to achieve the above object, a time axis correction device of the present invention is an AD converter that samples an input signal at a constant time interval and converts it into a digital signal, and the AD converter Time axis error detecting means for detecting a time error from the digital signal and outputting the time axis error information, and interpolation obtained by interpolating the signal amplitude based on the time axis error information from the digital signal obtained by the AD converter. Means, and a DA converter for converting the output signal of the interpolation means into an analog signal,
The interpolation means delays the input signal of the interpolation means to obtain sample values at a plurality of consecutive sample points,
Selection means for selecting and outputting a predetermined number of sample values before and after the time to be interpolated based on the time axis error information from sample values of the plurality of sample points, and to the selected predetermined number of sample values Coefficient generation means for obtaining a plurality of coefficients based on the time axis error information, a plurality of multiplication means for multiplying the plurality of coefficients respectively, and outputs of the plurality of multiplication means are added to obtain an interpolation output of the interpolation means. And adding means.

Action The present invention has the above-mentioned configuration and is configured to interpolate a signal corrected for time-axis fluctuations from a signal sampled with a clock having no time-axis fluctuations. No clock is required, and the entire device operates with only one system of clock that does not fluctuate on the time axis. Therefore, there is no need for analog means for generating a clock that follows the fluctuation of the input signal on the time axis.

Embodiment An embodiment of the time axis correction device of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of a time axis correction device of the present invention. In FIG. 1, a reproduction signal including a time base fluctuation is input from an input terminal 1. Clock generation circuit 107
Generates a clock with a constant cycle without time axis fluctuation, and AD converter 103, DA converter 106, and time axis error detection circuit 10
Supplied to 2, etc. In the AD converter 103, the input signal from the input terminal 1 is sampled by the clock having a constant cycle generated by the clock generation circuit 107 and converted into a digital signal.
This digital signal is guided to the time axis error detection circuit 102 and the interpolation circuit 104. In the time axis error detection circuit 102,
A time axis error is detected from the synchronizing signal or burst signal of the input digital signal, and the time axis error information is input to the interpolation circuit 104. On the other hand, the interpolation circuit 104 interpolates and obtains a signal whose time-axis error has been corrected from the signal digitized by the AD converter 103, based on the time-axis error information obtained from the time-axis error detection circuit 102. The signal with the corrected time axis error is supplied to the DA converter 106, converted into an analog signal, and output from the output terminal 8.

Next, the principle of correcting the time base fluctuation will be described on the time base using FIG. 7 as in the case of the prior art example. Seventh
In contrast to the original signal having no time-axis fluctuation shown in FIG. 10A, the signal reproduced by the VTR or the like has time-axis fluctuation as shown in FIG. 9B, and this is input to the input terminal 1 in FIG. . The AD converter 103 uses a clock with a constant cycle that does not fluctuate on the time axis.
Sample points 180 to 193 (indicated by □) in FIG. From the sampled signal, the sample value at the sample position synchronized with the time base fluctuation of the input signal in the interpolation circuit 104, that is, the seventh value
Same as the sampling points in the conventional example of FIG.
(Indicated by) is interpolated and obtained. As a result, as shown in FIG. 7 (c), it is possible to obtain a signal whose time axis fluctuation is corrected.

Here, the principle of interpolation in the interpolation circuit 104 will be described. Now, let the signal input to the input terminal 1 be v (t),
When the sampling period is T, the signal sampled by the AD converter 103 is represented by v (kt) (k is an integer). v
Since (t) is band-limited to a frequency equal to or less than 1/2 of the sampling frequency so as to satisfy the sampling theorem, the signal v (τ) at τ is sampled from the signal sampled at τ at any time by the sampling theorem. It can be obtained by the formula.

Here, s (t) is an interpolation function, and the input signal v
When the maximum frequency fm of (t) and the sampling frequency are fs = 1 / T, the transfer function S (f) (f is frequency) is at least Equal to the impulse response of a filter that satisfies. For example,
When the ideal low-pass filter whose frequency characteristic is shown in FIG. 2 is used as S (f), the interpolation function S which is its impulse response.
(T) is expressed by the following equation.

By the way, according to the formula, to obtain v (τ),
It is necessary to calculate k = −∽ to + ∽, and this calculation cannot be executed. However, in the present invention, since the signal is treated as a digital signal, there is no problem in practical use if it is obtained by v (τ) with an error within (1 quantization step) / 2. Therefore, the following formula is used.

Here, N and M are integers with finite values, and may be set so that the error of v (τ) obtained as described above is sufficiently small. As a result, the time τ at the sample position synchronized with the time axis fluctuation of the input signal can be obtained from the time axis error information obtained by the time axis error detection circuit 102, and the sample value at this time can be obtained by the equation.

Next, a specific example of the interpolation circuit 104 that performs the above-described interpolation will be described.

FIG. 3 shows a configuration example of the interpolation circuit 104. Here, a case where M and N in the equation satisfy N−M + 1 = 4, that is, a case where an interpolation output is obtained from four sample points will be described. Although each signal line is shown as a single line for simplicity, it actually transmits a signal of a plurality of bits. In FIG. 3, the signal input from the input terminal 111 of the interpolation circuit is input to the shift register 112 including a plurality of D-flip-flops. Shift register 112
From the respective D-flip-flops, the signals delayed by the clock unit are taken out, and guided to the selection circuit 119 as a pair of sampling points consisting of four consecutive sample values 113 to 118. The selection circuit 119 selects one of the sample point pairs indicated by 113 to 118 based on the error information 134 in units of clock cycles, which will be described later, and connects it to the sample point pair 120.

On the other hand, from the time axis error information input terminal 135, the time axis error information obtained by the time axis error detection circuit 102 of FIG. 1 is input. The time axis error information is the time axis error processing circuit.
In 133, it is converted into error information 134 in units of clock cycles and error information 132 within one clock cycle. This clock cycle unit error information 134 and one clock cycle error information 132
This will be described with reference to FIG. In FIG. 4, the horizontal axis represents time and the vertical axis represents the input signal amplitude. 140 to 148 indicated by □ are sample points, and each D of the shift register 112
-It is output from the flip-flop, and
150 indicated by is a sample point to be interpolated. Here, the error information 134 in clock units serves as a control signal for the selection circuit 119 to select a sample point pair consisting of four sample points 142 to 145 sandwiching the sample point 150 to be interpolated from both sides. Also, the error information within one clock cycle 13
2 indicates the time base error within one clock cycle indicated by Δt in FIG.

Now, the four sample values of the output sample point pair 120 of the selection circuit in FIG. 3 are guided to the multiplication circuits 121 to 124, respectively. On the other hand, the error information 132 within one clock period is input to the coefficient generation circuit 131, and the coefficient signals 127 to 130 are input to the other input terminals of the multiplication circuits 121 to 124, respectively. The coefficient signals 127 to 130 are s (τ ₋ T), s in the equation, respectively.
(Τ _- 2T), s (τ _- 3T), s (τ _- 4T), the coefficient generation circuit 131 is constituted by a ROM or the like. The output signals of the multiplication circuits 121 to 124 are added in the addition circuit 125 and output from the output terminal 126 as an interpolation output.

As described above, the interpolation circuit 104 that obtains the interpolation output represented by the equation can be configured.

Although a case of N−M + 1 = 4 has been described here for simplicity, N and M are set so that the error due to interpolation is sufficiently small. Also, the number of stages of the shift register may be determined according to the required time axis correction range.

As described above, according to the present embodiment, since the signal corrected for the time axis fluctuation is interpolated from the signal sampled by the clock having no time axis fluctuation, the entire apparatus does not have the time axis fluctuation. It can be operated with only one clock. In addition, all are composed of digital circuits, and analog circuits are not required. Further, since the time-axis error information is obtained from the signal before the time-axis correction, the feed-forward control is performed, and it is possible to respond to the time-axis fluctuation with high flux.

Here, in the previous embodiment, the equation which is the impulse response of the ideal low-pass filter is shown as the interpolation function, but when the maximum frequency fm of the input signal is smaller than 1/2 of the sampling frequency fs, As shown in FIG. 5, an impulse response of a filter having a frequency characteristic that satisfies the formula and smoothly changes fm to (fs−fm), for example, an interpolation function shown in the following formula may be used.

As a result, the value of N−M + 1 in the equation for sufficiently reducing the error due to interpolation, that is, the number of sampling points required for interpolation can be significantly reduced, and as a result, the circuit scale of the interpolation circuit can be reduced. .

Further, in the interpolation circuit of this embodiment, the shift register is used as the delay means and the selection circuit is used as the selection means, but the present invention is not limited to this. That is, a random access memory (RAM) may be used as the delay means and an address circuit of the memory may be used as the selection means.

EFFECTS OF THE INVENTION As described above, the present invention is configured to interpolate a signal whose time axis fluctuation is corrected from a signal sampled with a clock having no time axis fluctuation. Therefore, an analog means for obtaining a clock that follows the fluctuation of the input signal on the time axis is not required, and all can be configured by digital circuits. As a result, stable and highly accurate time axis correction can be performed without being affected by variations in circuit elements and temperature changes. Furthermore, since the entire device can be made into a semiconductor, downsizing and cost reduction can be achieved. Further, since the operation is performed by only one system clock having no time-axis fluctuation, complicated memory control by two system clocks is not necessary, and it is easy to connect with other digital processing circuits. In addition to these, the feedforward control has an excellent effect that it can respond to the fluctuation of the time axis at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a time axis correction device of the present invention, FIGS. 2 and 5 are frequency characteristic diagrams of an interpolation function in an interpolation circuit of an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a block diagram of an interpolation circuit in an example, FIG. 4 is an operation explanatory diagram of the interpolation circuit shown in FIG. 3, FIG. 6 is a block diagram of a conventional time axis correction device, and FIG. 7 is a conventional and an embodiment of the present invention. FIG. 103 ... AD converter, 104 ... Interpolation circuit, 102 ... Time axis error detection circuit, 107 ... DA converter.

Claims (1)

(57) [Claims] 1. An AD converter for sampling an input signal at fixed time intervals and converting it into a digital signal, and a time axis for detecting a time error from the digital signal obtained by the AD converter and outputting time axis error information. Error detection means, interpolation means obtained by interpolating the signal amplitude from the digital signal obtained by the AD converter based on the time axis error information, and DA converter for converting the output signal of the interpolation means into an analog signal The interpolating means delays the input signal of the interpolating means to obtain sample values at a plurality of consecutive sample points, and interpolates the sample values of the plurality of sample points based on the time error information. Selecting means for selecting and outputting a predetermined number of sample values before and after the time to be performed, and coefficient generating means for obtaining a plurality of coefficients based on the time error information for the selected predetermined number of sample values , Wherein the plurality of the plurality of multiplying means for multiplying each coefficient, the plurality of adding outputs of the multiplication means the time base corrector with an adding means for obtaining an interpolated output of the interpolation means.