JPH0210979A - Time base correction device - Google Patents

Abstract

PURPOSE:To constitute the device by digital circuits only and to attain stable time base correction with high accuracy by interpolating a signal subject to time base fluctuation correction and obtaining the result from a signal sampled by a clock not having a time base fluctuation. CONSTITUTION:An AD converter 103 uses a clock of a prescribed period generated from a clock generating circuit 107 so as to sample an input signal from an input terminal 1 and converts the signal into a digital signal. This signal is led to a time base error detection circuit 102 and an interpolation circuit 104. A time base error is detected from a synchronizing signal and a burst signal of the inputted digital signal in the circuit 102 and time base error information is given to the circuit 104. On the other hand, based on the time base error information obtained from the circuit 102, the circuit 104 interpolates the signal subject to time base error correction from the digitized signal. The signal subject to time base error correction is fed to a DA converter 106, in which the signal is converted into an analog signal and outputted from an output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time axis correction device for correcting time axis fluctuations of a reproduced signal in a signal reproducing apparatus such as a video tape recorder (VTR).

2. Description of the Related Art In recent years, digital time axis correction devices have been widely used in signal reproducing apparatuses such as broadcasting VTRs to correct time axis fluctuations of reproduced signals.

An example of the above-mentioned conventional time axis correction device will be described below with reference to the drawings.

FIG. 6 is a schematic diagram of a conventional time axis correction device. A signal including time axis fluctuation is input from input terminal 1 .

The write clock generation circuit 2 generates a clock that follows the time axis fluctuation of the input signal and supplies it to the AD converter 3, memory control circuit 5, and the like.

The AD converter 3 samples the input signal from the input terminal 1 using a clock that follows the time axis fluctuation of the input signal generated by the write clock generation circuit 2, converts it into a digital signal, and temporarily stores it in the memory 4.

On the other hand, the read clock generation circuit 7 generates a fixed clock with no time axis fluctuation, reads out the signal stored in the memory 4 in synchronization with this fixed clock, converts it back to an analog signal in the DA converter 6, and outputs it to the output terminal. Output from 8.

Note that the memory control circuit 5 controls the memory using two asynchronous clock signals, a write clock and a read clock, so that overwriting and reading are apparently performed independently and in parallel.

Next, the principle by which time axis fluctuations are corrected will be explained on the time axis using FIG. Figure 7(a) shows the original signal with no time axis fluctuations, and the signal recorded and reproduced from this signal has time axis fluctuations as shown in Figure 6. is input. The AD converter 3 samples points 160 to 172 (indicated by .) in Figure 7) using a clock that follows time axis fluctuations, temporarily stores them in memory, and then samples them using a fixed clock that does not have time axis fluctuations. By reading,
As shown in FIG. 7(C), a signal with time axis fluctuations corrected can be obtained. (For example, Japan Broadcasting Corporation record rVTR
"Technology", (October 20, 1982), Japan Broadcasting Publishing Association,
P, 118) Problems to be Solved by the Invention However, the above configuration requires analog means for generating a clock that follows the time axis fluctuations of the input signal. Therefore, the accuracy of time axis correction is affected by variations in analog circuit elements, temperature changes, and the like. Moreover, it becomes an obstacle when converting the entire device into a semiconductor. Furthermore, since it is controlled by two asynchronous clock signals, a write clock and a read clock, it becomes an obstacle in coupling with other digital processing circuits. Moreover, 2
It is necessary to control the memory so that overwriting and subsequent writing are performed apparently independently and in parallel using two asynchronous clock signals, which complicates the memory configuration and memory control, making the circuit large-scale, etc. It had the following problems.

The present invention has focused on the above-mentioned problems, and an object of the present invention is to provide a time axis correction device that can perform stable and highly accurate time axis correction without being affected by variations in circuit elements or temperature changes. A further object of the present invention is to provide a time axis correction device that can be made entirely of semiconductors and that operates only with one system of clocks without time axis fluctuations.

Means for Solving the Problems In order to achieve the above object, the time axis correction device of the present invention includes an AD converter that samples an input signal at regular time intervals and converts it into a digital signal, and a digital signal obtained by the AD converter. time-base error detection means for detecting a time-base error from a signal and outputting time-base error information; and a signal amplitude obtained by interpolating the digital signal obtained by the AD converter based on the time-base error information. The apparatus includes an interpolation means and a DA converter that converts the output signal of the interpolation means into an analog signal.

Operation The present invention has the above-described configuration to obtain a signal whose time axis fluctuations have been corrected by interpolating from a signal sampled by a clock that does not have time axis fluctuations, so that it can follow the time axis fluctuations of the input signal. There is no need for a separate clock, and the entire device operates with only one system of clocks with no time axis fluctuations. Further, for this reason, analog means for generating a clock that follows the time axis fluctuations of the input signal is not required.

Embodiment An embodiment of the time axis correction device of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of the time axis correction device of the present invention. In FIG. 1, a reproduced signal including time axis fluctuations is input from an input terminal 1. Clock generation circuit 107
In this case, a clock having a constant period without time axis fluctuation is generated and supplied to the AD converter 103, the DA converter 106, the time axis error detection circuit 102, and the like. In the AD converter 103, the input signal from the input terminal 1 is sent to the clock generation circuit 10.
The signal is sampled using a constant cycle clock generated in step 7 and converted into a digital signal. This digital signal is guided to a time axis error detection circuit 102 and an interpolation circuit 104. In the time axis error detection circuit 102, a time axis error is detected from the synchronization signal, burst signal, etc. of the input digital signal, and the time axis error is detected. The information is input to interpolation circuit 104. On the other hand, the interpolation circuit 104 interpolates a signal whose time axis error has been corrected from the signal digitized by the AD converter 103 based on the time axis error information obtained from the time axis error detection circuit 102. The signal with time axis error corrected is DA
The signal is supplied to the converter 106, converted into an analog signal, and outputted from the output terminal 8.

Next, as in the case of the prior art example, the principle of correcting time axis fluctuations will be explained on the time axis using FIG. In contrast to the original signal shown in FIG. 7(a), which has no time axis variation, the signal reproduced by a VTR etc. has time axis variation as shown in FIG. . The AD converter 103 samples points 180 to 193 (indicated by the numbers) in FIG. From the sampled signal, the interpolation circuit 104 calculates a sample value at a sample position synchronized with the time axis fluctuation of the input signal,
That is, sample values of 160 to 172 (indicated by *), which are the same as the sampling points in the conventional example shown in FIG. 7, are obtained by interpolation. As a result, as shown in FIG. 7(C), a signal with time axis fluctuations corrected can be obtained.

Here, the interpolation principle in interpolation circuit [04] will be explained. Now, the signal input to input terminal 1 is expressed as v (tl
, when the sampling period is T, the signal sampled by the AD converter 103 is expressed as v(kT) (k is an integer). Since v(t) is band-limited to a frequency less than 1/2 of the sampling frequency to satisfy the sampling theorem, the sampling theorem allows the signal V(t) at τ to be sampled at any time. It can be determined by the following equation 0.

v (T)−Σ v (kT) ・s (r −k
t) −■=−■ Here, 5(t) is an interpolation function, and the input signal v(t)
When the maximum frequency fm and the sampling frequency are fs-1/T, the transfer function 5(f) (f is the frequency) is at least equal to the impulse response of the filter that satisfies 0. For example,
When a low-pass filter whose frequency characteristics are shown in FIG. 2 is used as S Cf>, the interpolation function S (t''), which is the impulse response, is expressed by the following equation.

(π/T) ・t By the way, according to formula 0, in order to find V(τ), k
It is necessary to calculate −−ω to +ψ, and this calculation cannot be performed. However, in the present invention, since the signal is treated as a digital signal, there is no problem in practice as long as V(τ) can be determined with an error within (1 quantization step) 72. Therefore, the following equation 0 is used.

v(r)# Σ v (kT) ・s (t −kt
) −■where N and M are integers of finite value,
It is only necessary to set the error of V(τ) determined as described above to be sufficiently small.
The time τ of the sample position synchronized with the time axis fluctuation of the input signal can be obtained from the time axis error information obtained by 02, and the sample value at this time can be obtained using the equation 0.

Next, a specific embodiment of the interpolation circuit 104 that performs the above-mentioned interpolation will be described.

FIG. 3 shows an example of the configuration of the interpolation circuit 104, and here we will discuss the case where M and N in equation 0 satisfy N-M+1-4, that is, the case where interpolated output is obtained from four sample points. Furthermore, although each signal line is shown as one line for simplicity, it actually transmits a plurality of bits of signals. In FIG. 3, a signal input from an input terminal 111 of the interpolation circuit is input to a shift register 112 consisting of a plurality of D-flip-flops. From the shift register 112, signals delayed in clock units are taken out from the respective D-flip-flops, and the signals 113-
The sample points are guided to the selection circuit 119 as a sample point pair consisting of four consecutive sample values indicated by 118. The selection circuit 119 selects one of the sample point pairs 113 to 118 based on error information 134 in units of clock cycles, which will be described later, and connects it to the sample point pair 120 .

On the other hand, from the time axis error information input terminal 135, the time axis error information obtained by the time axis error detection circuit 102 of FIG. It is converted into unit error information 134 and error information 132 within one clock period. The error information 134 per clock cycle and the error information 132 within one clock cycle will be explained using FIG. 4.

In FIG. 4, the horizontal axis shows time and the vertical axis shows the input signal amplitude. Days 140 to 14, indicated by 0, are sample points, which are output from each D-flip-flop of the shift register 112. 150, which is indicated by "Yes" and ".", is a sample point to be obtained by interpolation.

Here, the error information 134 in units of clocks becomes a control signal for the selection circuit 119 to select a sample point pair consisting of four sample points 142 to 145 sandwiching the sample point 150 to be obtained by interpolation from both sides. Furthermore, the error information 132 within one clock period indicates a time axis error within one clock period, which is indicated by Δt in FIG.

Now, the four sample values of the output sample point pair 120 of the selection circuit in FIG. 3 are guided to multiplication circuits 121 to 124, respectively. On the other hand, error information 132 within one clock cycle is input to the coefficient generation circuit 131, and the coefficient signals 127 to 132 are input to the coefficient generation circuit 131.
are input to the other input terminals of multiplication circuits 121 to 124, respectively. The coefficient signals 127 to 130 are respectively S(τ-T) and s(τ-27)s(τ-3
7) A signal representing s (τ-4T), which is constituted by the coefficient generation circuit 131, ROM, etc. The output signals of the multiplier circuits 121 to 124 are added in an adder circuit 125 and output from an output terminal 126 as an interpolated output.

In the manner described above, the interpolation circuit 104 that obtains the interpolation output shown by equation (2) can be constructed.

Note that here we have explained the case of N-M+1-4 for simplicity, but N
and M are set. Also, the number of stages of the shift register is
It may be determined according to the required time axis correction range.

As explained above, according to this embodiment, a signal with time axis fluctuations corrected is obtained by interpolating a signal sampled by a clock that does not have time axis fluctuations, so that the entire device has no time axis fluctuations. It can be operated with only one clock system. Furthermore, it is constructed entirely of digital circuits and does not require analog circuits. Furthermore, since the configuration is such that time axis error information is obtained from a signal before time axis correction, feedforward control is performed, and it is possible to respond to time axis fluctuations with high flux.

In addition, in the previous example, equation 0, which is the impulse response of an ideal low-pass filter, was shown as the interpolation function, but if the maximum frequency fm of the input signal is smaller than 1/2 of S, As shown in FIG. 5, the impulse response of a filter that satisfies the equation 0 and has a frequency characteristic that smoothly changes fm ~ (fs - fm) may be used, for example, the interpolation function shown in the following equation 0 may be used. .

5(t) = ・sin ((g/l
)・tlπ・L X cos (x(2fm-1/T)・tlX
1/(14(2fm-1/T)"・L2) This greatly reduces the value of N-M+1 in formula (■) to sufficiently reduce the error caused by interpolation, that is, the number of sample points required for interpolation. As a result, the circuit scale of the interpolation circuit can be reduced.

Further, in the interpolation circuit of this embodiment, a shift register is used as the delay means, and a selection circuit is used as the selection means, but the present invention is not limited to this. In other words, a random access memory (RAM) is used as the delay means. , a memory address circuit may be used as the selection means.

Effects of the Invention As described above, the present invention is configured to interpolate and obtain a signal with time axis fluctuations corrected from a signal sampled with a clock having no time axis fluctuations. Therefore, there is no need for analog means for obtaining a clock that follows the time-base fluctuations of the input signal, and the entire system can be constructed using digital circuits. As a result, stable and highly accurate time axis correction can be performed without being affected by variations in circuit elements or temperature changes. Furthermore, since the entire device can be made into a semiconductor, it becomes possible to reduce the size and cost. Furthermore, since it operates with only one system of clocks having no time axis fluctuations, complicated memory control using two systems of clocks is not necessary, and it is easy to connect with other digital processing circuits. In addition to these, since it is a feedforward control, it has excellent effects such as being able to respond quickly to time axis fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the time axis correction device of the present invention, FIGS. 2 and 5 are frequency characteristic diagrams of the interpolation function in the interpolation circuit of the embodiment of the present invention, and FIG. 3 is a diagram of the implementation of the present invention. FIG. 4 is an explanatory diagram of the operation of the interpolation circuit shown in FIG. 3, FIG. 6 is a configuration diagram of a conventional time axis correction device, and FIG. 7 is a diagram of the conventional and embodiments of the present invention. It is an operation explanatory diagram. 103... AD converter, 104... Interpolation circuit, 102... Time axis error detection circuit, 10
7...DA converter. Name of agent: Patent attorney Toshio Nakao Diagram

Claims (2)

[Claims] (1) An AD converter that samples an input signal at regular time intervals and converts it into a digital signal, and a time axis error that detects a time axis error from the digital signal obtained by the AD converter and outputs time axis error information. a detection means, an interpolation means for interpolating the signal amplitude from the digital signal obtained by the AD converter based on the time axis error information, and a DA converter for converting the output signal of the interpolation means into an analog signal. A time axis correction device equipped with. (2) The interpolation means includes a delay means for delaying the input signal of the interpolation means to obtain sample values at a plurality of consecutive sample points, and a predetermined number of sample values from the sample values at the plurality of sample points on a time axis. selection means for selecting and outputting based on error information; coefficient generation means for obtaining a plurality of coefficients based on the time axis error information for the selected predetermined number of sample values; Claim 1 characterized in that it comprises a plurality of multiplication means for multiplying coefficients, and an addition means for adding the outputs of the plurality of multiplication means to obtain an interpolated output of the interpolation means.
) Time axis correction device described.