JP2785426B2 - Time axis correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device used for correcting a time axis fluctuation included in a reproduction signal of a video tape recorder (VTR) or the like.

2. Description of the Related Art Generally, in a VTR, time axis fluctuation occurs in a reproduced signal due to uneven rotation speed of a head / drum cylinder or the like. This time-axis variation causes image quality deterioration due to phase variation in the case of a color signal. As a means for improving the image quality deterioration due to the time axis fluctuation, a time axis correction device (or a time base collector) is used (for example, "Time axis fluctuation and its correction method" Konishi et al.
Journal of the Institute of Television Engineers of Japan 495-503, Vol. 3, No. 6, 1981
Year).

Hereinafter, an example of a conventional time axis correction device will be described with reference to the drawings.

FIG. 6 is a block diagram showing a configuration of a main part of a conventional time axis correction device. In FIG. 6, a reproduced video signal of a VTR is input from a terminal 101 and input to an AD converter 102 and a PLL circuit 104.

The PLL circuit 104 generates a clock synchronized with the phase of the synchronization signal or the color burst signal in the input video signal. This clock has a frequency of, for example, 13.5 MHz or four times the color subcarrier, and is input to the AD converter 102 and the memory 103. The clock generated from the PLL circuit 104 stores a time-axis fluctuation component for each horizontal synchronization period, and thus fluctuates according to the time-axis fluctuation of the input video signal. FIG. 7A shows this state. A clock having a phase variation shown by a broken line with respect to a time axis variation (phase variation) shown by a solid line is generated from the PLL circuit 104.

Using this clock, the input video signal is
The signal is converted into a digital signal in 2 and is simultaneously written into the memory 103. This writing operation removes the time axis fluctuation.

Further, in the PLL circuit 104, the phase of the clock is adjusted every one horizontal synchronization period, so that the phase error of the phase comparator in the PLL circuit 104 indicates the difference from the phase 1H before. FIG. 7 (b) shows the state of the phase error. This phase error is input to the velocity error control circuit 105.

In the velocity error control circuit 105, processing such as linear approximation (first-order hold) of the phase error for each 1H is performed.
Input to phase modulator 106. FIG. 7 (c) shows an example of the case of linear approximation. In the phase modulator 106, an accurate clock having no time-axis fluctuation output from the reference signal generator 107 is phase-modulated and input to the memory 103 and the DA converter 108.

The digital signal is read from the memory 103 by the clock output from the phase modulator 106, and is read by the DA converter 108.
It is DA converted and converted to an analog video signal corrected for velocity error.

Problems to be Solved by the Invention However, in the above conventional configuration, in order to oscillate the clock of the DA converter in order to correct the velocity error,
The output data of the memory is in a state including time axis fluctuation.
For this reason, for example, when trying to perform three-dimensional digital signal processing in the frame direction, inconvenience such as not being able to obtain a frame difference signal properly occurs.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a time axis correction apparatus which can obtain a digital signal without a time axis fluctuation at a fixed sampling period, which is different from the conventional time axis correction apparatus. And

Means for Solving the Problems In order to achieve this object, a time axis correction apparatus according to the present invention is provided with an AD converter that samples an input signal with a clock at fixed time intervals and converts it into a digital signal, and an AD converter. A memory for temporarily storing the obtained digital signal based on the same clock, a time axis error detecting means for detecting a time axis error of the digital signal obtained by the AD converter and outputting it as time axis error information, and a digital signal output from the memory. And interpolating means for interpolating the signal amplitude based on the time axis error information to obtain a digital signal having a reference time axis.

Operation The present invention corrects a time-axis variation included in a video signal sampled at a fixed time interval without swinging the clock by the above-described configuration.

Hereinafter, a time axis correction device according to an embodiment of the present invention will be described.
This will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of a time axis correction device according to an embodiment of the present invention. In FIG. 1, a reproduced video signal such as a VTR is input from a terminal 1 and an AD converter 2
Is input to In the AD converter 2, the reference signal generator 7
Is converted into a digital signal by a clock of a fixed period outputted from the. The output of the AD converter 2 is input to a synchronization signal detector 4, where a synchronization signal is detected. The synchronization detection signal output from the synchronization signal detector 4 is input to the write control circuit 5.

The write control circuit 5 outputs a write address to the memory 3 in response to a clock output from the reference signal generator 7. The write control circuit 5 resets the write address of the memory when the synchronization signal detection signal is input. That is, every time a synchronization signal is detected, writing is performed from the beginning of the 1H memory. For example, as shown in FIG.
It is composed of three line memories having a capacity of 1H + α, and the head addresses of the respective line memories are 0000, 1000, and 2000. When a video signal is input as shown in FIG. 4A, a synchronization detection signal is output from the synchronization signal detector 4 as shown in FIG. Is cleared and the process moves to the start address of the next line memory.

On the other hand, the output of the AD converter 2 is input to the time axis error detecting means 6. Hereinafter, the time axis error detecting means 6 will be described with reference to FIG. 3 and FIG.

The output of the synchronization signal detector 4 is input from a terminal 51 to a time axis error calculation circuit 52. Also, from the terminal 50, the AD converter 2
Is input. The time axis error calculation circuit 52 detects a time axis fluctuation of one clock or less from either the color burst signal or the horizontal synchronization signal when the synchronization signal is detected. E ₁
The state is shown in FIG. This E ₁ and 1H delay 53
And the time axis fluctuation E ₀ 1H before the output of the above is input to the velocity error detector 54. On the other hand, in the counter 56, the terminal
Using the sync detection signal input from the clock and a terminal 51 which is input from the 55 counts the clock from E ₀ is detected until E ₁ is detected, velocity error and the count value k Input to the detector 54. In velocity error detector 54, using the time k and E _0, E _1, determining the time H _E of 1H by the following equation.

_{H E = (1-E 0} ) + k + E 1 The time time axis errors from T _E of H _E asked for time H ₀ exact 1H, detected from the velocity error detector 54.

T _E = H ₀ -H _E The T _E and E ₀ are inputted respectively to the delay 57 and 58, receive the delay to match the timing of the data read from the memory 3. After that, the following equation is processed by the divider 60, the adders 61 and 63, and the flip-flop 62 to obtain the time axis error information E _OUT .

E _OUT = E ₀ + (T _E / 858) × i where i takes a value from _{0 to} 858 and is 0 at the start address of the line memory, but in actuality, the integrator comprising the adder 61 and the flip-flop 62 It can be realized by the configuration. Also,
The constant 858 in the above equation is when the clock frequency is 13.5 MHz.
This is the number of 1H clocks.

The time axis error information E _OUT is output from the terminal 64 and input to the interpolation means 9.

Further, the data is sequentially input to the interpolation means 9 by the read address output from the read control circuit 8 in the memory 3.
The read control circuit 8 generates a read address with a clock output from the reference signal generator 7. For example, if the clock frequency is 13.5 MHz, 1H is 858 samples, so after reading 858 data, the address is reset to the start address of the next line memory.

The output from the memory 3 input to the interpolation means 9 is output by interpolating the amplitude of the input signal based on the time axis error information obtained by the time axis error detection means 6.

The principle of the interpolation means 9 will be briefly described. The output v (t) of the interpolation means 9 at an arbitrary time t can be obtained from the following sample value v (kT) using the following equation.

Here, T is a sampling interval, and s (t) is an interpolation function, for example, an impulse response of a cosine roll-off LPF. Hereinafter, a description will be given along one configuration example of the interpolation means 9 shown in FIG.

FIG. 2 shows, as an example, four neighboring points with respect to the time to be interpolated.
The case where interpolation is performed from a sample is shown.

The signal input from the memory 3 is input to the shift register 32, and the signal one clock before is supplied to the flip-flops 43 to 49.
Are sent in sequence. Assuming that data for four clocks from the shift register 32 is one set, a plurality of sets of data are
Is input to

Further, time axis error information output from the time axis error detecting means 6 is input from the terminal 34 and input to the time axis error processing circuit 35. The time axis error processing circuit 35 divides the time axis error into clock time errors and clock time errors of one clock time or less. Here, the clock means a clock used at the time of sampling. The time axis error in clock units is input to the selector 33, and the selector 33 outputs a set of data based on the information. The data selected by the selector 33 is input to multipliers 37 to 40, respectively.

On the other hand, the time axis error of one clock time or less of the output of the time axis error processing circuit 35 is input to the coefficient generator 36. The coefficient generator 36 generates an impulse response coefficient for interpolation based on the input time axis error of one clock time or less, and the coefficient is input to the multipliers 37 to 40.

In the multipliers 37 to 40, the data is multiplied by the coefficient and output to the adder 41. In the adder 41, a multiplier
The sum of the outputs of 37 to 40 is obtained and output from the terminal 42 as the output of the interpolation means 9.

As a result, the signal output from the interpolation means 9 is a signal having a reference time axis.

The output of the interpolating means 9 is input to a DA converter 10 and is converted into an analog signal by a clock of a fixed time interval of the output of the reference signal generator 7 and is output from a terminal 11 as a signal whose time axis fluctuation has been corrected. .

As described above, according to the present embodiment, it is possible to detect a time-axis variation from a signal sampled with a clock at a fixed time interval, and to correct the time-axis variation using the interpolation means on the same clock. .

As described above, according to the present invention, a signal whose time axis fluctuation has been corrected can be obtained on a clock at a fixed time interval. Therefore, even if another digital signal processing system is inserted after the interpolation means, there is no inconvenience. Does not occur, accurate signal processing can be performed, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of a time axis correction device according to a first embodiment of the present invention, FIG. 2 is a block diagram of an interpolation unit in the embodiment, and FIG. 3 is an example of a time axis error detection unit in the embodiment. FIG. 4 is a schematic diagram showing how to write to a memory in the embodiment, FIG. 5 is a schematic diagram used for explaining the principle of a time axis fluctuation detecting means in the embodiment, and FIG. Block diagram of time axis correction device, seventh
The figure is a waveform diagram of a velocity error. 2 ... AD converter, 3 ... Memory, 5 ... Write control circuit,
6 Time axis error detecting means, 37 to 40 Multiplier, 63
Adder, 52: Time axis error calculation circuit, 54: Velocity error detector.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H04N 5/91-5/956 H04N 9/89-9/898 G11B 20/10 321

Claims (4)

(57) [Claims] 1. An AD converter for sampling an input signal with a clock at a fixed time interval and converting the sampled signal into a digital signal, inputting and outputting a digital signal obtained by the AD converter based on the clock, A memory for temporarily storing a signal of the digital signal obtained by the AD converter, and a write control circuit for controlling writing to start at a predetermined address in the memory each time a synchronization signal in the digital signal obtained by the AD converter is detected; A time axis error detecting means for detecting a time axis error of the digital signal obtained by the converter and outputting it as time axis error information; and interpolating a signal amplitude based on the time axis error information from the digital signal output from the memory, for reference. Interpolating means for obtaining a digital signal having the above-mentioned time axis. 2. An interpolator for delaying an input signal of the interpolator to obtain sample values at a plurality of successive sample points, and interpolating a predetermined number of sample values from the sample values at the plurality of sample points. Selecting means for selecting and outputting based on the time axis error information from the time axis error detecting means; and a coefficient based on the time axis error information from the time axis error detecting means for the selected predetermined number of sample values. 2. The time axis correction device according to claim 1, further comprising: a plurality of multiplying means for multiplying the multiplying means; and an adding means for adding outputs of the plurality of multiplying means to obtain an interpolation output of the interpolating means. A time axis error detecting means for calculating the phase of the color burst signal in the digital signal by arithmetic processing and outputting as a time axis error smaller than one sampling time interval; A velocity error detector for calculating an error with respect to one reference horizontal scanning time using an output of the arithmetic circuit; and a sampling time using the output of the time axis error arithmetic circuit and the output of the velocity error detector for each sampling time. 2. The time axis correction device according to claim 1, further comprising: a calculating means for calculating a time axis error of the time axis. 4. A time axis error calculating circuit for calculating and outputting a time axis error smaller than one sampling time interval of a horizontal synchronizing signal in a digital signal, and a time axis error calculating means. A velocity error detector for calculating an error with respect to one reference horizontal scanning time using an output of the circuit; and a sampling error for each sampling time using an output of the time axis error calculation circuit and an output of the velocity error detector. 2. The time axis correction device according to claim 1, further comprising a calculation unit for calculating a time axis error.