JPH0810925B2 - Time axis correction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction apparatus for correcting a time axis fluctuation of a reproduction signal in a signal reproduction apparatus such as a video tape recorder (VTR).

2. Description of the Related Art In recent years, in a signal reproducing apparatus such as a VTR for broadcasting, a digital type time axis correcting apparatus is widely used to correct a time axis fluctuation of a reproduced signal.

An example of the conventional time axis correction device described above will be described below with reference to the drawings.

FIG. 6 is a schematic configuration diagram of a conventional time axis correction device. A reproduction signal including a time axis fluctuation is input from the input terminal 1. The write clock generation circuit 2 generates a clock that is synchronized with the fluctuation of the input signal on the time axis and supplies it to the AD converter 3, the memory control circuit 5, and the like. In the AD converter 3, the input signal from the input terminal 1 is sampled with a clock synchronized with the time base fluctuation of the input signal generated by the write clock generation circuit 2, converted into a digital signal and temporarily stored in the memory 4. On the other hand, the read clock generation circuit 7 generates a fixed clock that does not fluctuate on the time axis, reads the signal stored in the memory 4 in synchronization with this fixed clock, converts it into an analog signal again with the DA converter 6, and outputs it. Output from 8. The memory control circuit 5 uses two asynchronous clock signals, a write clock and a read clock, to control the memory such that writing and reading are apparently independent and in parallel.

Next, the principle of correcting the time base fluctuation will be described on the time base with reference to FIG. FIG. 7 (a) is an original signal with no time-axis fluctuation, and the signal recorded / reproduced from this signal has time-axis fluctuation as shown in FIG. 7 (b), which is the input terminal 1 of FIG. Entered in. The AD converter 3 samples the sampling points 10A to 10M (indicated by ●) in FIG. 7 (b) with a clock synchronized with the time base fluctuation, and once stored in the memory, this is fixed clock without time base fluctuation. By reading with
As shown in FIG. 7 (c), it is possible to obtain a signal whose time axis fluctuation is corrected. (For example, “VTR Technology” edited by Japan Broadcasting Corporation, (October 20, Showa 57), Japan Broadcast Publishing Association, p.118) Problems to be Solved by the Invention However, in the above configuration, the write clock and the read clock are It is necessary to control the memory such that writing and reading are apparently independent and performed in parallel by two asynchronous clock signals, which complicates the memory configuration and memory control, and makes the circuit large-scale. Further, since the cycle of the clock synchronized with the time-axis fluctuation of the input signal changes according to the time-axis fluctuation, the configuration of the digital circuit portion operating with this clock becomes complicated. Further, there is a problem that it is difficult to integrate the entire device into a semiconductor because an analog circuit for generating a clock that is synchronized with the fluctuation of the input signal on the time axis is required.

An object of the present invention is to provide a time axis correction device which focuses on the above-mentioned problems and which can be operated by only one system clock having no time axis fluctuation and which can be integrated into a semiconductor device.

Means for Solving the Problems In order to solve the above problems, a time axis correction device of the present invention is a clock generation means for generating a clock signal of a constant cycle, and an input signal is sampled with the clock signal of the constant cycle. AD converter for converting into a digitalized signal, interpolation means for interpolating the signal amplitude based on the time error information from the digital signal obtained by the AD converter, and synchronization included in the signal obtained by the interpolation means From the phase of the signal and the reference phase obtained from the clock signal of the constant period,
A time axis error detecting means for detecting the time axis error of the signal obtained by the interpolating means and feeding back the time error information to the interpolating means; and a DA converter for converting the output signal of the interpolating means into an analog signal. Be prepared.

The present invention has the above-described configuration and is configured to interpolate a signal corrected for time-axis fluctuations from a signal sampled with a clock having no time-axis fluctuations. No clock is required, and the entire device operates with only one system of clock that does not fluctuate on the time axis.

Embodiment An embodiment of the time axis correction device of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of a time axis correction device of the present invention. In FIG. 1, a reproduction signal including a time base fluctuation is input from an input terminal 1. Clock generation circuit 107
Generates a clock with a constant cycle without time axis fluctuation, and AD converter 103, DA converter 106, time error detection circuit 102
Etc. In the AD converter 10, the input signal from the input terminal 1 is sampled by the clock having a constant cycle generated by the clock generation circuit 107 and converted into a digital signal. The interpolating circuit 104 interpolates and obtains a signal with a corrected time error from the signal digitized by the AD converter 103 based on the time error information obtained from the synchronization signal in the time error detecting circuit 102. The signal whose time error has been corrected is guided to the time error detection circuit 102 on the one hand, the time error is detected again and the error information is fed back to the interpolation circuit 104, while on the other hand it is supplied to the DA converter 106. It is converted into an analog signal and output from the output terminal 8. The time error detection circuit 102 can be realized by a known circuit configuration. In this embodiment, the reference phase obtained from the clock signal supplied from the clock generation circuit 107 and having no time axis fluctuation, and the output of the interpolation circuit 104. The time error information is obtained by comparing the phase of the sync signal of the reproduced signal included in the signal.

Next, the principle of correcting the time base fluctuation will be described on the time base using FIG. 7 as in the case of the prior art example. Seventh
In contrast to the original signal having no time-axis fluctuation shown in FIG. 7A, the reproduced signal has time-axis fluctuation as shown in FIG. 7B, and this is input to the input terminal 1 shown in FIG. The AD converter 103 samples the sampling points 20A to 20N (indicated by □) in FIG. 7 (b) with a clock having a constant cycle with no time axis fluctuation. From the sampled signal, the sampled value of the sampled position synchronized with the time-axis fluctuation of the input signal in the interpolator 104, that is, the same sampled points 10A to 10M as the sampled points in the conventional example of FIG. (Shown) is interpolated to obtain the sample value. As a result, as shown in FIG. 7 (c), it is possible to obtain a signal whose time axis fluctuation is corrected. The sample position synchronized with the time axis fluctuation is
A feedback loop between the error information obtained by the time error detection circuit 102 and the interpolation circuit 104 can be stably obtained.

Here, the principle of interpolation in the interpolation circuit 104 will be described. Now, let the signal input to the input terminal 1 be v (t),
When the sampling period is T, the signal sampled by the AD converter 103 is represented by v (kT) (k is an integer). v
Since (t) is band-limited to a frequency equal to or less than 1/2 of the sampling frequency so as to satisfy the sampling theorem, the signal v (τ) at an arbitrary time τ is sampled from the signal It can be obtained by a formula.

Where s (t) is an interpolation function, and the input signal v (t)
Where f _{m is} the maximum frequency and f _s = 1 / T is the sampling frequency, the transfer function S (f) (f is the frequency) is at least Equal to the impulse response of a filter that satisfies. For example,
When the ideal low-pass filter whose frequency characteristic is shown in FIG. 2 is used as S (f), the interpolation function s which is its impulse response
(T) is expressed by the following equation.

By the way, according to the formula, to obtain v (τ),
It is necessary to perform an operation for k = -∞ to + ∞, and this operation cannot be executed. However, in the present invention, since the signal is treated as a digital signal, if v (τ) is obtained with an error within (1 quantization step) / 2, there is no problem in practical use. Therefore, the following formula is used.

Here, N and M are integers with finite values, and may be set so that the error of v (τ) obtained as described above is sufficiently small. As a result, the time τ at the sample position synchronized with the time axis fluctuation of the input signal can be obtained from the error information obtained by the time error detection circuit 102, and the sample value at this time can be obtained by the formula.

Next, a specific example of the interpolation circuit 104 that performs the above-described interpolation will be described.

FIG. 3 shows a configuration example of the interpolation circuit 104. Here, a case where M and N in the equation satisfy N−M + 1 = 4, that is, a case where an interpolation output is obtained from four sample points will be described. Further, although each signal line is shown as one line for simplicity, it actually transmits a signal of a plurality of bits. In FIG. 3, the signal input from the input terminal 111 of the interpolation circuit is input to the shift register 112 including a plurality of D-flip-flops. Shift register 112
From the respective D-flip-flops, the signals delayed by the clock unit are taken out, and guided to the selection circuit 119 as a pair of sampling points consisting of four consecutive sample values 113 to 118. The selection circuit 119 selects one of the sample point pairs 113 to 118 based on the clock-based error information 134 and connects it to the sample point pair 120.

On the other hand, from the time error information input terminal 135, the time error information obtained by the time error detection circuit of FIG. 1 is input. The time error processing circuit 133 converts the time error information into error information 134 in units of clocks and error information 132 within one clock cycle. The error information 134 for each clock and the error information 132 within one clock period will be described with reference to FIG. In FIG. 4, the horizontal axis represents time and the vertical axis represents the input signal amplitude. 140 to 143 are sample points (indicated by □) which are output from each D-flip-flop of the shift register 112, and 150 (indicated by ●) are sample points to be interpolated. Here, the clock-based error information 134 serves as a control signal for the selection circuit 119 to select a sample point pair consisting of four sample points 140 to 143 sandwiching the sample point 150 to be obtained by interpolation. The error information 132 within one clock period indicates the time error within one clock period indicated by Δt in FIG.

Now, the four sample values of the output sample point pair 120 of the selection circuit in FIG. 3 are guided to the multiplication circuits 121 to 124, respectively. On the other hand, the error information 132 within one clock period is input to the coefficient generation circuit 131, and the coefficient signals 127 to 130 are input to the other input terminals of the multiplication circuits 121 to 124, respectively. Coefficient signal 12
7 to 130 are s (τ−T) and s (τ−
2T), s (τ−3T), s (τ−4T), and the coefficient generation circuit 131 is composed of a ROM or the like. Multiplier circuit 12
The output signals of 1 to 124 are added in the adder circuit 125 and output from the output terminal 126 as an interpolation output.

As described above, the interpolation circuit 104 that obtains the interpolation output represented by the equation can be configured.

Although a case of N−M + 1 = 4 has been described here for simplicity, N and M are set so that the error due to interpolation is sufficiently small. The number of stages of the shift register may be determined according to the required interpolation range.

As described above, according to the present embodiment, a signal corrected for time axis fluctuation can be interpolated from a signal sampled with a clock having no time axis fluctuation, and the entire apparatus It can be operated with only one system clock that does not have it.

Here, in the above embodiment, the equation which is the impulse response of the ideal low-pass filter is shown as the interpolation function. However, when the maximum frequency f _m of the input signal is smaller than 1/2 of the sampling frequency f _s , Looks at the equation, as shown in Figure 5,
In addition, an impulse response of a filter having a frequency characteristic that smoothly changes f _m to (f _s −f _m ), for example, an interpolation function shown in the following equation may be used.

As a result, the value of N−M + 1 in the equation for sufficiently reducing the error due to interpolation, that is, the number of sampling points required for interpolation can be significantly reduced, and as a result, the circuit scale of the interpolation circuit can be reduced. .

EFFECTS OF THE INVENTION As described above, the present invention has a configuration in which the signal corrected for the time axis fluctuation is interpolated from the signal sampled by the clock having no time axis fluctuation. It operates only with one system clock that does not have. Therefore, unlike the prior art, an analog circuit for generating a clock synchronized with a time-axis variation of an input signal is not required, the entire device can be made into a semiconductor, and downsizing and cost reduction can be achieved. In addition, since the operation is performed only by one system of clock having no time axis fluctuation, stable operation can be obtained with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a time axis correction device of the present invention,
2 and 5 are frequency characteristic diagrams which are the basis of the interpolation function in the interpolation circuit of one embodiment of the present invention, FIG. 3 is a configuration diagram of the interpolation circuit of one embodiment of the present invention, and FIG. 5 is an operation explanatory diagram of the interpolation circuit of FIG. 5, FIG. 6 is a configuration diagram of a conventional time axis correction device, and FIG. 7 is an operational explanatory diagram of a conventional and one embodiment of the present invention. 103 ... AD converter, 104 ... Interpolation circuit, 102 ... Time error detection circuit, 107 ... DA converter.

Claims (2)

[Claims] 1. A clock generation means for generating a clock signal of a constant cycle, an AD converter for sampling an input signal with the clock signal of the constant cycle, and converting it into a digital signal,
Interpolation means obtained by interpolating the signal amplitude from the digital signal obtained by the AD converter based on the time error information, and the phase of the synchronization signal contained in the signal obtained by the interpolation means and the clock signal of the constant cycle. A time axis error detecting means for detecting a time axis error of the signal obtained by the interpolating means from the reference phase and feeding back the time error information to the interpolating means, and an output signal of the interpolating means is converted into an analog signal. A time axis correction device equipped with a DA converter. 2. An interpolating means delays an input signal of the interpolating means to obtain sample values at a plurality of consecutive sample points, and a predetermined number of sample values from the sample values of the plurality of sample points. Selection means for selecting and outputting based on the time error information from the time axis error detecting means, and a coefficient based on the time error information from the time axis error detecting means for the selected predetermined number of sample values, respectively. The time axis according to claim 1, further comprising: a plurality of multiplying means for multiplying, and an adding means for adding outputs of the plurality of multiplying means to obtain an interpolation output of the interpolation means. Correction device.