JP2504049B2 - Synchronous multiplexing - Google Patents
Synchronous multiplexingInfo
- Publication number
- JP2504049B2 JP2504049B2 JP9886687A JP9886687A JP2504049B2 JP 2504049 B2 JP2504049 B2 JP 2504049B2 JP 9886687 A JP9886687 A JP 9886687A JP 9886687 A JP9886687 A JP 9886687A JP 2504049 B2 JP2504049 B2 JP 2504049B2
- Authority
- JP
- Japan
- Prior art keywords
- channel
- multiplexing
- present
- information
- synchronous multiplexing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデジタル通信の同期多重方式に関し、特に２
チャンネルの情報を多重化する場合の同期多重方式に関
する。TECHNICAL FIELD The present invention relates to a synchronous multiplex system for digital communication, and particularly to 2
The present invention relates to a synchronous multiplex system for multiplexing channel information.
従来、マーク率が共に1/2の２チャンネル（CH）のデ
ータを同期多重を用いて多重化した場合、多重化後のデ
ータもマーク率1/2となるが、1CHのみの場合、多重化後
のデータのマーク率は1/4と下がってしまう。Conventionally, when data of 2 channels (CH), both of which has a mark ratio of 1/2, is multiplexed using synchronous multiplexing, the data after the multiplexing also has a mark ratio of 1/2, but in the case of only 1CH, it is multiplexed. The mark rate of the latter data will drop to 1/4.
〔発明が解決しようとする問題点〕 上述した従来の技術では、1CHのみの場合、多重化後
のマーク率が1/4と下がってしまい、受信部においてマ
ーク率1/2の時と比べてクロック抽出が困難となる欠点
がある。[Problems to be Solved by the Invention] In the above-mentioned conventional technique, in the case of only 1CH, the mark ratio after multiplexing is reduced to 1/4, and compared with the case where the mark ratio is 1/2 in the receiving unit. There is a drawback that clock extraction becomes difficult.
本発明は、２チャンネルの多重化において片チャンネ
ルが実装されない場合、その未実装情報を用いて使用し
ているチャンネルの反転情報を未使用のチャンネルに挿
入する。これにより多重化後のデータのマーク率は1/2
となり、２チャンネル多重化の状態と同じとなる。According to the present invention, when one channel is not mounted in the multiplexing of two channels, the inversion information of the used channel is inserted into the unused channel by using the unmounted information. As a result, the mark ratio of the data after multiplexing is 1/2
And becomes the same as the two-channel multiplexing state.
次に本発明の実施例について図面を用いて説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
図は本発明の一実施例を示すブロック図である。図に
おいて、10がチャンネル１の入力端子,11がチャンネル
１の未実装情報用端子、12がチャンネル２の未実装情報
用端子,13がチャンネル２の入力端子、1,3,4,6,8がECL
のNORゲート、2,5が反転，非反転出力を有するECLゲー
ト、９が多重化部である。FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 10 is an input terminal of channel 1, 11 is an unmounted information terminal of channel 1, 12 is an unmounted information terminal of channel 2, 13 is an input terminal of channel 2, 1, 3, 4, 6, 8 Is ECL
NOR gates, 2, 5 are ECL gates having inverted and non-inverted outputs, and 9 is a multiplexer.
チャンネル１が未実装となった場合、端子10,11は共
にECLレベルの“L"となりゲート１と４が閉じ、ゲート
６が開く。これによりゲート３からチャンネル２の反転
情報が出力される。このときゲート８からはチャンネル
２の情報が出力される。When the channel 1 is not mounted, both terminals 10 and 11 become ECL level "L", gates 1 and 4 are closed, and gate 6 is opened. As a result, the inversion information of the channel 2 is output from the gate 3. At this time, the information of channel 2 is output from the gate 8.
以上説明した様に本発明は、実装側のチャンネルの反
転情報を未実装側のチャンネルへ挿入するので多重化後
のデータがマーク率1/2となり、受信部でのクロック抽
出が、２チャンネル多重化の場合と同じにできるという
効果がある。As described above, according to the present invention, since the inversion information of the mounting side channel is inserted into the non-mounting side channel, the data after multiplexing has a mark ratio of 1/2, and the clock extraction in the receiving section is performed by two-channel multiplexing. The effect is that it can be the same as the case of conversion.
図は本発明の実施例の回路図である。 1,2,3,4,5,6,7,8……ECLのNORゲート、９…多重化部、1
0…チャンネル１の入力端子、11…チャンネル１の未実
装情報用端子、12…チャンネル２の未実装情報用端子、
13…チャンネル２の入力端子FIG. 1 is a circuit diagram of an embodiment of the present invention. 1,2,3,4,5,6,7,8 ... NOR gate of ECL, 9 ... Multiplexer, 1
0 ... Channel 1 input terminal, 11 ... Channel 1 unmounted information terminal, 12 ... Channel 2 unmounted information terminal,
13 ... Channel 2 input terminal
Claims (1)
実装側のチャンネルに実装側のチャンネルの反転情報を
挿入し多重化することを特徴とする同期多重方式。1. A two-channel synchronous multiplexing method, wherein inversion information of a mounting side channel is inserted into a non-mounting side channel to perform multiplexing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9886687A JP2504049B2 (en) | 1987-04-21 | 1987-04-21 | Synchronous multiplexing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9886687A JP2504049B2 (en) | 1987-04-21 | 1987-04-21 | Synchronous multiplexing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63263843A JPS63263843A (en) | 1988-10-31 |
| JP2504049B2 true JP2504049B2 (en) | 1996-06-05 |
Family
ID=14231115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9886687A Expired - Lifetime JP2504049B2 (en) | 1987-04-21 | 1987-04-21 | Synchronous multiplexing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2504049B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088550B2 (en) * | 1990-04-13 | 1996-01-29 | 富士通株式会社 | Block interleaved multiple conversion system |
-
1987
- 1987-04-21 JP JP9886687A patent/JP2504049B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63263843A (en) | 1988-10-31 |
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