JP2025511310A5 - - Google Patents
Info
- Publication number
- JP2025511310A5 JP2025511310A5 JP2024558321A JP2024558321A JP2025511310A5 JP 2025511310 A5 JP2025511310 A5 JP 2025511310A5 JP 2024558321 A JP2024558321 A JP 2024558321A JP 2024558321 A JP2024558321 A JP 2024558321A JP 2025511310 A5 JP2025511310 A5 JP 2025511310A5
- Authority
- JP
- Japan
- Prior art keywords
- access
- instruction
- data values
- ordering
- memory address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB2205110.6A GB2617551B (en) | 2022-04-07 | 2022-04-07 | Technique for handling ordering constrained access operations |
| GB2205110.6 | 2022-04-07 | ||
| PCT/GB2023/050589 WO2023194702A1 (en) | 2022-04-07 | 2023-03-13 | Technique for handling ordering constrained access operations |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025511310A JP2025511310A (ja) | 2025-04-15 |
| JP2025511310A5 true JP2025511310A5 (enExample) | 2026-03-23 |
Family
ID=81653133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024558321A Pending JP2025511310A (ja) | 2022-04-07 | 2023-03-13 | 順序付け制約付きアクセス動作を処理するための技法 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20250190217A1 (enExample) |
| EP (1) | EP4505292B1 (enExample) |
| JP (1) | JP2025511310A (enExample) |
| KR (1) | KR20240167917A (enExample) |
| CN (1) | CN118974699A (enExample) |
| GB (1) | GB2617551B (enExample) |
| IL (1) | IL315456A (enExample) |
| TW (1) | TW202340938A (enExample) |
| WO (1) | WO2023194702A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2701463A (en) * | 2024-10-15 | 2026-04-29 | Arm Ltd | Masked load/store instruction for gpu |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5201039A (en) * | 1987-09-30 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Multiple address-space data processor with addressable register and context switching |
| US5887183A (en) * | 1995-01-04 | 1999-03-23 | International Business Machines Corporation | Method and system in a data processing system for loading and storing vectors in a plurality of modes |
| US6704833B2 (en) * | 2002-01-04 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Atomic transfer of a block of data |
| GB2549239A (en) * | 2014-11-13 | 2017-10-18 | Advanced Risc Mach Ltd | Context sensitive barriers in data processing |
| US10379855B2 (en) * | 2016-09-30 | 2019-08-13 | Intel Corporation | Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers |
| US20190065199A1 (en) * | 2017-08-31 | 2019-02-28 | MIPS Tech, LLC | Saving and restoring non-contiguous blocks of preserved registers |
-
2022
- 2022-04-07 GB GB2205110.6A patent/GB2617551B/en active Active
-
2023
- 2023-03-13 EP EP23711543.1A patent/EP4505292B1/en active Active
- 2023-03-13 JP JP2024558321A patent/JP2025511310A/ja active Pending
- 2023-03-13 CN CN202380031691.9A patent/CN118974699A/zh active Pending
- 2023-03-13 US US18/853,552 patent/US20250190217A1/en active Pending
- 2023-03-13 IL IL315456A patent/IL315456A/en unknown
- 2023-03-13 KR KR1020247036464A patent/KR20240167917A/ko active Pending
- 2023-03-13 WO PCT/GB2023/050589 patent/WO2023194702A1/en not_active Ceased
- 2023-04-06 TW TW112112848A patent/TW202340938A/zh unknown
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