JP2021509743A5 - - Google Patents

Info

Publication number
JP2021509743A5
JP2021509743A5 JP2020535645A JP2020535645A JP2021509743A5 JP 2021509743 A5 JP2021509743 A5 JP 2021509743A5 JP 2020535645 A JP2020535645 A JP 2020535645A JP 2020535645 A JP2020535645 A JP 2020535645A JP 2021509743 A5 JP2021509743 A5 JP 2021509743A5
Authority
JP
Japan
Prior art keywords
instruction
cache
entries
barrier
conditional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2020535645A
Other languages
English (en)
Japanese (ja)
Other versions
JP7406489B2 (ja
JP2021509743A (ja
Filing date
Publication date
Priority claimed from US16/208,701 external-priority patent/US10866805B2/en
Application filed filed Critical
Publication of JP2021509743A publication Critical patent/JP2021509743A/ja
Publication of JP2021509743A5 publication Critical patent/JP2021509743A5/ja
Application granted granted Critical
Publication of JP7406489B2 publication Critical patent/JP7406489B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2020535645A 2018-01-03 2018-12-14 推測バリア命令 Active JP7406489B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862613280P 2018-01-03 2018-01-03
US62/613,280 2018-01-03
US16/208,701 US10866805B2 (en) 2018-01-03 2018-12-04 Speculation barrier instruction
US16/208,701 2018-12-04
PCT/GB2018/053636 WO2019135063A1 (en) 2018-01-03 2018-12-14 Speculation barrier instruction

Publications (3)

Publication Number Publication Date
JP2021509743A JP2021509743A (ja) 2021-04-01
JP2021509743A5 true JP2021509743A5 (enExample) 2023-11-14
JP7406489B2 JP7406489B2 (ja) 2023-12-27

Family

ID=67058912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020535645A Active JP7406489B2 (ja) 2018-01-03 2018-12-14 推測バリア命令

Country Status (6)

Country Link
US (1) US10866805B2 (enExample)
EP (1) EP3735633B1 (enExample)
JP (1) JP7406489B2 (enExample)
KR (1) KR102727263B1 (enExample)
CN (1) CN111433740B (enExample)
WO (1) WO2019135063A1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2554096B (en) * 2016-09-20 2019-03-20 Advanced Risc Mach Ltd Handling of inter-element address hazards for vector instructions
US11265291B2 (en) 2017-08-25 2022-03-01 Red Hat, Inc. Malicious packet filtering by a hypervisor
US11675594B2 (en) * 2018-04-19 2023-06-13 Intel Corporation Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks
DE102019107055A1 (de) 2018-04-19 2019-10-24 Intel Corporation Systeme, Verfahren und Vorrichtungen zum Steuern der CPU-Spekulationen zur Verhinderung vn Seitenkanalangriffen
JP7064135B2 (ja) * 2018-05-15 2022-05-10 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US11106466B2 (en) * 2018-06-18 2021-08-31 International Business Machines Corporation Decoupling of conditional branches
US11119784B2 (en) * 2018-06-29 2021-09-14 Intel Corporation Efficient mitigation of side-channel based attacks against speculative execution processing architectures
US11334495B2 (en) * 2019-08-23 2022-05-17 Arm Limited Cache eviction
US11663014B2 (en) * 2019-08-26 2023-05-30 Arm Limited Speculatively executing instructions that follow a status updating instruction
US11709716B2 (en) * 2019-08-26 2023-07-25 Red Hat, Inc. Hardware offload support for an operating system offload interface using operation code verification
US11443044B2 (en) * 2019-09-23 2022-09-13 International Business Machines Corporation Targeted very long delay for increasing speculative execution progression
US20210096872A1 (en) * 2019-09-27 2021-04-01 Intel Corporation Hardware for eliding security checks when deemed safe during speculative execution
US12079197B2 (en) * 2019-10-18 2024-09-03 Dover Microsystems, Inc. Systems and methods for updating metadata
US10990393B1 (en) 2019-10-21 2021-04-27 Advanced Micro Devices, Inc. Address-based filtering for load/store speculation
CN111857825B (zh) 2020-07-20 2024-10-29 昆仑芯(北京)科技有限公司 指令执行方法、装置、电子设备、存储介质和程序产品
US11720360B2 (en) * 2020-09-11 2023-08-08 Apple Inc. DSB operation with excluded region
US20220091851A1 (en) * 2020-09-23 2022-03-24 Intel Corporation System, Apparatus And Methods For Register Hardening Via A Micro-Operation
US11675899B2 (en) * 2020-12-15 2023-06-13 International Business Machines Corporation Hardware mitigation for Spectre and meltdown-like attacks
US20220207147A1 (en) * 2020-12-26 2022-06-30 Intel Corporation Hardening registers against speculation vulnerabilities
US20220207138A1 (en) * 2020-12-26 2022-06-30 Intel Corporation Hardening store hardware against speculation vulnerabilities
DE102021102777A1 (de) * 2021-02-05 2022-08-11 Infineon Technologies Ag Verarbeitung von in einem speicher gespeicherter daten
CN113703842B (zh) * 2021-09-10 2024-03-26 中国人民解放军国防科技大学 一种基于分支预测的值预测方法、装置及介质
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction
US12578965B2 (en) 2023-07-25 2026-03-17 Apple Inc. Biased indirect control transfer prediction
US20260072693A1 (en) * 2024-09-10 2026-03-12 Arm Limited Speculation barrier
US12561144B1 (en) * 2024-09-27 2026-02-24 Intel Corporation Circuitry and methods for a conditional fence instruction

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611063A (en) * 1996-02-06 1997-03-11 International Business Machines Corporation Method for executing speculative load instructions in high-performance processors
US6484230B1 (en) 1998-09-28 2002-11-19 International Business Machines Corporation Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6493819B1 (en) * 1999-11-16 2002-12-10 Advanced Micro Devices, Inc. Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor
US6678810B1 (en) * 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
WO2003029961A1 (en) * 2001-10-02 2003-04-10 Koninklijke Philips Electronics N.V. Speculative execution for java hardware accelerator
DE10254657A1 (de) * 2002-11-22 2004-06-03 Philips Intellectual Property & Standards Gmbh Mikrocontroller und zugeordnetes Verfahren zum Abarbeiten der Programmierung des Mikrocontrollers
US8516201B2 (en) 2006-12-05 2013-08-20 Intel Corporation Protecting private data from cache attacks
US20090089564A1 (en) * 2006-12-06 2009-04-02 Brickell Ernie F Protecting a Branch Instruction from Side Channel Vulnerabilities
KR20140011940A (ko) * 2012-07-18 2014-01-29 한국전자통신연구원 분기 명령 실행 캐쉬를 이용한 프로세서 및 분기 명령 실행 캐쉬를 이용한 프로세서의 동작 방법
GB2509830B (en) * 2013-02-11 2014-12-24 Imagination Tech Ltd Speculative load issue
US9304940B2 (en) * 2013-03-15 2016-04-05 Intel Corporation Processors, methods, and systems to relax synchronization of accesses to shared memory
US9361144B2 (en) * 2013-06-28 2016-06-07 Globalfoundries Inc. Predictive fetching and decoding for selected return instructions
US9323535B2 (en) * 2013-06-28 2016-04-26 Intel Corporation Instruction order enforcement pairs of instructions, processors, methods, and systems
CN105005737A (zh) * 2015-07-31 2015-10-28 天津大学 一种面向分支预测攻击的微体系结构级安全防护方法

Similar Documents

Publication Publication Date Title
JP2021509743A5 (enExample)
KR102727263B1 (ko) 추측 장벽 명령
CN108780396B (zh) 程序循环控制
JP6660991B2 (ja) マルチスレッドプロセッサでのタスクのスケジューリング
TWI644254B (zh) 用於執行推論向量存取操作的資料處理裝置、電腦程式產品與方法
CN108885549B (zh) 分支指令
DE102015101541A1 (de) Prozessor mit granulärer addier-direktwert-fähigkeit & verfahren
JP7281491B2 (ja) トランザクショナル比較及び破棄命令
KR102509365B1 (ko) 보안 모드 상태 데이터 액세스 트랙킹
JP2018537800A5 (enExample)
US9817763B2 (en) Method of establishing pre-fetch control information from an executable code and an associated NVM controller, a device, a processor system and computer program products
CN108780397A (zh) 程序循环控制
US9361113B2 (en) Simultaneous finish of stores and dependent loads
JP7510253B2 (ja) 分岐予測器
JP6846405B2 (ja) 条件付きロードの抑制
KR20010001022A (ko) 병렬 프로세서를 위한 무순서 명령어 발행 방법 및 장치
JP6913689B2 (ja) レジスタ・アクセス制御
CN113544639B (zh) 数据结构放弃
US20150242211A1 (en) Programmable controller
JP2024523790A5 (enExample)
US20130332712A1 (en) Branch prediction table install source tracking
JP7269318B2 (ja) 早期リターン予測を有する分岐ターゲットバッファ
JP2025511310A5 (enExample)
KR102597201B1 (ko) 트랜잭션 네스팅 심도 시험 명령
US9870340B2 (en) Multithreading in vector processors