JP7406489B2 - 推測バリア命令 - Google Patents

推測バリア命令 Download PDF

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JP7406489B2
JP7406489B2 JP2020535645A JP2020535645A JP7406489B2 JP 7406489 B2 JP7406489 B2 JP 7406489B2 JP 2020535645 A JP2020535645 A JP 2020535645A JP 2020535645 A JP2020535645 A JP 2020535645A JP 7406489 B2 JP7406489 B2 JP 7406489B2
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instruction
speculative
barrier
cache
conditional
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JP2021509743A (ja
JP2021509743A5 (enExample
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ロイ グリセンスウェイト、リチャード
ガブリエッリ、ジャコモ
ジェイムズ ホースネル、マシュー
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アーム・リミテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1491—Protection against unauthorised use of memory or access to memory by checking the subject access rights in a hierarchical protection system, e.g. privilege levels, memory rings
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Databases & Information Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2020535645A 2018-01-03 2018-12-14 推測バリア命令 Active JP7406489B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862613280P 2018-01-03 2018-01-03
US62/613,280 2018-01-03
US16/208,701 US10866805B2 (en) 2018-01-03 2018-12-04 Speculation barrier instruction
US16/208,701 2018-12-04
PCT/GB2018/053636 WO2019135063A1 (en) 2018-01-03 2018-12-14 Speculation barrier instruction

Publications (3)

Publication Number Publication Date
JP2021509743A JP2021509743A (ja) 2021-04-01
JP2021509743A5 JP2021509743A5 (enExample) 2023-11-14
JP7406489B2 true JP7406489B2 (ja) 2023-12-27

Family

ID=67058912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020535645A Active JP7406489B2 (ja) 2018-01-03 2018-12-14 推測バリア命令

Country Status (6)

Country Link
US (1) US10866805B2 (enExample)
EP (1) EP3735633B1 (enExample)
JP (1) JP7406489B2 (enExample)
KR (1) KR102727263B1 (enExample)
CN (1) CN111433740B (enExample)
WO (1) WO2019135063A1 (enExample)

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JP7064135B2 (ja) * 2018-05-15 2022-05-10 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US11106466B2 (en) * 2018-06-18 2021-08-31 International Business Machines Corporation Decoupling of conditional branches
US11119784B2 (en) * 2018-06-29 2021-09-14 Intel Corporation Efficient mitigation of side-channel based attacks against speculative execution processing architectures
US11334495B2 (en) * 2019-08-23 2022-05-17 Arm Limited Cache eviction
US11663014B2 (en) * 2019-08-26 2023-05-30 Arm Limited Speculatively executing instructions that follow a status updating instruction
US11709716B2 (en) * 2019-08-26 2023-07-25 Red Hat, Inc. Hardware offload support for an operating system offload interface using operation code verification
US11443044B2 (en) * 2019-09-23 2022-09-13 International Business Machines Corporation Targeted very long delay for increasing speculative execution progression
US20210096872A1 (en) * 2019-09-27 2021-04-01 Intel Corporation Hardware for eliding security checks when deemed safe during speculative execution
US12079197B2 (en) * 2019-10-18 2024-09-03 Dover Microsystems, Inc. Systems and methods for updating metadata
US10990393B1 (en) 2019-10-21 2021-04-27 Advanced Micro Devices, Inc. Address-based filtering for load/store speculation
CN111857825B (zh) 2020-07-20 2024-10-29 昆仑芯(北京)科技有限公司 指令执行方法、装置、电子设备、存储介质和程序产品
US11720360B2 (en) * 2020-09-11 2023-08-08 Apple Inc. DSB operation with excluded region
US20220091851A1 (en) * 2020-09-23 2022-03-24 Intel Corporation System, Apparatus And Methods For Register Hardening Via A Micro-Operation
US11675899B2 (en) * 2020-12-15 2023-06-13 International Business Machines Corporation Hardware mitigation for Spectre and meltdown-like attacks
US20220207147A1 (en) * 2020-12-26 2022-06-30 Intel Corporation Hardening registers against speculation vulnerabilities
US20220207138A1 (en) * 2020-12-26 2022-06-30 Intel Corporation Hardening store hardware against speculation vulnerabilities
DE102021102777A1 (de) * 2021-02-05 2022-08-11 Infineon Technologies Ag Verarbeitung von in einem speicher gespeicherter daten
CN113703842B (zh) * 2021-09-10 2024-03-26 中国人民解放军国防科技大学 一种基于分支预测的值预测方法、装置及介质
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction
US12578965B2 (en) 2023-07-25 2026-03-17 Apple Inc. Biased indirect control transfer prediction
US20260072693A1 (en) * 2024-09-10 2026-03-12 Arm Limited Speculation barrier
US12561144B1 (en) * 2024-09-27 2026-02-24 Intel Corporation Circuitry and methods for a conditional fence instruction

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JP2005504390A (ja) 2001-10-02 2005-02-10 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ ジャバハードウェアアクセラレータ用の投機的実行
JP2006507594A (ja) 2002-11-22 2006-03-02 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ マイクロコントローラ、及びマイクロコントローラのプログラミングを処理するための割当方法
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Also Published As

Publication number Publication date
KR20200101943A (ko) 2020-08-28
CN111433740B (zh) 2024-07-30
KR102727263B1 (ko) 2024-11-07
US10866805B2 (en) 2020-12-15
CN111433740A (zh) 2020-07-17
US20190205140A1 (en) 2019-07-04
EP3735633A1 (en) 2020-11-11
EP3735633B1 (en) 2022-10-12
WO2019135063A1 (en) 2019-07-11
JP2021509743A (ja) 2021-04-01

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