JP2024075027A - Elastic wave device and module - Google Patents

Abstract

To provide an elastic wave device capable of improve heat dissipation of a chip substrate.SOLUTION: An elastic wave device comprises: a chip substrate; a wiring pattern which is formed on the chip substrate; a plurality of series resonators which are formed on the chip substrate and electrically connected by the wiring pattern; a first extension part which is made of metal, and extends from a region where the series resonators are connected directly and electrically to one another by the wiring pattern toward an outer edge part of the chip substrate; and a second extension part which extends from the first extension part toward the outer edge part of the chip substrate.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to an acoustic wave device and a module including the acoustic wave device.

Patent Document 1 discloses an acoustic wave device. This acoustic wave device has excellent power resistance and bondability.

JP 2022-028566 A

However, in the acoustic wave device described in Patent Document 1, heat is difficult to dissipate from the chip substrate. As a result, the chip substrate has poor heat dissipation properties.

The present disclosure has been made to solve the above-mentioned problems. The purpose of the present disclosure is to provide an acoustic wave device that can improve the heat dissipation of a chip substrate, and a module including the acoustic wave device.

The acoustic wave device according to the present disclosure comprises:
A chip substrate;
A wiring pattern formed on the chip substrate;
a plurality of series resonators formed on the chip substrate and electrically connected by the wiring pattern;
a first extension portion formed of a metal and extending from a region in the wiring pattern where the series resonators are directly and electrically connected to each other toward an outer edge portion of the chip substrate;
a second extension portion extending from the first extension portion along an outer edge portion of the chip substrate;
Equipped with:

It is an aspect of the present disclosure that the first extension portion and the second extension portion have a thermal conductivity higher than the thermal conductivity of the chip substrate.

It is an aspect of the present disclosure that the first extension portion and the second extension portion are formed integrally with the wiring pattern.

the first extension portion is adjacent to a region of the wiring pattern that is different from a region in which the series resonators are directly and electrically connected to each other,
According to one aspect of the present disclosure, the second extension portion extends in a direction away from a region of the wiring pattern that is different from a region in which the series resonators are directly and electrically connected to each other.

It is an aspect of the present disclosure that the second extension portion is formed from a highly thermally conductive insulator.

It is an aspect of the present disclosure that the second extension portion is joined to a region of the wiring pattern that is directly connected to the ground bump pad.

It is an aspect of the present disclosure that the second extension portion is formed away from the outer edge of the chip substrate.

It is an aspect of the present disclosure that the second extension portion is formed in an area up to 60 μm from the outer edge of the chip substrate.

an auxiliary extension portion formed of a highly thermally conductive insulator, extending from a region in the wiring pattern where the series resonators are directly and electrically connected to each other toward an outer edge of the chip substrate, and formed closer to the outer edge of the chip substrate than the region in the wiring pattern where the series resonators are directly and electrically connected to each other, and joined to a region of the wiring pattern that is directly connected to a ground bump pad;
It is an aspect of the present disclosure that the present invention is provided with the above.

a wiring substrate facing the chip substrate;
a sealing portion that hermetically seals the chip substrate together with the wiring substrate;
Equipped with
In one aspect of the present disclosure, the second extension portion is in contact with the sealing portion.

the sealing portion is disposed between the chip substrate and the wiring substrate from an outer edge portion of the chip substrate;
According to one embodiment of the present disclosure, the second extension portion is in contact with a region of the sealing portion that wraps around between the chip substrate and the wiring substrate.

The acoustic wave device according to the present disclosure comprises:
A chip substrate;
A wiring pattern formed on the chip substrate;
a plurality of series resonators formed on the chip substrate and electrically connected by the wiring pattern;
an auxiliary extension portion formed of a highly thermally conductive insulator, extending from a region in the wiring pattern where the series resonators are directly and electrically connected to each other toward an outer edge of the chip substrate, and formed closer to the outer edge of the chip substrate than the region in the wiring pattern where the series resonators are directly and electrically connected to each other, and joined to a region of the wiring pattern that is directly connected to a ground bump pad;
Equipped with:

A module including the acoustic wave device is one aspect of the present disclosure.

This disclosure makes it possible to improve the heat dissipation properties of the chip substrate.

1 is a cross-sectional view of an acoustic wave device according to a first embodiment. 2 is a view of the chip substrate seen from below after removing the wiring substrate in the acoustic wave device according to the first embodiment. FIG. FIG. 3 is an enlarged view of area A in FIG. 2 . FIG. 3 is an enlarged view of region B in FIG. 2 . FIG. 3 is an enlarged view of region C in FIG. 2 . FIG. 3 is an enlarged view of region D in FIG. 2 . 2A to 2C are diagrams illustrating a first example of an acoustic wave element of an acoustic wave device according to a first embodiment. 11 is a diagram illustrating a second example of an acoustic wave element of the acoustic wave device according to the first embodiment. FIG. 2 is a view of the chip substrate seen from below after removing the wiring substrate in the acoustic wave device according to the first embodiment. FIG. 10 is a cross-sectional view of the acoustic wave device corresponding to the cross section taken along line BB in FIG. 9. 10 is a cross-sectional view of the acoustic wave device corresponding to the cross section taken along line CC in FIG. 9. FIG. 11 is a view corresponding to FIG. 2 in the second embodiment. FIG. 13 is an enlarged view of area A in FIG. 12 . FIG. 13 is an enlarged view of region B in FIG. 12 . FIG. 13 is an enlarged view of region C in FIG. 12 . FIG. 13 is an enlarged view of region D in FIG. 12 . FIG. 11 is a view equivalent to FIG. 2 in the third embodiment. FIG. 18 is an enlarged view of region B in FIG. 17 . FIG. 18 is an enlarged view of region C in FIG. 17. FIG. 18 is an enlarged view of the vicinity of region B and region D in FIG. 17. FIG. 11 is a view equivalent to FIG. 2 in the fourth embodiment. 22 is an enlarged view of the vicinity of the auxiliary extension portion in FIG. 21 . 13 is a cross-sectional view of a module to which an acoustic wave device according to a fifth embodiment is applied.

The embodiment will be described with reference to the attached drawings. In each drawing, the same or corresponding parts are given the same reference numerals. Duplicate explanations of the parts will be appropriately simplified or omitted.

Embodiment 1.
FIG. 1 is a cross-sectional view of an acoustic wave device according to a first embodiment.

As shown in FIG. 1, the acoustic wave device 1 includes a wiring substrate 2, a chip substrate 3, a number of bumps 4, and a sealing portion 5.

For example, the wiring board 2 is a multi-layer board containing resin. For example, the wiring board 2 is a low temperature co-fired ceramics (LTCC) multi-layer board consisting of multiple dielectric layers. For example, the wiring board 2 incorporates a passive element (not shown) such as a capacitor or inductor. The wiring board 2 may be a printed circuit board (PCB). The wiring board 2 may be a high temperature co-fired ceramics (HTCC) multi-layer board consisting of multiple dielectric layers.

In FIG. 1, the upper surface of the wiring board 2 is a component mounting surface. A plurality of conductive pads 2A are formed on the upper surface of the wiring board 2. For example, the plurality of conductive pads 2A are made of copper. The lower surface of the wiring board 2 is a mounting surface for a mother board or the like. A plurality of conductive pads 2B are formed on the lower surface of the wiring board 2. For example, the plurality of conductive pads 2B are made of copper. A plurality of internal conductors 2C are built into the wiring board 2. For example, the plurality of internal conductors 2C are made of copper. Each of the internal conductors 2C electrically connects the corresponding conductive pads 2A and conductive pads 2B to each other.

The chip substrate 3 faces the wiring substrate 2. For example, the chip substrate 3 is a substrate formed of a piezoelectric single crystal such as lithium tantalate, lithium niobate, or quartz. For example, the chip substrate 3 is a substrate formed of a piezoelectric ceramic. For example, the chip substrate 3 is a substrate in which a piezoelectric substrate and a support substrate are bonded. For example, the support substrate is a substrate formed of sapphire, silicon, alumina, spinel, quartz, or glass.

For example, a receiving filter and a transmitting filter are formed on the main surface (the lower surface in FIG. 1) of the chip substrate 3.

The receiving filter is formed so that electrical signals in the desired frequency band can pass through. For example, the receiving filter is a ladder-type filter consisting of multiple series resonators and multiple parallel resonators.

The transmit filter is formed so that electrical signals in the desired frequency band can pass through. For example, the transmit filter is a ladder-type filter consisting of multiple series resonators and multiple parallel resonators.

The chip substrate 3 includes a wiring pattern 3A and a plurality of electrodes 3B. For example, the plurality of electrodes 3B are interdigital transducer (IDT) electrodes that have comb-shaped electrode fingers. The IDT electrodes receive a high-frequency electric field from the power supply lead terminal via the wiring pattern 3A to excite a surface acoustic wave, and the surface acoustic wave is converted into a high-frequency electric field by the piezoelectric effect to obtain the desired filter characteristics.

Each of the multiple bumps 4 is made of gold, conductive adhesive, solder, etc. For example, the height of the bumps 4 is 10 μm to 50 μm. Each of the multiple bumps 4 electrically connects the conductive pad 2A and the wiring pattern 3A at the corresponding position.

The sealing portion 5 hermetically seals the chip substrate 3 together with the wiring substrate 2 while leaving a space 6 between the wiring substrate 2 and the chip substrate 3. For example, the sealing portion 5 is formed of an insulating material such as a synthetic resin. The synthetic resin is an epoxy resin, a polyimide, or the like.

For example, after the chip substrate 3 is mounted on the wiring substrate 2, a resin sheet is placed across the chip substrate 3 to temporarily fix it. For example, the resin sheet is made into a sheet from liquid epoxy resin. For example, the resin sheet is formed from a synthetic resin such as polyimide, which is different from epoxy resin. For example, a protective film made of polyethylene terephthalate (PET) is provided on the upper surface of the resin sheet. For example, a base film made of polyester is provided on the lower surface of the resin sheet. The resin sheet is then heated to its softening temperature. As a result, the resin sheet fills the side surface of the chip substrate 3 and the upper surface of the wiring substrate 2. This method is called a hot roller lamination method. At this time, a certain amount of resin wraps around between the chip substrate 3 and the wiring substrate 2 from the outer edge of the chip substrate 3. The resin sheet is then heated to a hardening temperature to completely harden.

Next, the configuration of the chip substrate 3 will be described with reference to FIG.
Fig. 2 is a view of the chip substrate after removing the wiring substrate in the acoustic wave device according to the first embodiment, as viewed from below. Fig. 3 is an enlarged view of region A in Fig. 2. Fig. 4 is an enlarged view of region B in Fig. 2. Fig. 5 is an enlarged view of region C in Fig. 2. Fig. 6 is an enlarged view of region D in Fig. 2.

In FIG. 2, R1 is the area secured when the chip substrate 3 is cut out. For example, R1 is the area extending from the outer edge of the chip substrate 3 toward the center of the chip substrate 3 to 30 μm. R2 indicates the area where the sealing portion 5 wraps around from the outer edge of the chip substrate 3 between the chip substrate 3 and the wiring substrate 2. For example, R2 is the area extending from the outer edge of the chip substrate 3 toward the center of the chip substrate 3 to 60 μm.

As shown in FIG. 2, the wiring pattern 3A and the multiple acoustic wave elements 8 are formed on the main surface of the chip substrate 3.

The wiring pattern 3A is formed so as not to invade the region R1. For example, the wiring pattern 3A is formed of a metal or alloy such as silver, aluminum, copper, titanium, or palladium. For example, the wiring pattern 3A is formed by stacking multiple metal layers. For example, the thickness of the wiring pattern 3A is 1.0 μm to 5.0 μm.

The wiring pattern 3A includes an antenna bump pad ANT, a transmission bump pad Tx, a reception bump pad Rx, and four ground bump pads GND. These bump pads are electrically connected to the bump 4.

The multiple elastic wave elements 8 include multiple series resonators S1-Rx, S2-Rx, multiple parallel resonators P1-Rx, P2-Rx, and a multi-mode resonator DMS. The multiple series resonators S1-Rx, S2-Rx, the multiple parallel resonators P1-Rx, P2-Rx, and the multi-mode resonator DMS are electrically connected via wiring pattern 3A. The multiple series resonators S1-Rx, S2-Rx are not directly electrically connected to any of the ground bump pads GND. The multiple parallel resonators P1-Rx, P2-Rx, and the multi-mode resonator DMS are directly electrically connected to any of the ground bump pads GND.

The multiple series resonators S1-Rx, S2-Rx, the multiple parallel resonators P1-Rx, P2-Rx, and the multi-mode resonator DMS function as a receiving filter. Specifically, when an electrical signal is input to the antenna bump pad ANT, the electrical signal passes through the multiple series resonators S1-Rx, S2-Rx, the multiple parallel resonators P1-Rx, P2-Rx, and the multi-mode resonator DMS. At this time, only the electrical signal in the desired frequency band reaches the receiving bump pad Rx. As a result, only the electrical signal in the desired frequency band is output from the receiving bump pad Rx.

The elastic wave elements 8 include a plurality of series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx and a plurality of parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx. The series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx and the parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx are electrically connected via the wiring pattern 3A. The series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx are not directly electrically connected to any of the ground bump pads GND. The parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx are directly electrically connected to any of the ground bump pads GND.

The multiple series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx and the multiple parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx function as a transmission filter. Specifically, when an electrical signal is input to the transmission bump pad Tx, the electrical signal passes through the multiple series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx and the multiple parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx. At this time, only the electrical signal in the desired frequency band reaches the antenna bump pad ANT. As a result, only the electrical signal in the desired frequency band is output from the antenna bump pad ANT.

The chip substrate 3 has a plurality of extension portions 9. For example, the plurality of extension portions 9 are formed integrally with the wiring pattern 3A at the same time. The extension portions 9 have a first extension portion 9A and a second extension portion 9B.

For example, the first extension portion 9 is formed in region A on the right side of the chip substrate 3. Region A is shown in an enlarged view in FIG. 3. In region A, the first extension portion 9A extends from a region in the wiring pattern 3A where the series resonators S1-Tx and S2-Tx are directly electrically connected to each other toward the right outer edge of the chip substrate 3. For example, the first extension portion 9A is adjacent to a region in the wiring pattern 3A different from the region in which the series resonators S1-Tx and S2-Tx are directly electrically connected to each other. Specifically, the first extension portion 9A is adjacent to the ground bump pad GND on the right and lower side of the chip substrate 3. The second extension portion 9B extends from the end of the first extension portion 9A along the right outer edge of the chip substrate 3. At this time, the second extension portion 9B extends in a direction away from a region in the wiring pattern 3A different from the region in which the series resonators S1-Tx and S2-Tx are directly electrically connected to each other. Specifically, the second extension portion 9B extends in a direction away from the ground bump pad GND on the lower right side of the chip substrate 3 (downward in FIG. 2).

For example, the second extension portion 9 is formed in region B on the left side of the chip substrate 3. Region B is shown enlarged in FIG. 4. In region B, the first extension portion 9A extends from a region in the wiring pattern 3A where the series resonators S2-Tx (not shown in FIG. 4) and S3-Tx are directly electrically connected to each other toward the left outer edge of the chip substrate 3. The second extension portion 9B extends in the vertical direction from the end of the first extension portion 9A along the left outer edge of the chip substrate 3.

For example, the third extension portion 9 is formed in region C on the right side of the chip substrate 3. Region C is shown in an enlarged view in FIG. 5. In region C, the first extension portion 9A extends from a region in the wiring pattern 3A where the series resonators S3-Tx and S4-Tx (both not shown in FIG. 5) are directly electrically connected to each other toward the right outer edge of the chip substrate 3. For example, the first extension portion 9A is adjacent to a region in the wiring pattern 3A that is different from the region in which the series resonators S3-Tx and S4-Tx are directly electrically connected to each other. Specifically, the first extension portion 9A is adjacent to a region in the wiring pattern 3A that is directly electrically connected to the ground bump pad GND (not shown in FIG. 5) on the right and upper side of the chip substrate 3. The second extension portion 9B extends from the end of the first extension portion 9A along the right outer edge of the chip substrate 3. The second extension portion 9B extends in a direction away from a region in the wiring pattern 3A that is different from the region in which the series resonators S3-Tx and S4-Tx are directly and electrically connected to each other. Specifically, the second extension portion 9B extends in a direction away from the region in the wiring pattern 3A that is directly and electrically connected to the ground bump pad GND on the right and upper side of the chip substrate 3 (downward in FIG. 2).

For example, the fourth extension portion 9 is formed in region D on the left side of the chip substrate 3. Region D is shown enlarged in FIG. 6. In region D, the first extension portion 9A extends from a region in the wiring pattern 3A where the series resonators S3-Tx and S4-Tx (not shown in FIG. 6) are directly and electrically connected to each other toward the left outer edge of the chip substrate 3. The second extension portion 9B extends in the vertical direction from the end of the first extension portion 9A along the left outer edge of the chip substrate 3.

Of the multiple extension portions 9, the second extension portion 9B is formed so as not to intrude into region R1. The second extension portion 9B is formed so as to be in contact with the sealing portion 5. Specifically, the second extension portion 9B is formed so as to be in contact with the region of the sealing portion 5 that wraps around between the chip substrate 3 and the wiring substrate 2. More specifically, the second extension portion 9B is formed so that at least a portion of it intrudes into region R2.

Next, a first example of acoustic wave element 8 will be described with reference to FIG.
FIG. 7 is a diagram illustrating a first example of an acoustic wave element of an acoustic wave device according to the first embodiment. In FIG.

In FIG. 7, the acoustic wave element 8 is a SAW (Surface Acoustic Wave) resonator. As shown in FIG. 7, an IDT (Interdigital Transducer) 8A and a pair of reflectors 8B are formed on the main surface of the chip substrate 3. The IDT 8A and the pair of reflectors 8B are arranged so as to excite a surface acoustic wave.

For example, the IDT 8A and the pair of reflectors 8B are formed from an alloy of aluminum and copper. For example, the IDT 8A and the pair of reflectors 8B are formed from a suitable metal such as titanium, palladium, or silver, or an alloy of these metals. For example, the IDT 8A and the pair of reflectors 8B are formed from a laminated metal film in which multiple metal layers are stacked. For example, the thickness of the IDT 8A and the pair of reflectors 8B is 150 nm to 400 nm.

The IDT 8A has a pair of comb electrodes 8C. The pair of comb electrodes 8C face each other. The comb electrode 8C has a plurality of electrode fingers 8D and a bus bar 8E. The plurality of electrode fingers 8D are arranged with their longitudinal directions aligned. The bus bar 8E connects the plurality of electrode fingers 8D. One of the pair of reflectors 8B is adjacent to one side of the IDT 8A. The other of the pair of reflectors 8B is adjacent to the other side of the IDT 8A. For example, the IDT 8A and the pair of reflectors 8B are formed and patterned in the same process as the wiring pattern 3A (not shown in FIG. 3).

Next, a second example of acoustic wave element 8 will be described with reference to FIG.
FIG. 8 is a diagram illustrating a second example of the acoustic wave element of the acoustic wave device according to the first embodiment. In FIG.

.
In FIG. 8, the acoustic wave element 8 is an acoustic thin film resonator. For example, the chip substrate 3 is a semiconductor substrate such as silicon, or an insulating substrate such as sapphire, alumina, spinel, or glass. The piezoelectric film 8F is provided on the main surface of the chip substrate 3. For example, the piezoelectric film 8F is made of aluminum nitride. The lower electrode 8G and the upper electrode 8H are provided so as to sandwich the piezoelectric film 8F. For example, the lower electrode 8G and the upper electrode 8H are made of a metal such as ruthenium. A gap 8J is formed between the lower electrode 8G and the chip substrate 3. In the acoustic thin film resonator, the lower electrode 8G and the upper electrode 8H excite an acoustic wave in a thickness longitudinal vibration mode inside the piezoelectric film 8F.

Next, heat dissipation from the chip substrate 3 will be described with reference to FIGS.
Fig. 9 is a view of the chip substrate in the acoustic wave device according to the first embodiment after removing the wiring substrate, as viewed from below. Fig. 10 is a cross-sectional view of the acoustic wave device corresponding to the cross section taken along line B-B in Fig. 9. Fig. 11 is a cross-sectional view of the acoustic wave device corresponding to the cross section taken along line CC in Fig. 9. However, Figs. 10 and 11 are shown upside down to match the orientation with Fig. 1. Configurations unnecessary for the explanation are omitted as appropriate in Figs. 10 and 11.

9 to 11, the chip substrate 3 is made of lithium tantalate. The thermal conductivity of lithium tantalate at 25°C is about 4.6 W/m·K. The wiring pattern 3A and the extension portion 9 are integrally formed of aluminum. The thermal conductivity of aluminum at 25°C is about 204 W/m·K. The sealing portion 5 is formed of a highly thermally conductive resin. The thermal conductivity of the highly thermally conductive resin at 25°C is about 3.0 W/m·K. In FIGS. 10 and 11, the conductive pad 2A, the conductive pad 2B, and the internal conductor 2C are made of copper. The thermal conductivity of copper at 25°C is about 403 W/m·K. The bump 4 is made of gold. The thermal conductivity of gold at 25°C is about 295 W/m·K. The thermal conductivity of air at 25°C is about 0.025 W/m·K.

When the acoustic wave device 1 operates, the multiple acoustic wave elements 8 generate heat. Around each acoustic wave element 8, the heat is transferred to the chip substrate 3, the wiring pattern 3A, and the air. Here, the thermal conductivity of the wiring pattern 3A is higher than the thermal conductivity of the chip substrate 3 and the thermal conductivity of the air. Therefore, more heat is transferred to the wiring pattern 3A.

From the area of the wiring pattern 3A that is directly and electrically connected to any of the bump pads, more heat is transferred to the wiring board 2 via one of the bump pads and the bumps 4. In contrast, from the area of the wiring pattern 3A that is not directly and electrically connected to any of the bump pads, a very small amount of heat is transferred to one of the bump pads via the chip substrate 3 and the air. Therefore, only a small amount of heat is transferred to the wiring board 2 from the area of the wiring pattern 3A that is not directly and electrically connected to any of the bump pads.

However, from the regions corresponding to the four extensions 9 in the wiring pattern 3A, a lot of heat is transferred to one of the bump pads through the extensions 9 and the sealing portion 5. For example, from region A in FIG. 9, a lot of heat is transferred through the first extension 9 and the sealing portion 5 to the ground bump pad GND on the right side and the lower side of the chip substrate 3 and the transmission bump pad Tx. For example, from region B in FIG. 9, a lot of heat is transferred through the second extension 9 and the sealing portion 5 to the ground bump pad GND on the left side and the lower side of the chip substrate 3. For example, from region C in FIG. 9, a lot of heat is transferred to the ground bump pad GND on the right side and the lower side of the chip substrate 3 and the ground bump pad GND on the upper side. For example, in region D in FIG. 9, a lot of heat is transferred through the fourth extension 9 and the sealing portion 5 to the antenna bump pad ANT on the left side of the chip substrate 3. These bump pads release heat to the wiring substrate 2 through the bumps 4. This heat is dissipated to the outside of the acoustic wave device 1.

For example, in FIG. 10, the transmission bump pad Tx releases heat from the second extension portion 9B of the region A to the outside of the acoustic wave device 1 via the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B. For example, in FIG. 10, the ground bump pad GND on the right side releases heat from the second extension portion 9B of the region A to the outside of the acoustic wave device 1 via the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B. For example, in FIG. 10, the ground bump pad GND on the right side releases heat from the second extension portion 9B of the region C to the outside of the acoustic wave device 1 via the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B. For example, in FIG. 10, the ground bump pad GND on the left side releases heat from the second extension portion 9B of the region C to the outside of the acoustic wave device 1 via the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B.

For example, the ground bump pad GND on the left side of FIG. 11 releases heat from the second extension portion 9B in region B to the outside of the acoustic wave device 1 via the bump 4, conductive pad 2A, internal conductor 2C, and conductive pad 2B. For example, the antenna bump pad ANT in FIG. 11 releases heat from the second extension portion 9B in region D to the outside of the acoustic wave device 1 via the bump 4, conductive pad 2A, internal conductor 2C, and conductive pad 2B.

According to the first embodiment described above, the first extension portion 9A extends from the region in the wiring pattern 3A where the series resonators are directly and electrically connected to each other toward the outer edge of the chip substrate 3. The second extension portion 9B extends from the first extension portion 9A along the outer edge of the chip substrate 3. Therefore, compared to when the extension portion 9 does not exist, more heat can be dissipated from the region in the wiring pattern 3A where the series resonators are directly and electrically connected to each other through the first extension portion 9A and the second extension portion 9B. As a result, the heat dissipation properties of the chip substrate 3 can be improved.

In addition, the extension portion 9 has a thermal conductivity higher than that of the chip substrate 3. Therefore, the heat dissipation of the chip substrate 3 can be improved more reliably through the extension portion 9.

In addition, the extension portion 9 is formed integrally with the wiring pattern 3A. This improves the heat dissipation of the chip substrate 3 without the need for an additional process just for forming the extension portion 9.

In addition, in regions A and C, the first extension portion 9A is adjacent to a region in the wiring pattern 3A that is different from the region in which the series resonators are directly and electrically connected to each other. The second extension portion 9B extends in a direction away from the region in the wiring pattern 3A that is different from the region in which the series resonators are directly and electrically connected to each other. This makes it possible to improve the heat dissipation of the chip substrate 3 while maintaining the compact size of the acoustic wave device 1.

The second extension portion 9B is formed away from the outer edge of the chip substrate 3. This prevents the second extension portion 9B from coming into contact with the dicing blade when the chip substrate 3 is cut out from the wafer.

The second extension 9B also comes into contact with the area of the sealing portion 5 that wraps around between the chip substrate 3 and the wiring substrate 2. This allows more heat to be dissipated through the second extension 9B and the sealing portion 5 from the area in the wiring pattern 3A where the series resonators are directly and electrically connected to each other.

The second extension portion 9B is formed in a region up to 60 μm from the outer edge of the chip substrate 3. This allows the second extension portion 9B to be in contact with the sealing portion 5 more reliably.

The extension portion 9 is formed in a region where multiple series resonators that function as part of the transmission filter are directly and electrically connected to each other. This improves the dissipation of heat generated by the series resonators, particularly in transmission filters that generate a lot of heat.

Embodiment 2.
Fig. 12 is a view equivalent to Fig. 2 in embodiment 2. Fig. 13 is an enlarged view of area A in Fig. 12. Fig. 14 is an enlarged view of area B in Fig. 12. Fig. 15 is an enlarged view of area C in Fig. 12. Fig. 16 is an enlarged view of area D in Fig. 12. Note that parts that are the same as or equivalent to parts in embodiment 1 are given the same reference numerals. Description of these parts will be omitted.

In the extension portion 9 in Figures 12 to 16, the first extension portion 9A is formed integrally with the wiring pattern 3A at the same time. The second extension portion 9B is directly bonded to the first extension portion 9A. The second extension portion 9B is formed of a highly thermally conductive insulator. For example, the second extension portion 9B is formed of epoxy resin, polyimide resin, silicon, solder resist, boron nitride, aluminum nitride, aluminum oxide, zinc oxide, or silicon oxide.

According to the second embodiment described above, the second extension portion 9B is formed of a highly thermally conductive insulator. Therefore, as in the first embodiment, the heat dissipation of the chip substrate 3 can be improved. In particular, boron nitride, aluminum nitride, and aluminum oxide have high thermal conductivity. Specifically, the thermal conductivity of boron nitride is about 60 W/m·K. The thermal conductivity of aluminum nitride is about 150 W/m·K. The thermal conductivity of aluminum oxide is about 29 W/m·K. Therefore, if any of boron nitride, aluminum nitride, and aluminum oxide is used as the second extension portion 9B, the heat dissipation of the chip substrate 3 can be more reliably improved.

Embodiment 3.
Fig. 17 is a view corresponding to Fig. 2 in embodiment 3. Fig. 18 is an enlarged view of region B in Fig. 17. Fig. 19 is an enlarged view of region C in Fig. 17. Fig. 20 is an enlarged view of the vicinity of region B and region D in Fig. 17. Note that the same reference numerals are used to designate parts that are the same as or equivalent to those in embodiment 2. Description of these parts will be omitted.

As shown in Figures 17 and 18, in the extension portion 9 in region B, the second extension portion 9B is formed of a highly thermally conductive insulator. The second extension portion 9B is directly bonded to a region in the wiring pattern 3A that is directly connected to the ground bump pad GND (not shown in Figure 18) on the left and lower side of the chip substrate 3. As shown in Figures 17 and 19, in the extension portion 9 in region C, the second extension portion 9B is formed of a highly thermally conductive insulator. The second extension portion 9B is directly bonded to a region in the wiring pattern 3A that is directly connected to the ground bump pad GND (not shown in Figure 19) on the right and upper side of the chip substrate 3.

As shown in Figures 17 and 20, the second extension portions 9B of the extension portion 9 in region B and the extension portion 9 in region D are formed to be connected to each other. For example, the extension portion 9 in region B and the extension portion 9 in region D are formed integrally.

According to the third embodiment described above, the second extension portion 9B is joined to an area of the wiring pattern 3A that is directly connected to the ground bump pad GND. This allows the heat from the second extension portion 9B to be efficiently transferred to the ground bump pad GND. As a result, the heat dissipation of the chip substrate 3 can be more reliably improved.

Embodiment 4.
Fig. 21 is a view equivalent to Fig. 2 in embodiment 4. Fig. 22 is an enlarged view of the vicinity of the auxiliary extension portion in Fig. 21. Note that the same reference numerals are used to designate parts that are the same as or equivalent to parts in embodiment 3. Description of these parts will be omitted.

21 and 22, the auxiliary extension 10 is formed of a high thermal conductivity insulator equivalent to that of the second extension 9B (not shown in FIG. 22). For example, the auxiliary extension 10 is formed so as to extend from the right side of the region in the wiring pattern 3A where the series resonators S2-Tx and S3-Tx (not shown in FIG. 22) are directly and electrically connected to each other toward the right outer edge of the chip substrate 3. The auxiliary extension 10 is joined to a region formed on the right outer edge side of the chip substrate 3 (not shown in FIG. 22) rather than the region in the wiring pattern 3A where the series resonators S2-Tx and S3-Tx are directly and electrically connected to each other. This region is directly connected to the ground bump pad GND (not shown in FIG. 22) on the right and lower side of the chip substrate 3.

According to the fourth embodiment described above, the auxiliary extension portion 10 extends from the region in the wiring pattern 3A where the series resonators are directly and electrically connected to each other to the outside of the chip substrate 3. The auxiliary extension portion 10 is joined to the region in the wiring pattern 3A that is directly connected to the ground bump pad GND. Therefore, even if the heat dissipation from the region in the wiring pattern 3A where the series resonators S2-Tx and S3-Tx are directly and electrically connected to each other is insufficient, the heat can be efficiently dissipated from the region via the auxiliary extension portion 10.

Embodiment 5.
23 is a cross-sectional view of a module to which the acoustic wave device according to the fifth embodiment is applied. Note that the same reference numerals are used to designate the same or corresponding parts as those in the first embodiment, and the description of these parts will be omitted.

In FIG. 23, the module 100 includes a wiring board 101, an integrated circuit component 102, an acoustic wave device 1, an inductor 103, and a sealing portion 104.

The wiring board 101 is equivalent to the wiring board 2 of the first embodiment. The integrated circuit component 102 is mounted inside the wiring board 101. The integrated circuit component 102 includes a switching circuit and a low-noise amplifier. The acoustic wave device 1 is mounted on the main surface of the wiring board 101. The inductor 103 is mounted on the main surface of the wiring board 101. The inductor 103 is mounted for impedance matching. For example, the inductor 103 is an integrated passive device (IPD). The sealing portion 104 seals multiple electronic components including the acoustic wave device 1.

According to the fifth embodiment described above, the module 100 includes an acoustic wave device 1. Therefore, it is possible to realize a module 100 including an acoustic wave device 1 with high heat dissipation properties.

While several aspects of at least one embodiment have been described, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of, and are intended to be within the scope of, this disclosure.

It should be understood that the embodiments of the methods and apparatus described herein are not limited in their application to the details of construction and arrangement of components set forth in the above description or illustrated in the accompanying drawings. The methods and apparatus may be implemented in other embodiments and practiced or carried out in various ways.

The specific implementation examples are provided here for illustrative purposes only and are not intended to be limiting.

The phraseology and terminology used in this disclosure are for purposes of description and should not be regarded as limiting. The use herein of "including," "comprising," "having," "including" and variations thereof means the inclusion of the items listed thereafter and equivalents thereof as well as additional items.

References to "or" may be construed as meaning that any term described using "or" refers to one, more than one, and all of those described terms.

All references to front, back, left, right, top, bottom, top, bottom, width, length, front and back are intended for convenience of description. Such references are not intended to limit the components of this disclosure to any one positional or spatial orientation. Accordingly, the above description and drawings are by way of example only.

LIST OF SYMBOLS 1 Acoustic wave device, 2 Wiring substrate, 2A Conductive pad, 2B Conductive pad, 2C Internal conductor, 3 Chip substrate, 3A Wiring pattern, 3B Electrode, 4 Bump, 5 Sealing portion, 6 Space, 8 Acoustic wave element, 8A IDT, 8B Reflector, 8C Comb-shaped electrode, 8D Electrode finger, 8E Bus bar, 8F Piezoelectric film, 8G Lower electrode, 8H Upper electrode, 8J Air gap, 9 Extension portion, 9A First extension portion, 9B Second extension portion, 10 Auxiliary extension portion, 100 Module, 101 Wiring substrate, 102 Integrated circuit component, 103 Inductor, 104 Sealing portion

Claims (13)

A chip substrate;
A wiring pattern formed on the chip substrate;
a plurality of series resonators formed on the chip substrate and electrically connected by the wiring pattern;
a first extension portion formed of a metal and extending from a region in the wiring pattern where the series resonators are directly and electrically connected to each other toward an outer edge portion of the chip substrate;
a second extension portion extending from the first extension portion along an outer edge portion of the chip substrate;
An acoustic wave device comprising: The acoustic wave device according to claim 1, wherein the first extension portion and the second extension portion have a thermal conductivity higher than the thermal conductivity of the chip substrate. The acoustic wave device according to claim 1, wherein the first extension portion and the second extension portion are formed integrally with the wiring pattern. the first extension portion is adjacent to a region of the wiring pattern that is different from a region in which the series resonators are directly and electrically connected to each other,
The acoustic wave device according to claim 3 , wherein the second extension portion extends in a direction away from a region of the wiring pattern that is different from a region in which the series resonators are directly and electrically connected to each other. The acoustic wave device according to claim 1, wherein the second extension portion is formed from a highly thermally conductive insulator. The acoustic wave device according to claim 5, wherein the second extension portion is joined to an area of the wiring pattern that is directly connected to a ground bump pad. The acoustic wave device according to claim 1, wherein the second extension portion is formed away from the outer edge of the chip substrate. The acoustic wave device according to claim 1, wherein the second extension portion is formed in a region up to 60 μm from the outer edge of the chip substrate. an auxiliary extension portion formed of a highly thermally conductive insulator, extending from a region in the wiring pattern where the series resonators are directly and electrically connected to each other toward an outer edge of the chip substrate, and formed closer to the outer edge of the chip substrate than the region in the wiring pattern where the series resonators are directly and electrically connected to each other, and joined to a region of the wiring pattern that is directly connected to a ground bump pad;
The acoustic wave device according to claim 1 . a wiring substrate facing the chip substrate;
a sealing portion that hermetically seals the chip substrate together with the wiring substrate;
Equipped with
The acoustic wave device according to claim 1 , wherein the second extension portion is in contact with the sealing portion. the sealing portion is disposed between the chip substrate and the wiring substrate from an outer edge portion of the chip substrate;
The acoustic wave device according to claim 10 , wherein the second extension portion is in contact with a region of the sealing portion that extends between the chip substrate and the wiring substrate. A chip substrate;
A wiring pattern formed on the chip substrate;
a plurality of series resonators formed on the chip substrate and electrically connected by the wiring pattern;
an auxiliary extension portion formed of a highly thermally conductive insulator, extending from a region in the wiring pattern where the series resonators are directly and electrically connected to each other toward an outer edge of the chip substrate, and formed closer to the outer edge of the chip substrate than the region in the wiring pattern where the series resonators are directly and electrically connected to each other, and joined to a region of the wiring pattern that is directly connected to a ground bump pad;
An acoustic wave device comprising: A module comprising the acoustic wave device according to claim 1 .

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