CN118100847A

CN118100847A - Elastic wave device and module comprising same

Info

Publication number: CN118100847A
Application number: CN202311559265.0A
Authority: CN
Inventors: 桑原英司
Original assignee: Sanyan Japan Technology Co ltd
Current assignee: Sanyan Japan Technology Co ltd
Priority date: 2022-11-22
Filing date: 2023-11-21
Publication date: 2024-05-28
Also published as: JP2024075027A

Abstract

An elastic wave device comprising: a chip substrate; wiring patterns formed on the chip substrate; a plurality of series resonators formed on the chip substrate and electrically connected through the wiring pattern; a first extension portion formed of metal and extending from a region of the wiring pattern directly electrically connected between the series resonators toward an outer edge portion of the chip substrate; and a second extension portion extending from the first extension portion along an outer edge portion of the chip substrate. Thus, an elastic wave device capable of improving heat dissipation of the chip substrate can be provided.

Description

Elastic wave device and module comprising same

Technical Field

The present disclosure relates to an elastic wave device and a module including the same.

Background

Japanese patent document 1 (japanese patent application laid-open No. 2022-028566) exemplifies an elastic wave device. The elastic wave device has excellent power durability and bondability (bondability).

However, in the elastic wave device described in japanese patent document 1, heat from the chip substrate is difficult to dissipate. Therefore, the heat dissipation of the chip substrate is low.

Disclosure of Invention

In view of the foregoing, an object of the present disclosure is to provide an elastic wave device capable of improving heat dissipation of a chip substrate and a module including the elastic wave device.

The elastic wave device of the present disclosure includes:

A chip substrate;

wiring patterns formed on the chip substrate;

a plurality of series resonators formed on the chip substrate and electrically connected through the wiring pattern;

a first extension portion formed of metal and extending from a region of the wiring pattern directly electrically connected between the series resonators toward an outer edge portion of the chip substrate; and

And a second extension portion extending from the first extension portion along an outer edge portion of the chip substrate.

In one aspect of the present disclosure, the first extension and the second extension have a thermal conductivity higher than a thermal conductivity of the chip substrate.

In one aspect of the present disclosure, the first extension portion and the second extension portion are integrally formed with the wiring pattern.

In one aspect of the present disclosure, the first extension portion is adjacent to a region of the wiring pattern different from a region directly electrically connected between the series resonators, and the second extension portion extends in a direction away from a region of the wiring pattern different from a region directly electrically connected between the series resonators.

In one aspect of the present disclosure, the second extension is formed of a high thermal conductivity insulator.

In one aspect of the present disclosure, the second extension portion is connected to a region of the wiring pattern where the bump pad for grounding is not directly connected.

In one aspect of the present disclosure, the second extension portion is spaced from an outer edge portion of the chip substrate.

In one aspect of the present disclosure, the second extension portion is located in a region closer to 60 μm from an outer edge portion of the chip substrate toward a center side of the chip substrate.

In one embodiment of the present disclosure, the elastic wave device further includes an auxiliary extension portion formed of a high thermal conductive insulator and extending from a region directly electrically connected between the series resonators in the wiring pattern toward the outer edge portion of the chip substrate, the auxiliary extension portion being formed on a side of the wiring pattern closer to the outer edge portion of the chip substrate than the region directly electrically connected between the series resonators and being directly connected to a region directly connected to a bump pad for grounding of the wiring pattern.

In one aspect of the present disclosure, the elastic wave device further includes a wiring substrate facing the chip substrate, and a sealing portion for hermetically sealing the wiring substrate and the chip substrate, and the second extension portion is connected to the sealing portion.

An aspect of the present disclosure is characterized in that: the sealing part surrounds the space between the chip substrate and the wiring substrate from the outer edge part of the chip substrate, and the second extending part is connected with the sealing part and surrounds the space between the chip substrate and the wiring substrate.

The elastic wave device of the present disclosure includes:

A chip substrate;

wiring patterns formed on the chip substrate;

A plurality of series resonators formed on the chip substrate and electrically connected through the wiring pattern; and

The auxiliary extension part is formed by a high heat-conductive insulator, is directly and electrically connected with the region between the series resonators from the wiring pattern, extends towards the outer edge part of the chip substrate, and is connected with the region which is closer to the outer edge part side of the chip substrate than the region between the series resonators and is directly connected with the bump bonding pad for grounding of the wiring pattern.

One aspect of the present disclosure includes a module of the elastic wave device.

The invention has the beneficial effects that: according to the present disclosure, heat dissipation of the chip substrate can be improved.

Drawings

Fig. 1 is a cross-sectional view of an elastic wave device of a first embodiment.

Fig. 2 is a bottom view of the chip substrate of the elastic wave device according to the first embodiment, with the wiring substrate removed.

Fig. 3 is an enlarged view of the area a of fig. 2.

Fig. 4 is an enlarged view of the area B of fig. 2.

Fig. 5 is an enlarged view of the region C of fig. 2.

Fig. 6 is an enlarged view of the area D of fig. 2.

Fig. 7 is a schematic view of a first example of an elastic wave element of the elastic wave device of the first embodiment.

Fig. 8 is a schematic diagram of a second example of the elastic wave element of the elastic wave device of the first embodiment.

Fig. 9 is a bottom view of the chip substrate with the wiring substrate removed in the acoustic wave device of the first embodiment.

Fig. 10 is a cross-sectional view of the elastic wave device taken along section line B-B of fig. 9, upside down in order to conform to the direction of fig. 1.

Fig. 11 is a cross-sectional view of the elastic wave device taken along section line C-C of fig. 9, upside down in order to conform to the direction of fig. 1.

Fig. 12 is a view similar to fig. 2 of the second embodiment.

Fig. 13 is an enlarged view of the area a in fig. 12.

Fig. 14 is an enlarged view of area B in fig. 12.

Fig. 15 is an enlarged view of the area C in fig. 12.

Fig. 16 is an enlarged view of the area D in fig. 12.

Fig. 17 is a view similar to fig. 2 of the third embodiment.

Fig. 18 is an enlarged view of a region B in fig. 17.

Fig. 19 is an enlarged view of region C in fig. 17.

Fig. 20 is an enlarged view of the vicinity of the region B and the region D in fig. 17.

Fig. 21 is a view similar to fig. 2 of the fourth embodiment.

Fig. 22 is an enlarged view of the vicinity of the auxiliary extension in fig. 21.

Fig. 23 is a cross-sectional view of a module to which the elastic wave device of the fifth embodiment is applied.

Detailed Description

Specific embodiments of the present invention will be described below with reference to the accompanying drawings. The same or corresponding parts in the various drawings are denoted by the same reference numerals. The same or equivalent parts will be appropriately simplified or omitted from illustration.

(First embodiment)

Fig. 1 is a cross-sectional view of an elastic wave device 1 of a first embodiment.

As shown in fig. 1, the acoustic wave device 1 includes a wiring board 2, a chip board 3, a plurality of bumps 4, and a sealing portion 5.

For example, the wiring board 2 is a multilayer board including a resin. For example, the wiring substrate 2 is a low temperature co-fired ceramic (Low Temperature Co-FIRED CERAMICS, LTCC) multilayer substrate formed of a plurality of dielectric layers. A passive element (not shown) such as a capacitor or an inductor may be provided inside the wiring board 2. The wiring substrate 2 is a printed circuit board (Printed Circuit Board, PCB). The wiring substrate 2 is a high temperature co-fired ceramic (High Temperature Co-FIRED CERAMICS, HTCC) multilayer substrate formed of a plurality of dielectric layers.

In fig. 1, the upper surface of the wiring substrate 2 is an element mounting surface. A plurality of conductive pads 2A are formed on the upper surface of the wiring substrate 2. For example, a plurality of the conductive pads 2A are formed of copper. The lower surface of the wiring board 2 is a mounting surface of a motherboard. A plurality of conductive pads 2B are formed on the lower surface of the wiring substrate 2. For example, a plurality of the conductive pads 2B are formed of copper. The plurality of inner conductors 2C are provided inside the wiring board 2. For example, a plurality of the inner conductors 2C are formed of copper. The inner conductors 2C are electrically connected to the corresponding conductive pads 2A and 2B, respectively.

The chip substrate 3 faces the wiring substrate 2. For example, the chip substrate 3 is a substrate made of a single crystal such as lithium tantalate, lithium niobate, or crystal. The chip substrate 3 is, for example, a substrate made of piezoelectric ceramics. According to still another example, the chip substrate 3 is a substrate formed by bonding a piezoelectric substrate and a support substrate. For example, the support substrate is a substrate made of sapphire, silicon, alumina, spinel, crystal, or glass.

For example, in the main surface (lower surface in fig. 1) of the chip substrate 3, a reception filter and a transmission filter are formed.

The receive filter is capable of passing electrical signals in a desired frequency band. For example, the reception filter is provided with a ladder filter composed of a plurality of series resonators and a plurality of parallel resonators.

The transmit filter is capable of passing electrical signals in a desired frequency band. For example, the transmission filter is provided with a ladder filter composed of a plurality of series resonators and a plurality of parallel resonators.

The chip substrate 3 is formed with a wiring pattern 3A and a plurality of electrodes 3B. For example, the electrode 3B is an interdigital transducer (INTERDIGITAL TRANSDUCER, IDT) electrode having comb-shaped electrode fingers. The characteristics of the filter are obtained by exciting the surface acoustic wave by applying a high-frequency electric field to the IDT electrode from the lead terminal on the power supply side through the wiring pattern 3A, and converting the surface acoustic wave into a high-frequency electric field by the piezoelectric effect.

The bump 4 is formed of gold, conductive paste, solder, or the like. For example, the height of the bump 4 is 10 μm to 50 μm. The conductive pads 2A corresponding to the positions of the bumps 4 are electrically connected to the wiring patterns 3A.

The sealing portion 5 leaves a space 6 between the wiring substrate 2 and the chip substrate 3, and hermetically seals the wiring substrate 2 and the chip substrate 3. For example, the sealing portion 5 is formed of an insulator such as a synthetic resin. The synthetic resin is, for example, epoxy (Epoxy) or Polyimide (Polyimide) or the like.

For example, after the chip substrate 3 is mounted on the wiring substrate 2, the resin layer is temporarily fixed across the chip substrate 3. For example, the resin layer is obtained by pressing a liquid epoxy resin into a sheet. For example, the resin layer may be formed of a synthetic resin such as polyimide, which is different from the epoxy resin. For example, a protective film made of polyethylene terephthalate (Polyethylene Terephthalate, PET) may be provided on the upper surface of the resin layer, or a base film made of Polyester (Polyester) may be provided on the lower surface of the resin layer. Then, the resin layer is heated to a softening temperature. Thereby, the resin layer is filled in the side surface of the chip substrate 3 and the upper surface of the wiring substrate 2. This process is known as hot rolling. At this time, the resin is wound around the chip substrate 3 and the wiring substrate 2 by a predetermined amount from the outer edge of the chip substrate 3. Then, the resin layer is heated to a curing temperature to be completely cured.

Next, the structure of the chip substrate 3 will be described with reference to fig. 2.

Fig. 2 is a bottom view of the chip substrate of the elastic wave device of the first embodiment with the wiring substrate removed. Fig. 3 is an enlarged view of the area a of fig. 2. Fig. 4 is an enlarged view of the area B of fig. 2. Fig. 5 is an enlarged view of the region C of fig. 2. Fig. 6 is an enlarged view of the area D of fig. 2.

In fig. 2, R1 is a secured area when the chip substrate 3 is cut. For example, R1 is a region near 30 μm from the outer edge of the chip substrate 3 toward the center of the chip substrate 3. R2 is a region where the sealing portion 5 surrounds from the outer edge portion of the chip substrate 3 to between the chip substrate 3 and the wiring substrate 2. For example, R2 is a region near 60 μm from the outer edge of the chip substrate 3 toward the center of the chip substrate 3.

As shown in fig. 2, the wiring pattern 3A and the plurality of elastic wave elements 8 are formed on the main surface of the chip substrate 3.

The wiring pattern 3A does not enter the region R1. For example, the wiring pattern 3A may be formed of an appropriate metal such as silver, aluminum, copper, titanium, palladium, or an alloy thereof. For example, the wiring pattern 3A may be formed by laminating a plurality of metal films. For example, the wiring pattern 3A has a thickness of 1.0 μm to 5.0 μm.

The wiring pattern 3A includes an antenna bump pad ANT, a transmission bump pad Tx, a reception bump pad Rx, and four ground bump pads GND. These bump pads have portions that are electrically connected to the bumps 4 at the time of mounting.

The plurality of elastic wave elements 8 includes a plurality of series resonators S1-Rx, S2-Rx, a plurality of parallel resonators P1-Rx, P2-Rx, and a multimode resonator DMS. The plurality of series resonators S1-Rx, S2-Rx, the plurality of parallel resonators P1-Rx, P2-Rx, and the multimode resonator DMS are electrically connected by the wiring pattern 3A. The plurality of series resonators S1-Rx, S2-Rx are not directly electrically connected to any one of the ground bump pads GND. The plurality of parallel resonators P1-Rx, P2-Rx and the multimode resonator DMS are directly electrically connected to any one of the ground bump pads GND.

The plurality of series resonators S1-Rx, S2-Rx, the plurality of parallel resonators P1-Rx, P2-Rx, and the multimode resonator DMS have a function of a receiving filter. Specifically, once an electric signal is inputted to the bump pad ANT for antenna, the electric signal passes through the plurality of series resonators S1-Rx, S2-Rx, the plurality of parallel resonators P1-Rx, P2-Rx, and the multimode resonator DMS. At this time, only the electric signal of the desired frequency band reaches the receiving bump pad Rx. Therefore, only the electric signal of the desired frequency band is outputted from the receiving bump pad Rx.

The plurality of elastic wave elements 8 further includes a plurality of series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx, and a plurality of parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx. A plurality of the series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx, and a plurality of the parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx are electrically connected by the wiring pattern 3A. The plurality of series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx are not directly electrically connected to any one of the ground bump pads GND. The plurality of parallel resonators P1-Tx, P2-Tx, P3-Tx, and P4-Tx are directly electrically connected to any one of the ground bump pads GND.

The plurality of series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx, and the plurality of parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx have a function of a transmission filter. Specifically, once an electrical signal is input to the transmitting bump pad Tx, the electrical signal passes through the plurality of series resonators S1-Tx, S2-Tx, S3-Tx, S4-Tx, and the plurality of parallel resonators P1-Tx, P2-Tx, P3-Tx, P4-Tx. At this time, only the electric signal of the desired frequency band reaches the bump pad ANT for antenna. Therefore, only an electric signal of a desired frequency band is outputted from the antenna bump pad ANT.

The chip substrate 3 has a plurality of extensions 9 formed thereon. For example, a plurality of the extending portions 9 are formed integrally and simultaneously with the wiring pattern 3A. The extension 9 has a first extension 9A and a second extension 9B.

For example, the first one of the extensions 9 is formed in the area a on the right side of the chip substrate 3. The area a is shown enlarged in fig. 3. In the region a, the first extension 9A extends from the region of the wiring pattern 3A directly electrically connected between the series resonators S1-Tx and S2-Tx toward the right outer edge of the chip substrate 3. For example, the first extension 9A is adjacent to a region of the wiring pattern 3A that is different from a region directly electrically connected between the series resonators S1-Tx, S2-Tx. Specifically, the first extension 9A is adjacent to the ground bump pad GND on the lower right side of the chip substrate 3. The second extension 9B extends from an end of the first extension 9A along a right outer edge of the chip substrate 3. In this case, the second extension 9B extends in a direction away from a region of the wiring pattern 3A different from a region directly electrically connected between the series resonators S1-Tx, S2-Tx. Specifically, the region of the wiring pattern 3A different from the region directly electrically connected between the series resonators S1-Tx and S2-Tx is the ground bump pad GND (i.e., the ground bump pad GND located on the lower right side of the chip substrate 3) near the region of the wiring pattern 3A directly electrically connected between the series resonators S1-Tx and S2-Tx, and the second extension portion 9B extends from the end portion of the first extension portion 9A along the right outer edge portion of the chip substrate 3 in a direction away from the ground bump pad GND (downward direction in fig. 2).

For example, the second extension 9 is formed in the region B on the left side of the chip substrate 3. The region B is shown enlarged in fig. 4. In the region B, the first extension 9A extends from the region of the wiring pattern 3A directly electrically connected between the series resonators S2-Tx (not shown in fig. 4) and S3-Tx toward the left outer edge of the chip substrate 3. The second extension 9B extends up and down along the left outer edge of the chip substrate 3 from the end of the first extension 9A.

For example, the third extension 9 is formed in the region C on the right side of the chip substrate 3. The region C is shown enlarged in fig. 5. In the region C, the first extension portion 9A extends from the region of the wiring pattern 3A directly electrically connected between the series resonators S3-Tx and S4-Tx (both not shown in fig. 5) toward the right outer edge portion of the chip substrate 3. For example, the first extension 9A is adjacent to a region of the wiring pattern 3A different from a region directly electrically connected between the series resonators S3-Tx, S4-Tx. Specifically, the first extension 9A is adjacent to a region of the wiring pattern 3A that is directly electrically connected to the ground bump pad GND (not shown in fig. 5) on the upper right side of the chip substrate 3. The second extension 9B extends from an end of the first extension 9A along a right outer edge of the chip substrate 3. The second extension 9B extends in a direction away from a region of the wiring pattern 3A different from a region directly electrically connected between the series resonators S3-Tx and S4-Tx. Specifically, the second extension portion 9B extends in a direction away from a region of the wiring pattern 3A directly electrically connected to the ground bump pad GND on the upper right side of the chip substrate 3 (downward direction in fig. 2).

For example, the fourth extension 9 is formed in the region D on the left side of the chip substrate 3. The region D is shown enlarged in fig. 6. In the region D, the first extension portion 9A extends from the region of the wiring pattern 3A directly electrically connected between the series resonators S3-Tx, S4-Tx (not shown in fig. 6) toward the left outer edge portion of the chip substrate 3. The second extension 9B extends up and down along the left outer edge of the chip substrate 3 from the end of the first extension 9A.

Of the plurality of the extensions 9, the second extension 9B does not intrude into the region R1. The second extension 9B contacts the sealing portion 5. Specifically, the second extension 9B contacts the region of the sealing portion 5 surrounding the chip substrate 3 and the wiring substrate 2. More specifically, at least a part of the second extension 9B intrudes into the region R2.

Next, a first example of the elastic wave element 8 will be described with reference to fig. 7.

Fig. 7 is a schematic view of a first example of the elastic wave element 8 of the elastic wave device 1 of the first embodiment.

In fig. 7, the elastic wave element 8 is SAW (Surface Acoustic Wave) resonator. As shown in fig. 7, IDT (Interdigital Transducer) a and a pair of reflectors 8B are formed on the main surface of the chip substrate 3. The IDT 8A and the reflector 8B can excite a surface acoustic wave.

For example, the IDT 8A and the reflector 8B are formed of an alloy of aluminum and copper. For example, the IDT 8A and the reflectors 8B are formed of a suitable metal such as titanium, palladium, silver, or an alloy thereof. For example, the IDT 8A and the reflector 8B may be formed of a laminated metal film in which a plurality of metal films are laminated. For example, the thickness of the IDT 8A and the reflectors 8B is 150nm to 400nm.

The IDT 8A has a pair of comb electrodes 8C. The comb electrodes 8C are opposed to each other. The comb-shaped electrodes 8C each have a plurality of electrode fingers 8D and bus bars 8E. A plurality of the electrode fingers 8D extend in the longitudinal direction. The bus bar 8E connects a plurality of the electrode fingers 8D. One of the reflectors 8B abuts one side of the IDT 8A. One of the reflectors 8B abuts the other side of the IDT 8A. For example, the IDT 8A and the reflector 8B, and the wiring pattern 3A (not shown in fig. 3) may be formed and patterned in the same process.

Next, a second example of the elastic wave element 8 will be described with reference to fig. 8.

Fig. 8 is a second example of the elastic wave element 8 of the elastic wave device 1 of the first embodiment.

In the example of fig. 8, the elastic wave element 8 is an acoustic thin film resonator. For example, the chip substrate 3 is a semiconductor substrate such as silicon, or an insulating substrate such as sapphire, alumina, spinel, or glass. The piezoelectric film 8F is provided on the main surface of the chip substrate 3. For example, the piezoelectric film 8F is formed of aluminum nitride. The lower electrode 8G and the upper electrode 8H sandwich the piezoelectric film 8F. For example, the lower electrode 8G and the upper electrode 8H are formed of a metal such as ruthenium. A space 8J is formed between the lower electrode 8G and the chip substrate 3. In the acoustic thin film resonator, the lower electrode 8G and the upper electrode 8H excite elastic waves in the piezoelectric film 8F in a thickness longitudinal vibration mode.

Next, heat dissipation of the chip substrate 3 will be described with reference to fig. 9 to 11.

Fig. 9 is a bottom view of the chip substrate 3 after the wiring substrate 2 is removed from the acoustic wave device 1 of the first embodiment. Fig. 10 is a cross-sectional view of the elastic wave device 1 taken along a section line B-B of fig. 9. Fig. 11 is a cross-sectional view of the elastic wave device 1 taken along the section line C-C of fig. 9. However, fig. 10 and 11 are upside down in order to conform to the orientation of fig. 1. Unnecessary components are appropriately omitted in fig. 10 and 11 for convenience of explanation.

In fig. 9 to 11, the chip substrate 3 is formed of lithium tantalate. The thermal conductivity of lithium tantalate at 25℃was about 4.6W/mK. The wiring pattern 3A is integrally formed with the extension 9 with aluminum. The thermal conductivity of aluminum at 25℃is about 204W/mK. The sealing portion 5 is formed of a high heat conductive resin. The thermal conductivity of the high thermal conductivity resin at 25℃was about 3.0W/mK. In fig. 10 and 11, the conductive pad 2A, the conductive pad 2B, and the inner conductor 2C are formed of copper. The thermal conductivity of copper at 25℃is about 403W/mK. The bump 4 is formed of gold. Gold at 25℃has a thermal conductivity of about 295W/mK. The thermal conductivity of air at 25℃is about 0.025W/mK.

When the elastic wave device 1 is operated, the plurality of elastic wave elements 8 generate heat. The heat around the elastic wave element 8 is conducted to the chip substrate 3, the wiring pattern 3A, and the air. Here, the thermal conductivity of the wiring pattern 3A is higher than the thermal conductivity of the chip substrate 3 and the thermal conductivity of the air. Accordingly, more heat is conducted through the wiring pattern 3A.

In the wiring pattern 3A, more heat is conducted to the wiring substrate 2 via any one of the bump pads and the bump 4 from a region directly electrically connected to the bump pad. In contrast, in the wiring pattern 3A, there is no region directly electrically connected to any one of the bump pads to which a very small amount of heat is conducted via the chip substrate 3 and air. Therefore, in the wiring pattern 3A, there is no region directly electrically connected to any one of the bump pads, and only a small amount of heat is conducted to the wiring substrate 2.

However, in the region of the wiring pattern 3A corresponding to the four extension portions 9, more heat is conducted to any one of the bump pads via the extension portions 9 and the sealing portion 5. For example, from the region a of fig. 9, more heat is conducted to the ground bump pad GND and the transmitting bump pad Tx on the lower right side of the chip substrate 3 through the first extending portion 9 and the sealing portion 5. For example, from the region B of fig. 9, more heat is conducted to the ground bump pad GND on the lower left side of the chip substrate 3 through the second extending portion 9 and the sealing portion 5. For example, from the region C of fig. 9, more heat is conducted through the ground bump pad GND on the lower right side of the chip substrate 3 and the ground bump pad GND on the upper side. For example, from the region D of fig. 9, more heat is conducted to the antenna bump pad ANT on the left side of the chip substrate 3 through the fourth extension portion 9 and the sealing portion 5. The bump pads dissipate heat to the wiring substrate 2 via the bumps 4. The heat is radiated to the outside of the elastic wave device 1.

For example, in fig. 10, the heat from the second extension 9B of the region a is dissipated to the outside of the acoustic wave device 1 by the transmitting bump pad Tx, the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B. For example, in fig. 10, the heat from the second extension 9B of the region a is dissipated to the outside of the elastic wave device 1 by the ground bump pad GND, the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B on the right side. For example, in fig. 10, the heat from the second extension 9B of the region C is dissipated to the outside of the elastic wave device 1 by the ground bump pad GND, the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B on the right side. For example, in fig. 10, heat from the second extension 9B of the region C is dissipated to the outside of the elastic wave device 1 by the ground bump pad GND, the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B on the left side.

For example, the left bump pad GND for grounding in fig. 11 radiates heat from the second extension 9B of the region B to the outside of the acoustic wave device 1 via the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B. For example, the bump pad ANT for an antenna of fig. 11 radiates heat from the second extension 9B of the region D to the outside of the elastic wave device 1 via the bump 4, the conductive pad 2A, the internal conductor 2C, and the conductive pad 2B.

According to the first embodiment, the first extension portion 9A extends from the region of the wiring pattern 3A directly electrically connected between the series resonators toward the outer edge portion of the chip substrate 3. The second extension 9B extends from the first extension 9A along the outer edge of the chip substrate 3. Therefore, more heat is dissipated from the region directly electrically connected between the series resonators through the first extension 9A and the second extension 9B in the wiring pattern 3A than in the case where the extension 9 is not provided. Therefore, the heat dissipation of the chip substrate 3 can be improved.

The extension 9 has a higher thermal conductivity than the thermal conductivity of the chip substrate 3. Therefore, the heat dissipation of the chip substrate 3 can be improved with certainty by the extension 9.

The extension 9 is formed integrally with the wiring pattern 3A. Therefore, the heat dissipation of the chip substrate 3 can be improved without a separate process of forming the extension 9.

In the region a and the region C, the first extension 9A is adjacent to a region different from a region directly electrically connected between the series resonators in the wiring pattern 3A. The second extension 9B extends in a direction away from a region of the wiring pattern 3A different from a region directly electrically connected between the series resonators. Therefore, the heat dissipation of the chip substrate 3 can be improved while maintaining the miniaturization of the acoustic wave device 1.

The second extension 9B is away from the outer edge of the chip substrate 3. Therefore, the second extension 9B can be prevented from contacting a dicing blade when the chip substrate 3 is cut out from the wafer.

Further, the second extension 9B contacts the sealing portion 5 around the region between the chip substrate 3 and the wiring substrate 2. Accordingly, a large amount of heat in the wiring pattern 3A is dissipated from the region directly electrically connected between the series resonators through the second extension 9B and the sealing portion 5.

The second extension 9B is formed in a region 60 μm away from the outer edge of the chip substrate 3. Therefore, the second extension 9B can be surely brought into contact with the sealing portion 5.

The extension 9 functions as a part of a transmission filter, and is formed in a region corresponding to a region directly electrically connected between the series resonators. Therefore, heat dissipation of heat generated by the series resonator can be improved particularly in a transmission filter with a large heat dissipation.

(Second embodiment)

Fig. 12 is a view similar to fig. 2 of the second embodiment. Fig. 13 is an enlarged view of the area a in fig. 12. Fig. 14 is an enlarged view of area B in fig. 12. Fig. 15 is an enlarged view of the area C in fig. 12. Fig. 16 is an enlarged view of the area D in fig. 12. It should be understood that similar or identical parts to those of the first embodiment are provided with the same reference numerals. The description of the similar or identical parts will be omitted.

In the extension 9 of fig. 12 to 16, the first extension 9A is integrally formed simultaneously with the wiring pattern 3A. The second extension 9B is directly connected to the first extension 9A. The second extension 9B is formed of a high thermal conductivity insulator. For example, the second extension 9B is formed of epoxy resin, polyimide resin, silicon, solder resist, boron nitride, aluminum nitride, lead oxide, zinc oxide, or silicon oxide.

According to the second embodiment, the second extension 9B is formed of a high thermal conductive insulator. Therefore, as in the first embodiment, the heat dissipation of the chip substrate 3 can be improved. In particular boron nitride, aluminum nitride and aluminum oxide have high thermal conductivity. Specifically, the thermal conductivity of boron nitride is about 60W/mK. The thermal conductivity of aluminum nitride is about 150W/mK. The thermal conductivity of the alumina was about 29W/mK. Therefore, the second extension 9B is formed using any one of boron nitride, aluminum nitride and aluminum oxide, so that the heat dissipation of the chip substrate 3 can be improved.

(Third embodiment)

Fig. 17 is a view similar to fig. 2 of the third embodiment. Fig. 18 is an enlarged view of a region B in fig. 17. Fig. 19 is an enlarged view of region C in fig. 17. Fig. 20 is an enlarged view of the vicinity of the region B and the region D in fig. 17. It should be understood that similar or identical parts to those of the second embodiment are provided with the same reference numerals. The description of the similar or identical parts will be omitted.

As shown in fig. 17 and 18, in the extension 9 of the region B, the second extension 9B is formed of a high thermal conductive insulator. The second extension 9B is directly connected to a region of the wiring pattern 3A directly connected to a ground bump pad GND (not shown in fig. 18) on the lower left side of the chip substrate 3. As shown in fig. 17 and 19, in the extension 9 of the region C, the second extension 9B is formed of a high thermal conductive insulator. The second extension 9B is directly connected to a region of the wiring pattern 3A directly connected to the ground bump pad GND (not shown in fig. 19) on the upper right side of the chip substrate 3.

As shown in fig. 17 and 20, the extension 9 of the region B is connected to the second extension 9B of the extension 9 of the region D. For example, the extension 9 of the region B is integrally formed with the extension 9 of the region D.

According to the third embodiment, the second extension 9B connects the region of the wiring pattern 3A directly connected to the bump pad GND for grounding. Accordingly, the heat energy generated from the second extension 9B is efficiently conducted to the ground bump pad GND. Therefore, the heat dissipation of the chip substrate 3 can be improved surely.

(Fourth embodiment)

Fig. 21 is a view similar to fig. 2 of the fourth embodiment. Fig. 22 is an enlarged view of the vicinity of the auxiliary extension 10 in fig. 21. It should be understood that similar or identical parts to those of the third embodiment are provided with the same reference numerals. The description of the similar or identical parts will be omitted.

In fig. 21 and 22, the auxiliary extension 10 is formed of the same high thermal conductivity insulator as the second extension 9B. For example, the auxiliary extension 10 extends from the right side of the region directly electrically connected between the series resonators S2-Tx and S3-Tx (not shown in fig. 22) in the wiring pattern 3A toward the right outer edge of the chip substrate 3. The auxiliary extension 10 is connected to a region of the wiring pattern 3A closer to the right outer edge portion side of the chip substrate 3 (not shown in fig. 22) than a region directly electrically connected between the series resonators S2-Tx, S3-Tx. The region is a region directly connected to the ground bump pad GND (not shown in fig. 22) on the lower right side of the chip substrate 3.

According to the fourth embodiment, the auxiliary extension 10 extends from the region of the wiring pattern 3A directly electrically connected between the series resonators to the outside of the chip substrate 3. The auxiliary extension 10 connects a region of the wiring pattern 3A directly connected to the ground bump pad GND. Therefore, for example, even if the heat dissipation generated in the region directly electrically connected between the series resonators S2-Tx and S3-Tx in the wiring pattern 3A is insufficient, it can be effectively dissipated via the auxiliary extension 10.

(Fifth embodiment)

Fig. 23 is a cross-sectional view of a module 100 to which the elastic wave device 1 of the fifth embodiment is applied. It should be understood that similar or identical parts to those of the first embodiment are provided with the same reference numerals. The description of the similar or identical parts will be omitted.

In fig. 23, the module 100 includes a wiring board 101, an integrated circuit element 102, the elastic wave device 1, an inductor 103, and a sealing portion 104.

The wiring substrate 101 is the same as the wiring substrate 2 in the first embodiment. The integrated circuit element 102 is mounted inside the wiring substrate 101. The integrated circuit element 102 includes a switching circuit and a low noise amplifier. The acoustic wave device 1 is mounted on a main surface of the wiring board 101. The inductor 103 is mounted on a main surface of the wiring board 101. The inductor 103 is mounted for impedance matching. For example, the inductor 103 is an integrated passive device (INTEGRATED PASSIVE DEVICE, IPD). The sealing portion 104 seals a plurality of electronic components including the elastic wave device 1.

According to the fifth embodiment, the module 100 comprises the elastic wave device 1. Therefore, the module 100 including the elastic wave device 1 having high heat dissipation can be realized.

While at least one embodiment has been described above, it is to be appreciated various alterations, modifications, or improvements will readily occur to those skilled in the art. Such alterations, modifications, or improvements are intended to be part of this disclosure, and are intended to be within the scope of this disclosure.

It is to be understood that the aspects of the method or apparatus described herein are not limited in their implementation to the constructions and arrangements of parts described in the foregoing description or illustrated in the drawings. The methods and apparatus may be practiced or carried out in other embodiments.

The examples are given for illustration only and are not intended to be limiting.

The descriptions or words used in the present disclosure are words of description rather than limitation. The use of "including," "comprising," "having," "containing," and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

The use of the word "or any use of the word" or "described may be interpreted as one, more than one, or all of the described words.

References to front, back, left, right, top, bottom, upper, lower, horizontal, vertical, and front and back are for convenience of description and do not limit the position and spatial arrangement of any one of the constituent elements of the present invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. An elastic wave device, comprising:

A chip substrate;

wiring patterns formed on the chip substrate;

2. The elastic wave device according to claim 1, wherein: the first extension portion and the second extension portion have a higher thermal conductivity than that of the chip substrate.

3. The elastic wave device according to claim 1, wherein: the first extension portion and the second extension portion are integrally formed with the wiring pattern.

4. An elastic wave device according to claim 3, wherein: the first extension portion is adjacent to a region of the wiring pattern different from a region directly electrically connected between the series resonators, and the second extension portion extends in a direction away from a region of the wiring pattern different from a region directly electrically connected between the series resonators.

5. The elastic wave device according to claim 1, wherein: the second extension is formed of a high thermal conductivity insulator.

6. The elastic wave device according to claim 5, wherein: the second extension portion is connected to a region of the wiring pattern where the bump pad for grounding is not directly connected.

7. The elastic wave device according to claim 1, wherein: the second extension is spaced apart from the chip substrate.

8. The elastic wave device according to claim 1, wherein: the second extension portion is located in a region that is 60 μm closer to the center side of the chip substrate from the outer edge portion of the chip substrate.

9. The elastic wave device according to claim 1, wherein: the elastic wave device further includes an auxiliary extension portion formed of a high thermal conductive insulator and extending from a region directly electrically connected between the series resonators in the wiring pattern toward an outer edge portion of the chip substrate, the auxiliary extension portion being formed on a side of the wiring pattern closer to the outer edge portion of the chip substrate than the region directly electrically connected between the series resonators and being directly connected to a region directly connected to a bump pad for grounding of the wiring pattern.

10. The elastic wave device according to claim 1, wherein: the elastic wave device further includes a wiring substrate facing the chip substrate, and a sealing portion hermetically sealing the wiring substrate and the chip substrate, and the second extension portion is connected to the sealing portion.

11. The elastic wave device according to claim 10, wherein: the sealing part surrounds the space between the chip substrate and the wiring substrate from the outer edge part of the chip substrate, and the second extending part is connected with the sealing part and surrounds the space between the chip substrate and the wiring substrate.

12. An elastic wave device, comprising:

A chip substrate;

wiring patterns formed on the chip substrate;

13. A module comprising the elastic wave device of any one of claims 1 to 12.