JP2024019121A5 - - Google Patents

Info

Publication number
JP2024019121A5
JP2024019121A5 JP2023122543A JP2023122543A JP2024019121A5 JP 2024019121 A5 JP2024019121 A5 JP 2024019121A5 JP 2023122543 A JP2023122543 A JP 2023122543A JP 2023122543 A JP2023122543 A JP 2023122543A JP 2024019121 A5 JP2024019121 A5 JP 2024019121A5
Authority
JP
Japan
Prior art keywords
retimer
value
values
sample rate
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023122543A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024019121A (ja
Filing date
Publication date
Priority claimed from US17/876,194 external-priority patent/US11888963B1/en
Application filed filed Critical
Publication of JP2024019121A publication Critical patent/JP2024019121A/ja
Publication of JP2024019121A5 publication Critical patent/JP2024019121A5/ja
Pending legal-status Critical Current

Links

JP2023122543A 2022-07-28 2023-07-27 レート適合を用いたフレーム同期検出 Pending JP2024019121A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/876,194 2022-07-28
US17/876,194 US11888963B1 (en) 2022-07-28 2022-07-28 Frame synch detection with rate adaptation

Publications (2)

Publication Number Publication Date
JP2024019121A JP2024019121A (ja) 2024-02-08
JP2024019121A5 true JP2024019121A5 (https=) 2026-01-13

Family

ID=89575470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023122543A Pending JP2024019121A (ja) 2022-07-28 2023-07-27 レート適合を用いたフレーム同期検出

Country Status (3)

Country Link
US (2) US11888963B1 (https=)
JP (1) JP2024019121A (https=)
DE (1) DE102023119563A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11888963B1 (en) * 2022-07-28 2024-01-30 Cypress Semiconductor Corporation Frame synch detection with rate adaptation
US20250006216A1 (en) * 2023-06-27 2025-01-02 Qorvo Us, Inc. Systems and methods for low-power fully digital rate conversion using pre- or post- jitter noise reduction

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7583771B2 (en) * 2006-08-22 2009-09-01 Schweitzer Engineering Laboratories, Inc. Systems and methods for resampling unreliable data
US7929927B2 (en) 2007-10-29 2011-04-19 Freescale Semiconductor, Inc. Adaptive pre-distortion with interference detection and mitigation
JP5563469B2 (ja) * 2007-11-16 2014-07-30 テラダイン・インコーポレーテッド サンプルレート変換システムにおける補間係数を計算するための方法及び装置
US8831070B2 (en) * 2010-06-24 2014-09-09 Stichting Imec Nederland Method and apparatus for start of frame delimiter detection
US9977131B2 (en) * 2013-10-14 2018-05-22 etherwhere Corporation Fast fix using perfect reference in a satellite-based positioning system
US9729364B1 (en) 2016-06-28 2017-08-08 Nxp Usa, Inc. Frequency shift keying (FSK) demodulator and method therefor
US9794056B1 (en) 2016-10-03 2017-10-17 Nxp Usa, Inc. Tone rejection during synchronization in frequency shift keyed modulation systems
EP3370365B1 (en) * 2017-03-02 2020-07-01 Nxp B.V. Processing module and associated method
US10764097B1 (en) 2019-03-05 2020-09-01 Nxp Usa, Inc. Frequency shift keying (FSK) error detector and method therefor
US10819544B2 (en) 2019-03-29 2020-10-27 Nxp Usa, Inc. Symbol demodulator with error reduction
US10530905B1 (en) 2019-04-08 2020-01-07 Nxp Usa, Inc. Frame delimiter detection
US10880138B2 (en) 2019-04-24 2020-12-29 Nxp Usa, Inc. Acquisition of a data packet having a short preamble
US10804957B1 (en) 2019-05-09 2020-10-13 Nxp Usa, Inc. Preamble detection during acquisition
US10862729B1 (en) 2019-10-08 2020-12-08 Nxp Usa, Inc. Systems and methods for digital correction with selective enabling in low intermediate frequency (IF) receivers
US10862728B1 (en) 2019-10-08 2020-12-08 Nxp Usa, Inc. Systems and methods for digital correction in low intermediate frequency (IF) receivers
US10862505B1 (en) 2020-02-27 2020-12-08 Nxp Usa, Inc. Arbitrary rate decimator and timing error corrector for an FSK receiver
EP3968049A1 (en) 2020-09-11 2022-03-16 NXP USA, Inc. Methods and apparatus for estimating a time-of-arrival or a distance between two devices
EP4064568B1 (en) 2021-03-23 2025-05-07 Nxp B.V. Type-i plls for phase-controlled applications
EP4064569A1 (en) 2021-03-23 2022-09-28 Nxp B.V. Type-i plls for phase-controlled applications
US11888963B1 (en) * 2022-07-28 2024-01-30 Cypress Semiconductor Corporation Frame synch detection with rate adaptation

Similar Documents

Publication Publication Date Title
JP2024019121A5 (https=)
JPH09247569A5 (https=)
US20150312078A1 (en) Clock and Data Recovery Techniques
JPH06261031A (ja) Tdmaシステムにおける記号とフレームの同期装置およびその方法
US12592815B2 (en) Frame synch detection with rate adaptation
JP2002290485A (ja) 周波数誤差推定を行う受信機および周波数誤差の推定方法
CN110784213B (zh) 失锁检测器
EP3160077B1 (en) Clock recovery apparatus and clock recovery method
US6990615B2 (en) Data processing device
JP2019192989A (ja) 同期システム、タイムクライアントおよびプログラム
KR100556397B1 (ko) 타이밍 복구 장치 및 방법
JP3792904B2 (ja) 受信装置、及び通信装置
KR100493026B1 (ko) 전화선 모뎀을 위한 강건한 심벌 타이밍 복구 회로
JPH08317007A (ja) データ受信装置
JP4214089B2 (ja) 時間変調を用いたパケットネットワークにおける時間の測定とアラインメントの分解能を改善する方法
WO2006121378A1 (en) Synchronization of vodsl for dslam connected only to ethernet
JP3318179B2 (ja) データ受信装置
US8666006B1 (en) Systems and methods for high speed data recovery with free running sampling clock
JP3886392B2 (ja) クロック再生回路
JP5000635B2 (ja) 多ピン非同期シリアル・インタフェース全体に転送されるデータをビット同期する方法および装置
KR100479479B1 (ko) 수신기의 심볼 타이밍 복원 장치
KR100364542B1 (ko) 심볼 동기화 장치
JP3931969B2 (ja) 同期検出方法とその回路、無線基地局
JP2000068974A (ja) Ofdm受信装置
JPH07336343A (ja) 信号検出装置およびそれを用いたクロック再生装置