JP2024019121A - レート適合を用いたフレーム同期検出 - Google Patents

レート適合を用いたフレーム同期検出 Download PDF

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Publication number
JP2024019121A
JP2024019121A JP2023122543A JP2023122543A JP2024019121A JP 2024019121 A JP2024019121 A JP 2024019121A JP 2023122543 A JP2023122543 A JP 2023122543A JP 2023122543 A JP2023122543 A JP 2023122543A JP 2024019121 A JP2024019121 A JP 2024019121A
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JP
Japan
Prior art keywords
retimer
value
sample rate
data
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2023122543A
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English (en)
Japanese (ja)
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JP2024019121A5 (https=
Inventor
レイ クラウディオ
Rey Claudio
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Cypress Semiconductor Corp
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Cypress Semiconductor Corp
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Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of JP2024019121A publication Critical patent/JP2024019121A/ja
Publication of JP2024019121A5 publication Critical patent/JP2024019121A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2023122543A 2022-07-28 2023-07-27 レート適合を用いたフレーム同期検出 Pending JP2024019121A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/876,194 2022-07-28
US17/876,194 US11888963B1 (en) 2022-07-28 2022-07-28 Frame synch detection with rate adaptation

Publications (2)

Publication Number Publication Date
JP2024019121A true JP2024019121A (ja) 2024-02-08
JP2024019121A5 JP2024019121A5 (https=) 2026-01-13

Family

ID=89575470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023122543A Pending JP2024019121A (ja) 2022-07-28 2023-07-27 レート適合を用いたフレーム同期検出

Country Status (3)

Country Link
US (2) US11888963B1 (https=)
JP (1) JP2024019121A (https=)
DE (1) DE102023119563A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11888963B1 (en) * 2022-07-28 2024-01-30 Cypress Semiconductor Corporation Frame synch detection with rate adaptation
US20250006216A1 (en) * 2023-06-27 2025-01-02 Qorvo Us, Inc. Systems and methods for low-power fully digital rate conversion using pre- or post- jitter noise reduction

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7583771B2 (en) * 2006-08-22 2009-09-01 Schweitzer Engineering Laboratories, Inc. Systems and methods for resampling unreliable data
US7929927B2 (en) 2007-10-29 2011-04-19 Freescale Semiconductor, Inc. Adaptive pre-distortion with interference detection and mitigation
JP5563469B2 (ja) * 2007-11-16 2014-07-30 テラダイン・インコーポレーテッド サンプルレート変換システムにおける補間係数を計算するための方法及び装置
US8831070B2 (en) * 2010-06-24 2014-09-09 Stichting Imec Nederland Method and apparatus for start of frame delimiter detection
US9977131B2 (en) * 2013-10-14 2018-05-22 etherwhere Corporation Fast fix using perfect reference in a satellite-based positioning system
US9729364B1 (en) 2016-06-28 2017-08-08 Nxp Usa, Inc. Frequency shift keying (FSK) demodulator and method therefor
US9794056B1 (en) 2016-10-03 2017-10-17 Nxp Usa, Inc. Tone rejection during synchronization in frequency shift keyed modulation systems
EP3370365B1 (en) * 2017-03-02 2020-07-01 Nxp B.V. Processing module and associated method
US10764097B1 (en) 2019-03-05 2020-09-01 Nxp Usa, Inc. Frequency shift keying (FSK) error detector and method therefor
US10819544B2 (en) 2019-03-29 2020-10-27 Nxp Usa, Inc. Symbol demodulator with error reduction
US10530905B1 (en) 2019-04-08 2020-01-07 Nxp Usa, Inc. Frame delimiter detection
US10880138B2 (en) 2019-04-24 2020-12-29 Nxp Usa, Inc. Acquisition of a data packet having a short preamble
US10804957B1 (en) 2019-05-09 2020-10-13 Nxp Usa, Inc. Preamble detection during acquisition
US10862729B1 (en) 2019-10-08 2020-12-08 Nxp Usa, Inc. Systems and methods for digital correction with selective enabling in low intermediate frequency (IF) receivers
US10862728B1 (en) 2019-10-08 2020-12-08 Nxp Usa, Inc. Systems and methods for digital correction in low intermediate frequency (IF) receivers
US10862505B1 (en) 2020-02-27 2020-12-08 Nxp Usa, Inc. Arbitrary rate decimator and timing error corrector for an FSK receiver
EP3968049A1 (en) 2020-09-11 2022-03-16 NXP USA, Inc. Methods and apparatus for estimating a time-of-arrival or a distance between two devices
EP4064568B1 (en) 2021-03-23 2025-05-07 Nxp B.V. Type-i plls for phase-controlled applications
EP4064569A1 (en) 2021-03-23 2022-09-28 Nxp B.V. Type-i plls for phase-controlled applications
US11888963B1 (en) * 2022-07-28 2024-01-30 Cypress Semiconductor Corporation Frame synch detection with rate adaptation

Also Published As

Publication number Publication date
US20240039690A1 (en) 2024-02-01
US11888963B1 (en) 2024-01-30
US12592815B2 (en) 2026-03-31
DE102023119563A1 (de) 2024-02-08
US20240204983A1 (en) 2024-06-20

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