JP2024012029A - Copper foil for flexible printed substrate, and copper-clad laminate, flexible printed substrate and electronic device that employ the same - Google Patents

Copper foil for flexible printed substrate, and copper-clad laminate, flexible printed substrate and electronic device that employ the same Download PDF

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JP2024012029A
JP2024012029A JP2022168095A JP2022168095A JP2024012029A JP 2024012029 A JP2024012029 A JP 2024012029A JP 2022168095 A JP2022168095 A JP 2022168095A JP 2022168095 A JP2022168095 A JP 2022168095A JP 2024012029 A JP2024012029 A JP 2024012029A
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copper foil
flexible printed
copper
circuit
printed circuit
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慎介 坂東
Shinsuke Bando
裕士 石野
Yuji Ishino
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JX Nippon Mining and Metals Corp
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    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C9/00Alloys based on copper
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22FCHANGING THE PHYSICAL STRUCTURE OF NON-FERROUS METALS AND NON-FERROUS ALLOYS
    • C22F1/00Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22FCHANGING THE PHYSICAL STRUCTURE OF NON-FERROUS METALS AND NON-FERROUS ALLOYS
    • C22F1/00Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working
    • C22F1/08Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working of copper or alloys based thereon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate

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  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
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  • Parts Printed On Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

To provide: copper foil for a flexible printed substrate, which has good linear circuit properties and is suitable for a minute circuit; and a copper-clad laminate, a flexible printed substrate, and an electronic device that employ the same.SOLUTION: The copper foil for a flexible printed substrate is rolled copper foil containing at least 99.96 mass% of Cu, with the remainder being unavoidable impurities. When 300°C heat treatment is carried out for 30 minutes and a measurement field of view of 150 μm×150 μm of the rolling surface of the rolled copper foil is subjected to EBSD measurement, the average crystal diameter when a misorientation of 5° or more is regarded as a crystal boundary is 5.0 μm or less.SELECTED DRAWING: Figure 1

Description

本発明はフレキシブルプリント基板等の配線部材に用いて好適な銅箔、それを用いた銅張積層体、フレキシブル配線板、及び電子機器に関する。 The present invention relates to a copper foil suitable for use in wiring members such as flexible printed circuit boards, a copper-clad laminate using the same, a flexible wiring board, and an electronic device.

電子機器の回路基板として、フレキシブルプリント基板(フレキシブル配線板、以下、「FPC」と称する)が広く用いられている。FPCは銅箔と樹脂とを積層したCopper Clad Laminate(銅張積層体、以下CCLと称する)をエッチングすることで配線を形成し、その上をカバーレイと呼ばれる樹脂層によって被覆したものである。CCLに貼り合せる樹脂はポリイミド系、液晶ポリマー、PTFEが挙げられるがこれらに限定されない。 2. Description of the Related Art Flexible printed circuit boards (flexible printed circuit boards, hereinafter referred to as "FPC") are widely used as circuit boards for electronic devices. In FPC, wiring is formed by etching a copper clad laminate (hereinafter referred to as CCL), which is a layered layer of copper foil and resin, and the wiring is covered with a resin layer called a coverlay. Examples of the resin to be bonded to the CCL include, but are not limited to, polyimide, liquid crystal polymer, and PTFE.

そして、このように銅張積層体は、目的とする回路を形成するためにレジスト塗布及び露光工程により回路を印刷し、さらに銅層の不要部分を除去するエッチング処理を経るが、エッチングして回路を形成する際に、その回路が予め表面に形成されたマスクパターン通りの幅にならないという問題がある。
これは、エッチングすることにより形成される銅回路が、銅層の表面から下に向かって、すなわち樹脂層に向かって、末広がりにエッチングされる(ダレを発生する)ことによる。
そこで、この「ダレ」を減少させる技術が開発されている(特許文献1)。
In order to form the desired circuit, the copper-clad laminate is printed with a resist coating and exposure process, and then undergoes an etching process to remove unnecessary parts of the copper layer. When forming a circuit, there is a problem in that the width of the circuit does not match the mask pattern previously formed on the surface.
This is because the copper circuit formed by etching is etched downward from the surface of the copper layer, that is, toward the resin layer, so that it spreads out (sagging occurs).
Therefore, a technique for reducing this "sagging" has been developed (Patent Document 1).

特開2011-216528号公報JP2011-216528A

ところで、電子機器の小型、薄型、高性能化にともない、FPCの高密度実装が要求されている。FPCを高密度に実装するためには回路の微細化が必要であるが、微細回路ではインピーダンスの整合性を保つために回路幅が回路全体にわたって一定であることが重要となってくる。回路の幅が回路全体にわたって一定でない場合、回路が隣の回路にくっついて(接触して)しまい、不良となるおそれがあるからである。
そして、上述のように、回路幅は樹脂層側(ボトム側)で広がる傾向にあるため、ボトム側が隣の回路により接触し易く、ボトム側の回路幅(ボトム幅)を回路全体にわたって一定に保つことがより重要になってくる。特にボトム幅が35μm以下のような微細回路の場合このような不良がより起きやすい。
しかしながら、上述の特許文献1に記載されたように、回路のトップ幅とボトム幅の差(ダレ)を減少させる技術は開示されているものの、ボトム幅に着目した技術は見られなかった。
Incidentally, as electronic devices become smaller, thinner, and more sophisticated, there is a demand for high-density packaging of FPCs. In order to implement FPCs at high density, it is necessary to miniaturize circuits, and in order to maintain impedance matching in microcircuits, it is important that the circuit width be constant throughout the circuit. This is because if the width of the circuit is not constant over the entire circuit, there is a risk that the circuit will stick to (contact) an adjacent circuit, resulting in a defect.
As mentioned above, the circuit width tends to widen on the resin layer side (bottom side), so the bottom side comes into contact with the adjacent circuit more easily, and the circuit width on the bottom side (bottom width) is kept constant throughout the circuit. things become more important. Particularly in the case of a fine circuit with a bottom width of 35 μm or less, such defects are more likely to occur.
However, as described in Patent Document 1 mentioned above, although a technique for reducing the difference (sag) between the top width and bottom width of a circuit has been disclosed, no technique has been found that focuses on the bottom width.

本発明は上記の課題を解決するためになされたものであり、回路直線性が良く、微細回路に適したフレキシブルプリント基板用銅箔、それを用いた銅張積層体、フレキシブルプリント基板、及び電子機器の提供を目的とする。 The present invention was made to solve the above problems, and provides a copper foil for flexible printed circuit boards that has good circuit linearity and is suitable for fine circuits, a copper-clad laminate using the same, a flexible printed circuit board, and an electronic copper foil. The purpose is to provide equipment.

本発明者らは種々検討した結果、銅箔をエッチングして形成した回路の直線性を向上させるには、銅箔の金属組織が均一に近い、換言すれば結晶粒の大きさが揃っている(平均結晶粒径が小さい)ことが重要であることを見出した。これは、平均結晶粒径が小さいと、エッチングによる回路形成時の化学反応(エッチング反応)が均一に生じるためと考えられる。 As a result of various studies, the inventors of the present invention found that in order to improve the linearity of circuits formed by etching copper foil, the metal structure of the copper foil should be nearly uniform, in other words, the crystal grain sizes should be uniform. It has been found that (the average crystal grain size is small) is important. This is thought to be because when the average crystal grain size is small, the chemical reaction (etching reaction) during circuit formation by etching occurs uniformly.

すなわち、本発明のフレキシブルプリント基板用銅箔は、99.96質量%以上のCuを含有し、残部不可避的不純物からなる圧延銅箔であって、300℃×30分の熱処理を行ったとき、前記圧延銅箔の圧延面の測定視野150μm×150μmをEBSD測定し、方位差5°以上を結晶粒界とみなしたときの平均結晶粒径が5.0μm以下である。 That is, the copper foil for flexible printed circuit boards of the present invention is a rolled copper foil containing 99.96% by mass or more of Cu, with the remainder consisting of unavoidable impurities, and when heat treated at 300°C for 30 minutes, An EBSD measurement is performed on a measuring field of 150 μm x 150 μm on the rolled surface of the rolled copper foil, and the average crystal grain size is 5.0 μm or less when misorientation of 5° or more is regarded as a grain boundary.

本発明のフレキシブルプリント基板用銅箔は、前記EBSD測定した前記結晶粒径の標準偏差が3.0μm以下であることが好ましい。
本発明のフレキシブルプリント基板用銅箔は、JIS-H3100(C1100)に規格するタフピッチ銅又はJIS-H3100(C1020)の無酸素銅からなることが好ましい。
本発明のフレキシブルプリント基板用銅箔は、10~50質量ppmのPを含有することが好ましい。
In the copper foil for a flexible printed circuit board of the present invention, it is preferable that the standard deviation of the crystal grain size measured by the EBSD is 3.0 μm or less.
The copper foil for a flexible printed circuit board of the present invention is preferably made of tough pitch copper compliant with JIS-H3100 (C1100) or oxygen-free copper compliant with JIS-H3100 (C1020).
The copper foil for flexible printed circuit boards of the present invention preferably contains 10 to 50 mass ppm of P.

本発明の銅張積層体は、前記フレキシブルプリント基板用銅箔と、樹脂層とを積層してなる。
本発明のフレキシブルプリント基板は、前記銅張積層体における前記銅箔に回路を形成してなる。
本発明の電子機器は、前記フレキシブルプリント基板を用いてなる。
The copper-clad laminate of the present invention is formed by laminating the copper foil for a flexible printed circuit board and a resin layer.
The flexible printed circuit board of the present invention is formed by forming a circuit on the copper foil of the copper clad laminate.
An electronic device of the present invention uses the flexible printed circuit board.

本発明によれば、回路直線性が良く、微細回路に適したフレキシブルプリント基板用銅箔が得られる。 According to the present invention, a copper foil for flexible printed circuit boards with good circuit linearity and suitable for fine circuits can be obtained.

エッチングして形成した回路のボトム幅wを示す図である。FIG. 3 is a diagram showing the bottom width w of a circuit formed by etching. 回路のボトム幅wを複数測定する方法を示す平面図である。FIG. 3 is a plan view showing a method of measuring a plurality of bottom widths w of a circuit. 回路直線性を評価する際の直線回路をエッチング形成するための露光マスクを示す図である。FIG. 3 is a diagram showing an exposure mask for etching a linear circuit when evaluating circuit linearity. 直線回路において、エッチングが進行する状態を示す模式図である。FIG. 3 is a schematic diagram showing a state in which etching progresses in a linear circuit. 金属組織が均一でない(結晶粒の大きさが揃っていない)場合に、回路直線性が低下するメカニズムを示す模式図である。FIG. 2 is a schematic diagram illustrating a mechanism in which circuit linearity decreases when the metal structure is not uniform (crystal grain sizes are not uniform).

以下、本発明に係る銅箔の実施の形態について説明する。なお、本発明において%は特に断らない限り、質量%を示すものとする。 Embodiments of the copper foil according to the present invention will be described below. In the present invention, % indicates mass % unless otherwise specified.

<組成>
本発明に係る銅箔は、99.96質量%以上のCuを含有し、残部不可避的不純物からなる。添加元素として10~50質量ppmのPを含有すると好ましい。ここで、Cuが99.96質量%以上となる範囲であれば、銅箔の機械的特性を改善する目的で、銅箔にAg、Sn、Zr等を微量に含有させてもよい。
添加元素としてPを含有すると、金属組織(結晶粒径)が均一になりやすく、さらにエッチング後の回路のボトム幅が一定になる傾向にある。但し、Pの含有量が50質量ppm (0.005質量%)を超えると、導電率が低下し、フレキシブルプリント基板に適さない。
<Composition>
The copper foil according to the present invention contains 99.96% by mass or more of Cu, and the remainder consists of inevitable impurities. It is preferable to contain 10 to 50 mass ppm of P as an additional element. Here, as long as Cu is in a range of 99.96% by mass or more, the copper foil may contain a trace amount of Ag, Sn, Zr, etc. for the purpose of improving the mechanical properties of the copper foil.
When P is contained as an additive element, the metal structure (crystal grain size) tends to become uniform, and the bottom width of the circuit after etching tends to become constant. However, if the content of P exceeds 50 mass ppm (0.005 mass %), the electrical conductivity will decrease, making it unsuitable for flexible printed circuit boards.

本発明に係る銅箔を、JIS-H3100(C1100)に規格するタフピッチ銅又はJIS-H3100(C1020)の無酸素銅の組成、又はAg、Sn、Zr等を微量に含有する無酸素銅若しくはタフピッチ銅としてもよく、さらにこれらの組成に、添加元素として10~50質量ppmのPを含有してもよい。 The copper foil according to the present invention has a composition of tough pitch copper compliant with JIS-H3100 (C1100) or oxygen-free copper of JIS-H3100 (C1020), or oxygen-free copper or tough pitch containing trace amounts of Ag, Sn, Zr, etc. Copper may be used, and 10 to 50 mass ppm of P may be added to these compositions as an additional element.

P濃度の分析は、JIS H 1058(銅及び銅合金中のりん定量方法)に規定されるモリブドりん酸抽出モリブドりん酸青吸光光度法(P濃度:0.0005%~0.01%に適用)を用いて実施する。 The P concentration was analyzed using molybdophosphoric acid extraction molybdophosphate blue absorption spectrophotometry (applicable to P concentration: 0.0005% to 0.01%) specified in JIS H 1058 (method for determining phosphorus in copper and copper alloys). ).

<平均結晶粒径>
圧延銅箔に300℃×30分の熱処理を行ったとき、熱処理後の圧延面の測定視野150μm×150μmをEBSD測定し、方位差5°以上を結晶粒界とみなしたときの平均結晶粒径が5.0μm以下である。
平均結晶粒径は、EBSD(ElectronBack Scatter Diffraction:電子後方散乱回折)測定における結晶方位解析により算出する。
実際の測定は、試料表面を電解研磨後にSEM-EBSD(日本電子株式会社JSM-IT500HR、TSL EDAX SCAN GENERATOR-II、TSL OIM DATA COLECTION7)で下記の条件で観察する。
なお、EBSD測定は、熱処理後の銅箔から切り出したサンプル板(150mm×150mm)に対して行えばよい。
<Average grain size>
When a rolled copper foil is heat treated at 300°C for 30 minutes, the average crystal grain size is measured by EBSD over a measurement field of 150 μm x 150 μm on the rolled surface after heat treatment, and misorientation of 5° or more is regarded as a grain boundary. is 5.0 μm or less.
The average crystal grain size is calculated by crystal orientation analysis in EBSD (Electron Back Scatter Diffraction) measurement.
In the actual measurement, the surface of the sample is electrolytically polished and then observed using a SEM-EBSD (JEOL Ltd. JSM-IT500HR, TSL EDAX SCAN GENERATOR-II, TSL OIM DATA COLECTION 7) under the following conditions.
Note that the EBSD measurement may be performed on a sample plate (150 mm x 150 mm) cut out from the copper foil after heat treatment.

・WD:15.0mm or 16.0mm
・Camera Elavation Angle:2.7 degrees
・Sample Tilt:70.0 degrees
・Camera Azimuthal Angle:0.0 degrees
・加速電圧:15.0kV
・プローブ電流:9.5nA
・SS―CCD Camera:Binning 8×8
・Gain:300~350(Pattern brightness:0.90~0.95)
・Exposure time:4ms
・Background integration count:20times
・観察倍率: 600倍
・観察視野: 150μm×150μm
・ステップサイズ 0.5μm
・Scan Mode: Hexagonal Glid
・Phase List: Copper
・WD: 15.0mm or 16.0mm
・Camera Elevation Angle: 2.7 degrees
・Sample Tilt: 70.0 degrees
・Camera azimuthal angle: 0.0 degrees
・Acceleration voltage: 15.0kV
・Probe current: 9.5nA
・SS-CCD Camera: Binning 8×8
・Gain: 300-350 (Pattern brightness: 0.90-0.95)
・Exposure time: 4ms
・Background integration count: 20times
・Observation magnification: 600x ・Observation field: 150μm x 150μm
・Step size 0.5μm
・Scan Mode: Hexagonal Grid
・Phase List: Copper

また、得られた測定データの解析はOIM Analysis Ver8.0 x64 Advanced packageを用いて下記の条件で実施する。
・Grain Dilation法によるCrean Upを1回実施(Grain Tolerance angle:5,Minimum Grain size:2 points,Multi Row:1, Iteration Fraction:0.25)
・EBSDマップのエッジにかかった結晶粒は計算から除外
・Area Fraction法により、結晶粒径(Diameter)の平均値、標準偏差を算出
Furthermore, analysis of the obtained measurement data is performed using OIM Analysis Ver8.0 x64 Advanced package under the following conditions.
- Perform Clean Up once using the Grain Dilation method (Grain Tolerance angle: 5, Minimum Grain size: 2 points, Multi Row: 1, Iteration Fraction: 0.25)
・Crystal grains that touch the edges of the EBSD map are excluded from calculations. ・Calculate the average value and standard deviation of the crystal grain diameter (Diameter) using the Area Fraction method.

ここで、Area Fraction法では、各結晶粒の面積が観察視野全面積に占める割合を各面積値に乗した値の平均値から結晶粒径の平均値を算出する。すなわち、観察視野内において粗大な結晶粒が1つでも観察される場合、Number法よりも平均結晶粒径が大きくなりやすく、Area Fraction法で平均結晶粒径が小さいことは結晶粒の大きさが揃っていてかつ小さいことを示している。 Here, in the Area Fraction method, the average value of the crystal grain size is calculated from the average value of the values obtained by multiplying each area value by the ratio of the area of each crystal grain to the total area of the observation field. In other words, if even one coarse crystal grain is observed within the observation field, the average crystal grain size tends to be larger than in the Number method, and the smaller average crystal grain size in the Area Fraction method means that the size of the crystal grains is smaller. This shows that they are uniform and small.

平均結晶粒径、特にArea Fraction法による平均結晶粒径が5.0μm以下であれば、銅箔の金属組織が均一に近く(結晶粒の大きさが揃っていて)、エッチングによる回路形成時の化学反応(エッチング反応)が均一に生じると考えられる。 If the average crystal grain size, especially the average crystal grain size measured by the Area Fraction method, is 5.0 μm or less, the metal structure of the copper foil is nearly uniform (crystal grain sizes are uniform), and it is difficult to form a circuit by etching. It is thought that the chemical reaction (etching reaction) occurs uniformly.

<回路直線性>
銅箔に表面処理をした後にサンプル板(150mm×150mm)を切り出し、熱処理を加えて銅張積層板とした後に以下のエッチング条件で銅張積層板の銅箔側から直線回路(図2参照)を形成し、回路のボトム幅wを複数測定したとき、ボトム幅w(μm)の標準偏差σ(μm)と、ボトム幅wの平均値Aw(μm)で表されるσ/Awが0.03未満であると好ましい。σ/Awが0.03未満であると、回路直線性に優れる傾向にあることが経験的に得られているからである。
エッチング条件:
エッチング液の組成:CuCl-2HO=3mol/L(比重1.24)、HCl=4mol/L、液温度=50℃、エッチング液のスプレー圧=0.22MPaとし、回路部分をマスクした圧延銅箔をエッチング処理して回路を形成する。
σ/Awは、エッチング形成した回路の実際のボトム幅wを複数(好ましくは、10カ所以上、より好ましくは、50カ所、さらに好ましくは、回路の長手方向30μmごとに100カ所)測定してσ及びAwを求め、σ/Awを算出する。
<Circuit linearity>
After surface-treating the copper foil, cut out a sample board (150 mm x 150 mm), heat-treat it to make a copper-clad laminate, and then create a straight circuit from the copper foil side of the copper-clad laminate under the following etching conditions (see Figure 2). When the bottom width w of the circuit is formed and the bottom width w of the circuit is measured multiple times, σ/Aw expressed by the standard deviation σ (μm) of the bottom width w (μm) and the average value Aw (μm) of the bottom width w is 0. It is preferable that it is less than 0.03. This is because it has been empirically found that when σ/Aw is less than 0.03, circuit linearity tends to be excellent.
Etching conditions:
Etching solution composition: CuCl 2 -2H 2 O = 3 mol/L (specific gravity 1.24), HCl = 4 mol/L, solution temperature = 50°C, etching solution spray pressure = 0.22 MPa, and the circuit part was masked. A circuit is formed by etching rolled copper foil.
σ/Aw is determined by measuring the actual bottom width w of the etched circuit at multiple locations (preferably at 10 or more locations, more preferably at 50 locations, and even more preferably at 100 locations every 30 μm in the longitudinal direction of the circuit). and Aw, and calculate σ/Aw.

具体的には、図1に示すように、銅箔をエッチングして形成した回路21、22は、表面から下方(樹脂層4側(ボトム側))に向かって広がっており、このボトム側の回路幅(ボトム幅)wを複数測定する。ここで、符号wtは表面(トップ)側の回路幅(トップ幅)である。
なお、図2に示すように、別々の回路21、22からそれぞれ所定の測定点にて回路幅w1、w2、w100、w101、w102、w200・・・のように50カ所測定することができる。1つの回路上で測定してもよい。
Specifically, as shown in FIG. 1, the circuits 21 and 22 formed by etching copper foil extend downward from the surface (toward the resin layer 4 side (bottom side)), and Measure the circuit width (bottom width) w multiple times. Here, the symbol wt is the circuit width (top width) on the surface (top) side.
As shown in FIG. 2, the circuit widths can be measured at 50 locations such as w1, w2, w100, w101, w102, w200, . . . at predetermined measurement points from the separate circuits 21 and 22, respectively. Measurements may be made on one circuit.

σ/Awが0.03未満であると、ボトム幅wのバラツキが小さく、回路直線性が優れていることを示す。特に、ボトム幅wが10~35μmの範囲においても回路直線性が優れていることが好ましい。 When σ/Aw is less than 0.03, the variation in the bottom width w is small, indicating that the circuit linearity is excellent. In particular, it is preferable that the circuit linearity is excellent even when the bottom width w is in the range of 10 to 35 μm.

銅箔の回路部分のマスクは、例えばフォトレジスト(ドライフィルムレジスト等)を用いてフォトマスクにより回路として残る部分のみにレジストを残す公知の方法で形成できる。ドライフィルムレジストとしては、例えば日立化成製の製品名RY-5107 (厚み7μm)を用いることができる。 The mask for the circuit portion of the copper foil can be formed by, for example, a known method using a photoresist (dry film resist, etc.) and leaving the resist only on the portion that remains as the circuit. As the dry film resist, for example, Hitachi Chemical's product name RY-5107 (thickness: 7 μm) can be used.

ここで、図3は、回路直線性を評価する際の直線回路をエッチング形成するための露光マスクを示す。露光マスクのレジスト/スペースのパターンは10種類あり、図3の左側(番号10側)ほどスペースが広く、右側ほど狭くなる設計である。そして、全パターンに対し、露光、現像、エッチング、ドライフィルム剥離を順に行った後に、SEMを使用して目標のL/S(L/S=10/40~30/20)に近い回路を、全パターンの中から1個選択し、評価に用いる。 Here, FIG. 3 shows an exposure mask for etching a linear circuit when evaluating circuit linearity. There are 10 types of resist/space patterns on the exposure mask, and the space is designed to be wider on the left side (number 10 side) in FIG. 3 and narrower on the right side. Then, after sequentially exposing, developing, etching, and peeling off the dry film for all patterns, a circuit close to the target L/S (L/S = 10/40 to 30/20) was created using SEM. Select one from all patterns and use it for evaluation.

銅箔の厚さは、JISC6515に規定される公称厚さで17μm以下が好ましい。厚さが薄い程、銅箔にかかる応力が小さくなるため折り曲げ性の向上に資すると共にポータブル機器の小型化、薄型化、軽量化にも資する。 The thickness of the copper foil is preferably 17 μm or less as the nominal thickness specified in JISC6515. The thinner the copper foil, the smaller the stress applied to the copper foil, which contributes to improved bendability and also contributes to making portable devices smaller, thinner, and lighter.

<製造>
本発明の銅箔は、例えば以下のようにして製造することができる。まず、銅インゴットに必要に応じてPを添加して溶解、鋳造した後、熱間圧延し、冷間圧延と焼鈍を繰り返し行うことにより箔を製造することができる。
ここで、冷間圧延の途中で、所定の冷却速度の中間焼鈍を実施し、中間焼鈍の際に発生した酸化スケールを除去して中間冷間圧延を行った後に最終焼鈍、最終冷間圧延をして目的とする最終厚さの箔を得ることができる。
中間焼鈍の最高温度は、350~500℃とすることができる。中間焼鈍の冷却速度は、中間焼鈍における最高温度TM(℃)から、(TM-200)℃の温度まで50~150℃/hで冷却することが好ましい。
<Manufacturing>
The copper foil of the present invention can be manufactured, for example, as follows. First, a foil can be manufactured by adding P to a copper ingot as needed, melting and casting the ingot, hot rolling it, and repeating cold rolling and annealing.
Here, in the middle of cold rolling, intermediate annealing is performed at a predetermined cooling rate, and after removing the oxide scale generated during intermediate annealing and performing intermediate cold rolling, final annealing and final cold rolling are performed. The desired final thickness of the foil can be obtained.
The maximum temperature of intermediate annealing can be 350 to 500°C. The cooling rate of intermediate annealing is preferably 50 to 150° C./h from the maximum temperature TM (° C.) in intermediate annealing to a temperature of (TM-200)° C.

以上のように中間焼鈍の冷却速度を50~150℃/hに設定すると、一般的な条件よりも冷却速度が遅くなる。そして、中間焼鈍の冷却速度が遅いほど、材料内の温度勾配が小さくなる(一番初めに冷却される箇所と一番遅く冷却される箇所の温度差が小さくなる)ことにより、金属組織が均一となりやすく(結晶粒の大きさが揃い)、最終厚さの箔を熱処理したときの平均結晶粒径が小さくなる。その結果、エッチングによる回路形成時の化学反応(エッチング反応)が均一に生じるために回路直線性が向上すると考えられる。
これは、上述の通り、AreaFraction法による結晶粒径が小さいほど、結晶粒の大きさが揃っていて、かつ個々結晶粒の粒径が小さいことを意味するためである。
As described above, when the cooling rate for intermediate annealing is set to 50 to 150°C/h, the cooling rate becomes slower than under general conditions. The slower the cooling rate during intermediate annealing, the smaller the temperature gradient within the material (the smaller the temperature difference between the first and last cooled areas), which results in a more uniform metal structure. (crystal grain sizes are uniform), and the average crystal grain size becomes smaller when the final thickness foil is heat treated. As a result, it is thought that the chemical reaction (etching reaction) during circuit formation by etching occurs uniformly, resulting in improved circuit linearity.
This is because, as described above, the smaller the crystal grain size determined by the AreaFraction method, the more uniform the crystal grain sizes are, and the smaller the grain size of each crystal grain.

図4,図5は金属組織が均一(結晶粒の大きさが揃う)なほど、回路直線性が向上するメカニズムを示す。
図4に示すように、エッチングは、レジストの無い部分(直線回路の間のスペースに相当)からエッチング液が銅箔内部に侵入して進行するが、スペースから銅箔の左右に向かってエッチングが進む。このとき、図1に示したように、エッチング(回路)は、表面から下方(樹脂層側(ボトム側))に向かって広がっていく。
4 and 5 show the mechanism by which circuit linearity improves as the metal structure becomes more uniform (crystal grain sizes are more uniform).
As shown in Figure 4, etching progresses as the etching solution enters the copper foil from the areas without resist (corresponding to the spaces between linear circuits), but the etching progresses from the spaces toward the left and right of the copper foil. move on. At this time, as shown in FIG. 1, the etching (circuit) spreads downward from the surface (toward the resin layer side (bottom side)).

ここで、図5(a)に示すように、金属組織が均一でない(結晶粒の大きさが揃っていない)場合、図1に示した回路21、22のボトム幅wのバラツキが大きくなる(図5(a)で回路21、22の縁が直線状でなく、波打つように曲がっている)。
この理由は、図5(b)に示すように、例えば視野150μm×150μm内で、回路21側の銅箔の結晶粒が大きく、回路22側の銅箔の結晶粒が小さいと、金属組織が均一でなく(結晶粒の大きさが揃わず)、結晶粒が大きい回路21側でのエッチング速度が大きくなり、結晶粒が小さい部位との間でエッチング量が変わり、ひいてはボトム幅wのバラツキが大きくなるためと考えられる。
Here, as shown in FIG. 5(a), if the metal structure is not uniform (crystal grain sizes are not uniform), the variation in the bottom width w of the circuits 21 and 22 shown in FIG. 1 becomes large ( In FIG. 5(a), the edges of the circuits 21 and 22 are not straight but curved in a wavy manner).
The reason for this is that, as shown in FIG. 5(b), for example, if the crystal grains of the copper foil on the circuit 21 side are large and the crystal grains of the copper foil on the circuit 22 side are small within a field of view of 150 μm x 150 μm, the metal structure will change. The etching rate is not uniform (crystal grain size is not uniform), and the etching rate on the side of the circuit 21 where the crystal grains are large increases, and the etching amount changes between the parts where the crystal grains are small, and the bottom width w varies. This is thought to be due to the increase in size.

なお、図5(b)において、結晶粒と結晶粒界ではエッチングされる速度が異なるので、結晶粒の大きさが揃っていないと、エッチング速度が局所的に大きく変動することになる。なお、本試験のエッチング液では結晶粒よりも結晶粒界のエッチング速度が遅かったが、逆の場合もある。 Note that in FIG. 5B, the etching speed is different between crystal grains and grain boundaries, so if the crystal grains are not uniform in size, the etching speed will locally vary greatly. Although the etching solution used in this test etched grain boundaries slower than crystal grains, the opposite may be true.

上記のEBSD測定した結晶粒径の標準偏差が3.0μm以下であると、結晶粒の大きさがより一層揃うので好ましい。結晶粒径の標準偏差の測定法は、上述のEBSD測定について記載した通りであり、測定結果に対してAreaFraction法により、結晶粒径の平均値(平均結晶粒径)だけでなく、標準偏差も算出される。 It is preferable that the standard deviation of the crystal grain size measured by the above-mentioned EBSD is 3.0 μm or less because the crystal grain sizes are more uniform. The method for measuring the standard deviation of the crystal grain size is as described above for the EBSD measurement, and the AreaFraction method is used to calculate not only the average value of the crystal grain size (average grain size) but also the standard deviation. Calculated.

<銅張積層体及びフレキシブルプリント基板>
又、本発明の銅箔に例えば(1)樹脂前駆体(例えばワニスと呼ばれるポリイミド前駆体)をキャスティングして熱をかけて重合させること、(2)ベースフィルムと同種の熱可塑性接着剤を用いてベースフィルムを本発明の銅箔にラミネートすること、により、銅箔と樹脂基材の2層からなる銅張積層体(CCL)が得られる。又、本発明の銅箔に接着剤を塗着したベースフィルムをラミネートすることにより、銅箔と樹脂基材とその間の接着層の3層からなる銅張積層体(CCL)が得られる。これらのCCL製造時に銅箔が熱処理されて再結晶化する。
これらにフォトリソグラフィー技術を用いて回路を形成し、必要に応じて回路にめっきを施し、カバーレイフィルムをラミネートすることでフレキシブルプリント基板(フレキシブル配線板)が得られる。
<Copper-clad laminate and flexible printed circuit board>
In addition, for example, (1) casting a resin precursor (for example, a polyimide precursor called varnish) on the copper foil of the present invention and polymerizing it by applying heat; (2) using the same type of thermoplastic adhesive as the base film; By laminating the base film on the copper foil of the present invention, a copper clad laminate (CCL) consisting of two layers of copper foil and a resin base material is obtained. Further, by laminating a base film coated with an adhesive on the copper foil of the present invention, a copper clad laminate (CCL) consisting of three layers of the copper foil, a resin base material, and an adhesive layer therebetween can be obtained. During the manufacture of these CCLs, the copper foil is heat treated and recrystallized.
A flexible printed circuit board (flexible wiring board) is obtained by forming a circuit on these using photolithography technology, plating the circuit as necessary, and laminating a coverlay film.

従って、本発明の銅張積層体は、銅箔と樹脂層とを積層してなる。又、本発明のフレキシブルプリント基板は、銅張積層体の銅箔に回路を形成してなる。
樹脂層としては、PET(ポリエチレンテレフタレート)、PI(ポリイミド)、LCP(液晶ポリマー)、PEN(ポリエチレンナフタレート)が挙げられるがこれに限定されない。また、樹脂層として、これらの樹脂フィルムを用いてもよい。
樹脂層と銅箔との積層方法としては、銅箔の表面に樹脂層となる材料を塗布して加熱成膜してもよい。又、樹脂層として樹脂フィルムを用い、樹脂フィルムと銅箔との間に以下の接着剤を用いてもよく、接着剤を用いずに樹脂フィルムを銅箔に熱圧着してもよい。但し、樹脂フィルムに余分な熱を加えないという点からは、接着剤を用いることが好ましい。
Therefore, the copper-clad laminate of the present invention is formed by laminating copper foil and a resin layer. Further, the flexible printed circuit board of the present invention is formed by forming a circuit on the copper foil of the copper-clad laminate.
Examples of the resin layer include, but are not limited to, PET (polyethylene terephthalate), PI (polyimide), LCP (liquid crystal polymer), and PEN (polyethylene naphthalate). Further, these resin films may be used as the resin layer.
As a method of laminating the resin layer and the copper foil, a material that will become the resin layer may be applied to the surface of the copper foil and then heated to form a film. Alternatively, a resin film may be used as the resin layer and the following adhesive may be used between the resin film and the copper foil, or the resin film may be thermocompression bonded to the copper foil without using an adhesive. However, from the viewpoint of not applying excess heat to the resin film, it is preferable to use an adhesive.

樹脂層としてフィルムを用いた場合、このフィルムを、接着剤層を介して銅箔に積層するとよい。この場合、フィルムと同成分の接着剤を用いることが好ましい。例えば、樹脂層としてポリイミドフィルムを用いる場合は、接着剤層もポリイミド系接着剤を用いることが好ましい。尚、ここでいうポリイミド接着剤とはイミド結合を含む接着剤を指し、ポリエーテルイミド等も含む。 When a film is used as the resin layer, this film is preferably laminated on the copper foil via an adhesive layer. In this case, it is preferable to use an adhesive having the same components as the film. For example, when a polyimide film is used as the resin layer, it is preferable that the adhesive layer also uses a polyimide adhesive. Note that the polyimide adhesive herein refers to an adhesive containing an imide bond, and also includes polyetherimide and the like.

なお、本発明は、上記実施形態に限定されない。又、本発明の作用効果を奏する限り、上記実施形態における銅合金がその他の成分を含有してもよい。
例えば、銅箔の表面に、粗化処理、防錆処理、耐熱処理、またはこれらの組み合わせによる表面処理を施してもよい。
Note that the present invention is not limited to the above embodiments. Moreover, the copper alloy in the above embodiment may contain other components as long as the effects of the present invention are achieved.
For example, the surface of the copper foil may be subjected to surface treatment such as roughening treatment, rust prevention treatment, heat resistance treatment, or a combination thereof.

次に、実施例を挙げて本発明をさらに詳細に説明するが、本発明はこれらに限定されるものではない。
電気銅を用いてインゴットを非酸化性雰囲気で作製した。インゴットに含まれる銅の割合は99.96質量%以上であった。このインゴットを900℃以上で均質化焼鈍後、熱間圧延と冷間圧延を行った。冷間圧延中に最高温度400℃の中間焼鈍を実施し、中間焼鈍の冷却速度を最高温度より200℃低い温度まで表1の値として冷却した。実施例の冷却速度は、該実施例と別の材料を焼鈍した時の材料温度実測データから推算した。中間焼鈍の際に発生した酸化スケールを除去して中間冷間圧延を行った後に最終焼鈍、最終冷間圧延をして目的とする最終厚さ12μmの箔を得た。なお、比較例については、最高温度より200℃低い温度までの中間焼鈍の冷却速度を伝熱シミュレーションにより求め、表1に記載した。
Next, the present invention will be explained in more detail with reference to Examples, but the present invention is not limited thereto.
Ingots were produced using electrolytic copper in a non-oxidizing atmosphere. The proportion of copper contained in the ingot was 99.96% by mass or more. This ingot was homogenized and annealed at 900° C. or higher, and then hot rolled and cold rolled. Intermediate annealing was performed at a maximum temperature of 400° C. during cold rolling, and the cooling rate for intermediate annealing was set to the values shown in Table 1 to a temperature 200° C. lower than the maximum temperature. The cooling rate of the example was estimated from actual material temperature measurement data when a material different from that of the example was annealed. After removing the oxide scale generated during intermediate annealing and performing intermediate cold rolling, final annealing and final cold rolling were performed to obtain a foil having the desired final thickness of 12 μm. In addition, for the comparative example, the cooling rate of intermediate annealing to a temperature 200° C. lower than the maximum temperature was determined by heat transfer simulation and is listed in Table 1.

得られた箔に対し、大気雰囲気において、300℃×30分の熱処理を加え、銅箔サンプルを得た。具体的には、酸化防止の為に幅30mm×長さ130mm×厚み0.15mmのC7025板2枚の間に銅箔サンプルを挟み、A4サイズのアニール済みのC1100でパッキングを行った後に、300℃になった高温熱風乾燥機の扉を開けて投入し、30分後に扉を開けてを回収し、銅箔サンプルを取り出した。熱処理後の銅箔は、CCLの積層時に熱処理を受けた状態を模している。熱処理後の銅箔の圧延面を電解研磨した後に測定視野150μm×150μmをEBSD測定し、方位差5°以上を結晶粒界とみなしたときの結晶粒径の平均値(平均結晶粒径)及び標準偏差を求めた。EBSD測定の条件は上述の記載通りとした。 The obtained foil was heat treated at 300° C. for 30 minutes in an air atmosphere to obtain a copper foil sample. Specifically, in order to prevent oxidation, a copper foil sample was sandwiched between two C7025 plates of 30 mm width x 130 mm length x 0.15 mm thickness, and after packing with A4 size annealed C1100, The door of the high-temperature hot air dryer, which had reached ℃, was opened and the sample was put in. After 30 minutes, the door was opened and the sample was collected, and the copper foil sample was taken out. The copper foil after heat treatment simulates the state that was heat treated during lamination of CCL. After electrolytically polishing the rolled surface of the copper foil after heat treatment, EBSD measurement was performed on a measurement field of 150 μm x 150 μm, and the average value of the crystal grain size (average grain size) and The standard deviation was calculated. The conditions for the EBSD measurement were as described above.

また、最終冷間圧延をして得られた箔に表面処理を行った後に、ユーピレックスVT(宇部興産株式会社製)25μmを積層し,加熱プレス機で300℃×30minの熱処理を行って銅張積層板とした後、ドライフィルムレジスト(日立化成製の製品名RY-5107、厚み7μm)を用い、銅箔の回路部分をフォトリソによりマスクし、L+Sが50μmピッチのドライフィルムパターニングを行った。レジストの現像、エッチング及びレジストの剥離は、サンテクノシステム株式会社の「現像・エッチング・剥離ライン」(装置名:DERM)を用いた。エッチング条件は上述の「<回路直線性>」で記載した通りである。 In addition, after surface treatment was performed on the foil obtained by final cold rolling, Upilex VT (manufactured by Ube Industries, Ltd.) of 25 μm was laminated and heat treated at 300°C for 30 minutes using a hot press machine to form copper cladding. After forming a laminate, using a dry film resist (product name RY-5107 manufactured by Hitachi Chemical, thickness 7 μm), the circuit portion of the copper foil was masked by photolithography, and dry film patterning was performed with an L+S pitch of 50 μm. For resist development, etching, and resist peeling, a "Development/Etching/Removal Line" (equipment name: DERM) manufactured by Sun Techno System Co., Ltd. was used. The etching conditions are as described in "<Circuit Linearity>" above.

<回路直線性の評価>
上記したエッチング条件により、目標L/S(L/S=10/40~30/20)に近くなるよう各実施例及び各比較例ごとにエッチング時間を種々変えて条件設定したものを、実際に測定したところ、ボトム幅wの平均値Awは表1に示すような値となった。平均値AwはL/SのLを表す。また、「50μm-平均値Aw」はL/SのSを表す。各実施例及び各比較例ごとに、それぞれ各回路のボトム幅wを図2に示すようにして50カ所測定し、平均値Awを求めた。
なお、各実施例はそれぞれ同じ銅箔について、36~54秒の範囲でエッチング時間をそれぞれ変えた。同様に、各比較例はそれぞれ同じ銅箔について、36~54秒の範囲でエッチング時間をそれぞれ変えた。
<Evaluation of circuit linearity>
According to the etching conditions described above, the conditions were set by changing the etching time variously for each example and each comparative example so that it was close to the target L/S (L/S = 10/40 to 30/20). When measured, the average value Aw of the bottom width w was as shown in Table 1. The average value Aw represents L of L/S. Further, "50 μm-average value Aw" represents S of L/S. For each example and each comparative example, the bottom width w of each circuit was measured at 50 locations as shown in FIG. 2, and the average value Aw was determined.
In each example, the etching time was changed in the range of 36 to 54 seconds for the same copper foil. Similarly, in each comparative example, the etching time was changed in the range of 36 to 54 seconds for the same copper foil.

得られた結果を表1に示す。ここで、実施例1~7のP濃度は10~50質量ppmの範囲であり、比較例1~7のP濃度は10ppm未満であった。P濃度の分析は上述した方法により行った。 The results obtained are shown in Table 1. Here, the P concentrations in Examples 1 to 7 were in the range of 10 to 50 mass ppm, and the P concentrations in Comparative Examples 1 to 7 were less than 10 ppm. Analysis of P concentration was performed by the method described above.

Figure 2024012029000002
Figure 2024012029000002

平均結晶粒径が5.0μm以下である実施例の銅箔を用いてフレキシブルプリント基板を作成したところ、σ/Awが0.03未満であり、隣り合う回路との接触がほとんど見られず、回路直線性に優れていることがわかった。
一方、平均結晶粒径が5.0μmを超えた比較例銅箔を用いてフレキシブルプリント基板を作成したところ、σ/Awが0.03以上であり、隣り合う回路との接触が散見され、回路直線性に劣ることがわかった。
When a flexible printed circuit board was created using the copper foil of the example with an average crystal grain size of 5.0 μm or less, σ/Aw was less than 0.03, and almost no contact with adjacent circuits was observed. It was found that the circuit linearity was excellent.
On the other hand, when a flexible printed circuit board was created using a comparative example copper foil with an average crystal grain size exceeding 5.0 μm, the σ/Aw was 0.03 or more, and contact with adjacent circuits was observed here and there. It was found that the linearity was poor.

Claims (7)

99.96質量%以上のCuを含有し、残部不可避的不純物からなる圧延銅箔であって、
300℃×30分の熱処理を行ったとき、前記圧延銅箔の圧延面の測定視野150μm×150μmをEBSD測定し、方位差5°以上を結晶粒界とみなしたときの平均結晶粒径が5.0μm以下であるフレキシブルプリント基板用銅箔。
A rolled copper foil containing 99.96% by mass or more of Cu, the remainder consisting of unavoidable impurities,
When heat treatment was performed at 300°C for 30 minutes, EBSD measurement was performed on a measurement field of 150 μm x 150 μm on the rolled surface of the rolled copper foil, and the average crystal grain size was 5 when misorientation of 5° or more was regarded as a grain boundary. Copper foil for flexible printed circuit boards with a thickness of .0μm or less.
前記EBSD測定した前記結晶粒径の標準偏差が3.0μm以下である請求項1に記載のフレキシブルプリント基板用銅箔。 The copper foil for a flexible printed circuit board according to claim 1, wherein the standard deviation of the crystal grain size measured by the EBSD is 3.0 μm or less. JIS-H3100(C1100)に規格するタフピッチ銅又はJIS-H3100(C1020)の無酸素銅からなる請求項1又は2に記載のフレキシブルプリント基板用銅箔。 The copper foil for a flexible printed circuit board according to claim 1 or 2, comprising tough pitch copper compliant with JIS-H3100 (C1100) or oxygen-free copper compliant with JIS-H3100 (C1020). 10~50質量ppmのPを含有する請求項1又は2に記載のフレキシブルプリント基板用銅箔。 The copper foil for a flexible printed circuit board according to claim 1 or 2, containing 10 to 50 mass ppm of P. 請求項1又は2に記載のフレキシブルプリント基板用圧延銅箔と、樹脂層とを積層してなる銅張積層体。 A copper-clad laminate comprising the rolled copper foil for flexible printed circuit boards according to claim 1 or 2 and a resin layer. 請求項5に記載の銅張積層体における前記圧延銅箔に回路を形成してなるフレキシブルプリント基板。 A flexible printed circuit board formed by forming a circuit on the rolled copper foil in the copper-clad laminate according to claim 5. 請求項6に記載のフレキシブルプリント基板を用いた電子機器。 An electronic device using the flexible printed circuit board according to claim 6.
JP2022168095A 2022-07-14 2022-10-20 Copper foil for flexible printed substrate, and copper-clad laminate, flexible printed substrate and electronic device that employ the same Pending JP2024012029A (en)

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