JP2023539923A - Boundary scan test method - Google Patents

Abstract

The boundary scan test method for testing connectivity from a first device to a second device PAD includes the steps of setting the FPGA in test mode, editing user logic functions, and providing a bypass circuit (S10). , selecting a PAD to be tested and loading a test command to test connectivity from the output PAD to the input PAD to be tested (S20); inputting a test excitation (S30); The method includes the steps of removing the test excitation by TDO of the FPGA lower device (S40), and performing response analysis and fault diagnosis (S50). Editing user logic functions and providing bypass circuitry can bypass PADs that do not need to be tested, shorten test scan chains, increase test speed, and increase test flexibility. [Selection diagram] Figure 1

Description

TECHNICAL FIELD This application relates to the field of chip testing, and more particularly to boundary scan testing methods.

JTAG (Joint Test Action Group, an international standard test protocol) is based on an international standard test protocol (IEEE 1149.1 exchange) and is mainly used for chip internal testing. Currently, most advanced devices can support the JTAG protocol, such as DSP, FPGA devices, etc. JTAG testing can perform test excitation and analysis test response through JTAG pins to enable fault diagnosis of the circuit under test. Boundary scan test (BST) implements testing of digital circuits using a boundary scan unit of a chip pin (PAD) through a JTAG bus. Boundary scan testing is simple and fast, and has the advantage of covering the entire product cycle from research and development to production and maintenance, which can significantly reduce product testing costs. Boundary scan units are arranged at the device signal input end, output end, bidirectional end, and dry state port end, and the boundary scan units are connected to form a boundary scan chain. Currently, boundary scan testing is performed in hardware, but implementing boundary scan in hardware has relatively major drawbacks. Firstly, the need to perform boundary scan testing on all PADs increases test time, and secondly, test placement is not flexible and it is not possible to identify which PADs need to be tested. .

In view of these, a new boundary scan testing method is urgently needed to solve the above problems, realize faster and more flexible boundary scan testing, and improve test efficiency.

Based on this, the present application provides a boundary scan test method that only tests PADs that need to be tested and skips PADs that do not need to be tested, thereby performing a boundary scan test more quickly.

To achieve the above objective, the present application provides a boundary scan test method for testing connectivity from a first device to a second device PAD, the method comprising:
S10, setting the FPGA in test mode and editing user logic functions to provide a bypass circuit;
S20, loading a test command for testing connectivity from an output PAD to be tested to an input PAD to be tested;
S30, inputting a test excitation;
S40, removing the test excitation by a TDO of the FPGA sub-device;
S50, a step of performing response analysis and fault diagnosis.

Preferably, the first device is the FPGA host device, the second device is the FPGA, the output PAD of the test target is an output PAD of the test target of the FPGA host device, and the test target The input PAD is the input PAD to be tested of the FPGA,
The step S10 includes user logic that sets the FPGA to test mode via a JTAG daisy chain and connects the input PAD under test of the FPGA to the last multiplex or general purpose PAD of the boundary scan chain of the FPGA. including editing features;
The step S30 includes inputting a test excitation, inputting an EXTEST command, moving and updating the test excitation to the boundary scan register of the output PAD to be tested of the FPGA host device, and moving the test excitation to the boundary scan register of the output PAD to be tested of the FPGA host device. updating the boundary scan register of the input PAD under test, entering an INTEST command and moving the test excitation by a bypass circuit to the last multiplexed or general purpose PAD of the boundary scan chain of the FPGA.

Preferably, the first device is the FPGA upper device, the second device is the FPGA lower device, the output PAD to be tested is an output PAD to be tested of the FPGA upper device, and the The input PAD to be tested is the input PAD to be tested for the FPGA lower device;
The step S30 includes inputting a test excitation, inputting an EXTEST command, moving and updating the test excitation to the boundary scan register of the output PAD to be tested of the FPGA upper device, and moving the test excitation to the boundary scan register of the output PAD to be tested of the FPGA upper device. This includes updating the input PAD of the device being tested.

Preferably, the first device is the FPGA, the second device is the FPGA host device, the output PAD of the test target is an output PAD of the FPGA, and the input of the test target is preferably an output PAD of the FPGA. PAD is an input PAD for the FPGA upper device test target,
The step S10 sets the FPGA to a test mode via a JTAG daisy chain, and sets the first multiplexed or general-purpose PAD of the boundary scan chain of the FPGA to the output PAD of the FPGA to be tested plus the bounce of the FPGA. editing the user logic function of connecting to the last multiplex or general purpose PAD of the dally scan chain;
The step S30 includes inputting a test excitation, inputting an INTEST command, and moving and updating the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general-purpose PAD; updating the test excitation to the boundary scan register of the output PAD to be tested of the FPGA by a bypass circuit, inputting an EXTEST command and moving the test excitation to the boundary scan register of the input PAD of the FPGA upper device to be tested; moving the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general purpose PAD; entering an INTEST command and moving the test excitation to the bounce of the FPGA by a bypass circuit; Includes multiplexing at the end of the dally scan chain or populating the generic PAD.

Preferably, the first device is the FPGA, the second device is the FPGA lower device, the output PAD of the test object is an output PAD of the FPGA, and the input of the test object is preferably an output PAD of the FPGA. PAD is an input PAD for the FPGA lower device test target;
The step S10 includes setting the FPGA in a test mode via a JTAG daisy chain and connecting a first multiplexed or general-purpose PAD of a boundary scan chain of the FPGA to an output PAD of the FPGA to be tested. including editing user logic functions;
The step S30 includes inputting a test excitation, inputting an INTEST command, moving the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary register of a general-purpose PAD, and updating the test excitation. updating an excitation to a boundary scan register of an output PAD under test of the FPGA by a bypass circuit, inputting an EXTEST command and incorporating the test excitation into an input PAD of the FPGA sub-device under test.

Preferably, the first device is the FPGA lower device, the second device is the FPGA upper device, the output PAD to be tested is the output PAD to be tested of the FPGA lower device, and the The input PAD to be tested is the input PAD to be tested by the FPGA upper-level device;
Said step S10 sets the FPGA to a test mode via a JTAG daisy chain, and connects the first multiplex or general purpose PAD of the boundary scan chain of said FPGA to the last multiplex or of the boundary scan chain of said FPGA. including editing a user logic function to connect to a generic PAD;
The step S30 includes inputting a test excitation, inputting an INTEST command, and moving and updating the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general-purpose PAD; incorporating a test excitation into a final multiplex of a boundary scan chain of said FPGA or a boundary scan register of a general purpose PAD by a bypass circuit; moving said test excitation to an output PAD under test of said FPGA sub-device for updating; , inputting an EXTEST command to capture the test excitation into a boundary scan register of an input PAD of the FPGA upper device under test; moving to and updating a boundary scan register, entering an INTEST command and incorporating the test excitation into the last multiplex of the boundary scan chain of the FPGA or the boundary scan register of a general purpose PAD by a bypass circuit;

Preferably, the first device is the FPGA sub-device, the second device is the FPGA, the output PAD of the test object is an output PAD of the FPGA sub-device, and the test object The input PAD is the input PAD to be tested of the FPGA,
Said step S10 sets the FPGA to a test mode via a JTAG daisy chain, and connects the first multiplex or general purpose PAD of the boundary scan chain of said FPGA to the last multiplex or of the boundary scan chain of said FPGA. editing a user logic function to connect to a general purpose PAD and connect an input PAD under test of the FPGA to a second multiplexing or general purpose PAD from the end of a boundary scan chain of the FPGA;
The step S30 includes inputting a test excitation, inputting an INTEST command, moving and updating the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general purpose PAD, and bypassing. incorporating the test excitation by a circuit into a last multiplexed or general purpose PAD of a boundary scan chain of the FPGA; moving and updating the test excitation into a boundary scan register of an output PAD under test of the FPGA sub-device; entering an EXTEST command to incorporate and update said test excitation into a boundary scan register of an input PAD under test of said FPGA; This includes loading into the boundary scan unit of the general-purpose PAD.

The present application has the following beneficial effects. The present application provides a boundary scan test method, which performs function editing in FPGA user logic, provides a bypass circuit, and removes PADs that do not need to be tested by the bypass circuit. The present application can shorten the boundary scan chain, realize faster and more flexible boundary scan testing, and improve test efficiency. Furthermore, it is possible to deploy test PADs without having to test all PADs.

1 is a flowchart of the boundary scan test method of the present application. FIG. 1 is a schematic diagram of Example 1 of the present application. FIG. 2 is a schematic diagram of Example 2 of the present application. FIG. 3 is a schematic diagram of Example 3 of the present application. FIG. 4 is a schematic diagram of Example 4 of the present application. It is a schematic diagram of Example 5 of this application. FIG. 6 is a schematic diagram of Example 6 of the present application.

In order that the present application may be more easily understood, the present application will now be described more fully with reference to the associated accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, this application may be implemented in a variety of different configurations and is not limited to the examples described herein. Rather, these examples are provided in order to provide a more thorough and comprehensive understanding of the disclosure of this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present application.

Referring to FIG. 1, there is a flowchart of the boundary scan testing method of the present application. The present application provides a boundary scan test method for testing connectivity from a first device to a second device PAD, the method comprising:
S10, setting the FPGA in test mode, editing user logic functions, and providing a bypass circuit;
S20, loading a test command for testing connectivity from an output PAD to be tested to an input PAD to be tested;
S30, inputting a test excitation by TDI (test data input);
S40, removing the test excitation by TDO (test data output) of the FPGA lower device;
S50, response analysis and fault diagnosis steps are included.

This application shortens the scan chain of boundary scan tests by editing user logic functions to connect PADs required for testing and skipping PADs not required for testing by bypass circuits, increasing test speed and flexibility. can increase sex. Hereinafter, the steps of the present application will be explained in more detail with reference to more specific examples.

(Example 1)
FIG. 2 is a schematic diagram of the boundary scan test method of Example 1 of the present application. Specifically, in this embodiment, the first device is an FPGA host device, the second device is an FPGA, and the output PAD (output PAD S) to be tested of the FPGA host device is connected to the input to be tested of the FPGA. Test connectivity to PAD (input PAD D).

Specifically, the boundary scan test is realized by the following steps.
S10, edit the user logic function of setting the FPGA to test mode via the JTAG daisy chain, connecting the input PAD D to the output PADE E, and providing a bypass circuit. Here, PAD E is the last multiplexed or general purpose PAD in the boundary scan chain of the FPGA.

S20, loads a test command to test the connectivity from the FPGA upper device output PAD S to the FPGA input PAD D;

S30, input test excitation, input EXTEST (external test) command, transition to SHIFT-DR (shift) state, move test excitation to boundary scan register of output PAD S, then UPDATE-DR (data UPDATE-) state, updates the test excitation to the boundary-scan register of the output PAD S, enters the CAPTURE-DR state, captures the test excitation to the boundary-scan register of the input PAD D, and updates the test excitation to the boundary-scan register of the input PAD S. Go to the DR state, update the test excitation to the boundary scan register of input PAD D, input the INTEST command, go from the CAPTURE-DR state to the SHIFT-DR state, and update the test excitation to the boundary of the FPGA by the bypass circuit. Move to scan chain output PAD E.

Here, the EXTEST command is used to perform an interconnect test between different devices PAD. A PRELOAD command operation is required before the EXTEST command to preload the test excitation. When the EXTEST command is executed, the preloaded test excitation is moved to the output PAD, ensuring that the output PAD state is controllable.

The INTEST command uses boundary scan registers as inputs and outputs of devices, allowing static testing of system logic. A PRELOAD command operation is required before the INTEST command to preload the test excitation. When the INTEST command is executed, the preloaded test excitation is moved to the input PAD, ensuring that the state of the input PAD is controllable.

S40, transition to SHIFT-DR state and remove test excitation by TDO of FPGA lower device.

S50: Response analysis and failure diagnosis.

This embodiment edits the FPGA user logic function to connect input PAD D to output PAD E, provides a bypass circuit, and removes PADs that do not need to be tested by the bypass circuit. This embodiment can shorten the boundary scan chain, realize faster and more flexible boundary scan testing, and improve test efficiency. Additionally, it provides flexibility in placing test PADs without having to test all PADs.

(Example 2)
FIG. 3 shows a boundary scan test method according to Example 2 of the present application. Specifically, in this embodiment, the first device is an FPGA upper device, the second device is an FPGA lower device, and the output PAD of the FPGA lower device is calculated from the output PAD to be tested (output PAD S) of the FPGA upper device. Test connectivity to the input PAD to be tested (input PAD D).

Specifically, the boundary scan test is realized by the following steps.
S10, set FPGA to test mode,
S20, loading a test command to test the connectivity from the FPGA upper device output PAD S to the FPGA lower device input PAD D;
S30, input the test excitation, input the EXTEST command, move to the SHIFT-DR state, move the test excitation to the boundary scan register of the output PAD S, then move to the UPDATE-DR state and output the test excitation Update to boundary scan register of PAD S, enter CAPTURE-DR (data acquisition) state, take test excitation to input PAD D, enter UPDATE-DR state, update test excitation to boundary scan register of input PAD D Update to the register,
S40, transition to SHIFT-DR state, remove test excitation by TDO of FPGA lower device;
S50: Response analysis and failure diagnosis.

This embodiment shortens the boundary scan chain, realizes faster and more flexible boundary scan testing, and improves test efficiency. Additionally, test PADs can be flexibly placed without the need to test all PADs.

(Example 3)
FIG. 4 is a boundary scan test method according to Example 3 of the present application. Specifically, in this embodiment, the first device is an FPGA, the second device is an FPGA host device, and the output PAD (output PAD S) to be tested of the FPGA is connected to the input to be tested of the FPGA host device. Test connectivity to PAD (input PAD D).

Specifically, the boundary scan test is realized by the following steps.
S10, set the FPGA to test mode via the JTAG daisy chain, edit the user logic functions to connect input PAD H to outputs PAD S and PAD E, and provide bypass circuitry. Here, PAD H is the first multiplex or general purpose PAD of the FPGA's boundary scan chain, and PADE E is the last multiplex or general purpose PAD of the FPGA's boundary scan chain.
S20, loading a test command to test the connectivity from the FPGA output PAD S to the FPGA upper device input PAD D;
S30, input test excitation, input INTEST command, move to SHIFT-DR state, move test excitation to boundary scan register of input PAD H, then move to UPDATE-DR state, input test excitation Update the boundary scan register of PAD H, update the test excitation to the boundary scan register of output PAD S by the bypass circuit, input the EXTEST command, move the test excitation to the boundary scan register of PAD D, and execute the test. Move the excitation to the boundary-scan register of input PAD H, enter the INTEST command, go to the UPDATE-DR state, update the test excitation to the boundary-scan register of input PAD H, go to the CAPTURE-DR state. , the test excitation is taken into the boundary scan register of the output PAD E by the bypass circuit,
S40, transition to SHIFT-DR state, remove test excitation by TDO of FPGA lower device;
S50: Response analysis and failure diagnosis.

This embodiment edits the user logic function to connect input PAD H to outputs PAD S and PAD E, and provides a bypass circuit to remove PADs that do not need to be tested by the bypass circuit. This embodiment shortens the boundary scan chain, realizes faster and more flexible boundary scan testing, and improves test efficiency. Additionally, test PADs can be flexibly placed without the need to test all PADs.

(Example 4)
FIG. 5 is a boundary scan test method according to Example 4 of the present application. Specifically, in this embodiment, the first device is an FPGA, the second device is an FPGA lower device, and the output PAD (output PAD S) to be tested of the FPGA is connected to the input to be tested of the FPGA lower device. Test connectivity to PAD (input PAD D).

Specifically, the boundary scan test is realized by the following steps.
S10, set the FPGA to test mode via the JTAG daisy chain, edit the user logic functions to connect the input PAD H to the output PAD S, and provide a bypass circuit. Here, PAD H is the first multiplex or general purpose PAD of the boundary scan chain of the FPGA.
S20, loading a test command to test the connectivity from the FPGA output PAD S to the FPGA lower device input PAD D;
S30, input test excitation, input INTEST command, move to SHIFT-DR state, move test excitation to boundary scan register of input PAD H, then move to UPDATE-DR state, input test excitation Updates the boundary scan resist of PAD H, moves to the CAPTURE-DR state, takes the test excitation into the boundary scan register of the output PAD S by the bypass circuit, moves to the UPDATE-DR state, and transfers the test excitation to the output PAD S , enters the EXTEST command, enters the CAPTURE-DR state, and captures the test excitation into the boundary scan register of input PADD.
S40, transition to SHIFT-DR state, remove by TDO of FPGA lower device,
S50: Response analysis and failure diagnosis.

In this embodiment, the user logic function is edited to connect the input PAD H to the output PAD S, and a bypass circuit is provided so that the PADs that do not need to be tested are removed by the bypass circuit. This embodiment shortens the boundary scan chain, realizes faster and more flexible boundary scan testing, and improves test efficiency. Additionally, test PADs can be flexibly placed without the need to test all PADs.

(Example 5)
FIG. 6 is a boundary scan test method according to Example 5 of the present application. Specifically, in this embodiment, the first device is an FPGA lower device, the second device is an FPGA upper device, and the output PAD (output PAD S) to be tested of the FPGA lower device is connected to the FPGA upper device. Test connectivity to the input PAD to be tested (input PAD D).

Specifically, the boundary scan test is realized by the following steps.
S10, set the FPGA to test mode via the JTAG daisy chain, edit the user logic functions to connect the input PAD H to the output PADE E, and provide a bypass circuit. Here, PAD H is the first multiplex or general purpose PAD of the FPGA's boundary scan chain, and PADE E is the last multiplex or general purpose PAD of the FPGA's boundary scan chain.
S20, loading a test command to test the connectivity from the FPGA lower device output PAD S to the FPGA upper device input PAD D;
S30, input test excitation, input INTEST command, move to SHIFT-DR state, move test excitation to boundary scan register of input PAD H, then move to UPDATE-DR state, input test excitation Updates the boundary scan resist of PAD H, moves to the CAPTURE-DR state, takes the test excitation into the boundary scan register of the output PAD E by the bypass circuit, moves to the SHIFT-DR state, and transfers the test excitation to the output PAD S After moving to the boundary-scan register of the output PAD, go to the UPDATE-DR state, update the test excitation to the boundary-scan register of the output PAD S, enter the EXTEST command, go to the CAPTURE-DR state, and update the test excitation to the boundary-scan register of the output PAD S. Transfers the test excitation to the boundary scan register of input PAD D, moves to the SHIFT-DR state, moves the test excitation to the boundary scan register of input PAD H, transfers to the UPDATE-DR state, and transfers the test excitation to the boundary scan register of input PAD H. Update the boundary scan register, input the INTEST command, move to the CAPTURE-DR state, take the test excitation into the boundary scan register of the output PAD E by the bypass circuit,
S40, transition to SHIFT-DR state, remove test excitation by TDO of FPGA lower device;
S50: Response analysis and failure diagnosis.

In this embodiment, the user logic function is edited to connect the input PAD H to the output PAD E, and a bypass circuit is provided so that the PAD that does not need to be tested is removed by the bypass circuit. This embodiment shortens the boundary scan chain, realizes faster and more flexible boundary scan testing, and improves test efficiency. Additionally, test PADs can be flexibly placed without the need to test all PADs.

(Example 6)
FIG. 7 is a boundary scan test method according to Example 6 of the present application. Specifically, in this embodiment, the first device is an FPGA lower device, the second device is an FPGA, and the output PAD (output PAD S) to be tested of the FPGA lower device is connected to the input to be tested of the FPGA. Test connectivity to PAD (input PAD D).

Specifically, the boundary scan test is realized by the following steps.
S10, set the FPGA to test mode via the JTAG daisy chain and edit the user logic functions to connect input PAD H to output PAD E and connect input PAD D to output PAD E1. where PAD H is the first multiplex or general purpose PAD in the FPGA's boundary scan chain, PAD E is the last multiplex or general purpose PAD in the FPGA's boundary scan chain, and PAD E1 is the first multiplex or general purpose PAD in the FPGA's boundary scan chain. It is the penultimate multiplex or general purpose PAD in the dally scan chain.
S20, loading a test command to test the connectivity from the FPGA lower device output PAD S to the FPGA input PAD D;
S30, input test excitation, input INTEST command, move to SHIFT-DR state, move test excitation to boundary scan register of input PAD H, then move to UPDATE-DR state, input test excitation Updates the boundary scan resist of PAD H, moves to the CAPTURE-DR state, takes the test excitation into the boundary scan register of the output PAD E by the bypass circuit, moves to the SHIFT-DR state, and transfers the test excitation to the output PAD S After moving to the boundary-scan register of the output PAD, enter the UPDATE-DR state, update the test excitation to the boundary-scan register of the output PAD S, enter the EXTEST command, enter the CAPTURE-DR state, and update the test excitation to the boundary-scan register of the output PAD S. Loads into the boundary scan register of input PAD D, moves to UPDATE-DR state, updates test excitation to boundary scan register of input PAD D, inputs INTEST command, moves to CAPTURE-DR state, bypass circuit capture the test excitation into the boundary scan register of output PAD E1 by
S40, transition to SHIFT-DR state, remove test excitation by TDO of lower device;
S50: Response analysis and failure diagnosis.

This embodiment uses a bypass circuit to remove PADs that do not need to be tested by editing the user logic function to connect input PAD H to output PAD E and connect input PAD D to output PAD E1. This embodiment shortens the boundary scan chain, realizes faster and more flexible boundary scan testing, and improves test efficiency. Additionally, test PADs can be flexibly placed without the need to test all PADs.

Although the above examples specifically and in detail describe preferred embodiments of the present application, it should be understood that they are not intended to limit the scope of the present application. It should be noted that various modifications and improvements made by those skilled in the art without departing from the concept of the present application are all included in the protection scope of the present application. Therefore, the scope of protection of this application shall be subject to the claims.

Claims (7)

A boundary scan test method for testing connectivity from a first device to a second device PAD, comprising:
step S10 of setting the FPGA in test mode and editing user logic functions to provide a bypass circuit;
step S20 of loading a test command for testing connectivity from the output PAD to be tested to the input PAD to be tested;
step S30 of inputting a test excitation;
step S40 of removing the test excitation by a TDO of the FPGA sub-device;
Step S50 of performing response analysis and fault diagnosis;
A boundary scan test method comprising: The first device is the FPGA host device, the second device is the FPGA, the output PAD of the test target is the output PAD of the test target of the FPGA host device, and the input PAD of the test target is the input PAD to be tested in the FPGA,
The step S10 involves the user setting the FPGA to test mode via a JTAG daisy chain and connecting the input PAD to be tested of the FPGA to the last multiplexing or general purpose PAD of the boundary scan chain of the FPGA. including editing logical functions;
The step S30 includes inputting a test excitation and inputting an EXTEST command to move and update the test excitation to the boundary scan register of the output PAD to be tested of the FPGA host device; updating the boundary scan register of the input PAD under test of the FPGA, entering an INTEST command and moving the test excitation by a bypass circuit to the last multiplexed or general purpose PAD of the boundary scan chain of the FPGA. ,
The boundary scan test method according to claim 1, characterized in that: The first device is the FPGA upper device, the second device is the FPGA lower device, the output PAD of the test target is the output PAD of the test target of the FPGA upper device, and the second device is the FPGA lower device. The input PAD is an input PAD to be tested for the FPGA lower device;
The step S30 includes inputting a test excitation, inputting an EXTEST command, moving and updating the test excitation to the boundary scan register of the output PAD to be tested of the FPGA upper device, and moving the test excitation to the boundary scan register of the output PAD to be tested of the FPGA upper device. updating the input PAD of the device being tested;
The boundary scan test method according to claim 1, characterized in that: The first device is the FPGA, the second device is the FPGA host device, the output PAD of the test target is the output PAD of the FPGA, and the input PAD of the test target is the FPGA. It is an input PAD for FPGA upper device testing,
The step S10 sets the FPGA to a test mode via a JTAG daisy chain, and connects the first multiplexed or general-purpose PAD of the boundary scan chain of the FPGA to the output PAD to be tested of the FPGA and the bounds of the FPGA. editing the user logic function of connecting to the last multiplex or general purpose PAD of the dally scan chain;
The step S30 includes inputting a test excitation, inputting an INTEST command, and moving and updating the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general-purpose PAD; updating the test excitation to the boundary scan register of the output PAD to be tested of the FPGA by a bypass circuit, inputting an EXTEST command and moving the test excitation to the boundary scan register of the input PAD of the FPGA upper device to be tested; moving the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general purpose PAD; entering an INTEST command and moving the test excitation to the bounce of the FPGA by a bypass circuit; including multiplexing the end of a dally scan chain or incorporating it into a generic PAD;
The boundary scan test method according to claim 1, characterized in that: The first device is the FPGA, the second device is the FPGA lower device, the output PAD of the test target is the output PAD of the FPGA, and the input PAD of the test target is the FPGA lower device. It is an input PAD for FPGA lower device testing,
The step S10 includes setting the FPGA in a test mode via a JTAG daisy chain and connecting a first multiplexed or general-purpose PAD of a boundary scan chain of the FPGA to an output PAD of the FPGA to be tested. including editing user logic functions;
The step S30 includes inputting a test excitation, inputting an INTEST command, moving the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary register of a general-purpose PAD, and updating the test excitation. updating an excitation to a boundary scan register of an output PAD under test of the FPGA by a bypass circuit; inputting an EXTEST command to incorporate the test excitation into an input PAD of the FPGA sub-device under test;
The boundary scan test method according to claim 1, characterized in that: The first device is the FPGA lower device, the second device is the FPGA upper device, the test target output PAD is the test target output PAD of the FPGA lower device, and the test target output PAD is the test target output PAD of the FPGA lower device. The input PAD is the input PAD to be tested for the FPGA upper-level device,
Said step S10 sets the FPGA to a test mode via a JTAG daisy chain, and connects the first multiplex or general purpose PAD of the boundary scan chain of said FPGA to the last multiplex or of the boundary scan chain of said FPGA. including editing a user logic function to connect to a generic PAD;
The step S30 includes inputting a test excitation, inputting an INTEST command, and moving and updating the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general-purpose PAD; incorporating a test excitation into a final multiplex of a boundary scan chain of said FPGA or a boundary scan register of a general purpose PAD by a bypass circuit; moving said test excitation to an output PAD under test of said FPGA sub-device for updating; , inputting an EXTEST command to capture the test excitation into a boundary scan register of an input PAD of the FPGA upper device under test; moving to and updating a boundary scan register, entering an INTEST command and incorporating the test excitation into the last multiplex of the boundary scan chain of the FPGA or the boundary scan register of a general purpose PAD by a bypass circuit;
The boundary scan test method according to claim 1, characterized in that: The first device is the FPGA lower device, the second device is the FPGA, the output PAD of the test target is the output PAD of the FPGA lower device, and the input PAD of the test target is the output PAD of the FPGA lower device. is the input PAD to be tested in the FPGA,
Said step S10 sets the FPGA to a test mode via a JTAG daisy chain, and connects the first multiplex or general purpose PAD of the boundary scan chain of said FPGA to the last multiplex or of the boundary scan chain of said FPGA. editing a user logic function to connect to a general purpose PAD and connect an input PAD under test of the FPGA to a second multiplexing or general purpose PAD from the end of a boundary scan chain of the FPGA;
Step S30 includes inputting a test excitation, inputting an INTEST command to move and update the test excitation to a first multiplex of a boundary scan chain of the FPGA or a boundary scan register of a general purpose PAD; incorporating the test excitation into the last multiplexed or general-purpose PAD of a boundary scan chain of the FPGA by a bypass circuit; moving and updating the test excitation into a boundary scan register of the output PAD under test of the FPGA sub-device; , inputting an EXTEST command to incorporate and update the test excitation into a boundary scan register of an input PAD under test of the FPGA; inputting an INTEST command to multiplex the test excitation into the penultimate multiplex of the FPGA; or including importing into a general-purpose PAD boundary scan device,
The boundary scan test method according to claim 1, characterized in that: