CN100365584C

CN100365584C - Method and apparatus for realizing boundary Scanning test

Info

Publication number: CN100365584C
Application number: CNB031439063A
Authority: CN
Inventors: 王�华
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2003-07-28
Filing date: 2003-07-28
Publication date: 2008-01-30
Anticipated expiration: 2023-07-28
Also published as: CN1577284A

Abstract

The present invention discloses a method for realizing a boundary scan test. The method tests by defining a specific data structure and repeatedly utilizing a group of 16-bit test mode selection sequences, and greatly decreases test data amount. If the boundary scan test is realized by the EPLD logic of Altera, macro units do not exceed 128; hardware resources can be fully saved. The present invention also discloses a boundary scan test bus controller.

Description

A kind of implementation method of boundary scan testing and device

Technical field

The present invention relates to measuring technology, particularly a kind of implementation method of boundary scan testing and device.

Background technology

In boundary scanning device, the input and output pin that each is important has all increased a multiduty storage unit, is called as boundary scan cell.Boundary scan cell on the input pin is called input block, the boundary scan cell on the output pin is called output unit, and input and output are internal logics of relative device.In boundary scanning device, boundary scan cell is organized into the shift register of parallel input PI (Paralell Input) and line output PO (Paralell Output), as shown in Figure 1.Parallel input (Capture) operation makes the signal value on the device input pin, is loaded in the input block; The value of device inside logic is loaded in the output unit.And line output (Update) operation, the value in the output unit is delivered on the output pin of device; Value in the input block is delivered to device inside in logic.

Fig. 2 is a kind of common boundary scan cell, is referred to as BC_1 (Boundary-Scan Cell).Value in the boundary scan cell can also be shifted serially, from the input pin TDI of device special use, to the special-purpose output pin TDO end of device.Test clock is from the special-purpose input pin TCK input of another of device, and operational mode is come Serial Control by the special-purpose input pin TMS of device.Chip boundary sweep test structure such as Fig. 3 of the suggestion of JTAG tissue wherein comprise following content:

1, four special test pins, test data input TDI (Test Data In), test data output TDO (Test Data Out), test pattern is selected TMS (Test Mode Select) and test clock TCK (Test Clock), an optional test reset pin TRST (Test Reset).These test pin are referred to as test channel mouth TAP (Test Access Port) together.

2, on each important input and output pin of device a boundary scan cell is arranged all, inside connects into the boundary scan register (Boundary Scan) of serial.

3, control the TAP finite state machine by input signal TCK, TMS and TRST.

4, the order register (register except that order register is referred to as data register) of a N (N＞=2) position.

5, straight-through (Bypass) register of one 1.

6, optional 32 identification code registers are used for keeping a permanent device identification code.

The TAP controller, according to the command code in the order register, translation instruction when Update_IR.Different registers is chosen in different instructions, and behind the command decoder, TDI is serially connected to selected register to TDO.

The pressure test command of JTAG tissue definition is as follows:

1, boundary scan register is chosen in external testing (Extest) instruction, and order code is complete 0.

2, straight-through register is chosen in straight-through (Bypass) instruction, and order code is complete 1.

3, boundary scan register is chosen in prepackage/sampling (Preload/Sample) instruction, and order code is stipulated.What Fig. 4 represented is 16 state machines of TAP controller, and the numeral outside the TAP state box is the value of TMS.The state of TAP controller changes at the rising edge of TCK, and the output valve of controller changes at the negative edge of TCK.As we can see from the figure, 6 steady state (SS)s are arranged in 16 state machines (when TMS is constant, state machine state is constant): test logic reset (Test_Logic_Reset), sky closes (Run_Test_Idle), instruction shift (Shift_IR), data shift (Shift_DR), instruction shift suspend (Pause_IR) and data shift suspends (Pause_DR).

The TAP controller, when power-up initializing and TRST=0, state is Test_Logic_Reset, when TMS remained 1 (default value), state machine state remained unchanged.In addition, no matter what state state machine is in, and keeping TMS be height, import continuous 5 tck clocks after, state machine can both be got back to the Test_Logic_Reset state.Under the Test_Logic_Reset state, the register of choosing is that straight-through register or identification code register (have the identification code register as device, then choose the identification code register; As there is not the identification code register then to choose straight-through register).Under the control of TMS and TCK, instruction can be moved into order register (selecting the path, right side among Fig. 4), when update instruction (Update_IR), instruction will be decoded, can choose corresponding data register simultaneously.At this moment, TMS and TCK control state machine are walked the path (without Test_Logic_Reset) on Fig. 4 left side, data can be moved into from TDI, and original data shift out from TDO in the data register simultaneously.

Fig. 5 is the ultimate principle of jtag test.The JTAG chain of being made up of 4 devices among the figure, TCK and TMS are delivered on each device, and like this, the TAP state machine of each device is synchronous operation.TDI receives on upper right first device U1, and its TDO output is connected to the TDI input of next device U2, and 4 devices are linked to be a serial chain, and the output of last U4 is connected to TDO.

Like this, just instruction and test data can be delivered on each device serially, the signal annexation of each device is tested.

In the JTAG chain that Fig. 5 connects into, suppose that the command register of all devices is 2, the boundary scan cell of each device pin is 1, and the device top is an input pin, and the below is an output pin.If the annexation of the O1 of test component U3 output and the I3 input of device U2, can allow the O1 pin of U3, export high level and low level respectively, in the enterprising detection of the I3 of U2.The specific implementation step, from Test_Logic_Reset, control TMS, make the TAP state of all devices all enter Shift_IR, two devices of U1 and U4 move into the Bypass instruction on the chain, and two devices of U2 and U3 move into Extest external testing command instruction, data sequence is as follows, and X is an arbitrary value:

TMS 01100 00000001 10

TDI XXXXX 11000011 XX

Above TMS and TDI data, after moving into device under the control of tck clock, U1 and the U4 straight-through instruction of having packed into, U2 and the U3 external testing instruction of having packed into.All devices all are in the Run_Test_Idle state.

Control TMS then, make the TAP state of all devices enter into Shift_DR, move into test data (because U1 and U4 device are Bypass, be shifted after 21 times, TDI data of Yi Ruing at first arrive the scanning element of last pin of U3 device), the data sequence of TDI and TMS is as follows:

TMS 100 000000000000000000001 10

TDI XXX 11111XXXXX11111XXXXXX XX

When covering top state, the TAP state of all devices is in Run_Test_Idle again.But through new data (Updata_DR) state more the time, the value 1 of the 8th TDI will be exported from the O1 pin of U3 from left to right.

Above twice boundary scan cell mobile data the time, all do not pay close attention to the output of TDO, at every turn from TDI input data in device, also from the TDO output data of device.When entering Shift_DR from the Run_Test_Idle state once more, the middle data (Capture_DR) of catching can be packed the value on the input pin pin in the shift register.Concerning the I3 pin of device U2, when carrying out Capture_DR, the O1 output valve of U3 can be caught in the shift register, when then entering into Shift_DR, the data that shift out are as follows:

TMS 100 000000000000000000001 10

TDO XXX XXXXXXXXXXXXXXXXXX1XX XX

TDI XXX XXXXXXXXXXXXXXXXXXXXX XX

Because the I3 of U2 comes the 19th (beginning counting from TDO) of scan chain, can be shifted out (the TDO value of shifting out the when front has 3 TAP to walk state machine) so be worth 1 in the time of the 22nd of TDO data.In like manner can allow O1 export 0, adopt back 0 from I3.

It more than is the ultimate principle of boundary scan testing.Be used for producing and the device or the system of these boundary scan signals (TRST, TCK, TMS, TDI and TDO) of sampling are called test bus controller TBC (Test Bus Control).

Can see that in test sample if more boundary scan cell is arranged on the scan chain, amount of test data is big (TMS, TDI and TDO) quite; If wish that the annexation of test is many more, the data volume of test is also big more.Therefore, how the tested tissue data also are emphasis of boundary scan testing.

At present, there are a lot of producers and company that oneself boundary scan testing bus controller is all arranged, as the LVT8980 of TI company, the SCANSTA101 of NS company etc., in order to the JATG test bus of the system-level or single-plate grade of controlling a product, to realize structured testing to product and veneer.

For the test data of boundary scan, what the industry application was more is a kind of file of the SVF of being referred to as form, and it is a kind of text, comes presentation directives and corresponding test data with text.Therefore, the file data amount of this form is bigger.

NS has a kind of file of EVF form, be aim at the said firm SCAN series of tests bus controller (SCANPSC100, SCANSTA101) and the design.The data volume of this file layout is slightly littler than SVF, but needs special hardware supported.

Altera corp has designed a kind of Jam interpreter for realizing the loading of its programming device.Boundary scan data can be deposited with compressed format, and data volume is less.But this data file can not staging treating.Big depositing still of data need take more resource.

Industry also has some producers and supplier that oneself language and interpreter are arranged, but all needs special-purpose software or hardware to support usually, explains the boundary scan testing order.And the data volume of test data is all bigger, and the resource that takies is more.

Summary of the invention

The invention provides a kind of implementation method and device of boundary scan testing, to solve in the existing measuring technology because of needing deal with data to cause taking the too many shortcoming of resource too much.

Implementation of the present invention:

A kind of implementation method of boundary scan testing, this method cooperates by terminal, test bus controller tests boundary scanning device, described terminal provides the boundary scan testing data to test bus controller, described test bus controller provides test data input data and test pattern to select to boundary scanning device, comprises the steps:

A, terminal are selected shift register sequential machine according to the order in the boundary scan testing data with test vector counter, scan chain length register and test pattern that the test vector number in these boundary scan testing data, scan chain length and test pattern select sequence to write test bus controller respectively;

B, test clock control test bus controller state machine write the scan chain length counter with the scan chain length value, and test pattern is selected the value of shift register sequential machine select the head of shift register sequential machine to shift out by turn from test module, this value that will shift out simultaneously turns back to described test module and selects the afterbody of shift register sequential machine to requeue to form ring shift;

C, when test pattern selects the 8th displacement of sequence to go out, detect the scan chain length counter; Data do not shift out if the value representation of scan chain length counter has the test data input, then carry out step e; Otherwise test pattern selects shift register sequential machine to stop displacement, and to keep the test pattern selective value be that the 8th place value is constant, and described terminal is imported data with test data and write test data input shift register in the described test bus controller;

D, test bus controller state machine shift out the data in the described test data input shift register under test clock control, and whenever shift out one the scan chain length counter successively decreased, be to shift out last bit data at 1 o'clock up to scan chain length;

E, continuation ring shift test pattern are selected shift register sequential machine, and when shifting out the 16th checkout vector count device, if the value of test vector counter shows all test vectors and has all transmitted, then the test bus controller state machine stops test, otherwise the value of test vector counter is subtracted 1 and carry out step B.

According to said method:

Whether carry out step D Pretesting bus controller state machine checkout data input shift register has data, and if do not have data would stop test clock and etc. data to be written.

Among the step C, write test data input shift register in the test bus controller, comprise also among the step D that then terminal reads the data in the test data Output Shift Register if described terminal is imported data with test data.

Described boundary scan testing data are made up of the data packet head and the test data input/test data output data of a plurality of double bytes, wherein this data packet head has a plurality of double bytes, comprises order/status word, special control word, test vector number, scan chain length and test pattern selection sequence in this data packet head.

Test data input data are corresponding with test vector number and scan chain length, and its total length is 16 multiple.

A kind of boundary scan testing bus controller, it comprises:

Cpu bus is by interface and terminal interaction information;

The test bus controller control state machine is used for the state of test bus control is controlled;

The test vector counter is connected with the test bus controller control state machine with cpu bus and links to each other;

Scan chain length value register is connected with cpu bus, is used for the number of scanning element on the memory scanning chain;

The scan chain length counter is connected with the sweep length value register by the CPU general line, is connected with the test bus controller control state machine by signal wire;

Test pattern is selected shift register sequential machine, is connected with the test bus controller control state machine with cpu bus respectively;

The test data input shift register is connected with the test bus controller control state machine with the CPU general line respectively;

The test data Output Shift Register is connected with cpu bus;

Clock provides work clock to aforesaid counter and register.

The present invention has following advantage:

1, test bus controller does not need to explain the various command of boundary scan.

2, because test pattern is selected reusing of (TMS) sequence, reduced data quantity transmitted, reduced the holding time of CPU simultaneously.

3, software and hardware realizes that succinctly it is few to take resource.Adopt the data of specific format of the present invention, almost can transmit test data fully pellucidly.The software and hardware resources that needs all seldom.If with the EPLD logic realization of Altera, macroelement will be no more than 128.Can fully save hardware resource.

Description of drawings

Fig. 1 is the boundary scan principle schematic;

Fig. 2 is a BC-1 scanning element structural representation;

Fig. 3 is a chip JTAG structural representation;

Fig. 4 is the test access port controller view;

Fig. 5 is jtag test ultimate principle figure;

Fig. 6 is a boundary scan testing bus controller schematic diagram of the present invention;

Fig. 7 is a process flow diagram of the present invention.

Embodiment

From the ultimate principle test sample of boundary scan testing, can find out the rule (the scape technology of passing away) of test data, when carrying out state transition (the test pattern selective values on delegation both sides), test data input (TDI) and test data output (TDO) are nonsensical; And when data shift (Shift_IR and Shift_DR state) (the TMS value of an interline), (TMS) is regular for the test pattern selective value, after promptly entering the data shift state, the test pattern selective value remains unchanged always, only just begins to change when leaving the data shift state.No matter in addition, can see from the state machine of Fig. 4, be to carry out instruction shift or data shift, can not surpass 8 test pattern selective values at most from a steady state (SS) to another steady state (SS).

Select sequences to come the trend of control state machine with 16 test patterns, wherein the 8th and the 16th test pattern selective value make state machine be in steady state (SS).For the operation that moves into instruction, the sequence of TMS is as follows:

1------8 9-----16

TMS 1101100011000000

At the 7th TMS place, the TAP state machine enters the Shift_IR state.The 8th TMS place, the FDI data begin to move into scan chain (IR register), and in the end one digit number is according to before the immigration TDI, and TMS will keep the 8th value constant always.When in the end TDI data moved into, the 9th of TMS moved into simultaneously, and with the 10th to the 15th state transition of controlling TAP of TMS, entered Run_Test_Idle.The 16th of TMS, may command TAP state machine is waited at this.

By above principle as can be known,, only just can finish, can significantly reduce the data volume of test with 16 bit test mode selection data for arbitrary instruction scan operation and data scanning operation.As a secondary data (instruction) scanning migration process is called a vector, so, in the actual boundary sweep test, what have that a lot of test vectors use is that identical test pattern is selected sequence, as return Run_Test_Idle from Run_Test_Idle to Shift_DR.An available like this counter is represented the length of scan chain, and the another one counter is represented the number of test vector.Use same test pattern to select sequence repeatedly, and do not need new test pattern to select data.

Based on above-mentioned principle, be the data volume that reduces the boundary scan testing data, the communications of being convenient to test data.Define a kind of boundary scan testing data of specific format, as shown in the table.

In proper order	Meaning		Explanation
	Meaning			15-8	7-0
	1	Keep		15-8	7-0	Order/state	Biography is to the order that is of TBC direction, and reverse is state
2	1	Keep	Keep			Order/state
2	3	Keep
4	3	Keep		Special control	Keep
4	5	The TMS control sequence		Special control	Keep
6	5	The TMS control sequence		Scan chain length
6	7	The test vector number		Scan chain length
8	7	The test vector number		Keep
8	9	The TDI/TDO data		Keep		That transmit to TBC is TDI, sends into scan chain; Be reversed TDO, export from scan chain.
...	9	The TDI/TDO data
...	n	The TDI/TDO data

In the table, the front is the data packet head of 8 double words, and what follow later is test data.Definition according to order can not have test data yet.Wherein:

Order/state: the user can define voluntarily, two kinds of main orders are for sending data (promptly not needing to receive the TDO on the scan chain) and receiving and dispatching two kinds of data (promptly in TDI input data, the TDO output data on the reception scan chain) on the scan chain simultaneously to scan chain.Also other control command of definable is explained by software or hardware.In this case, the parameter of back can be inoperative.Replying when state is used for oppositely transmitting.When not needing oppositely to transmit TDO, a reply data packet header.

TMS control sequence: the TMS sequence of introducing previously.

Special control: transmit some controls of this scan operation, the user can define voluntarily.Explain by software or hardware.

Scan chain length: the number of scan chain coboundary scanning element.

The test vector number: the number of times of reusing the TMS sequence subtracts one, and promptly when only using one time, this value is 0.

TDI data: the TDI data corresponding with test vector number and scan chain length.For each test vector (promptly carry out a data shift or instruction shift), when calculating total TDI data length, length should be taken as 16 multiple.If that is: the scanning chain length is 21, then need to transmit the TDI data, and the TDI data of 16 of back less thaies are placed on the low level of TDI data (in snap 16 bit data 0) with two 16.If the test vector number is 3, then total TDI data are the 2*16*3 bit data, transmit with 6 16.Therefore, the n=in the table 1 (scan chain length/16+ remainder) * test vector number, if scan chain length can be divided exactly by 16 in the formula, remainder is 0, otherwise remainder is 1.

Keep: keep standby.The user can be according to requirement definition and the explanation of oneself.

Present embodiment utilizes above-mentioned specific boundary scan testing data, be connected with boundary scanning device by terminal (as functionally similar devices such as terminal or embedded type CPUs), test bus controller boundary scanning device is tested, terminal provides the boundary scan testing data to test bus controller, and bus controller provides test data input data and test pattern to select to boundary scanning device.

Consult Fig. 6, comprise with the test bus controller of logic realization:

Cpu bus is by interface and terminal interaction information;

The test bus controller state machine is used to control the state transition of test bus control;

16 test vector counter is connected with control state machine with cpu bus and links to each other;

16 scan chain length counter is connected with cpu bus, is used for the number of scanning element is counted;

16 scan chain length value register is connected with bus, is used for the number of scanning element on the memory scanning chain;

16 test pattern is selected shift register sequential machine, is connected with control state machine with bus respectively;

8 or 16 s' test data input shift register is connected with control state machine with general line respectively;

8 or 16 s' test data Output Shift Register is connected with described bus;

Clock provides work clock to aforesaid counter and register spy.

Test terminal or embedded type CPU be in advance according to the command format of the description of table one, preset test vector counter, scan chain length counter and the TMS sequential register in the test bus controller after, start test.State machine in the test bus controller moves the state of oneself according to the prevalue of front.

If the EPLD with Altera realizes that macroelement will be no more than 128.

Consult Fig. 6, Fig. 7, the step of testing is as follows:

Step 10: the boundary scan testing data that produce specific format offer terminal.Comprise order, TMS control sequence, scan chain length, test vector number and TDI data in these data.Order in this example is for sending data to scan chain.

Step 20: terminal makes an explanation to the order in the scan test data of border, and according to sending test vector counter, scan chain length value register and the TSM shift register sequential machine that data command writes the test vector number in the boundary scan testing data, scan chain length value and TSM sequence respectively test bus controller to scan chain.

Step 30: terminal control test start-stop control signal, starting test.

This moment TBC controller state machine, under the control of work clock, with the scan chain length value scan chain length counter of packing into, and control TSM shift register sequential machine displacement, the TMS value is shifted out in decline at each test clock (TCK), the value that TMS the is shifted out afterbody that turns back to the TMS sequential register requeues simultaneously, promptly forms ring shift.

Step 40: after shifting out preceding 7 TMS values, the 8th TMS value sent, simultaneously, detected whether the scan chain length counter is 0.

If be 0, showing does not need the TDI data shift, just does TAP state transition, forwards step 60 to.

If the scan chain length counter is not 0, then showing has the TDI data to shift out, and TBC controller state machine will detect and have no datat to wait in the TDI shift register to shift out this moment, as not have, and the TCK that then can stop exports, the waiting for CPU TDI data of packing into.

Step 50: but terminal duplicate detection TDI shift register write data sign writes TDI data (2n byte).If need sampling TDO data, then also need from the TDO shift register, to read the data that sampling is returned.

The machine examination of TBC controller state at the TCK negative edge, is shifted out the TDI data after measuring and having the data wait to shift out in the TDI shift register.Simultaneously in TCK rising edge sampling TDO data and displacement.Whenever shift out one, the scan chain length counter is subtracted 1.This moment, TMS kept the value of the 8th TMS in the TSM sequence always.When the scan chain length counter is reduced to 1, shift out last TDI of this test vector.

Step 60: back 8 the TMS values that continue to shift out the TMS sequence.

Step 70: when shifting out last TMS value of TMS sequence (the 16th time), whether checkout vector count device is 0.

If be 0, show that all test vectors have all transmitted, the TBC controller state machine TCK that stops waits for stopping test signal.

If be not 0, show that test vector has not all transmitted, and turns back to step 30.Because the TMS shift register of this moment ring shift is altogether crossed 16 times, has got back to the initial value states that initial CPU packs into.Turn back to the 30th step scan chain length counter of can again the scan chain length value being packed into.

Step 80: terminal control test start-stop control signal stops test.

TBC controller state machine is got back to original state after receiving and stopping test signal.

By as can be seen above, utilize table one definition data structure, almost can transmit test data fully pellucidly.The software and hardware resources that needs all seldom.If with the EPLD logic realization of Altera, macroelement will be no more than 128.Can fully save hardware resource.Because reusing of TMS sequence reduced amount of test data, also reduce the operation of CPU simultaneously in addition, can reduce the holding time of CPU.

Claims

1. the implementation method of a boundary scan testing, this method cooperates by terminal, test bus controller tests boundary scanning device, described terminal provides the boundary scan testing data to test bus controller, and described test bus controller provides test data input data and test pattern to select to boundary scanning device; It is characterized in that the method comprising the steps of:

D, test bus controller state machine shift out the data in the described test data input shift register under test clock control, and whenever shift out one the scan chain length counter subtracted 1, be to shift out last bit data at 1 o'clock up to scan chain length;

2. the method for claim 1 is characterized in that, whether carry out step D Pretesting bus controller state machine checkout data input shift register has data, and if do not have data would stop test clock and etc. data to be written.

3. the method for claim 1, it is characterized in that, among the step C, write test data input shift register in the test bus controller, comprise also among the step D that then terminal reads the data in the test data Output Shift Register if described terminal is imported data with test data.

4. as claim 1,2 or 3 described methods, it is characterized in that, described boundary scan testing data are made up of data packet head and test data input/test data output data, wherein this data packet head has a plurality of double bytes, comprises order/status word, special control word, test vector number, scan chain length and test pattern selection sequence in this data packet head.

5. method as claimed in claim 4 is characterized in that, test data input data are corresponding with test vector number and scan chain length, and its total length is 16 multiple.

6. method as claimed in claim 4 is characterized in that, also comprises reserve bytes in the described data packet head.

7. method as claimed in claim 4 is characterized in that, order/state and special control word account for a byte respectively, and test vector number, scan chain length, test pattern select sequence and one group of test data input/test data output data to account for two bytes respectively.

8. a boundary scan testing bus controller is characterized in that, comprising:

Cpu bus is by interface and terminal interaction information;

The test bus controller state machine is used for the state of test bus control is controlled;

The test vector counter is connected with the test bus controller state machine with cpu bus and links to each other;

The scan chain length counter is connected with the sweep length value register by cpu bus, is connected with the test bus controller state machine by signal wire;

Test pattern is selected shift register sequential machine, is connected with the test bus controller state machine with cpu bus respectively;

The test data input shift register is connected with the test bus controller state machine with cpu bus respectively;

The test data Output Shift Register is connected with described cpu bus;

Clock provides work clock to aforesaid counter and register.

9. test bus controller as claimed in claim 8 is characterized in that, described test vector counter, scan chain length value register, scan chain length counter and test pattern select shift register sequential machine to be 16 bits.

10. test bus controller as claimed in claim 8 or 9 is characterized in that described test data input shift register and test data Output Shift Register are 8 bits or 16 bits.

11. test bus controller as claimed in claim 8 is characterized in that, described test bus controller state machine is 16 state machines.