CN103678068B - A kind of annular boundary scanning means and method - Google Patents
A kind of annular boundary scanning means and method Download PDFInfo
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- CN103678068B CN103678068B CN201310718369.1A CN201310718369A CN103678068B CN 103678068 B CN103678068 B CN 103678068B CN 201310718369 A CN201310718369 A CN 201310718369A CN 103678068 B CN103678068 B CN 103678068B
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Abstract
The present invention provides a kind of annular boundary scanning means, and including controller, multiple input shift register and multiple Output Shift Register, controller, for judging whether to external chip input be input data；If input is input data, input data are exported to chip by controller, and effective result that chip is obtained after processing is sent to Output Shift Register；And invalid data is automatically exported to chip by controller, invalid data is directly sent to Output Shift Register by chip, and this invalid data is effective result extrusion of the original storage in Output Shift Register, and is sent to emulator and/or controller.The present invention solves the technical problem that input/output shift register is uniformly controlled scheduling, solves the technical problem needing that Output Shift Register is manually entered invalid data.
Description
Technical field
The present invention relates to the hardware debugging field of chip, particularly relate to a kind of annular boundary scanning means and side
Method.
Background technology
Boundary-scan test technology (Enhanced Joint Test Action Group, EJTAG) is standard
Test access port and boundary scan architecture, be usually used in chip hardware debugging.
In EJTAG hardware circuit design, boundary scan is an important ingredient.Border is swept
Retouching is to increase a series of shift register on the input/output port of chip, and chip is debugged at EJTAG
Under state, emulator carrys out, by a series of shift registers, the work shape that control chip works or observes chip
State.Wherein Fig. 1 is that traditional EJTAG debugs system block diagram.
In FIG, debugging system controls emulator by the debugging software in computer, and emulator leads to
Cross the instruction that the debugging software received sends, be sent to the chip with EJTAG function through conversion,
EJTAG debugging is carried out with this.Chip with EJTAG function then sends by performing emulator
Instruction, is sent to EJTAG emulator the data returned, and EJTAG emulator resolves, and returns
Return to the debugging software in computer shows, thus complete an EJTAG debugging.
The scanning circuit of the border chain type of traditional chip with EJTAG function and emulator, often
Increasing a shift register on one port, each shift register controls end by one respectively
Control.When chip is properly functioning, control end can shield these shift registers, user it is believed that
Scanning circuit now is transparent.When chip is in EJTAG test state, each shift register
Be linked in whole chip, and by the serial input port of data, to chip internal input data and
Instruction carrys out control chip, and user can observe, from the serial output port of data, each number that chip returns
According to, so that it is determined that the state of chip.
But, traditional border chain type scanning circuit is due to the restriction of chain structure, and in scan chain, each moves
Bit register all has data, but cannot automatically export.If can only manually input at data serial input terminal
Data in Output Shift Register are moved out to data serial output port, then give by dry extraneous data
Emulator resolves.
Therefore, traditional border chain type scanning circuit, from the point of view of the hardware of system makes, which increases system
Hardware quantity, also have impact on system perform the time.And this traditional chain type scanning circuit there is also as
Lower shortcoming: instruction is long for input time, and emulator utilization ratio is low, debugging software realizes complexity.
Summary of the invention
The technical problem to be solved in the present invention is: solve and input/output shift register is unified control
The technical problem of system scheduling, solve further need Output Shift Register is manually entered invalid
The technical problem of data；With and improve EJTAG emulator instruction conversion speed；Thus promote
The operating accuracy of whole EJTG debugging system and efficiency；Reduce the cost making hardware circuit.
In order to solve the problems referred to above, the invention provides a kind of annular boundary scanning means include controller,
Multiple input shift registers and multiple Output Shift Register,
Described controller, for judging outwards according to unified clock signal and scanning annular control bit
Whether portion's chip input is input data；
If input be described input data, controller described input data step-by-step is in turn exported to
Described input shift register, described input data are exported to chip, core by described input shift register
Described input data are carried out processing the effective result of acquisition by sheet, and described effective result are sent
To Output Shift Register；And
Controller by invalid data step-by-step input successively to described input shift register, described input
Described invalid data is exported to chip by shift register, and chip does not process described invalid data directly by institute
Stating invalid data and be sent to Output Shift Register, Output Shift Register utilizes described invalidation result
Described effective result in described Output Shift Register is extruded, and is sent to emulator and/or control
Device processed.
Preferably, described controller at least includes:
Data serial Output Shift Register, is used for receiving described clock signal；And by described invalid data
It is sent to data selector；
Data selector, for the scanning annular control bit according to state machine output, determines it is to select institute
State invalid data, or select the described input data from external emulator；
State machine, for generating described scan ring according to described clock signal and described Data Control position
Shape control bit controls the output of described data selector.
Preferably, described state machine at least includes data file and instruction file, wherein
Described data file at least includes: data displaced condition, exit chained record input state, data
Ring connection status and exit annular data input state；
Described instruction file at least includes: exit chain type instruction input state, instruction ring connection status and
Exit annular instruction input state.
Preferably, when described state machine performs described data ring connection status, described state machine is by described
Scanning annular control bit is sent to described data selector, and described data selector then selects described invalid number
According to and described invalid data is sent to described state machine.
Preferably, described state machine is by cyclically performing described data displaced condition, by described input number
According to or the input of described invalid data in chip.
Preferably, when described state machine performs described instruction ring connection status, described state machine is by described
Scanning annular control bit is sent to described data selector, and described data selector then selects described invalid finger
Order.
Preferably, described data Output Shift Register is further used for: be sent to by described invalid data
Described data selector.Such as, when invalid data is after chip, and this invalid data is not carried out by chip
Process.This invalid data is sent to data Output Shift Register by chip.These data output shift LD
Invalid data is sent to controller by device, i.e. data selector in controller receives this invalid data.
Preferably, the combination of described input shift register and described Output Shift Register at least includes: 8
Individual input shift register and 8 Output Shift Registers, 16 input shift registers and 16
Individual Output Shift Register, 32 input shift registers and 32 Output Shift Registers, 64
Input shift register and 64 Output Shift Registers.
Preferably, the combination of described input shift register and Output Shift Register at least include with down to
One of few: 8 Bit datas, 16 Bit datas, 32 Bit datas, 64 Bit datas.
The present invention also provides for a kind of annular boundary scan method, including:
Receive the input data from emulator；
Judge whether to chip input be described input data；
If being described input data to chip input, then by described input data step-by-step input successively
To input shift register；Described input data are exported to chip, core by described input shift register
Described input data are carried out processing the effective result of acquisition by sheet, and described effective result are sent
To Output Shift Register；By invalid data step-by-step input successively in described input shift register,
Described invalid data is exported to chip by described input shift register, and described invalid data is carried out by chip
Process and obtain invalidation result, and described invalidation result is sent to Output Shift Register, will
Described effective result extrusion in described Output Shift Register, and it is sent to emulator and/or control
Device.
Further, it is judged that whether to chip input is that described input data at least include:
Scan ring shape control bit is generated according to described clock signal and described Data Control position；
According to described scanning annular control bit, determine it is to select invalid data, or select from outside
The described input data of emulator.
Further, it at least includes that holding state machine generates described scanning annular control bit, wherein said shape
State machine at least includes data file and instruction file, wherein:
Described data file at least includes: data displaced condition, exit chained record input state, data
Ring connection status and exit annular data input state；
Described instruction file at least includes: exit chain type instruction input state, instruction ring connection status and
Exit annular instruction input state.
Further, when described state machine performs described data ring connection status, described state machine is by institute
Stating scanning annular control bit and be sent to described data selector, described data selector then selects described invalid
Described invalid data is also sent to described state machine by data.
Further, when described state machine performs described instruction ring connection status, described state machine is by institute
Stating scanning annular control bit and be sent to described data selector, described data selector then selects described invalid
Instruction.
In sum, by application the present invention provide annular boundary scanning means, solve to input/
Output Shift Register carries out being uniformly controlled the technical problem of scheduling, solves needs further and moves output
Bit register carries out being manually entered the technical problem of invalid data；With and improve EJTAG emulator
The speed of instruction conversion；Thus promote operating accuracy and the efficiency of whole EJTG debugging system；Reduce
Make the cost of hardware circuit.
Accompanying drawing explanation
Fig. 1 is that traditional EJTAG debugs system block diagram；
Fig. 2 is the schematic diagram of the annular boundary scanning means of the present invention；
Fig. 3 is the schematic diagram of the annular boundary scan method of the present invention；
Fig. 4 is the structural representation of the data flow operating procedure one of the annular boundary scanning means of the present invention
Figure；
Fig. 5 is the structural representation of the data flow operating procedure two of the annular boundary scanning means of the present invention
Figure；
Fig. 6 is the structural representation of the data flow operating procedure three of the annular boundary scanning means of the present invention
Figure；
Fig. 7 is the structural representation of the controller in the annular boundary scanning means of the present invention；
Fig. 8 is the state transition diagram of the annular EJTAG state machine of the present invention；
Fig. 9 is the state transition diagram of traditional chain structure EJTAG state machine.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing
Embodiments of the invention are described in detail.It should be noted that in the case of not conflicting, this Shen
Embodiment in please and the feature in embodiment can mutual combination in any.
Fig. 2 is the composition structural representation of the annular boundary scanning means of the present invention, as shown in Figure 2.Its
At least include controller, multiple input shift register and multiple Output Shift Register, wherein:
Controller, for judging to external core according to unified clock signal and scanning annular control bit
Sheet input is input data, or invalid data；If input is input data, controller is by defeated
Entering data step-by-step and in turn export to input shift register, input shift register will input data output
To chip, input data are carried out processing the effective result of acquisition by chip, and effective result are sent out
Give Output Shift Register；And
Controller, by invalid data step-by-step input successively to input shift register, inputs shift LD
Invalid data is exported to chip by device, and invalid data is carried out processing acquisition invalidation result by chip, and
Invalidation result is sent to Output Shift Register, and Output Shift Register utilizes invalidation result
Effective result in Output Shift Register is extruded, and is sent to emulator and/or controller.Excellent
Choosing, controller is kept apart chip with emulator, is uniformly controlled data serial input, clock, number
According to control bit and data serial input.When emulator needs to enter data to control chip to chip, control
The input of input data, by a unified clock and Data Control position, is posted by device processed to each input displacement
In storage.These input data are processed by chip.Send result to after process export shift LD
Device.Output Shift Register stores these data.Now, then invalid data is given core by controller again
Sheet, chip is returned to Output Shift Register after processing.At this moment, the output result of this invalid data can be upper
The result of the input data of secondary Output Shift Register storage is extruded, and therefore the result of these input data can
To select to be sent to emulator, it is also possible to select to be sent to controller.
Preferably, controller at least includes: data serial Output Shift Register, is used for receiving clock letter
Number；And invalid data is sent to data selector；Data selector, for according to state machine output
Scanning annular control bit, determines it is to select invalid data, or selects the input from external emulator
Data；State machine, for generating scan ring shape control bit according to clock signal and Data Control position
Control the output of data selector.Such as, controller is by data Serial output shift register, a number
According to selector and a state machine composition.Data serial Output Shift Register be responsible for depositing every time from
The data of scanning circuit Serial output as invalid data, then by data selector select be currently need from
Emulator serial input data is input to control chip execution corresponding operating in the middle of scanning circuit and needs for defeated
Enter invalid data the data of the Output Shift Register in scanning circuit are shifted out to give emulator solution
Analysis.After data selector chooses desired data, these data being sent in the middle of state machine module, state machine leads to
Oversampling clock coordinates with Data Control position, the annular control bit of output scanning simultaneously and the number of entrance scanning circuit
According to input.The initial value of wherein scanning annular control bit is 0, and chooses the serial input of data as sweeping
The data input of scanning circuit, after chip has performed first time operation, emulator is by controlling data control
Position processed and clock, the data selecting the next one to be input to scanning circuit be the data that send of emulator or
One invalid data.
Wherein, state machine at least includes data file and instruction file, and data file at least includes: data
Displaced condition, exit chained record input state, data ring connection status and exit annular data input
State；Instruction file at least includes: exits chain type instruction input state, instruction ring connection status and moves back
Go out annular instruction input state.Preferably, state machine has data file and instruction file.Data file
Include: select data entry mode state, data capture state, data displaced condition, exit chain type
Data input state, data ring connection status, exit annular data input state and more new data shape
State.Instruction file includes: select instruction input mode state, instruction trapped state, instruction shift shape
State, exit chain type instruction input state, instruction ring connection status, exit annular instruction input state, with
And renewal command status.
Preferably, when state machine performs chained record input state, scanning annular is not controlled by state machine
Position is sent to data selector, and data selector then selects input data and input data are sent to state
Machine.Input data, by cyclically performing data displaced condition, are inputted to chip by state machine.Such as,
When state machine is in chained record input state, scanning annular control bit (is not worked as state machine by state machine
State skip state 6 or during state 13, this scanning annular control bit is invalid) be sent to data selector,
Data selector then selects input data and input data are sent to state machine.Only enter when state machine
During to state 6 or state 13, state machine just exports annular control bit.
Preferably, state machine, will input data or invalid data by cyclically performing data displaced condition
Input to chip.In like manner, state machine by cyclically perform instruction shift state, by input instruct or
Illegal command inputs to chip.
Preferably, when state machine performs data ring connection status, invalid data is sent to core by state machine
Sheet.Such as, in the state transition diagram of state machine it can be seen that when entering data ring connection status,
Then need to input invalid data.The concrete feelings needing to input invalid data are illustrated below in conjunction with Fig. 7
Condition, when needs input invalid data, the scanning annular control bit of data selector is effective, and data select
Device selects invalid data, and it is inputed to again state machine, and after entering state machine, this invalid data leads to
Oversampling clock and Data Control position, then these invalid data data are inputed to scanning circuit.
Preferably, when state machine performs instruction ring connection status, scanning annular control bit is sent out by state machine
Giving data selector, data selector then selects illegal command.Such as, the state at state machine shifts
It can be seen that when entry instruction ring connection status, then need to input illegal command in figure.
Preferably, data serial Output Shift Register is further used for: by input number after treatment
According to being sent to external emulator；Invalid data is sent to data selector.
Preferably, the combination of input shift register and Output Shift Register at least includes: 8 inputs
Shift register and 8 Output Shift Registers, 16 input shift registers and 16 outputs
Shift register, 32 input shift registers and 32 Output Shift Registers, 64 inputs move
Bit register and 64 Output Shift Registers.
Preferably, the type of input data at least includes at least one of: 8 Bit datas, 16
Bit data, 32 Bit datas, 64 Bit datas.
Fig. 3 is the schematic diagram of the annular boundary scan method of the present invention, and it comprises the steps
Step 302: receive the input data from emulator；
Step 304: according to unified clock and Data Control position, judges that to chip input be defeated
Enter data, or invalid data；
Step 306: if being input data to chip input, then by input data step-by-step successively defeated
Enter to input shift register；Input data are exported to chip by input shift register, and chip is by defeated
Enter data and carry out processing the effective result of acquisition, and be sent to effective result export shift LD
Device；By in invalid data step-by-step input successively to input shift register, input shift register is by nothing
Effect data export to chip, and invalid data is carried out processing acquisition invalidation result by chip, and by invalid
Result is sent to Output Shift Register, the effective result in Output Shift Register is extruded,
And it is sent to emulator and/or controller.
At present, chip is all to process 32, the Bit data of 64.The present invention can to 8,16
Position, 32, the Bit data of 64 processes.
The present invention is as a example by the Bit data process of 8, and combines the following example to round-looking scan method
It is described in detail.
On the whole, traditional chain type scan mode is changed over circular scanning mode by the present invention, eliminates
Original and shift register controls end one to one, adds a unified controller, and revises
The state machine of original controller.
Specifically, as seen from Figure 2, circular scanning circuit is to be controlled by a unified controller.
This controller is kept apart chip with emulator, is uniformly controlled data serial input, clock, data control
Position processed and data serial input.When emulator needs to enter data to control chip to chip, by one
Individual unified clock and Data Control position, enter data into each input shift register.Now can
There are the data equal with input data length to be moved from each Output Shift Register, enter into control
Store in the middle of device.When chip has performed once-through operation and exported data from output port, last
The data being moved from each Output Shift Register are again automatically into each input shift register
In, simultaneously the data of chip output from shift register output, then export from data serial delivery outlet,
Deliver to emulator resolve.Wherein when chip receives data or the instruction that input shift register sends, core
These data and instruction are processed by sheet.Its processing procedure is as prior art chips is to data or instruction
Process.
Inputted data by emulator, control these data through controller and be input to core from input shift register
Sheet, chip exports to Output Shift Register after processing, then is exported to controller by Output Shift Register
Detailed process as shown in Figure 4, Figure 5 and Figure 6.
Fig. 4 is operating procedure 1.Posted to each input displacement by emulator input data 7 ' b10101010
Storage, owing to the initial value of each shift register is 1 ' b0, so being moved into data in controller
It is 7 ' b00000000.
Fig. 5 is operating procedure 2.When chip has performed once-through operation, from delivery outlet output data by more
It is newly 7 ' b9999.
Fig. 6 is operating procedure 3.After each numerical value of Output Shift Register is updated, control
The data that device can export the last time automatically from each Output Shift Register are being input to each input displacement
In order to the data that this operation is obtained from chip export shift LD from each in the middle of depositor
Device removes, and now by controller control, is input to the data in each input shift register only for shifting
Go out data, do not enter chip internal and perform any operation.
By Fig. 4, Fig. 5 and Fig. 6 it can be seen that performed once-through operation, only need to be by emulator from data
Serial input mouth inputs a secondary data, and other process chip with controller performs automatically.Due to hardware
The execution speed of circuit is much larger than the input of emulator embedded software program and controls speed, and EJTAG
Debugging system is completed by some such operating process, so using the operation that round-looking scan chain structure performs
Speed is significantly larger than the speed of service of traditional chain type scan chain architecture, and improves the work of emulator
Efficiency.
Specifically, structural representation such as Fig. 7 institute of the controller in the annular boundary scanning means of the present invention
Show.
As can be seen from Figure 7, controller by a data Serial output shift register, data selector, with
And a state machine composition.Data serial Output Shift Register is responsible for depositing every time from scanning circuit serial
The data of output are as invalid data, then selected to be currently that needs are defeated from emulator serial by data selector
Enter data to be input in the middle of scanning circuit control chip and perform corresponding operating and need for inputting invalid data
The data of the Output Shift Register in scanning circuit are shifted out and give emulator parsing.Data selector
After choosing desired data, these data being sent in the middle of state machine module, state machine is by clock and data control
The cooperation of position processed, the data input of the annular control bit of output scanning simultaneously and entrance scanning circuit.Wherein sweep
The initial value retouching annular control bit is 0, and chooses the serial input of data defeated as the data of scanning circuit
Entering, after chip has performed first time operation, emulator, by controlling Data Control position and clock, comes
Selecting the next one to be input to the data of scanning circuit is the data that send of emulator or an invalid data.
The state transition diagram of the annular EJTAG state machine of the present invention is as shown in Figure 8.Fig. 9 is traditional
The state transition diagram of chain structure EJTAG state machine.
As shown in Figure 8: the state machine of the present invention has data file and instruction file.Data file is wrapped
Include: select data entry mode state, data capture state, data displaced condition, exit chained record
Input state, data ring connection status, exit annular data input state and update data mode.
Instruction file include: select instruction input mode state, instruction trapped state, instruction shift state,
Exit chain type instruction input state, instruction ring connection status, exit annular instruction input state, Yi Jigeng
New command status.The most above-mentioned data ring connection status represents: the input that controller will obtain from emulator
After data give chip process, its result is stored in Output Shift Register, if now entered
Data ring connection status, then invalid data is automatically given chip by controller, and chip exports and moves to output
Bit register, this invalid data extrudes the result of the input data of last stored.
When the state machine of the present invention performs data capture state, when Data Control position, input controls data " 0 "
Time, then this state machine enters data displaced condition, and data displaced condition now represents: will enter ring
Shape connection status or wait enter and update data mode, and the most do not carry out any operation, under wait
One state.
Otherwise, when state machine is in data displaced condition, and input controls data " 1 " when Data Control position
Time, then state machine enters and exits chained record input state.Now, state machine will scanning annular control bit
Being sent to data selector, data selector then selects input data and input data are sent to state machine.
Exit chained record input state when state machine is in, and input controls data when Data Control position
Time " 0 ", then state machine enters data ring connection status.When entering into data ring connection status, first
Individual invalid data enters in the middle of input shift register.Continue the input to Data Control position simultaneously and control number
According to " 0 ', then second invalid data enters in the middle of input shift register.Repeat above-mentioned execution process,
Until input shift register is filled complete by all invalid datas, now to Data Control position, input controls
Data 1, exit annular data input, again input 1, enter more newly inputted data mode, now own
Data in input shift register have disposably been input in scanning circuit, and this input displacement is posted
Data in storage are all captured by chip.
It addition, when state machine performs chained record input state, state machine will scanning annular control bit
Being sent to data selector, data selector then selects input data and input data are sent to state machine.
Input data, by cyclically performing data displaced condition, are inputted to chip by state machine.Such as, when
When state machine is in chained record input state, state machine will not scan annular control bit (when state machine
When state skip state 6 or state 13, this scanning annular control bit is invalid) it is sent to data selector,
Data selector then selects input data and input data are sent to state machine.Only enter when state machine
During to state 6 or state 13, state machine just exports annular control bit.
It should be noted that the principle of state machine execution instruction file performs this data file such as state machine
Principle.Such as, exit chain type instruction input state when state machine is in, and when instruction control bit is defeated
When entering control instruction " 0 ", then state machine entry instruction ring connection status.Shape is connected when entering into instruction ring
During state, first illegal command enters in the middle of input shift register.Continue to instruction control bit simultaneously
" 0 ', then second illegal command enters in the middle of input shift register input control instruction.On repeating
State execution process, until input shift register is filled complete by all illegal commands, now to instruction control
Position processed input control instruction 1, exits annular instruction input, again inputs 1, enter more newly inputted instruction shape
State, the instruction in the most all input shift registers has disposably been input in scanning circuit, and
Instruction in this input shift register is all captured by chip.
Comparison diagram 8, Fig. 9 understand, and the difference of two state transition diagrams is the shape that data input state arranges
State 4 state 7, and instruction input state column-shaped state 12 state 14.That is, the state in the present invention
4 states 7 are to make state machine exit chained record input mode hence into annular data input side respectively
Formula；State 12 state 14 in the present invention be respectively make state machine exit chain type instruction input mode from
And enter annular instruction input mode.The numerical value that in figure 1/0 inputs for Data Control position.At each
In clock cycle, by the difference of the value of the Data Control position of input, different states can be entered.Figure
Middle data, instruction input divide into two-way file, can be considered as the control number different to chip input here
According to, do not do differentiation in detail.In traditional E JTAG state transition diagram, only exist data/commands input,
Capturing, shift, update, suspend and exit several state, each of which file exists two and exits state,
In actual applications, can arbitrarily select one and exit state, i.e. can be considered and there is redundant state.Further,
Traditional EJTAG state machine only one of which data output end is used for being connected with scanning circuit.In annular
In EJTAG state transition diagram, change the function of state 4 and state 12, eliminate in each file
One is exited state, adds and exits chained record input state, i.e. can by the two state respectively
Select the annular connection of instruction/data chain.This state machine has two output ports, and one is data output end
Being used for being connected with scanning circuit, one is scanning annular control bit, is used for selecting to input in state machine
Data are the serial input data that is given of emulator or an invalid data.
Above example is only in order to illustrate technical scheme and unrestricted, reference only to preferably implementing
The present invention has been described in detail by example.It will be understood by those within the art that, can be to this
Bright technical scheme is modified or equivalent, without deviating from spirit and the model of technical solution of the present invention
Enclose, all should contain in the middle of scope of the presently claimed invention.
Claims (14)
1. an annular boundary scanning means, it is characterised in that include that controller, multiple input displacement are posted
Storage and multiple Output Shift Register,
Described controller, for judging outwards according to unified clock signal and scanning annular control bit
Whether portion's chip input is input data；
If input be described input data, controller described input data step-by-step is in turn exported to
Described input shift register, described input data are exported to chip, core by described input shift register
Described input data are carried out processing the effective result of acquisition by sheet, and described effective result are sent
To Output Shift Register；And
Controller by invalid data step-by-step input successively to described input shift register, described input
Described invalid data is exported to chip by shift register, and chip does not process described invalid data directly by institute
Stating invalid data and be sent to Output Shift Register, Output Shift Register utilizes described invalidation result
Described effective result in described Output Shift Register is extruded, and is sent to emulator and/or control
Device processed.
2. annular boundary scanning means as claimed in claim 1, it is characterised in that: described controller is extremely
Include less:
Data serial Output Shift Register, is used for receiving described clock signal；And by described invalid data
It is sent to data selector；
Data selector, for the scanning annular control bit according to state machine output, determines it is to select institute
State invalid data, or select the described input data from emulator；
State machine, for generating described scanning annular control according to described clock signal and Data Control position
Position processed controls the output of described data selector.
3. annular boundary scanning means as claimed in claim 2, it is characterised in that: described state machine is extremely
Include data file and instruction file less, wherein
Described data file at least includes: data displaced condition, exit chained record input state, data
Ring connection status and exit annular data input state；
Described instruction file at least includes: exit chain type instruction input state, instruction ring connection status and
Exit annular instruction input state.
4. annular boundary scanning means as claimed in claim 3, it is characterised in that: when described state machine
When performing described data ring connection status, described scanning annular control bit is sent to described by described state machine
Data selector, described data selector then selects described invalid data and is sent to by described invalid data
Described state machine.
5. annular boundary scanning means as claimed in claim 3, it is characterised in that: described state machine leads to
Cross and cyclically perform described data displaced condition, described input data or described invalid data are inputted to core
In sheet.
6. annular boundary scanning means as claimed in claim 3, it is characterised in that: when described state machine
When performing described instruction ring connection status, described scanning annular control bit is sent to described by described state machine
Data selector, described data selector then selects described illegal command.
7. annular boundary scanning means as claimed in claim 1, it is characterised in that: described data serial
Output Shift Register is further used for:
Described invalid data is sent to described data selector.
8. annular boundary scanning means as claimed in claim 1, it is characterised in that: described input displacement
The combination of depositor and described Output Shift Register at least includes: 8 input shift registers and 8
Individual Output Shift Register, 16 input shift registers and 16 Output Shift Registers, 32
Input shift register and 32 Output Shift Registers, 64 input shift registers and 64
Output Shift Register.
9. annular boundary scanning means as claimed in claim 1, it is characterised in that: described input displacement
Depositor and the combination of Output Shift Register, the data type of process at least includes at least one of: 8
Position Bit data, 16 Bit datas, 32 Bit datas, 64 Bit datas.
10. an annular boundary scan method, it is characterised in that:
Receive the input data from emulator；
Judge whether to chip input be described input data；
If being described input data to chip input, then by described input data step-by-step input successively
To input shift register；Described input data are exported to chip, core by described input shift register
Described input data are carried out processing the effective result of acquisition by sheet, and described effective result are sent
To Output Shift Register；By invalid data step-by-step input successively in described input shift register,
Described invalid data is exported to chip by described input shift register, and described invalid data is carried out by chip
Process and obtain invalidation result, and described invalidation result is sent to Output Shift Register, will
Described effective result extrusion in described Output Shift Register, and it is sent to emulator and/or control
Device.
11. annular boundary scan methods as claimed in claim 10, it is characterised in that: judge to chip
Whether input is that described input data at least include:
Scan ring shape control bit is generated according to clock signal and Data Control position；
According to described scanning annular control bit, determine it is to select invalid data, or select from emulation
The described input data of device.
12. annular boundary scan methods as claimed in claim 11, the most at least include performing shape
State machine generates described scanning annular control bit, and wherein said state machine at least includes that data file and instruction are vertical
Row, wherein:
Described data file at least includes: data displaced condition, exit chained record input state, data
Ring connection status and exit annular data input state；
Described instruction file at least includes: exit chain type instruction input state, instruction ring connection status and
Exit annular instruction input state.
13. annular boundary scan methods as claimed in claim 12, it is characterised in that: when described state
When machine performs described data ring connection status, described scanning annular control bit is sent to institute by described state machine
Stating data selector, described data selector then selects described invalid data and is sent by described invalid data
To described state machine.
14. annular boundary scan methods as claimed in claim 12, it is characterised in that: when described state
When machine performs described instruction ring connection status, described scanning annular control bit is sent to institute by described state machine
Stating data selector, described data selector then selects described illegal command.
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