CN113010361B - MIO function rapid verification method of fully programmable SOC chip - Google Patents
MIO function rapid verification method of fully programmable SOC chip Download PDFInfo
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Abstract
The invention discloses a method for quickly verifying MIO function of a fully programmable SOC chip, which relates to the technical field of chip verification, and utilizes a verification environment platform integrated with an AXI system environment to quickly add a verification case into a verification environment according to MIO parameter data of the fully programmable SOC chip, and a corresponding sequence provided by the AXI system environment can traverse all functional modes of all MIO ports for quick verification, thereby effectively improving verification speed, verification coverage rate and debugging efficiency, and being capable of quickly iterating and re-simulating when the MIO parameter data changes, and meeting the requirement of MIO function verification of the fully programmable SOC chip.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to a method for quickly verifying an MIO function of a fully programmable SOC chip.
Background
With the continuous and rapid development of semiconductor manufacturing technology, the integration level of a chip is higher and higher, the functions are stronger and stronger, and the traditional SOC chip cannot meet the requirements, so that the fully programmable SOC chip has come to the end, integrates an embedded processor and an FPGA chip, provides a more flexible solution, has all the advantages of the traditional SOC chip, and overcomes the defects of poor flexibility, strong specificity and complex design of the traditional SOC chip.
The fully programmable SOC chip contains more Multiplex IO (MIO), which is a window for interaction between internal data and peripheral devices, so that functional verification of the MIO is the last gateway for ensuring normal operation of the chip. In a fully programmable SOC chip, each MIO can be configured as an input/output port, in the two cases of input/output, the MIO can be configured into a pull-up state and a tri-state respectively, adjustment of output driving strength is achieved, meanwhile, various MOS types exist, various functional modes can be triggered in the actual use process of the chip, therefore, the verification process is complex and tedious, currently, the verification of the MIO is realized by manually writing each MIO test case, the verification period is long, the verification coverage rate is difficult to guarantee, and the verification efficiency is low.
Disclosure of Invention
The invention provides a method for quickly verifying an MIO function of a fully programmable SOC chip aiming at the problems and technical requirements, and the technical scheme of the invention is as follows:
a MIO function rapid verification method of a fully programmable SOC chip comprises the following steps:
initializing a verification environment platform, wherein the verification environment platform comprises a test case layer and a verification environment layer contained in the test case layer, and the verification environment layer is integrated with an AXI system environment;
the method comprises the steps that MIO parameter data of a to-be-verified fully programmable SOC chip are input into a test case layer of a verification environment platform, the test case layer calls test codes to construct verification cases in a verification environment according to the MIO parameter data, and the MIO parameter data at least comprise the number of MIO ports in the fully programmable SOC chip and all function modes of each MIO port;
configuring a register in a fully programmable SOC chip by using a master _ base _ sequence in an AXI system environment according to an ith target address and jth target data and configuring the register of the ith target address as jth target data by using a verification case, so that an ith MIO port controlled by the register of the ith target address in the fully programmable SOC chip works in a jth functional mode corresponding to the jth target data, i and j are parameters and the initial values are 1; the test case calls uvm _ hdl _classfunction to test the jth functional mode of the ith MIO port by using test data to obtain a verification result;
if j is less than N, j is equal to j +1, if j is equal to N and i is less than M, i is equal to i +1 and j is equal to 1, and the step of configuring the register in the fully programmable SOC chip according to the ith target address and the jth target data by using the master _ base _ sequence in the AXI system environment is executed again;
and if j is equal to N and i is equal to M, completing the MIO function verification of the fully programmable SOC chip, wherein N is the total number of the function modes of the ith MIO port, and M is the number of the MIO ports in the fully programmable SOC chip.
The further technical scheme is that the function mode of the MIO port comprises all MOS tube transmission types, all pull-up state voltage values and all tri-state voltage values when the MIO port is used as an input port, and all MOS tube transmission types, all pull-up state voltage values and all tri-state voltage values when the MIO port is used as an output port.
The further technical scheme is that the method also comprises the following steps:
writing the configuration operation of a master _ base _ sequence in an AXI system environment to a register into a macro function by using macro definition with parameters, wherein the parameters of the macro function comprise a register address and a configuration value;
configuring a register in the fully programmable SOC chip according to the ith target address and the jth target data by using a master _ base _ sequence in the AXI system environment, including:
and taking the ith target address as the register address of the macro function, taking the jth target data as the configuration value of the macro function, calling the macro function to generate data conforming to the AXI protocol, and performing access configuration on the register in the fully programmable SOC chip.
The technical scheme is that the register addresses of registers in the fully programmable SOC chip are continuous, the ith target address is the sum of a base address and an offset address, the offset address is related to the value of a cycle number variable i, and the base address is the first target address.
The further technical scheme is that the test data comprises a plurality of test input values and output pre-evaluation values corresponding to the test input values, and the test data is used for testing the jth functional mode of the ith MIO port to obtain a verification result, and the method comprises the following steps:
when the jth functional mode is the functional mode when the ith MIO port is used as an input port, sequentially inputting a test input value at the ith MIO port, acquiring a corresponding test actual value at the output end of an IO module in the fully programmable SOC chip, and comparing the test actual value with a corresponding output estimated value to obtain a verification result;
and when the jth functional mode is the functional mode when the ith MIO port is used as the output port, sequentially inputting a test input value at the input end of an IO module in the fully programmable SOC chip, acquiring a corresponding test actual value at the ith MIO port, and comparing the test actual value with the corresponding output estimated value to obtain a verification result.
The technical scheme is that the method comprises the following steps of sequentially inputting a test input value at the ith MIO port and acquiring a corresponding test actual value at the output end of an IO module in a fully programmable SOC chip, wherein the method comprises the following steps:
forming a back gate operation address of an ith MIO port according to a cycle number variable i by using a $ psprintf formatting output function, transmitting uvm _ hdl _ destination function as a parameter, transmitting a test input value in test data into a uvm _ hdl _ destination function as a parameter, and calling a uvm _ hdl _ destination function to write the test input value into the ith MIO port by using the back gate operation address of the ith MIO port;
and transferring a back gate operation address of the ith MIO port of the output function into uvm _ hdl _ read function as a parameter by using the $ psprintf format, and calling uvm _ hdl _ read function to read the value of the output end of the IO module in the fully programmable SOC chip by using the back gate operation address of the ith MIO port to obtain a corresponding test actual value.
The further technical scheme is that the method also comprises the following steps:
and outputting a simulation log and a simulation waveform for verifying the MIO function of the fully programmable SOC chip.
The beneficial technical effects of the invention are as follows:
the method can rapidly add a verification case into a verification environment according to MIO parameter data of the fully programmable SOC by utilizing a verification environment platform integrated with an AXI system environment, automatically traverse all MIO ports in the verification case to perform rapid verification of functions including read-write test, state control and the like, can cover all functional modes of all MIO ports at one time, and improves verification speed, verification coverage rate and debugging efficiency. In addition, the method can quickly iterate and re-simulate when the MIO parameter data changes, reduces the repeated work and the maintenance burden of the later environment, and meets the requirement of MIO function verification of the fully programmable SOC chip.
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FIG. 1 is a schematic flow diagram of a method disclosed herein.
Fig. 2 is a schematic structural diagram of a verification environment platform in the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a method for quickly verifying an MIO function of a fully programmable SOC chip, which comprises the following steps, please refer to FIG. 1:
1. and initializing a verification environment platform. Referring to fig. 2, the verification environment platform includes a Test case layer Test and a verification environment layer SOC _ ENV included therein, the verification environment layer SOC _ ENV integrates an AXI system environment Axi _ ENV, and the verification environment layer SOC _ ENV also integrates agent environments of other modules. The AXI system environment Axi _ env mainly includes an AXI sequencer module (Axi _ sequence), an AXI driver (driver), a Master interface and a Slave interface, and the application uses the Master interface to connect a to-be-verified fully programmable SOC chip. Axi _ env is a new VIP environment, and by integrating Axi _ env, the sequence in the AXI system environment can be called to replace the cpu of the fully programmable SOC chip to send commands to modules such as a register, a RAM and a DDR in the fully programmable SOC chip to carry out read-write operation. Various sequences in Axi _ env can be used for verifying different soft cores and hard cores in the fully programmable SOC chip, and meanwhile debugging time of a verification environment can be greatly reduced.
2. And inputting MIO parameter data of the to-be-verified fully programmable SOC chip into a Test case layer Test of the verification environment platform. The MIO parameter data in the application at least comprises the number of MIO ports in a fully programmable SOC chip and all function modes of each MIO port, wherein the function modes of each MIO port comprise all MOS tube transmission types, all pull-up state voltage values and all tri-state voltage values of the MIO port serving as an input port, and all MOS tube transmission types, all pull-up state voltage values and all tri-state voltage values of the MIO port serving as an output port.
3. And the Test case layer Test calls a Test code to construct a verification case in a verification environment according to the MIO parameter data. In order to reduce the complexity of the environment, the Test code of the application is written in the main function of the Test case layer Test so as to facilitate debug. The test code utilizes two loop structures, the outer loop is used for controlling the verification of each MIO port, and the inner loop is used for controlling the verification of different functional modes of one MIO port, so that a corresponding verification case is generated to automatically realize the rapid verification on the MIO function of the fully programmable SOC chip. In order to ensure the completeness of verification and simplify the verification process, the test codes are packaged into the scripts, so that the verification case can be constructed only by executing the scripts, the code accuracy is ensured, and the verification period is shortened. Meanwhile, when the MIO netlist changes to cause the change of the MIO parameter data, the simulation can be iterated and re-simulated quickly, and the repeated work and the maintenance burden of the later environment are reduced.
4. The verification case is implemented according to two loop structures of the test code, and the implementation process is as follows:
(1) and configuring a register in the fully programmable SOC chip according to the ith target address and the jth target data by using a master _ base _ sequence in the AXI system environment, and configuring the register of the ith target address as the jth target data. The MIO ports in the fully programmable SOC chip are controlled by corresponding registers, the registers with different register addresses control different MIO ports, and when the configuration values of the registers are different, the registers control the corresponding MIO ports to work in corresponding functional modes, so that the ith target address serves as a register address, and the jth target data serves as the configuration value of the register, and the ith MIO port controlled by the register of the ith target address in the fully programmable SOC chip works in the jth functional mode corresponding to the jth target data. Wherein i and j are both parameters and the starting values are both 1.
According to the method, the macro definition with parameters is used for compiling the register configuration operation of the master _ base _ sequence in the AXI system environment into the macro function, the parameters of the macro function comprise register addresses and configuration values, then the ith target address is used as the register address of the macro function, the jth target data is used as the configuration value of the macro function, the macro function is directly called to generate data meeting the AXI protocol for carrying out access configuration on the registers in the fully programmable SOC chip, the compiling and maintaining time of case codes is greatly reduced, and the code structure is simple and easy to understand.
In addition, since register addresses of registers in the fully programmable SOC chip are consecutive, the ith target address is the sum of a base address and an offset address, the base address is the first target address, the offset address is related to the value of the cycle number variable i, and the offset address can be expressed as (i-1) × fixed offset, so that the ith target address is the base address plus (i-1) × fixed offset, and the fixed offset is related to the MIO parameter data. For example, in a practical example, there are 54 MIO ports in the fully programmable SOC chip that need to be verified, and each MIO port has 7 MOS transistor transmission types when it is used as an input/output port, so that the ith target address is base address + (i-1) × 32' h 4.
(2) And calling uvm _ hdl _classfunction to test the jth functional mode of the ith MIO port by using the test data to obtain a verification result. The test data includes a plurality of test input values and corresponding output estimates, and the actual test input values include 0/1 input values.
And when the jth functional mode is the functional mode when the ith MIO port is used as the input port, sequentially inputting a test input value at the ith MIO port, acquiring a corresponding test actual value at the output end of the IO module in the fully programmable SOC chip, and comparing the test actual value with the corresponding output estimated value to obtain a verification result. Specifically, the operation address of the back gate of the MIO port in the system is fixed, only array index numbers change, for example, the operation address of the back gate of the ith MIO port may be expressed as xxx. And transferring a back gate operation address of the ith MIO port in a character string form into uvm _ hdl _ read function as a parameter by using a $ psprintf formatted output function, and calling uvm _ hdl _ read function to read the value of the output end of the IO module in the fully programmable SOC chip by using the back gate operation address of the ith MIO port to obtain a corresponding test actual value.
And when the jth functional mode is the functional mode when the ith MIO port is used as an output port, sequentially inputting a test input value at the input end of an IO module in the fully programmable SOC chip, acquiring a corresponding test actual value at the ith MIO port, and comparing the test actual value with the corresponding output estimated value to obtain a verification result. The specific operation mode is also similar, and the detailed description is omitted in the present application.
(3) And if j is less than N, j is equal to j +1, if j is equal to N and i is less than M, i is equal to i +1 and j is equal to 1, and then the step of configuring the register in the fully programmable SOC chip according to the ith target address and the jth target data by using the master _ base _ sequence in the AXI system environment is executed again, namely the step (1) and the step (2) are executed again to verify the next functional mode of the MIO port or the next MIO port is verified. Wherein, N is the total number of the functional modes of the ith MIO port, and M is the number of the MIO ports in the fully programmable SOC chip.
(4) If j is equal to N and i is equal to M, the MIO function verification of the fully programmable SOC chip is completed, the whole verification process is simplified, the verification period is greatly shortened, the coverage rate of verification is improved, and the quality of the chip is ensured.
The Test case layer Test of the application integrates abundant printing mechanisms in the Test codes in the main function, so that when the application is executed, simulation logs and simulation waveforms for MIO function verification of the fully programmable SOC chip can be output, and analysis by verification personnel is facilitated.
The method provided by the application can meet the requirement of the smoke test in the early stage of the chip, can also meet the requirement of the test of the bist code of the whole chip, and can also meet the requirement of a designer for verifying the system simulation. And when the code changes, debug can be quickly re-simulated in a short time, so that the chip verification period is shortened. The method has the function of flexibly generating the verification cases of different chips MIO, can reduce the compiling and maintenance of environment codes and test files, improve the verification efficiency, improve the coverage rate of the verification module to the maximum extent, and can meet the requirement of MIO function verification of the fully programmable SOC circuit.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (6)
1. A method for quickly verifying an MIO function of a fully programmable SOC chip is characterized by comprising the following steps:
initializing a verification environment platform, wherein the verification environment platform comprises a test case layer and a verification environment layer contained in the test case layer, and the verification environment layer integrates an AXI system environment;
inputting MIO parameter data of a to-be-verified fully programmable SOC chip into a test case layer of the verification environment platform, calling a test code by the test case layer to construct a verification case in a verification environment according to the MIO parameter data, wherein the MIO parameter data at least comprise the number of MIO ports in the fully programmable SOC chip and all function modes of each MIO port, and the function modes of the MIO ports comprise all MOS tube transmission types, all pull-up state voltage values and all tri-state voltage values when the MIO ports are used as input ports, and all MOS tube transmission types, all pull-up state voltage values and all tri-state voltage values when the MIO ports are used as output ports;
configuring a register in the fully programmable SOC chip by using a master _ base _ sequence in the AXI system environment according to an ith target address and a jth target data, and configuring the register of the ith target address as the jth target data, so that an ith MIO port controlled by the register of the ith target address in the fully programmable SOC chip works in a jth functional mode corresponding to the jth target data, i and j are parameters, and the initial values are both 1; the test case calls uvm _ hdl _ type function to test the jth functional mode of the ith MIO port by using test data to obtain a verification result;
if j < N, let j = j +1, if j = N and i < M, let i = i +1 and let j =1, and execute the step of configuring the register in the fully programmable SOC chip according to the ith target address and the jth target data by using the master _ base _ sequence in the AXI system environment again;
and if j = N and i = M, completing the MIO function verification of the fully programmable SOC chip, wherein N is the total number of the functional modes of the ith MIO port, and M is the number of the MIO ports in the fully programmable SOC chip.
2. The method of claim 1, further comprising:
writing a register configuration operation of a master _ base _ sequence in the AXI system environment as a macro function using a macro definition with parameters, the parameters of the macro function including a register address and a configuration value;
configuring a register in the fully programmable SOC chip according to the ith target address and the jth target data by using a master _ base _ sequence in the AXI system environment, including:
and calling the macro function to generate data conforming to an AXI protocol to perform access configuration on a register in the fully programmable SOC chip by taking the ith target address as a register address of the macro function and the jth target data as a configuration value of the macro function.
3. The method of claim 1,
if the register addresses of the registers in the fully programmable SOC chip are continuous, the ith target address is the sum of a base address and an offset address, the offset address is related to the value of a cycle number variable i, and the base address is the first target address.
4. The method of claim 1, wherein the test data comprises a plurality of test input values and corresponding output pre-estimated values, and the testing the jth functional mode of the ith MIO port using the test data to obtain the verification result comprises:
when the jth functional mode is the functional mode when the ith MIO port is used as an input port, sequentially inputting a test input value at the ith MIO port, acquiring a corresponding test actual value at the output end of an IO module in the fully programmable SOC chip, and comparing the test actual value with a corresponding output estimated value to obtain a verification result;
and when the jth functional mode is the functional mode when the ith MIO port is used as an output port, sequentially inputting a test input value at the input end of an IO module in the fully programmable SOC chip, acquiring a corresponding test actual value at the ith MIO port, and comparing the test actual value with a corresponding output estimated value to obtain a verification result.
5. The method of claim 4, wherein the sequentially inputting a test input value at the ith MIO port and obtaining a corresponding test actual value at an output end of an IO module in the fully programmable SOC chip comprises:
forming a back gate operation address of an ith MIO port according to a cycle number variable i by using a $ psprintf formatting output function, transmitting uvm _ hdl _ destination function as a parameter, transmitting a test input value in the test data into a uvm _ hdl _ destination function as a parameter, and calling a uvm _ hdl _ destination function to write the test input value into the ith MIO port by using the back gate operation address of the ith MIO port;
and transmitting a back gate operation address of the ith MIO port of the output function into uvm _ hdl _ read function as a parameter by using the $ psprintf formatted output function, and calling uvm _ hdl _ read function to read the value of the output end of the IO module in the fully programmable SOC chip by using the back gate operation address of the ith MIO port to obtain a corresponding test actual value.
6. The method of claim 1, further comprising:
and outputting a simulation log and a simulation waveform for MIO function verification of the fully programmable SOC chip.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106599343A (en) * | 2016-11-01 | 2017-04-26 | 深圳国微技术有限公司 | SOC system verification method and apparatus for improving simulation efficiency |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102799509B (en) * | 2012-07-10 | 2014-12-10 | 中国科学技术大学 | High-bandwidth extendable complex logic verification system based on double FPGA (Field- Programmable Gate Array) chips |
| CN103713993B (en) * | 2013-05-30 | 2015-07-22 | 深圳市汇春科技有限公司 | Chip verification platform and method for implementing chip testing |
| US9448917B2 (en) * | 2014-04-09 | 2016-09-20 | Samsung Electronics Co., Ltd. | System on chip and verification method thereof |
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