JP2023505585A - モノリシック発光ダイオード前駆体を形成する方法 - Google Patents
モノリシック発光ダイオード前駆体を形成する方法 Download PDFInfo
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Abstract
Description
本開示は、発光ダイオード(light emitting diodes:LEDs)に関する。特に、本開示は、III族窒化物を含むLEDに関する。
マイクロLEDアレイは、通常、100×100μm2以下のサイズを有するLEDのアレイとして定義される。マイクロLEDアレイは、スマートウォッチ、頭部装着型ディスプレイ、ヘッドアップディスプレイ、カムコーダ、ビューファインダ、マルチサイト励起源、およびピコプロジェクタ等の種々のデバイスにおける使用に好適な、マイクロディスプレイ/プロジェクタ内の自己発光構成要素である。
本発明の目的は、EQEが改善されたLED前駆体を提供することである。したがって、本発明の目的は、LED構造の側壁に欠陥、たとえばエッチングステップから生じる欠陥を導入しないプロセスを使用して、LED構造を形成することである。
(a)上面を有する基板を設けることと、
(b)基板の上面に、III族窒化物を含む第1の半導体層を形成することと、
(c)第1の半導体層をLEDマスク層で選択的にマスキングすることとを備え、LEDマスク層は、LEDマスク層の厚さを通して第1の半導体層のマスキングされていない部分までLEDウェルを画定する開口を含み、LEDウェルは、第1の半導体層の上面からLEDマスク層の上面まで延在するLEDウェル側壁を含み、方法はさらに、
(d)第1の半導体層のマスキングされていない部分の上のLEDウェル内にモノリシックLEDスタックを選択的に形成することを備え、モノリシックLEDスタックは、
第1の半導体層上に形成された、III族窒化物を含むn型半導体層と、
1つ以上の量子井戸副層を含む、第1の半導体層上に形成された活性層であって、III族窒化物を含む活性層と、
第2の半導体層上に形成された、III族窒化物を含むp型半導体層とを含み、
第1の半導体層の上面から延在するモノリシックLEDスタックのLEDスタック側壁は、LEDマスク層のLEDウェル側壁に一致する。
(f)LEDマスク層がモノリシックLEDスタックの上面と共に平坦化された表面を形成するように、LEDマスク層の第2の部分をLEDマスク層の上面から除去することを備える。
(f)モノリシックLEDスタックの形成に続いて、LEDマスク層の全てを選択的に除去することを備える。
(g)LED前駆体の平坦化された表面を、バックプレーン電子デバイスを含むさらに別の基板に接合することと、任意に、
(h)第1の半導体層から基板を除去することとを備え得る。
本開示のある実施形態によれば、LED前駆体を形成する方法100が提供される。LED前駆体は、複数のIII族窒化物層を含む。方法100のフロー図を図1に示す。
(a)基板を設けるステップ(101)と、
(b)基板上に第1の半導体層を形成するステップ(102)と、
(c)第1の半導体層を選択的にマスキングするステップ(103)と、
(d)LEDウェル内にモノリシックLEDスタックを選択的に形成するステップ(104)と、
(e)モノリシックLEDスタックを含む平坦化された表面を形成するステップ(105)と、
(f)LED前駆体をバックプレーン電子基板に対して位置合わせし、接合するステップ(106)と、
(g)基板を除去するステップ(107)とを備える。
Claims (16)
- モノリシックLED前駆体を形成する方法であって、
(a)上面を有する基板を設けることと、
(b)前記基板の前記上面に、III族窒化物を含む第1の半導体層を形成することと、
(c)前記第1の半導体層をLEDマスク層で選択的にマスキングすることとを備え、前記LEDマスク層は、前記LEDマスク層の厚さを通して前記第1の半導体層のマスキングされていない部分までLEDウェルを画定する開口を含み、前記LEDウェルは、前記第1の半導体層の上面から前記LEDマスク層の上面まで延在するLEDウェル側壁を含み、前記方法はさらに、
(d)前記第1の半導体層の前記マスキングされていない部分の上の前記LEDウェル内にモノリシックLEDスタックを選択的に形成することを備え、前記モノリシックLEDスタックは、
前記第1の半導体層上に形成された、III族窒化物を含むn型半導体層と、
1つ以上の量子井戸副層を含む、前記第1の半導体層上に形成された活性層であって、III族窒化物を含む前記活性層と、
前記活性層上に形成された、III族窒化物を含むp型半導体層とを含み、
前記第1の半導体層の前記上面から延在する前記モノリシックLEDスタックのLEDスタック側壁は、前記LEDマスク層の前記LEDウェル側壁に一致する、方法。 - 前記第1の半導体層をLEDマスク層で選択的にマスキングすることは、
前記第1の半導体層の前記上面にわたって前記LEDマスク層を堆積させることと、
前記LEDマスク層の厚さを通して前記LEDマスク層の第1の部分を選択的に除去して、前記LEDウェルを形成することとを含む、請求項1に記載の方法。 - 前記LEDウェル側壁は、前記第1の半導体層の前記上面に対して略垂直な方向に延在する、請求項1または2に記載の方法。
- 前記第1の半導体層と前記LEDマスク層の前記上面との間に延在する前記LEDウェル側壁の一部は、前記第1の半導体層の前記上面に垂直な方向に対して傾斜している、先行する請求項のいずれか1項に記載の方法。
- 前記第1の半導体層の前記上面に平行な平面における前記LEDウェルの断面積が、前記第1の半導体層の前記上面から前記LEDマスク層の前記上面に向かう方向に減少するように、前記LED側壁は傾斜している、請求項4に記載の方法。
- 前記第1の半導体層の前記上面に平行な平面における前記LEDウェルの断面積が、前記第1の半導体層の前記上面から前記LEDマスク層の前記上面に向かう方向に増加するように、前記LEDウェル側壁は傾斜している、請求項5に記載の方法。
- 前記第1の半導体層から延在する各LEDウェル側壁のコリメート部分が、前記第1の半導体層に略垂直な方向に延在し、
前記第1の半導体層の前記上面に平行な平面における前記LEDウェルの断面積が、前記第1の半導体層の前記上面から前記LEDマスク層の前記上面に向かう方向に減少するように、前記コリメート部分と前記LEDマスク層の前記上面との間に延在する各LEDウェル側壁のテーパ部分が傾斜している、請求項4または5に記載の方法。 - (f)前記LEDマスク層が前記モノリシックLEDスタックの上面と共に平坦化された表面を形成するように、前記LEDマスク層の第2の部分を前記LEDマスク層の前記上面から除去することをさらに備える、先行する請求項のいずれか1項に記載の方法。
- 前記LEDマスク層の前記第2の部分は、研磨プロセスを使用して除去される、請求項8に記載の方法。
- (f)前記モノリシックLEDスタックの形成に続いて、前記LEDマスク層の全てを選択的に除去することをさらに備える、請求項1~7のいずれか1項に記載の方法。
- 前記モノリシックLEDスタックを取り囲む前記第1の半導体層の前記上面に、ギャップ充填絶縁体を堆積させることをさらに備え、前記ギャップ充填絶縁体は、前記モノリシックLEDスタックの上面と共に平坦化された表面を形成する、請求項10に記載の方法。
- (g)前記LED前駆体の前記平坦化された表面を、バックプレーン電子デバイスを含むさらに別の基板に接合することをさらに備える、請求項8、9または11に記載の方法。
- (h)前記第1の半導体層から前記基板を除去することをさらに備える、請求項12に記載の方法。
- 前記LEDマスク層は、誘電体、たとえばSiO2またはSiNxを含む、先行する請求項のいずれか1項に記載の方法。
- 前記第1の半導体層上の前記LEDウェルの断面積は、100μm×100μm以下である、先行する請求項のいずれか1項に記載の方法。
- 請求項1~15のいずれか1項に記載の方法に従って、基板に複数のLED前駆体を形成することを備える、LEDアレイ前駆体を形成する方法。
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PCT/EP2020/084546 WO2021115934A1 (en) | 2019-12-12 | 2020-12-03 | Method of forming a monolithic light emitting diode precursor |
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JP2009292713A (ja) * | 2008-06-03 | 2009-12-17 | Samsung Electro-Mechanics Co Ltd | 窒化物単結晶の成長方法及び窒化物半導体発光素子の製造方法 |
JP2011228628A (ja) * | 2010-04-16 | 2011-11-10 | Invenlux Corp | 垂直型の光抽出メカニズムを備える発光素子及びその製造方法 |
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WO2021115934A1 (en) | 2021-06-17 |
KR20220107267A (ko) | 2022-08-02 |
EP4073843A1 (en) | 2022-10-19 |
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