JP2023162102A - Video data identification circuit and panel system controller - Google Patents

Abstract

To dynamically set a drive current of a source driver to an optimum value to achieve low power consumption and improved image quality in a panel system.SOLUTION: A video data identification circuit 12 for identifying video data output from a video data reception circuit 11 and controlling a drive current of a source driver, includes: a memory 122 for storing video data of a current horizontal line and video data of a plurality of horizontal lines preceding the current horizontal line in the output video data; an image pattern detection circuit 123 that reads the pattern of the video data of the plurality of horizontal lines stored in the memory 122 when the video data of the current horizontal line and the video data of the preceding horizontal line are compared and do not match; and a drive current setting circuit 124 that sets a drive current of the source driver 13 for driving the current horizontal line on the basis of the pattern of the video data of the plurality of horizontal lines read from the memory 122 by the image pattern detection circuit 123.SELECTED DRAWING: Figure 12

Description

The present invention relates to a panel system controller that outputs analog video data of a display panel and a video data identification circuit included therein. Specifically, the present invention relates to a circuit technique that minimizes errors in the driving voltage of a source driver.

In the mobile device market such as notebook computers and tablet computers, there is a constant need to reduce power consumption and cost. On the other hand, as the resolution of panels and the image quality of displays improve, the amount of data processed and operating frequency continue to increase, and reducing power consumption and cost have become contradictory issues. The circuit that inputs the drawing data signal to the display panel of a notebook computer or tablet computer is a CPU (Central Processing Unit) or GPU (Graphics Processing Unit) that is responsible for calculating the drawing data itself, various calculation processing, and graphics processing. A processor, a timing controller (TCON) that receives drawing data sent from this processor and performs timing control and image processing for the display panel, and a timing controller (TCON) that receives drawing data from the timing controller and performs drawing according to the specifications of the display panel. It is composed of a driver chip such as a source driver (SD) that outputs data in analog form.

In mobile devices such as notebook computers and tablet computers, the timing controller and source driver are often separated. For example, in the case of a FHD (Full High Definition: 1920×1080 pixels) display panel shown in FIG. 1, one timing controller and four source drivers are often required. Furthermore, in the case of a 4K2K panel (a panel with a resolution close to 4000 x 2000 pixels), one timing controller and eight source drivers are often required. Furthermore, as shown in Figure 1, FPCs (Flexible Printed Cables) that connect the timing controller and source drivers are required for each source driver, and as the resolution of the panel increases, the number of parts increases and costs increase. This was a contributing factor. Furthermore, it is necessary to provide an interface between the timing controller and the source driver, which consumes power. Against this background, with the circuit configuration shown in FIG. 1, it has been difficult to reduce costs and power consumption.

Therefore, in order to reduce the number of parts and power consumption, it is also possible to consider a so-called system driver (TCON+SD) in which the timing controller and source driver are integrated into one chip as shown in FIGS. 2 and 3. FIG. 2 shows a configuration in which two system drivers are provided, and FIG. 3 shows a configuration in which one system driver is integrated. By making it a system driver, the number of parts is reduced and costs can be reduced. Furthermore, since there is no interface between the timing controller and source driver, it is possible to reduce power consumption. In particular, from the viewpoint of reducing the number of parts and power consumption, it is preferable to have only one system driver, as shown in FIG. 3. However, the system driver is mounted on the glass of the liquid crystal panel, similar to the conventional source driver. Drawing data is directly input from the processor (CPU/GPU) to the system driver via the eDP interface or the MIPI interface.

Here, the liquid crystal panel is composed of a source line and a gate line. In the case of an FHD panel, 1920×3 (RGB) lines are required for source lines, and 1080 lines are required for gate lines. The source lines are lines (data lines) for analog output of drawing data from the source driver, and are wired parallel to each other at predetermined intervals. The gate lines are control lines that drive the drawing data of the source lines while temporally shifting one gate line at a time, and are wired parallel to each other at predetermined intervals in a direction perpendicular to the source lines. A display pixel is provided at each intersection between the gate line and the source line. Furthermore, at present, a method in which a source driver and a system driver are mounted on liquid crystal glass, a so-called COG (Chip On the Glass) method, is mainstream.

As shown in Figure 4, in the case of a configuration in which four source drivers are arranged in the frame area and video data is output from these four source drivers to source lines on the display panel, the required amount is required to drive one source driver. The COG wiring load can be small, and the difference in wiring length between the longest source line and the shortest source line can also be small. However, as shown in FIG. 5, in the case of a configuration in which only one system driver consisting of a source driver and a timing controller is arranged in the frame area and video data is output from one source driver to all source lines on the display panel, The COG wiring load required to drive the driver output increases with each stage, and the difference in wiring length between the longest source line and the shortest source line also increases. A display panel such as a liquid crystal panel adjusts the brightness of an image based on the voltage level (potential) of an analog voltage of image data output by a source driver. Therefore, if the output voltage of the source driver does not reach the expected voltage level correctly, display problems such as dark areas appearing in a part of the panel will occur.

Figure 6 shows a model of the wiring load on the source line of the liquid crystal panel. A liquid crystal panel is divided into a fan out area (corresponding to a frame area) where a source driver is mounted, and an active area where liquid crystal pixels are arranged in an array. When a large number of source drivers are mounted as shown in Figure 4, the load on the fan-out area driven by one source driver is small, but in the case of a single-chip configuration as shown in Figure 5 or when the panel size increases, The load will increase. The source driver is required to drive while receiving such a load from the panel and display images on the display.

Next, FIG. 7 shows the driving timing of one source line of the liquid crystal panel. A source line with a small load (a line with a short COG wiring length) reaches the expected voltage level quickly, but a line with a large load (a line with a long COG wiring length) reaches the expected voltage level slowly. In the case of an FHD panel, the time for one horizontal line is 7.5 μs (in the case of a dual gate panel), so it is necessary to reach the expected voltage level within this time. However, in the case of a one-chip configuration as shown in FIG. 5 or when the panel size is large, the wiring load becomes larger, so there is a possibility that the expected value voltage level cannot be reached within this driving time.

Further, FIG. 8 shows the driving timing of the source line depending on the magnitude of the driving current (driving ability) of the source driver. When the drive current of the source driver is large, the expected value voltage level is reached quickly, but when the drive current is small, the expected value voltage level is reached slowly. This will affect the display quality if the expected voltage level is not reached. This is similar to the case where there is a difference in the COG wiring length shown in FIG. Furthermore, if the drive current is large, the power consumption of the panel will be large, and if the drive current is small, the power consumption of the panel will be small.

As described above, as the panel size increases, the load from the panel on the source line increases, and the source driver may not be able to drive the source line to the expected voltage level within a predetermined time. Additionally, as the resolution of the panel increases, the time required to drive one source line becomes shorter, so even if the load capacity of the panel's source line is the same, the source driver may not be able to drive the source line to the expected voltage level. . Furthermore, in a configuration in which the timing controller and source driver are integrated into one chip, the load capacitance of the source line of the panel that needs to be driven increases, and the source driver may not be able to drive the source line to the expected voltage level. As mentioned above, display panels such as LCD panels adjust the image brightness based on the voltage level of the analog voltage of the image data output by the source driver, so the output voltage of the source driver correctly reaches the expected value voltage level. Otherwise, problems will occur with display quality. Furthermore, for the same reason, if the drive current (drive capacity) of the source driver is small, a problem will arise in display image quality.

Low power consumption of panel systems is an important differentiating factor for notebook computers and smartphones. To address this issue, the source driver has been designed to increase the drive current of the entire source driver in advance to match the source line that physically has a large wiring load, so that it can be charged to the expected voltage level within one horizontal line. You can leave it as An example of a source line with a physically large wiring load is a line with a long COG wiring length, as described above. However, in that case, the power consumption of the panel increases because the drive current of the source driver increases. Another possible measure is to set the drive current to a large value in advance for source lines with a large panel load, and to set the drive current to a small value in advance for source lines with a small panel load. In this way, by adjusting the drive current for each source line according to the panel load and fixing the setting of the drive current, it is possible to optimize the power consumption of the panel system to some extent.

Furthermore, the applicant of the present application has proposed a circuit technology that minimizes the error in the driving voltage of a source driver (Patent Document 1). The data output device described in Patent Document 1 includes a source driver that drives a plurality of source lines of a display panel, and controls the source driver to overdrive the source lines for a predetermined period of time at a voltage level that exceeds an expected voltage level. The overdrive controller is equipped with an overdrive control section. The overdrive control unit includes an overdrive setting table in which an overdrive voltage and/or an overdrive time are set according to the difference in voltage level between the image data of the current horizontal line and the previous horizontal line. , has an overdrive setting control circuit that controls the overdrive voltage and overdrive time of the source line that drives the current horizontal line based on this overdrive setting table. By appropriately adjusting the overdrive setting voltage and setting time in this way, it is possible to improve the image quality of the liquid crystal panel.

JP2018-63332A

By the way, the image pattern of a display does not repeat the transition between high level and low level for each horizontal line, and in many cases, consecutive horizontal lines are at the same voltage level. As described above, in the conventional technology, the source driver sets a large drive current for a source line with a large panel load, and sets a small drive current for a source line with a small panel load. However, it has been difficult to identify image patterns in the same horizontal line and dynamically change the drive current of the source driver. This is because in the panel configuration of conventional notebook computers, the TCON and source driver are configured on separate chips as shown in Figure 1, and although the TCON can have an input pattern detection function, it actually drives the source line. The main reason for this is that it was difficult to flexibly control the drive current of the source driver because it was a separate chip from the source driver IC. If the drive current of the source driver can be dynamically optimized according to the image pattern, it can greatly contribute to reducing the power consumption of the panel system.

Note that, as in the data output device described in Patent Document 1, by dynamically setting a voltage (overdrive voltage) that exceeds the expected voltage level for a certain period of time within the time of one horizontal line, the rise is made steeper. This can speed up the time it takes to reach the expected voltage level. In order to control the source driver with an overdrive voltage, it is necessary to rapidly increase the drive current of the source driver, and there is a problem that power consumption increases accordingly. In addition, controlling the source driver with an overdrive voltage when the amount of change in voltage level is large, such as when the voltage level changes from the maximum value to the minimum value in a continuous horizontal line, improves the image quality of the LCD panel. Although it is effective in terms of the above, Patent Document 1 does not consider the case where there is no difference in voltage level between consecutive horizontal lines. In particular, in applications such as notebook computers and tablet computers, there are many cases where there is no difference in voltage level between consecutive horizontal lines, and in such cases, reducing power consumption is described in Patent Document 1, This was not achieved and this remained an issue. Furthermore, in a liquid crystal panel, not only when there is no difference in voltage level between all source driver channels on consecutive horizontal lines, but also when there is no difference in voltage level between some source driver channels on consecutive horizontal lines. Patent Document 1 does not consider suppressing power consumption.

Therefore, the present invention has been made to solve the problems of the conventional technology, and dynamically sets the drive current of the source driver to an optimal value, thereby reducing power consumption of the panel system and improving image quality. The main purpose is to realize the following.

The inventors of the present invention, as a result of intensive study on means for solving the problems of the prior art, temporarily stored video data of the current horizontal line and two or more previous horizontal lines in a memory. We have discovered that it is possible to reduce power consumption and improve image quality in panel systems by dynamically setting the drive current of the source driver for driving current horizontal lines based on the pattern of stored video data. Obtained. Based on the above knowledge, the present inventors came up with the idea that the problems of the prior art could be solved, and completed the present invention. Hereinafter, the configuration of the present invention will be specifically explained.

A first aspect of the present invention is a video data identification circuit. A video data identification circuit according to the present invention is a circuit for identifying video data output from a video data receiving circuit and controlling a drive current of a source driver. The video data identification circuit basically includes a memory, an image pattern detection circuit, and a drive current setting circuit. The memory stores video data of the current horizontal line and video data of n horizontal lines (n is an integer of 2 or more, the same applies hereinafter) before the current horizontal line among the video data output from the video data receiving circuit. and hold. In other words, at least three horizontal lines of video data are temporarily stored in the memory. The image pattern detection circuit first compares the video data of the current horizontal line and the video data of the immediately previous horizontal line to determine whether they match. If they match, the image pattern detection circuit transmits a signal indicating this to the drive current setting circuit. On the other hand, if they do not match, the image pattern detection circuit reads the image data pattern for n horizontal lines before the current horizontal line stored in the memory and transmits it to the current setting circuit. . Here, if the video data of the current horizontal line and the video data of the immediately previous horizontal line match, the drive current setting circuit determines, for example, the drive current of the source driver for driving the current horizontal line. should be set to the minimum level. On the other hand, if they do not match, the drive current setting circuit sets a current value for driving the current horizontal line based on the pattern of video data for n horizontal lines read out from the memory by the image pattern detection circuit. Set the source driver drive current. In other words, the drive current setting circuit determines the current Set the horizontal line drive current. The drive current setting value determined by the drive current setting circuit is output to the source driver. Note that the "minimum level" means a current value level that is smaller than the drive current when the video data of the current horizontal line and the video data of the immediately preceding horizontal line do not match, and is not zero. For example, if the drive current level can be set in five levels from 1 to 5, if the video data of the current horizontal line and the video data of the immediately preceding horizontal line do not match, A drive current is set to a level of 1, and when the video data of the current horizontal line and the video data of the immediately previous horizontal line match, the drive current is set to a level of 1 (ie, the minimum level). The minimum value of the drive current may be set to a level that prevents liquid crystal leakage, for example. Note that the "minimum level" of the drive current referred to here means the minimum level within the range that is controlled according to the comparison result of the current horizontal line and the previous horizontal line, and is the minimum level that is actually controlled by the source driver. may be driven at a current value smaller than the above-mentioned minimum level under different control.

As in the above configuration, when there is a difference in the driving voltage level between consecutive horizontal lines, the drive current (drive capacity) of the current horizontal line source driver is Optimization based on values is effective in improving image quality and reducing power consumption of liquid crystal panels. For example, a case will be described in which an 8-bit, 256-gradation liquid crystal panel is used, and the current horizontal line video data is a white level (255 level). For example, if the video data is at black level (0 level) in three consecutive horizontal lines, and immediately after that, the current horizontal line changes to white level (in the case of black, black, black, white), If the video data is at the white level for two consecutive horizontal lines, then the current horizontal line changes to the white level after it becomes the black level for one horizontal line (in the case of white, white, black, white) The drive current of the source driver required to drive the current horizontal line differs between the two. Therefore, by adjusting the drive current of the source driver when driving the current horizontal line based on the drive pattern of multiple horizontal lines before it, it is effective to optimize the power consumption of the LCD panel and improve the image quality. It is.

In the video data identification circuit according to the present invention, the image pattern detection circuit compares the video data of a specific portion that is part of the current horizontal line with the video data of a portion corresponding to the specific portion of the horizontal line immediately before the current horizontal line. It may also be determined whether or not they match. Examples of the "specific portion" are 50% of the left half of the liquid crystal panel, 50% of the right half, and x% of the left side and x% of the right side. If they do not match, the image pattern detection circuit detects the video data of the part corresponding to the above-mentioned specific part among the video data of n horizontal lines before the current horizontal line stored in the memory. Read out the pattern. Here, if the video data of a specific part of the current horizontal line and the video data of a part corresponding to the specific part of the immediately preceding horizontal line match, the drive current setting circuit, for example, What is necessary is to set the drive current of the source driver to the minimum level for driving a specific portion of the source driver. On the other hand, if they do not match, the drive current setting circuit, based on the pattern of the video data of the part corresponding to the specific part of n horizontal lines read from the memory by the image pattern detection circuit, Sets the source driver drive current to drive a specific portion of the current horizontal line.

As in the above configuration, even if the video data does not completely match in the entire two horizontal lines before and after, if the video data matches in a part of the two horizontal lines before and after, the match will occur. Power consumption can be suppressed by reducing the drive current of the source driver to the minimum level. For example, if there is no change in the source driver channel between the front and rear horizontal lines at 50% of the left half of the LCD panel screen, or if there is no change in the source driver channel between the front and rear horizontal lines at 25% of the left side of the screen, there may be a partial The drive current of the source driver may be set to the minimum level.

A second aspect of the invention relates to a panel system controller. A panel system controller according to the present invention includes a video data identification circuit, a video data reception circuit, and a source driver. The video data receiving circuit is related to the first aspect described above. The video data receiving circuit receives video data from an external processor (CPU or GPU) and outputs the video data to the video data identification circuit. The source driver is driven by a drive current set by the video data identification circuit and has a plurality of output channels that output video data at a predetermined voltage level to the source line of the display panel.

In the panel system controller according to the present invention, the video data identification circuit and the source driver are preferably configured as an integrated one-chip semiconductor device (system driver). Particularly, from the viewpoint of reducing the number of parts and power consumption, it is preferable that only one such one-chip semiconductor device be provided for the display panel. In such a single-chip configuration, as mentioned above, the load capacitance of the source line of the panel that needs to be driven becomes large, and the source driver cannot drive the source line to the expected voltage level, resulting in poor display image quality. There is a risk that problems may occur. In this regard, according to the present invention, since the drive current of the output of the source driver can be dynamically controlled, improvement in display image quality can be expected even with a one-chip configuration. Furthermore, by integrating the video data identification circuit, video data receiving circuit, and source driver, the signal transmission speed between each circuit can be increased, making it possible to flexibly control the drive current of the source driver. Become.

A third aspect of the present invention relates to a video data identification circuit different from the first aspect. The video data identification circuit according to the third aspect identifies the video data output from the video data receiving circuit and controls the drive current of the source driver. The video data identification circuit includes an image pattern detection circuit and a drive current setting circuit. The image pattern detection circuit compares the video data of a specific part of the current horizontal line with the video data of the part corresponding to the specific part of the immediately preceding horizontal line among the video data output from the video data receiving circuit. Determine whether or not it is correct. The drive current setting circuit drives the specific portion of the current horizontal line when the video data of the specific portion of the current horizontal line matches the video data of the portion corresponding to the specific portion of the horizontal line immediately before it. The drive current of the source driver for this purpose is set to the minimum level, and the set value is output to the source driver.

According to the present invention, it is possible to dynamically set the drive current of a source driver to an optimal value, thereby achieving lower power consumption and improved image quality in a panel system.

FIG. 1 is a block diagram showing the overall configuration of a display module in which a timing controller and a source driver are separated. FIG. 2 is a block diagram showing the overall configuration of a display module including two system drivers in which a timing controller and a source driver are integrated. FIG. 3 is a block diagram showing the overall configuration of a display module that includes only one system driver in which a timing controller and a source driver are integrated. FIG. 4 is a diagram showing wiring of source lines in a frame area (fan-out area) and an active area of a liquid crystal panel in a display module in which a timing controller and a source driver are separated. FIG. 5 is a diagram showing wiring of source lines in a frame area (fan-out area) and an active area of a liquid crystal panel in a display module in which a timing controller and a source driver are integrated. FIG. 6 is a diagram showing the distribution of wiring resistance and wiring capacitance of source line wiring of a liquid crystal panel. FIG. 7 is a diagram for explaining how the voltage of the source line changes depending on the magnitude of the wiring load of the liquid crystal panel (particularly the length of the wiring of the source line). FIG. 8 is a diagram for explaining how the voltage of the source line changes depending on the magnitude of the drive current of the source driver of the liquid crystal panel. FIG. 9 is a diagram for explaining the output voltage waveform for each source line when the voltage level of the horizontal line changes from the maximum value to the minimum value. FIG. 10 is a diagram for explaining the output voltage waveform for each source line when the voltage level of the horizontal line changes from the maximum value to the intermediate value. FIG. 11 is a diagram for explaining the output voltage waveform for each source line when the video data does not change during consecutive horizontal line periods. FIG. 12 is a block diagram schematically showing the overall configuration of a panel system controller according to an embodiment of the present invention. FIG. 13 is a flow diagram showing an example of the control logic of the source driver by the drive current setting circuit. FIG. 14 is a diagram showing the relationship between the output voltage waveform of the source driver and the drive current setting value in the present invention. FIG. 15 is a diagram showing the configuration of a general liquid crystal panel. FIG. 16 is a diagram illustrating an example of a method for controlling the current horizontal line driving capability based on a plurality of horizontal line image patterns stored in a memory. FIG. 17 is a diagram illustrating another example of the current method of controlling horizontal line driving capability based on a plurality of horizontal line image patterns stored in memory. FIG. 18 is a diagram showing an example of overdrive control. FIG. 19 is a diagram showing an example in which the drive level of the liquid crystal panel changes between a black level (minimum), a white level (maximum), and an intermediate level. FIG. 20 is a diagram showing an example of comparing the video data of the current horizontal line and the previous horizontal line on each of the left half and right half of the liquid crystal panel. FIG. 21 is a diagram showing an example of a case where the current horizontal line and video data of a plurality of horizontal lines stored in the memory are compared in a part of the horizontal lines of the liquid crystal panel.

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated using drawings. The present invention is not limited to the embodiments described below, but also includes modifications from the following embodiments as appropriate within the range obvious to those skilled in the art.

FIG. 12 shows a panel system controller 1 according to an embodiment of the present invention. The panel system controller 1 is an integrated circuit that can be mounted in a frame area of a display panel, such as a liquid crystal panel or an organic EL panel. The panel system controller 1 mainly outputs analog video signals to a large number of source lines constituting the panel 21, and also controls the video signals output to each source line. The panel system controller 1 contributes to lower power consumption of the panel system, for example in a notebook computer or a tablet computer, by optimizing the drive current of the source driver 13 in accordance with video data. Furthermore, the panel system controller 1 not only reduces the drive current of the source driver 13 to the minimum value, but also stops the clock signal to the source driver 13 and stops the video data to the source driver 13. It is also possible to disable the internal operation of the source driver 13 and reduce power consumption while the source driver 13 remains powered on.

The panel 21 has a general configuration and mainly includes a source line, a gate line, and display pixels. A plurality of source lines are provided in parallel to each other at predetermined intervals on a panel substrate made of glass or the like. A plurality of gate lines are provided on the same panel substrate in parallel to each other at predetermined intervals along a direction perpendicular to the source line. A display pixel is provided at each intersection of the source line and the gate line. A TFT (Thin Film Transistor) as a switching element is connected to each display pixel. For example, as shown in FIG. 15, an FHD liquid crystal panel requires 1920×3 (RGB) source lines and 1080 gate lines. The panel system controller 1 mainly performs processing for outputting video signals to source lines.

As shown in FIG. 12, the panel system controller 1 according to this embodiment includes a video data receiving circuit 11, a video data identification circuit 12, and a source driver 13. These circuits 11, 12, and 13 are preferably mounted on liquid crystal glass using a so-called COG (Chip On the Glass) method.

Further, in the panel system controller 1 of the present invention, the video data identification circuit 12 and the source driver 13 can be integrated into one semiconductor chip. If the video data identification circuit 12 and the source driver 13 are composed of separate semiconductor chips, data communication is required between them. For example, when the video data identification circuit 12 is implemented using a TCON (timing controller), it is required to transmit the drive current setting value of the source driver 13 detected by the TCON during a blanking period when no video data is displayed. . Further, after the drive current setting value of the source driver 13 transmitted during the blanking period is received by the source driver 13, the panel is driven with the changed drive current value only after changing the drive current of the source driver 13. become. In this way, the latency from when video data is input to the TCON until when the drive current of the source driver is changed becomes large. On the other hand, if the video data identification circuit 12 (TCON) and the source driver 13 are integrated into one semiconductor chip, the control can be performed within the same chip, and the latency can be reduced.

The video data receiving circuit 11 is a circuit for receiving digital video data and a clock signal from the processor. The video data receiving circuit 11 transmits the received video data to the video data identifying circuit 12. Further, the video data receiving circuit 11 shares the received clock signal with the video data identifying circuit 12 and the source driver 13. The video data receiving circuit 11 can be configured with a high-speed serial interface such as an eDP receiver circuit or a MIPI receiver circuit, for example. The video data input to the video data receiving circuit 11 is subjected to various arithmetic processing and graphics processing by a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) as shown in FIG. It is data.

The source driver 13 is a circuit for driving the source line of the panel 21. The source driver 13 is connected to a plurality of source lines and applies a driving voltage (gradation display voltage) to each source line. Although the panel system controller 1 can include a plurality of source drivers 13 for one panel 21, it is preferable to have only one source driver 13 for one panel 21 from the viewpoint of reducing the number of parts and power consumption. is suitable. Further, although not shown, the panel system controller 1 may include a gate driver that drives the gate line of the panel 21. However, the gate driver is not an essential component for the panel system controller 1 of the present invention, and it is also possible to arrange it outside the panel system controller 1. The gate driver sequentially applies a scanning signal to each gate line to turn on the TFT. When a driving voltage is applied from the source driver 13 to the source line while the TFT is in an on state due to an operation signal being applied to the gate line by the gate driver, charge is accumulated in the display element located at the intersection of the two. Thereby, the light transmittance of the display element changes according to the drive voltage applied to the source line, and an image is displayed through the display element. Further, the source driver 13 may have a function of overdriving each source line (see Patent Document 1).

The video data identification circuit 12 is a circuit for controlling the drive current setting of the source driver 13. The video data identification circuit 12 can determine appropriate drive current settings for each of the plurality of source lines coupled to the source driver 13. The drive current setting for the source driver 13 determined by the video data identification circuit 12 is input to the source driver 13 as a control signal. The source driver 13 controls driving of each source line according to the control signal input here. Further, the clock output from the video data receiving circuit 11 is input to the video data identification circuit 12 and the source driver 13, and serves as a reference clock for each internal circuit.

As shown in FIG. 1, in this embodiment, the video data identification circuit 12 includes a level detection circuit 121, a memory 122, an image pattern detection circuit 123, a drive current setting circuit 124, and a blanking period detection circuit 125. ing.

The level detection circuit 121 receives the digital video data output from the video data receiving circuit 11 and detects the analog voltage level of the source driver 13. That is, the source line level detection circuit 121 detects, based on the digital video data received by the video data receiving circuit 11, the level of the analog voltage output from the source driver 13 to each source line of the panel 21. The detection result of the source line level detection circuit 121 is outputted to the drive current setting circuit 124 as a control signal.

The memory 122 is a storage circuit for holding the video data output from the video data receiving circuit 11 for a predetermined period of time. Specifically, the memory 122 is set to be able to hold video data for a predetermined number of horizontal lines. Since the video data includes a horizontal synchronization signal for dividing the period of each horizontal line, the memory 122 is configured to hold video data for a predetermined number of horizontal lines based on this horizontal synchronization signal, for example. Just do it. Note that the length of video data that can be held in the memory 122 is limited to a predetermined value, and the memory 122 sequentially stores video data while sequentially deleting the same amount of video data. Furthermore, the predetermined number of horizontal lines that can be held in the memory 122 can be adjusted as appropriate by setting registers. In other words, the predetermined number can be changed for each arbitrary number of horizontal lines. Further, the video data held in the memory 122 can be one or more horizontal lines, such as one horizontal line or two horizontal lines, or less than one horizontal line, such as 1/2 horizontal line or 1/4 horizontal line. It is also possible to do this. For example, in the case of an FHD panel (1920x1080), one horizontal line has 1920 pixels, so the number of analog voltage output channels of the source driver 13 is 1920x3 (RGB) = 5760 channels. If the predetermined number of horizontal lines is less than one horizontal line, the predetermined number can also be specified by this number of output channels. For example, in the case of an FHD panel, a 1/2 horizontal line has 2880 channels, and a 1/4 horizontal line has 1440 channels.

In particular, in the present invention, the video data stored in the memory 122 is set to three or more horizontal lines. Specifically, in addition to the video data of the current horizontal line, the memory 122 stores video data of two or more horizontal lines before the current horizontal line. Note that when the current horizontal line video data is newly stored in the memory 122, the oldest horizontal line video data stored in the memory 122 is deleted. The video data to be stored in the memory 122 may be 4 or more horizontal lines including the current horizontal line, 5 or more horizontal lines, 6 horizontal lines, 7 horizontal lines, or more. There may be.

Note that with reference to FIG. 15, a general liquid crystal panel driving method will be described. Lines in the vertical direction are source lines for driving video data, and in the case of an FHD panel, 5760 lines are provided. Each of the 5760 source lines is driven by a source driver. The horizontal direction is called gate line, and there are 1080 lines in the case of an FHD panel. They are turned on sequentially in time from the 1st line in the upper direction to the 1080th line in the lower direction. A liquid crystal element is located at the intersection of the source line and the gate line, and video data is stored here. The operation timing is as follows: First, the gate line of the first line is turned on, all source lines are turned on, and video data is written to the liquid crystal elements of the first line, 5760 in total. Next, the first gate line is turned off, the second gate line is turned on, and all the source lines are similarly turned on, and video data is written to the second line of liquid crystal elements, 5760 in total. In this way, images are sequentially written to the liquid crystal element from the 1st line to the 1080th line.

The image pattern detection circuit 123 receives the current horizontal line of video data output from the video data receiving circuit 11 and the video data of a plurality of horizontal lines held in the memory 122. Then, the image pattern detection circuit 123 first compares the video data of the current horizontal line and the video data of the immediately previous horizontal line to detect matching of image patterns. At this time, the image pattern detection circuit 123 may detect that the image patterns match in all channels of the current horizontal line and the immediately preceding horizontal line, or may detect that the image patterns match between the current horizontal line and the immediately preceding horizontal line. , it is also possible to detect that the image patterns match for 1/2 horizontal line, or that the image patterns match for 1/4 horizontal line. The video data input to the image pattern detection circuit 123 includes current horizontal line video data input directly from the video data reception circuit 11 and past video data input from the video data reception circuit 11 via the memory 122. There are two types of video data of multiple horizontal lines. The current horizontal line video data from the video data receiving circuit 11 is input to the image pattern detection circuit 123 in real time. Note that at this time, the current horizontal line video data is also input to the memory 122 at the same time. On the other hand, the memory 122 temporarily stores video data for a plurality of horizontal lines before the current horizontal line. Therefore, past video data for a plurality of horizontal lines is input from the memory 122 to the image pattern detection circuit 123. Therefore, the image pattern detection circuit 123 receives the current horizontal line of video data from the video data receiving circuit 11 in real time, and receives the video data of a plurality of past horizontal lines from the memory 122. Then, the image pattern detection circuit 123 first compares the video data of the current horizontal line and the video data of the immediately previous horizontal line, and determines whether part or all of their image patterns match. . If the two image patterns match, it can be seen that at least the video data of the current horizontal line has not changed from the video data of the immediately previous horizontal line. The image pattern detection circuit 123 thus compares the current video data and the immediately previous video data, and if the two image patterns match, outputs the result to the drive current setting circuit 124 as a control signal. In this case, the drive current setting circuit 124 sets the drive current of the source driver that drives the current horizontal line to the minimum level, as will be described later.

On the other hand, when the image pattern detection circuit 123 compares the video data of the current horizontal line and the video data of the immediately previous horizontal line as described above and determines that the two image patterns do not match, Next, reads the pattern of video data for a plurality of past horizontal lines stored in the memory 122, and outputs the pattern as a control signal to the drive current setting circuit 124. In this case, as described later, the drive current setting circuit 124 sets the behavioral current of the source driver that drives the current horizontal line based on the pattern of video data for a plurality of past horizontal lines stored in the memory 122. This will be set.

The blanking period detection circuit 125 receives the video data output from the video data receiving circuit 11, and detects a blanking period from this video data. In addition to a vertical synchronization signal and a vertical synchronization signal, the video data includes a signal indicating a horizontal blanking period and a signal indicating a vertical blanking period. When the blanking period detection circuit 125 detects a horizontal blanking period or a vertical blanking period based on such video data, it outputs the detection result to the drive current setting circuit 124 as a control signal. Note that the blanking period detection circuit 125 may detect only the vertical blanking period, for example.

The drive current setting circuit 124 receives various control signals output from each of the level detection circuit 121, the image pattern detection circuit 123, and the blanking period detection circuit 125, and controls the source driver 13 based on these control signals. Set the drive current.

FIG. 13 shows an example of control logic by the drive current setting circuit 124. First, the drive current setting circuit 124 determines whether the current period is a blanking period based on a detection signal from the blanking period detection circuit 125. If it is a blanking period, the blanking period detection circuit 125 outputs the detection signal, so when the drive current setting circuit 124 receives this detection signal, it can determine that the current period is the blanking period. . During the blanking period, there is no need to output video data from the source driver 13 to the panel 21. Therefore, when the current blanking period is in progress, the drive current setting circuit 124 sets the drive current of the source driver 13 to the minimum level. The blanking period includes a horizontal blanking period and a vertical blanking period, but since the vertical blanking period is longer, the drive current of the source driver 13 is set to the minimum level during the vertical blanking period. is particularly effective. Similarly, the drive current of the source driver 13 can be kept at the minimum level during the horizontal blanking period as well.

Further, during the blanking period, in addition to setting the drive current of the source driver 13 to the minimum level, the drive current setting circuit 124 supplies a clock signal to the source driver 13 and inputs video data to the source driver 13. It is also possible to stop the supply. A switch circuit (not shown) that can cut off the signal line is provided in the signal line that supplies video data and a clock signal to the source driver 13, and the drive current setting circuit 124 is connected to these switch circuits. All you have to do is connect. This allows the drive current setting circuit 124 to control the supply of video data and clock signals to the source driver 13. By disabling the internal operation of the source driver 13 during the blanking period, it is possible to significantly reduce power consumption while the source driver 13 remains powered on. Note that the source driver 13 generally has an internal data latch, and as long as the power is on, even if the input clock signal or input video data is stopped, the video data is stored in the internal latch. remains retained. Therefore, even if the clock signal or input video data is stopped, the source driver 13 continues to output the video data of the internal latch, and no display problem occurs on the panel 21.

On the other hand, if it is not the blanking period, the drive current setting circuit 124 determines, based on the detection signal from the image pattern detection circuit 123, that the image patterns of the video data of the current horizontal line and the video data of the immediately previous horizontal line are aligned. Determine whether or not it is correct. If the two image patterns match, the image pattern detection circuit 123 outputs the detection signal, so when the drive current setting circuit 124 receives this detection signal, the current horizontal line and its It can be determined that the immediately previous image pattern matches. Specifically, when the video data of the current horizontal line and the immediately preceding horizontal line match, this indicates that there is no change in the voltage level of the source driver 13 from the immediately preceding horizontal line to the current horizontal line. In this case, the drive current setting circuit 124 can set the drive current to the minimum level in all output channels of the source driver 13.

Furthermore, when the detection signal from the image pattern detection circuit 123 indicates that the image patterns match across one horizontal line, the drive current setting circuit 124 determines whether When the image patterns match in all output channels, during the period when the image patterns match, in addition to setting the drive current of the source driver 13 to the minimum value, supplying a clock signal to the source driver 13. Alternatively, the supply of video data to the source driver 13 may be stopped. In this way, power consumption can be significantly reduced by disabling the internal operation of the source driver 13 while keeping the source driver 13 powered on with the minimum drive current. Note that if the period during which the image patterns match is less than one horizontal line, disabling the source driver 13 will make it impossible to display different parts of the image pattern. 13 continues to be supplied with video data and clock signals.

On the other hand, as described above, in notebook computers, there are often no differences in voltage levels between consecutive horizontal lines, and it is important to suppress power consumption even in such cases. For example, in a case where the image patterns match in the drive channels of all the source drivers of the two horizontal lines before and after, and the image patterns match in the drive channels of some source drivers of the two horizontal lines before and after, However, it is important to reduce power consumption. Therefore, the detection signal of the image pattern detection circuit 123 indicates, for example, that the image patterns match by 1/2 horizontal line or that the image patterns match by 1/4 horizontal line. In this case, the drive current setting circuit 124 can set the drive current to the minimum value only for the output channels corresponding to the portions where the image patterns match among all the output channels of the source driver 13. For example, in the case of an FHD panel (1920x1080), one horizontal line has 1920 pixels, so the number of analog voltage output channels of the source driver 13 is 1920x3 (RGB) = 5760 channels. 5760 channels of this source driver 13 are connected to source lines on the panel 21, respectively. Since the video data may be different for each output channel, the source driver 13 and the drive current setting circuit 124 are configured so that the drive current can be arbitrarily set for each output channel of the source driver 13. This makes it possible to optimize power consumption.

Next, as shown in FIG. 13, if it is not the blanking period and the image patterns do not match in the previous and subsequent horizontal lines, the drive current setting circuit 124 selects a plurality of past horizontal lines stored in the memory 122. Refer to the pattern of video data for the line. The control here will be explained with reference to FIGS. 16 and 17.

If there is a difference in the driving voltage level between the previous and next consecutive horizontal lines, the drive current of the source driver that drives the current horizontal line should be adjusted by considering the data values of multiple horizontal lines, including the previous horizontal line. Optimization is effective in improving the image quality of liquid crystal panels. Here, an 8-bit, 256-gradation liquid crystal panel will be described as an example. In the example shown in FIG. 16, the current horizontal line of video data is the fourth line in the figure, and is output at a white level (255 level). Furthermore, FIG. 16 shows a case where a change to the white level (current horizontal line) occurs immediately after the video data from the current horizontal line to three lines before has been at the black level three times in a row. . On the other hand, in FIG. 17, the video data of the current horizontal line is the 4th line in the figure, and the video data of the current horizontal line is set to the white level (255 level), but it is 3 lines before the current horizontal line. This example differs from the example shown in FIG. 16 in that the video data up to this point continuously changes from black level (0 level) to white level (255 level) to black level (0 level).

Here, in the examples shown in FIGS. 16 and 17, the memory 122 can record video data for four horizontal lines. That is, in addition to the video data of the current horizontal line, the video data of the previous three horizontal lines are sequentially recorded in the memory 122. In the example shown in FIG. 16, since the video data from the current horizontal line to three lines before can be stored in the memory, the drive current setting circuit 124 can refer to the memory 122 to select black, black, black, etc. A white pattern can be detected. Similarly, in the example shown in FIG. 17, the drive current setting circuit 124 can detect that the pattern is black, white, black, white by referring to the memory 122. In this way, with the 4-line memory, it is possible to consider the pattern of video data up to the past three lines.

In the example shown in FIG. 16, first, the black level video data of the first line is stored in the memory 122. At this time, since the black level video data of the first line is the first data, it cannot be compared with previous video data. In this case, the drive current of the source driver 13 for driving the first line may be set by simply referring to the video data of the first line itself. Next, the black level video data of the second line is stored in the memory 122. At this time, when the video data of the first line and the second line are compared, both have the same black level (255 level). Therefore, in this case, as described above, the drive current of the source driver 13 when operating the second line may be set to the minimum level. Next, the black level video data of the third line is stored in the memory 122. At this time, when the video data of the second line and the third line are compared, both have the same black level (0 level). Therefore, in this case as well, as described above, the drive current of the source driver 13 when operating the third line may be set to the minimum level.

Next, the video data of the fourth line of white level (255 level) is stored in the memory 122. As a result, video data for four horizontal lines is accumulated in the memory 122. At this time, when comparing the video data of the 3rd line and the 4th line, the 3rd line is at the black level, while the 4th line is at the white level. ) is not sufficient at the minimum level and must be made larger than this. That is, in a liquid crystal panel, even a transition from the same black level to white level may be affected by the data of the previous line. Therefore, when the current horizontal line reaches the white level (255 level) after the black level (0 level) continues for three horizontal lines, the source driver 13 that drives this current horizontal line is set to the target level at an early stage. In order to increase the voltage level to the expected value, for example, the drive current of the source driver 13 may be raised to the maximum level at once, or the overdrive voltage and time disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2018-63332) may be increased. It is preferable to multiply by (see FIG. 18).

On the other hand, in the example shown in FIG. 17, first, the black level video data of the first line is stored in the memory 122. At this time, since the black level video data of the first line is the first data, it cannot be compared with previous video data. In this case, the drive current of the source driver 13 for driving the first line may be set by simply referring to the video data of the first line itself. The process up to this point is the same as the example shown in FIG. Next, the white level video data of the second line is stored in the memory 122. At this time, when the video data of the first line and the second line are compared, they do not match each other. Furthermore, at this point, the memory 122 has not stored video data for a predetermined line. In this case, the drive current is adjusted according to the difference in voltage level between the previous horizontal line and the current horizontal line according to the flow shown in FIG. 13, but details regarding this point will be described later. Basically, due to the transition from the black level to the white level, it is necessary to set the drive current of the source driver 13 to a large value. Next, the black level video data of the third line is stored in the memory 122. At this time, when the video data of the second line and the third line are compared, they do not match each other. In this case as well, the drive current is adjusted according to the difference in voltage level between the previous horizontal line and the current horizontal line according to the flow shown in FIG. Basically, due to the transition from the white level to the black level, it is necessary to set the drive current of the source driver 13 to a large value.

Next, the video data of the fourth line of white level (255 level) is stored in the memory 122. As a result, video data for four horizontal lines is accumulated in the memory 122. At this time, when comparing the video data of the 3rd line and the 4th line, the 3rd line is at the black level, while the 4th line is at the white level. ) must also be increased. However, when comparing the example in FIG. 16 and the example in FIG. 17, in the example in FIG. 17, the second line was at the white level, so even if the third line was at the black level, the fourth line When raising the level to white, the second line is affected by the white level. Therefore, compared to the case where the white level is reached after three consecutive lines of black level as in the example of FIG. 16, in the example of FIG. 17, the source driver for outputting the white level of the fourth line is 13 drive current can be suppressed. That is, for the fourth line in the example of FIG. 17, the drive current of the source driver 13 may be set to a lower level than for the fourth line in the example of FIG. For example, if the drive current level is set to the maximum level (for example, 5 levels) in the example of FIG. 16, the drive current level may be set to a lower level than the maximum level (for example, 4 levels) in the example of FIG. . In this manner, the drive current of the source driver 13 that drives the current horizontal line can be controlled based on the pattern of video data for multiple lines stored in the memory 122. This is expected to reduce the power consumption of LCD panels and improve image quality.

To explain with yet another example, when driving a liquid crystal panel, it is necessary to consider not only the black level (0 level) and white level (255 level), but also the intermediate gradation level (for example, 125 level). . FIG. 19 shows an example of the transition of the drive current from the black level to the white level to the intermediate gradation level. Display at this intermediate gradation level (125 level) is generally said to be highly sensitive to human eyes. For example, if the video data of the current horizontal line is at the intermediate gradation level (125 level), and the video data from the current horizontal line to 3 horizontal lines before is all black level (0 level). , when the video data from the current horizontal line to three horizontal lines before changes like black level, intermediate gradation level, black level, drive the intermediate gradation level (125 level) level of the current horizontal line. The drive current of the source driver 13 required to do this differs. For example, assuming that the drive current level of the source driver 13 can be adjusted in five stages, the current horizontal line (intermediate level What is necessary is to set the drive current of the control level). Note that the setting example below is just an example, and the setting of the drive current can be adjusted as appropriate.
[Example of setting drive current level]
1) Black → Black → Black → Medium: Level 5 (maximum)
2) White → White → White → Medium: Level 5 (maximum)
3) Medium → White → White → Medium: Level 4
4) Medium → Black → Black → Medium: Level 4
5) Medium → White → Black → Medium: Level 4
6) Medium → Black → White → Medium: Level 4
7) Black → Medium → Black → Medium: Level 3
8) Black → Medium → White → Medium: Level 3
9) White → Medium → Black → Medium: Level 3
10) White → Medium → White → Medium: Level 3
11) Medium → Medium → Black → Medium: Level 2
12) Medium → Medium → White → Medium: Level 2
13) Black → Black → Medium → Medium: Level 1 (minimum)
14) White → White → Medium → Medium: Level 1 (minimum)
15) White → Black → Medium → Medium: Level 1 (minimum)
16) Black → White → Medium → Medium: Level 1 (minimum)
17) Black → Medium → Medium → Medium: Level 1 (minimum)
18) White → Medium → Medium → Medium: Level 1 (minimum)

Furthermore, the control method for setting the drive current of the source driver 13 that drives the current horizontal line based on the pattern of video data of a plurality of past horizontal lines is not limited to controlling the entire horizontal line; It can also be applied to some control of

Specifically, assuming control of the entire horizontal line, the number of channels of all source drivers that drive the liquid crystal panel is, for example, in the case of FHD, 1920x3 (R/G/B) = 5760 channels, and all It is compared whether the source driver channels of the current line and the previous line match, and if all source driver channels match, the driving ability of the source driver can be lowered for all channels. The present invention is not limited to this, and as shown in FIG. When the source driver channels match, the source driver drive current can be lowered by all channels in the left half of the screen by 50%. Similarly, for example, only in the 50% right half area of the screen of the LCD panel, compare the current line and the previous line to see if they match, and if all source driver channels in the right 50% of the screen match, the source driver The drive current for all channels in the right half of the screen can be lowered by 50%. Note that in the example of FIG. 20, the liquid crystal panel is divided into two areas of 50% left and right, but it is also possible to divide the liquid crystal panel into three areas or four or more areas and perform similar processing. It is. In this way, not only the entire screen matches, but also the LCD panel screen is divided into multiple areas, and if there is no change in the drive channels of the source drivers of the two lines before and after it, the drive power of the source driver will be reduced. can be reduced. Of course, if there is a change between the current line and the previous line, the driving ability of the source driver can be increased in accordance with the amount of change.

Furthermore, even in a mode in which the screen of the liquid crystal panel is divided into a plurality of regions and changes in video data are detected in each region, as explained with reference to FIGS. 16 and 17, the current horizontal line The drive current of the source driver that drives the current horizontal line can be optimized by taking into account the influence of the video data of a plurality of previous horizontal lines. That is, FIG. 21 shows a timing chart of the liquid crystal panel. For example, if the source driver has 5760 channels, the left half of the screen is source channels 1 to 2880 channels, and the right half of the screen is source channels 2881 to 5760 channels. In addition, in FIG. 21, d1 to d5760 are the video data of the current horizontal line, c1 to c5760 are the video data of the horizontal line immediately before the current horizontal line, and b1 to b5760 are the video data of the horizontal line two before the current horizontal line. The video data of the horizontal line, a1 to a5760, is the video data of the three horizontal lines before the current horizontal line. The video data for these four horizontal lines is stored in the memory 122. Further, d1 to d2880 are the video data corresponding to the left half of the screen of the liquid crystal panel among the current horizontal lines, and c1 to c2880, b1 to 2880, and a1 to a2880 are the past video data corresponding to the left half of the screen. This is horizontal line video data.

In this case, when setting the drive current of the source driver that outputs the video data d1 to d2880 corresponding to the left half of the screen among the current horizontal lines, it is necessary to It is sufficient to refer to the past horizontal line video data pattern corresponding to the left half of the screen. For example, assume that the video data d1 to d2880 corresponding to the left half of the fourth line and the video data c1 to c2880 corresponding to the left half of the third line do not match. In this case, the current fourth line is It is possible to determine the drive current of the source driver of d1 to d2880 corresponding to the left half of . Note that such partial drive current control can be performed not only for the left half of the screen but also for the right half of the screen.

Next, referring back to FIG. 13, the explanation will be given again. As shown in FIG. 13, if the image patterns do not match in the preceding and succeeding horizontal lines rather than during the blanking period, and the video data for a predetermined number of horizontal lines is not recorded in the memory 122, the drive current is set. The circuit 124 compares the voltage levels of the front and rear horizontal lines based on the detection value of the level detection circuit 121, and sets the drive current of the source driver 13 according to the difference between the voltage levels. For example, if the voltage level of the previous horizontal line is the maximum value and the voltage level of the current horizontal line is the minimum value, the difference between the voltage levels of both lines is the maximum. In this case, the drive current setting circuit 124 sets the drive current of the source driver 13 to the maximum value. Alternatively, even if the voltage level of the previous horizontal line is the maximum value, if the voltage level of the current horizontal line is an intermediate value, the difference between the voltage levels of both lines is intermediate. In this case, the drive current setting circuit 124 sets the drive current of the source driver 13 to a medium value.

FIG. 14 shows an example of a drive current setting operation by the drive current setting circuit 124. FIG. 14 shows an example of a change in the voltage level of a certain source line. This source line has a minimum voltage level during the vertical blanking period, then a maximum voltage level during the first horizontal line period, and the voltage level remains at the maximum value during the second horizontal line period. Then, in the third horizontal line period that follows, the voltage level becomes medium, in the fourth horizontal line period that follows, the voltage level again reaches the minimum value, and in the fifth horizontal line period that follows, the voltage level becomes medium. It reaches the maximum value again. Looking at the change in voltage level between each horizontal line period, the amount of change in voltage level is maximum in the first horizontal line period, the voltage level does not change in the second horizontal line period, and the amount of change in voltage level is the largest in the first horizontal line period, and the voltage level does not change in the second horizontal line period. In the period, the amount of change in the voltage level becomes medium, in the fourth horizontal line period, the amount of change in the voltage level becomes medium again, and in the fifth horizontal line period, the amount of change in the voltage level becomes the maximum again.

Then, the drive current setting circuit 124 sets the drive current of the source driver 13 according to the amount of change in this voltage level. Basically, the drive current of the source driver 13 is proportional to the amount of change in voltage level in each horizontal line period. That is, since the amount of change in voltage level is maximum during the first horizontal line period, the drive current of the source driver 13 is set to the maximum value. Furthermore, since the voltage level does not change during the second horizontal line period, the drive current of the source driver 13 is set to the minimum value. Furthermore, since the amount of change in the voltage level is moderate in the third horizontal line period, the drive current of the source driver 13 is set to an intermediate value. Furthermore, in the fourth horizontal line period, since the amount of change in the voltage level is again medium, the drive current of the source driver 13 is set to an intermediate value. Furthermore, since the amount of change in voltage level is maximum in the fifth horizontal line period, the drive current of the source driver 13 is set to the maximum value. Accordingly, for example, during the second horizontal line period in which the voltage level does not change, the drive current of the source driver 13 can be suppressed to the minimum value, so that power consumption can be suppressed. Further, since the drive current of the source driver 13 can be set by the amount necessary to maintain the display quality of the panel 21, unnecessary power consumption can be suppressed. In particular, since the drive current of the source driver 13 can be carefully adjusted for each horizontal line, the power consumption of the source driver 13 can be optimized.

As mentioned above, in this specification, in order to express the content of the present invention, embodiments of the present invention have been described with reference to the drawings. However, the present invention is not limited to the above-described embodiments, and includes modifications and improvements that are obvious to those skilled in the art based on the matters described in this specification.

1...Panel system controller 11...Video data receiving circuit 12...Video data identification circuit 121...Level detection circuit 122...Memory 123...Image pattern detection circuit 124...Drive current setting circuit 13...Source driver 21...Panel

Claims (5)

A video data identification circuit that identifies video data output from a video data receiving circuit and controls a drive current of a source driver,
Among the video data output from the video data receiving circuit, video data of the current horizontal line and video data of n horizontal lines (n is an integer of 2 or more, the same applies hereinafter) before the current horizontal line. and a memory that holds the
The video data of the current horizontal line and the video data of the immediately previous horizontal line are compared to determine whether they match, and if they do not match, the video data of the current horizontal line stored in the memory is an image pattern detection circuit that reads out a pattern of video data for n horizontal lines before the horizontal line;
A drive current of the source driver for driving the current horizontal line is set based on a pattern of video data for the n horizontal lines read out from the memory by the image pattern detection circuit, and the set value is set. A video data identification circuit comprising a drive current setting circuit that outputs to the source driver. The image pattern detection circuit includes:
Comparing video data of a specific portion that is part of the current horizontal line and video data of a portion corresponding to the specific portion of the immediately previous horizontal line to determine whether they match;
If they do not match, read out a pattern of video data of a portion corresponding to the specific portion among video data for n horizontal lines before the current horizontal line stored in the memory;
The drive current setting circuit is
driving the specific portion of the current horizontal line based on a pattern of video data of a portion corresponding to the specific portion of the n horizontal lines read out from the memory by the image pattern detection circuit; The video data identification circuit according to claim 1, further comprising: setting a drive current of a source driver. The video data identification circuit according to claim 1;
a video data receiving circuit that receives video data and outputs the video data to the video data identification circuit;
A panel system controller comprising a source driver having a plurality of output channels that are driven by a drive current set by the video data identification circuit and output the video data at a predetermined voltage level to a source line of a display panel. The panel system controller according to claim 3, wherein the video data identification circuit and the source driver are configured as an integrated one-chip semiconductor device. A video data identification circuit that identifies video data output from a video data receiving circuit and controls a drive current of a source driver,
Among the video data output from the video data receiving circuit, video data of a specific portion of the current horizontal line is compared with video data of a portion corresponding to the specific portion of the immediately previous horizontal line to determine whether they match. an image pattern detection circuit that determines whether the
If the video data of the specific portion of the current horizontal line and the video data of the portion corresponding to the specific portion of the immediately preceding horizontal line match, the specific portion of the current horizontal line is driven. A video data identification circuit comprising: a drive current setting circuit that sets a drive current of the source driver to a minimum level and outputs the set value to the source driver.

Images