CN116403542A

CN116403542A - Image data identification circuit and panel system controller

Info

Publication number: CN116403542A
Application number: CN202310464149.4A
Authority: CN
Inventors: 加藤雅弘; 长野英生; 山野要; 友国哲男; 牧野努
Original assignee: CEREBREX Inc
Current assignee: CEREBREX Inc
Priority date: 2022-04-26
Filing date: 2023-04-26
Publication date: 2023-07-07
Anticipated expiration: 2043-04-26
Also published as: JP2023162102A; TW202343408A; KR20230151899A; CN116403542B; JP7276948B1; KR102599528B1; TWI813531B

Abstract

The solution of the present invention is an image data recognition circuit (12) which recognizes image data outputted from an image data receiving circuit (11) to control a driving current of a source driver, and which comprises: a memory (122) for storing image data of a current horizontal line and image data of a plurality of previous horizontal lines among the image data; an image pattern detection circuit (123) which reads the pattern of the image data of a plurality of horizontal lines stored in the memory (122) when the image data of the current and previous horizontal lines are not identical; and a drive current setting circuit (124) for setting a drive current for driving the source driver (13) of the current horizontal line, based on the pattern of the image data of the plurality of horizontal lines read from the memory (122) by the image pattern detecting circuit (123).

Description

Image data identification circuit and panel system controller

Technical Field

The present invention relates to a panel system controller for outputting analog image data of a display panel and an image data recognition circuit included in the panel system controller. Specifically, the present invention relates to a circuit technique for minimizing an error in a driving voltage of a source driver.

Background

In the market of mobile devices such as notebook computers and tablet computers, there is a constant demand for reduction in power consumption and cost. On the other hand, with the improvement of resolution of a panel and the improvement of image quality of display, there is no increase in data processing amount and operation frequency, and reduction of power consumption and cost have become a major problem against the background. In a notebook computer or a tablet computer, a circuit for inputting a signal of drawing data to a display panel is composed of: a processor such as a CPU (Central Processing Unit ) or GPU (Graphics Processing Unit, graphics processing unit) that is responsible for the operation of drawing data itself or various arithmetic processing or graphics processing; a timing controller (Timing Controller: TCON) for performing timing control of the display panel or image processing with the drawing data transmitted from the processor as an input; and a Driver chip such as a Source Driver (SD) which takes the drawing data from the timing controller as an input and outputs the drawing data in a simulation manner in accordance with the type of the display panel.

In mobile devices such as notebook computers and tablet computers, the timing controller and the source driver are often separated. For example, in the case of the FHD (Full High Definition, full high definition: 1920×1080 pixels) display panel shown in FIG. 1, one timing controller and four source drivers are often required. In addition, in the case of a 4K2K panel (a panel having a resolution close to 4000×2000 pixels), there are many cases where one timing controller 1 and eight source drivers are required. Further, as shown in fig. 1, FPCs (Flexible Printed Cable, flexible printed cables) connecting the timing controller and the source drivers need to be matched with the number of source drivers, and as the panel resolution increases, the number of components increases, which is a factor of cost increase. Furthermore, although an interface is necessary between the timing controller and the source driver, the interface causes power consumption. Due to such background factors, the circuit configuration shown in fig. 1 is in a situation where it is difficult to reduce the cost and the power consumption.

Therefore, in order to reduce the number of components and power consumption, a so-called system driver (tcon+sd) in which the timing controller and the source driver as shown in fig. 2 and 3 form one chip may also be studied. Fig. 2 shows a configuration in which two system drivers are provided, and fig. 3 shows a configuration in which the system drivers are integrated into one. By the system driving, the number of components can be reduced and the cost can be reduced. Furthermore, since there is no interface between the timing controller and the source driver, power consumption can be reduced. In particular, from the viewpoint of the number of components and the reduction of power consumption, as shown in fig. 3, it may be said that only one system driver is preferable. However, the system driver is mounted on the glass of the liquid crystal panel in the same manner as the conventional source driver. Drawing data is then input from the processor (CPU/GPU) to the system driver directly via the eDP interface or mipi interface to the system driver.

The liquid crystal panel is composed of source lines and gate lines. In the case of the FHD panel, 1920×3 (RGB) lines are required for the source lines, and 1080 lines are required for the gate lines. The source lines are lines (data lines) for analog output of drawing data from the source driver, and are wired in parallel with each other with a predetermined interval therebetween. The gate lines are control lines for driving drawing data of the source lines while moving time by time for each gate line, and are wired in parallel with each other at predetermined intervals in a direction orthogonal to the source lines. Display pixels (pixels) are provided at respective intersections of the gate lines and the source lines. In addition, at present, a source driver or a system driver is mainly mounted on a liquid crystal glass, that is, a so-called COG (Chip On the Glass, flip-chip on glass) method.

As shown in fig. 4, in the case of a configuration in which four source drivers are arranged in the frame region and image data is output from these four source drivers to source lines on the display panel, the wiring load of COG required for driving one source driver may be small, and the difference in wiring length between the longest source line and the shortest source line may be small. However, as shown in fig. 5, in the case where only one system driver including a source driver and a timing controller is disposed in the frame region and image data is output from one source driver to all source lines on the display panel, the wiring load of COG required for driving the driver output is significantly increased and the difference in wiring length between the longest source line and the shortest source line is also increased. Display panels such as liquid crystal panels adjust the brightness of an image by the voltage level (potential) of the analog voltage of the image data output from the source driver. Therefore, if the output voltage of the source driver does not accurately reach the desired voltage level, a problem occurs in display such as a dark spot formed in a part of the panel.

Fig. 6 shows a model of wiring load of a source line of a liquid crystal panel. The liquid crystal panel is divided into a Fan-out Area (Fan-out Area) (corresponding to a frame Area) where the source driver is mounted and an Active Area (Active Area) where pixels of liquid crystal are arranged in an array. In the case where a plurality of source drivers are mounted as shown in fig. 4, although the load of the fan-out area driven by one source driver is small, the load becomes large if the size of the panel becomes large or the case of one chip configuration shown in fig. 5. The source driver is required to drive the display under the load of the panel, thereby displaying an image on the display.

Next, fig. 7 shows a driving timing of one source line of the liquid crystal panel. Although the source line with a small load (a line with a short COG wiring length) rapidly reaches the desired value voltage level, the line with a large load (a line with a long COG wiring length) slowly reaches the desired value voltage level. In the case of FHD panels, the desired voltage level needs to be reached during this time, since the time for one horizontal row is 7.5 mus (in the case of double gate panels). However, in the case of the one-chip configuration shown in fig. 5 or in the case of a large panel size, the wiring load is changed greatly, and therefore, there is a possibility that the desired voltage level cannot be reached within this driving time.

Fig. 8 shows a drive timing of the source line based on the magnitude of the drive current (drive capability) of the source driver. In the case where the driving current of the source driver is large, the desired value voltage level is rapidly reached, and in the case where the driving current is small, the desired value voltage level is slowly reached. This affects the display image quality when the desired voltage level is not reached. As in the case of the COG wiring length difference shown in fig. 7. Further, if the driving current is large, the power consumption of the panel increases, and if the driving current is small, the power consumption of the panel decreases.

As described above, if the panel size increases, the load on the source line from the panel increases, and the source driver may not be able to drive the source line to a desired voltage level for a predetermined time. In addition, if the resolution of the panel increases, the time for driving one source line becomes shorter, and therefore, even if the load capacitance of the source line of the panel is the same, the source driver may not be able to drive the source line to a desired voltage level. Further, in a configuration in which the timing controller and the source driver are provided as one chip, the load capacitance of the source line of the panel to be driven increases, and the source driver may not be able to drive the source line to a desired voltage level. As described above, since the display panel such as a liquid crystal panel adjusts the brightness of an image by the voltage level of the analog voltage of the image data outputted from the source driver, if the output voltage of the source driver does not accurately reach the desired voltage level, a problem occurs in the display image quality. In addition, in the case where the driving current (driving capability) of the source driver is small, the display image quality is problematic for the same reason.

In a notebook computer or a smart phone, a reduction in power consumption of a panel system is an important differentiation index. In order to solve the above problem, the drive current of the entire source driver can be increased in advance by matching the source line with a physically large wiring load in the source driver, and the source driver can be charged to a desired voltage level within one horizontal line. An example of a source line with a physically large wiring load is a row with a long COG wiring length as described above. However, in this case, since the driving current of the source driver becomes large, the power consumption of the panel becomes large. As another countermeasure, it is also conceivable that the drive current is set to be large in advance for the source line with a large panel load and to be small in advance for the source line with a small panel load. In this way, by adjusting the driving current according to the panel load and by each source line and fixing the setting of the driving current, the power consumption of the panel system can be rationalized to some extent.

In addition, the applicant of the present application has proposed a circuit technique that minimizes an error in the driving voltage of the source driver (patent document 1). The data output device described in patent document 1 includes: a source driver driving a plurality of source lines of the display panel; and an overdrive control section that controls the source driver to overdrive the source line at a voltage level exceeding a desired value voltage level for a predetermined time. The overdrive control unit includes: an overdrive setting table that sets either or both of overdrive voltage and overdrive time in accordance with a difference in voltage level of image data of a current horizontal line and a previous horizontal line thereof; and an overdrive setting control circuit that controls an overdrive voltage and an overdrive time for driving the source line of the current horizontal line based on the overdrive setting table. By appropriately adjusting the overdrive voltage and the overdrive time in this manner, the image quality of the liquid crystal panel can be improved.

Prior art literature

Patent literature

Patent document 1: japanese patent application laid-open No. 2018-63332

Disclosure of Invention

Problems to be solved by the invention

However, the image pattern of the display does not repeatedly transition to a high level or a low level between each horizontal line, and the continuous horizontal lines continue to the same voltage level in many cases. As described above, in the prior art, the source driver sets the drive current to a large value in the source line with a large panel load, and reduces the drive current in the source line with a small panel load. However, in the same horizontal line, it is difficult to recognize an image pattern and dynamically change the driving current of the source driver. The main reason for this is that the conventional panel structure of the notebook computer is composed of separate chips as the TCON and the source driver shown in fig. 1, and the TCON can have an input pattern detection function, but the actual source line is driven by a different chip from the source driver IC, so that it is difficult to flexibly control the driving current of the source driver. As long as the driving current of the source driver can be dynamically optimized according to the image pattern, the power consumption of the panel system can be greatly reduced.

In the data output device described in patent document 1, a voltage (overdrive voltage) exceeding a desired value voltage level is dynamically set for a certain fixed time within a single horizontal line amount time, so that the rise can be made steep, and the time to reach the desired value voltage level can be made faster. In order to control the source driver with the overdrive voltage, it is necessary to rapidly increase the driving current of the source driver, and accordingly there is a problem that the power consumption increases. In addition, for example, in a case where the amount of change in the voltage level is large, such as when the voltage level changes from the maximum value to the minimum value in successive horizontal lines, controlling the source driver with the overdrive voltage is effective in improving the image quality of the liquid crystal panel, but in patent document 1, no study is made of a case where no difference occurs in the voltage level in successive horizontal lines. In particular, in the use of a notebook computer or a tablet computer, there are many cases where there is no difference in voltage level between successive horizontal lines, and in such cases, it is not possible to achieve suppression of power consumption by the data output device described in patent document 1. In addition, in the liquid crystal panel, not only in the case where the voltage levels of the channels of all the source drivers do not differ in consecutive horizontal lines, but also in the case where the voltage levels of the channels of some of the source drivers do not differ in consecutive horizontal lines, suppression of power consumption has not been studied in patent document 1.

The present invention has been made to solve the problems of the conventional art, and its main object is to dynamically set the driving current of the source driver to an optimum value, thereby achieving a reduction in power consumption and an improvement in image quality of the panel system.

Means for solving the problems

The inventors of the present invention have conducted intensive studies on a solution to the problems of the prior art, and as a result, have found the following findings: the image data of the current horizontal line and the first two or more horizontal lines are temporarily stored in a memory, and the driving current for driving the source driver of the current horizontal line is dynamically set based on the pattern of the image data stored in the memory, thereby reducing the power consumption of the panel system and improving the image quality. The present inventors have also conceived that the problems of the conventional techniques can be solved based on the above-described findings, and have completed the present invention. The constitution of the present invention will be specifically described below.

The first side of the invention is an image data identification circuit. The image data recognition circuit of the present invention is a circuit for recognizing the image data outputted from the image data receiving circuit to control the driving current of the source driver. The image data recognition circuit basically includes a memory, an image pattern detection circuit, and a drive current setting circuit. The memory stores video data of a current horizontal line and video data of n horizontal line amounts (n is an integer of 2 or more, and the same applies hereinafter) preceding the current horizontal line among the video data outputted from the video data receiving circuit. That is, at least three horizontal lines of image data are temporarily stored in the memory. The image pattern detection circuit first compares the image data of the current horizontal line with the image data of the previous horizontal line and determines whether or not the image data are identical. When the video data match, the image pattern detection circuit transmits a signal indicating the match to the drive current setting circuit. On the other hand, in the case where the image data does not match, the image pattern detection circuit reads the pattern of the image data of n horizontal line amounts stored before the current horizontal line of the memory, and transmits the pattern to the current setting circuit. Here, when the image data of the current horizontal line and the image data of the previous horizontal line match, the drive current setting circuit may set the drive current of the source driver for driving the current horizontal line to the minimum level, for example. On the other hand, in the case where the image data does not match, the drive current setting circuit sets the drive current for driving the source driver of the current horizontal line based on the pattern of the image data of n horizontal line amounts read from the memory by the image pattern detecting circuit. That is, the drive current setting circuit sets the drive current of the present horizontal line based not only on the relationship between the present horizontal line and the image data of the immediately preceding horizontal line, but also on the pattern of the image data of a plurality of horizontal lines preceding the present horizontal line. The set value of the driving current determined by the driving current setting circuit is outputted to the source driver. The "minimum level" is a level of a current value which is smaller than the drive current and is non-zero when the video data of the current horizontal line and the video data of the previous horizontal line do not match. For example, in the case where the level of the driving current can be set to five levels of one to five, the driving current is set to two to five levels in the case where the image data of the current horizontal line and the image data of the previous horizontal line do not coincide, and the driving current is set to one level (i.e., the minimum level) in the case where the image data of the current horizontal line and the image data of the previous horizontal line coincide. The minimum value of the drive current may be, for example, a level that prevents leakage of the liquid crystal. Here, the "minimum level" of the driving current refers to a minimum level within a range controlled based on a comparison result between the current horizontal line and the previous horizontal line, and in practice, there may be a case where the source driver is driven at a current value smaller than the minimum level in other control.

In the case where the voltage levels for driving in successive horizontal lines are different as described above, the driving current (driving capability) of the source driver in the current horizontal line is optimized by the value of the video data in the first few lines including the previous line, and this is effective in improving the image quality of the liquid crystal panel and reducing the power consumption. For example, in the case of an 8-bit 256-gradation liquid crystal panel, the case where the video data of the current horizontal line is at the white level (255 levels) will be described as an example. For example, in a case where video data is continuously black level (0 level) in three horizontal lines and the current horizontal line immediately after it is changed to white level (in a case of black, white), and in a case where video data is continuously white level in two horizontal lines and then is black level in only one horizontal line, then the current horizontal line is changed to white level (in a case of white, black, white), the driving current of the source driver required to drive the current horizontal line is different. Therefore, by adjusting the driving current of the source driver for driving the current horizontal line based on the driving patterns of the previous horizontal lines, it is effective to optimize the power consumption of the liquid crystal panel and to improve the image quality.

In the image data identifying circuit of the present invention, the image pattern detecting circuit may compare the image data of a specific portion which is a portion of the current horizontal line with the image data of a portion corresponding to the specific portion which is a portion of the previous horizontal line, and determine whether or not the image data are identical. Examples of the "specific portion" are left half 50% or right half 50%, other left x% or right x% of the liquid crystal panel. When the image data does not match, the image pattern detection circuit reads the image data pattern of the portion corresponding to the specific portion among the n horizontal line amounts of image data stored in the memory before the current horizontal line. Here, when the image data of the specific portion of the current horizontal line and the image data of the portion corresponding to the specific portion of the previous horizontal line match, the drive current setting circuit may set the drive current of the source driver for driving the specific portion of the current horizontal line to the minimum level, for example. On the other hand, in the case where the image data does not match, the drive current setting circuit sets the drive current of the source driver for driving the specific portion of the current horizontal line based on the pattern of the image data of the portion corresponding to the specific portion of the n horizontal line amounts read from the memory by the image pattern detecting circuit.

Even if the image data does not completely match the entire front and rear horizontal lines as in the above configuration, when the image data matches a part of the front and rear horizontal lines, the power consumption can be suppressed by setting the driving current of the source driver to the minimum level at the matched part. For example, in the case where the channel of the left 50% source driver of the liquid crystal panel is not changed in the front-rear horizontal line or in the case where the channel of the left 25% source driver is not changed in the front-rear horizontal line, the driving current of the source driver may be set to the minimum level locally.

The second aspect of the invention relates to a panel system controller. The panel system controller of the present invention includes an image data recognition circuit, an image data receiving circuit, and a source driver. The image data receiving circuit is the image data identifying circuit of the first side. The image data receiving circuit receives image data from an external processor (CPU or GPU) and outputs the image data to the image data identifying circuit. The source driver is driven by a driving current set by the image data recognition circuit, and has a plurality of output channels for outputting image data to source lines of the display panel at a predetermined voltage level.

In the panel system controller of the present invention, it is preferable that the image data recognition circuit and the source driver are integrated into a single chip semiconductor device (system driver). In particular, from the viewpoint of reducing the number of components and power consumption, it is preferable to provide only one such chip-type semiconductor device for the display panel. In such a chip-type configuration, as described above, the load capacitance of the source line of the panel to be driven increases, and the source driver cannot drive the source line to a desired voltage level, which may cause a problem in display quality. In this regard, according to the present invention, since the driving current of the output of the source driver can be dynamically controlled, improvement of the display quality can be expected even with a single chip type configuration. In addition, by integrating the image data recognition circuit, the image data receiving circuit, and the source driver, the signal transmission speed between the circuits can be increased, and thus the driving current of the source driver can be flexibly controlled.

A third aspect of the present invention relates to an image data recognition circuit different from the first aspect. The image data recognition circuit of the third side recognizes the image data outputted from the image data receiving circuit to control the driving current of the source driver. The image data recognition circuit includes an image pattern detection circuit and a drive current setting circuit. The image pattern detection circuit compares the image data of the specific portion of the current horizontal line with the image data of the portion corresponding to the specific portion of the previous horizontal line among the image data outputted from the image data reception circuit and determines whether or not the image data are identical. In the case where the image data of the specific portion of the current horizontal line and the image data of the portion corresponding to the specific portion preceding the current horizontal line are identical, the drive current setting circuit sets the drive current of the source driver for driving the specific portion of the current horizontal line to the minimum level and outputs the set value thereof to the source driver.

Effects of the invention

According to the present invention, the driving current of the source driver can be dynamically set to an optimum value, thereby achieving low power consumption and improved image quality of the panel system.

Drawings

Fig. 1 is a block diagram showing the overall configuration of a display module in which a timing controller and a source driver are separated;

fig. 2 is a block diagram showing the overall configuration of a display module including two system drivers integrating a timing controller and a source driver;

fig. 3 is a block diagram showing the overall configuration of a display module including only one system driver integrating a timing controller and a source driver;

fig. 4 is a diagram showing wirings of source lines in a frame region (fan-out region) and an effective region of a liquid crystal panel in a display module in which a timing controller and a source driver are separated;

fig. 5 is a diagram showing wirings of source lines in a frame region (fan-out region) and an effective region of a liquid crystal panel in a display module in which a timing controller and a source driver are integrated;

fig. 6 is a diagram showing distribution of wiring resistance and wiring capacitance of wirings of source lines of a liquid crystal panel;

fig. 7 is a diagram for explaining how the voltage of the source line varies by the magnitude of the wiring load of the liquid crystal panel (in particular, the length of the wiring of the source line);

Fig. 8 is a diagram for explaining how the voltage of the source line varies by the magnitude of the driving current of the source driver of the liquid crystal panel;

fig. 9 is a diagram for explaining an output voltage waveform of each source line in a case where the voltage level of the horizontal line is changed from the maximum value to the minimum value;

fig. 10 is a diagram for explaining an output voltage waveform of each source line in a case where the voltage level of the horizontal line is changed from the maximum value to the intermediate value;

fig. 11 is a diagram for explaining an output voltage waveform of each source line in a case where image data is not changed during consecutive horizontal lines;

FIG. 12 is a block diagram schematically showing the overall construction of a panel system controller according to an embodiment of the present invention;

fig. 13 is a flowchart showing an example of control logic of the source driver by the drive current setting circuit;

fig. 14 is a diagram showing a relationship between an output voltage waveform of a source driver and a driving current set value in the present invention;

fig. 15 is a diagram showing a structure of a general liquid crystal panel;

fig. 16 is a diagram showing an example of a method of controlling the driving capability of the current horizontal line based on the image patterns stored in the plurality of horizontal lines of the memory;

FIG. 17 is a diagram showing another example of a method of controlling the driving capability of the current horizontal line based on the image patterns of the plurality of horizontal lines stored in the memory;

fig. 18 is a diagram showing an example of overdrive control;

fig. 19 is a diagram showing an example of a case where the driving level of the liquid crystal panel is shifted to a black level (minimum), a white level (maximum), and a halftone level;

fig. 20 is a diagram showing an example of a case where image data of a current horizontal line and image data of a previous horizontal line are compared in a left half and a right half of a liquid crystal panel, respectively;

fig. 21 is a diagram showing an example of a case where video data of a current horizontal line and a plurality of horizontal lines stored in a memory are compared with each other in a part of the horizontal lines of a liquid crystal panel.

Description of the reference numerals

1: panel system controller

11: image data receiving circuit

12: image data identification circuit

121: level detection circuit

122: memory device

123: image pattern detection circuit

124: drive current setting circuit

13: source driver

21: panel board

Detailed Description

Hereinafter, modes for carrying out the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments, and includes embodiments appropriately modified within the scope of the present invention apparent to those skilled in the art from the following embodiments.

Fig. 12 shows a panel system controller 1 according to an embodiment of the present invention. The panel system controller 1 is an integrated circuit that can be mounted in a frame region of a display panel typified by a liquid crystal panel or an organic EL panel. The panel system controller 1 mainly outputs analog video signals to a plurality of source lines constituting the panel 21, and performs control related to the video signals output to the respective source lines. The panel system controller 1 optimizes the driving current of the source driver 13 in response to the image data in a notebook computer or a tablet computer, for example, and thereby contributes to the reduction of the power consumption of the panel system. The panel system controller 1 can stop the clock signal to the source driver 13 or stop the image data to the source driver 13 in addition to the minimum driving current of the source driver 13, thereby also stopping the internal operation of the source driver 13 and reducing the power consumption while keeping the power of the source driver 13 on.

The panel 21 has a normal structure and mainly includes source lines, gate lines, and display pixels. The source lines are provided in parallel with each other at predetermined intervals on a panel substrate made of glass or the like. The gate lines are disposed in parallel to each other at predetermined intervals along a direction orthogonal to the source lines on the same panel substrate. The display pixels are disposed at the intersections of the source lines and the gate lines. Each display pixel is connected to a TFT (Thin Film Transistor ) as a switching element. For example, as shown in fig. 15, in the case of the FHD liquid crystal panel, 1920×3 (RGB) lines are required for the source lines, and 1080 lines are required for the gate lines. The panel system controller 1 mainly performs processing for outputting video signals to source lines.

As shown in fig. 12, the panel system controller 1 of the present embodiment includes an image data receiving circuit 11, an image data recognizing circuit 12, and a source driver 13. These

circuits

11, 12, 13 are preferably mounted on liquid crystal glass in a so-called COG (Chip On the Glass, chip on glass) mode.

In the panel system controller 1 of the present invention, the image data recognition circuit 12 and the source driver 13 may be integrated into one semiconductor chip. If the image data recognition circuit 12 and the source driver 13 are formed of separate semiconductor chips, data communication is required between the two. For example, in the case where the video data recognition circuit 12 is implemented by TCON (timing controller), it is required to transmit the driving current set value of the source driver 13 detected by TCON in the blanking period in which the video data is not displayed. The driving current set value of the source driver 13 transmitted in the blanking period is received by the source driver 13, and then the driving current of the source driver 13 is changed, and finally the panel is driven with the changed driving current value. In this way, a delay from when the video data is input TCON to when the driving current of the source driver is changed becomes large. In contrast, if the video data recognition circuit 12 (TCON) and the source driver 13 are integrated in one semiconductor chip, the same chip is controlled, and the delay can be reduced.

The video data receiving circuit 11 is a circuit for receiving digital video data and a clock signal from a processor. The image data receiving circuit 11 transmits the received image data to the image data identifying circuit 12. The video data receiving circuit 11 shares the received clock signal with the video data identifying circuit 12 and the source driver 13. The image data receiving circuit 11 may be constituted by a high-speed serial interface such as an eDP receiver circuit or an MIPI receiver circuit. The image data input to the image data receiving circuit 11 is data obtained by performing various arithmetic processing or graphics processing by a processor such as a CPU (Central Processing Unit ) or GPU (Graphics Processing Unit, graphics processing unit) shown in fig. 1.

The source driver 13 is a circuit for driving source lines of the panel 21. The source driver 13 is connected to a plurality of source lines, and applies a driving voltage (gradation display voltage) to each source line. The panel system controller 1 may include a plurality of source drivers 13 for one panel 21, but from the viewpoint of reducing the number of components and power consumption, it is preferable to include only one source driver 13 for one panel 21. Although not shown, the panel system controller 1 may include a gate driver for driving gate lines of the panel 21. However, the gate driver is not necessarily configured for the panel system controller 1 of the present invention, and may be disposed outside the panel system controller 1. The gate driver sequentially applies a scanning signal for turning on the TFT to each gate line. When an operation signal is applied to the gate line by the gate driver and the TFT is turned on, a driving voltage is applied to the source line from the source driver 13, and thus charges are accumulated in the display element located at the intersection. Accordingly, the light transmittance of the display element changes according to the driving voltage applied to the source line, and image display is performed through the display element. The source driver 13 may also have a function of overdriving each source line (see patent document 1).

The image data recognition circuit 12 is a circuit for controlling the driving current setting of the source driver 13. The image data recognition circuit 12 can determine the appropriate driving current setting for each of the source lines coupled to the source driver 13. The driving current setting of the source driver 13 determined by the image data recognition circuit 12 is inputted to the source driver 13 as a control signal. The source driver 13 controls driving of each source line in accordance with a control signal input thereto. The clock output from the video data receiving circuit 11 is input to the video data identifying circuit 12 and the source driver 13, and is used as a clock for each internal circuit.

As shown in fig. 12, in the present embodiment, the image data recognition circuit 12 is configured by a level detection circuit 121, a memory 122, an image pattern detection circuit 123, a drive current setting circuit 124, and a blanking period detection circuit 125.

The level detection circuit 121 receives the digital video data output from the video data reception circuit 11, and detects the analog voltage level of the source driver 13. That is, the level detection circuit 121 detects at which level the analog voltage of each source line output from the source driver 13 to the panel 21 is based on the digital video data received by the video data receiving circuit 11. The detection result of the level detection circuit 121 is output to the drive current setting circuit 124 as a control signal.

The memory 122 is a storage circuit for storing the video data outputted from the video data receiving circuit 11 for a predetermined period. Specifically, the memory 122 is configured to store a predetermined number of horizontal lines of video data. Since the video data includes a horizontal synchronization signal for dividing the period of each horizontal line, the memory 122 may store a predetermined number of video data of the horizontal line in accordance with the horizontal synchronization signal, for example. The length of the video data that can be stored in the memory 122 is limited by a predetermined value, and the memory 122 sequentially deletes the same amount as the video data while sequentially storing the video data. In addition, the predetermined number of horizontal lines that can be stored in the memory 122 can be appropriately adjusted by setting registers. That is, the predetermined number may be changed for every arbitrary number of horizontal lines. In addition, the image data stored in the memory 122 may be set to one horizontal line or more, for example, one horizontal line or two horizontal lines, or may be set to less than one horizontal line, for example, 1/2 horizontal line or 1/4 horizontal line. In the case of an FHD panel (1920×1080), for example, the output channel number of the analog voltage of the source driver 13 is 1920×3 (RGB) =5760 channels because of one horizontal line of 1920 pixels. In the case where the predetermined number of horizontal lines is smaller than one horizontal line, the predetermined number may be specified by using the number of output channels. For example, in the case of FHD panels, 1/2 horizontal behavior 2880 channels, 1/4 horizontal behavior 1440 channels.

In particular, in the present invention, the video data stored in the memory 122 is set to three horizontal lines or more. Specifically, the memory 122 stores therein image data of two or more horizontal lines preceding the current horizontal line in addition to image data of the current horizontal line. In the case where the image data of the current horizontal line is newly stored in the memory 122, the image data of the oldest horizontal line stored in the memory 122 is deleted. The image data stored in the memory 122 may be four or more horizontal lines including the current horizontal line, five or more horizontal lines, six or seven or more horizontal lines.

A driving method of a normal liquid crystal panel will be described with reference to fig. 15. The vertical lines are source lines for driving image data, and 5760 lines are provided in the case of the FHD panel. 5760 source lines are driven by source drivers, respectively. The FHD panel has 1080 lines in the case of a lateral direction called gate lines. Sequentially switching on from the first line in the upper direction to the 1080 line in the lower direction in time sequence. A liquid crystal element is provided at a position where the source line and the gate line intersect, and image data is stored therein. In terms of operation timing, first, the first gate line is turned on, all the source lines are turned on, and image data is written into the total 5760 liquid crystal elements in the first row. Next, the first gate line is turned off, the second gate line is turned on, and all the source lines are similarly turned on, so that image data is written into 5760 liquid crystal elements in the second row. Thus, images are written in the liquid crystal element sequentially from the first to 1080 th stripes.

The image pattern detection circuit 123 receives the image data of the current horizontal line outputted from the image data reception circuit 11 and the image data of a plurality of horizontal lines stored in the memory 122. Then, the image pattern detection circuit 123 first compares the image data of the current horizontal line with the image data of the previous horizontal line, and detects the consistency of the image pattern. At this time, the image pattern detection circuit 123 may detect that the image pattern is uniform in all channels of the current horizontal line and the previous horizontal line thereof, or may detect that the image pattern is uniform only in 1/2 horizontal line amount among the current horizontal line and the previous horizontal line thereof or that the image pattern is uniform only in 1/4 horizontal line amount. The image data input to the image pattern detection circuit 123 includes the following two types of data: image data of the current horizontal line directly input from the image data receiving circuit 11; and the past plural horizontal lines of image data temporarily input from the image data receiving circuit 11 via the memory 122. Then, the image data of the current horizontal line from the image data receiving circuit 11 is input to the image pattern detecting circuit 123 in real time. At this time, the image data of the current horizontal line is also input to the memory 122. On the other hand, the memory 122 temporarily stores a plurality of horizontal lines of image data that are more than the current horizontal line. Accordingly, the past image data of a plurality of horizontal lines is input from the memory 122 to the image pattern detection circuit 123. Accordingly, the image pattern detection circuit 123 receives the image data of the current horizontal line from the image data reception circuit 11 in real time, and receives the image data of a plurality of horizontal lines from the memory 122. Then, the image pattern detection circuit 123 first compares the image data of the current horizontal line with the image data of the previous horizontal line, and determines whether or not a part or all of the image patterns of both match. Then, if the image patterns of the two are identical, it is at least known that the image data of the current horizontal line is not changed from the image data of the previous horizontal line. When the current image data and the previous image data are compared in this way and the image patterns of the two are identical, the image pattern detection circuit 123 outputs the result as a control signal to the drive current setting circuit 124. In this case, as described later, the driving current setting circuit 124 sets the driving current of the source driver driving the present horizontal line to the minimum level.

On the other hand, when the image pattern detection circuit 123 determines that the image patterns of the current horizontal line and the image data of the previous horizontal line are not identical as a result of comparing the image data of the current horizontal line with the image data of the previous horizontal line as described above, then the image pattern detection circuit reads the image data of the previous horizontal lines stored in the memory 122, and outputs the image data as a control signal to the drive current setting circuit 124. In this case, as described later, the drive current setting circuit 124 sets the drive current of the source driver for driving the current horizontal line based on the pattern of the image data of the past plurality of horizontal lines stored in the memory 122.

The blanking period detection circuit 125 receives the image data output from the image data reception circuit 11, and detects a blanking period from the image data. The video data includes a signal indicating a horizontal blanking period and a signal indicating a vertical blanking period in addition to the horizontal synchronization signal and the vertical synchronization signal. When the horizontal blanking period and the vertical blanking period are detected based on such image data, the blanking period detection circuit 125 outputs the detection results to the drive current setting circuit 124 as control signals. Further, the object detected by the blanking period detection circuit 125 may be set to, for example, only the vertical blanking period.

The drive current setting circuit 124 receives various control signals output from the level detection circuit 121, the image pattern detection circuit 123, and the blanking period detection circuit 125, and sets the drive current of the source driver 13 based on these control signals.

Fig. 13 shows an example of control logic performed by the drive current setting circuit 124. First, the drive current setting circuit 124 determines whether or not the blanking period is now a blanking period based on the detection signal from the blanking period detection circuit 125. If the blanking period is detected, the blanking period detection circuit 125 outputs the detection signal, and thus the drive current setting circuit 124 can determine that the blanking period is now detected when receiving the detection signal. In the blanking period, the source driver 13 does not need to output video data to the panel 21. Therefore, in the case of the blanking period now, the drive current setting circuit 124 sets the drive current of the source driver 13 to the minimum level. Although the horizontal blanking period and the vertical blanking period exist in the blanking period, the vertical blanking period is long, and therefore it is particularly effective to set the driving current of the source driver 13 to the minimum level in the vertical blanking period. Similarly, the driving current of the source driver 13 can be set to the minimum level in the horizontal blanking period.

In addition, the driving current setting circuit 124 may stop the supply of the clock signal to the source driver 13 or stop the supply of the video data to the source driver 13, in addition to setting the driving current of the source driver 13 to the minimum level in the blanking period. A switching circuit (not shown) capable of cutting off the signal line of the signal line is provided in advance on the signal line for supplying the video data or the signal line for supplying the clock signal to the source driver 13, and the driving current setting circuit 124 may be connected to these switching circuits. Accordingly, the driving current setting circuit 124 can control the supply of the video data or the clock signal to the source driver 13. The internal operation of the source driver 13 is also disabled during the blanking period, and thus the power consumption can be greatly reduced while the power supply of the source driver 13 is kept on. The source driver 13 generally has a data latch therein, and when the power is turned on, even if the clock signal is stopped or the video data is stopped, the video data is still stored in the latch therein. Therefore, even when the clock signal is stopped or the video data is inputted, the video data of the internal latch is continuously outputted from the source driver 13, and no problem occurs in display on the panel 21.

On the other hand, in the case of the non-blanking period, the drive current setting circuit 124 determines whether or not the image pattern of the image data of the current horizontal line and the image data of the previous horizontal line coincide based on the detection signal from the image pattern detection circuit 123. If the image patterns match, the image pattern detection circuit 123 outputs a detection signal, and thus the drive current setting circuit 124 can determine that the image pattern of the current horizontal line matches the image pattern of the previous horizontal line when receiving the detection signal. Specifically, in the case where the image data of the current horizontal line and the previous horizontal line thereof are identical, it means that the voltage level of the source driver 13 does not change from the previous horizontal line to the current horizontal line. In this case, the driving current setting circuit 124 may set the driving current to the minimum level in all the output channels of the source driver 13.

In addition, in a case where the detection signal from the image pattern detection circuit 123 indicates that the image pattern is identical in the whole of one horizontal line, that is, in a case where the image pattern is identical in all the output channels of the previous horizontal line and the current horizontal line, the drive current setting circuit 124 may stop the supply of the clock signal to the source driver 13 or the supply of the video data to the source driver 13 in addition to setting the drive current of the source driver 13 to the minimum value during the period in which the image pattern is identical. In this way, the internal operation of the source driver 13 is disabled while the power supply of the source driver 13 is kept on with the minimum drive current, and thus the power consumption can be greatly reduced. If the period during which the image patterns match is smaller than one horizontal line, the source driver 13 is deactivated, and a different portion of the image pattern cannot be displayed, so that the image data or the clock signal is continuously supplied to the source driver 13 in this case.

On the other hand, as described above, in a notebook computer, there are many cases where there is no difference in voltage level among successive horizontal lines, and it is also important to suppress power consumption in such an example. Suppressing power consumption is also important in the following examples: for example, in addition to the case where the image pattern is uniform in the driving channels of the source drivers of all of the front and rear horizontal lines, there is also the case where the image pattern is uniform in the driving channels of the source drivers of a part of the front and rear horizontal lines. Therefore, in a case where the detection signal of the image pattern detection circuit 123 indicates that the image pattern is uniform in only the 1/2 horizontal line amount or the image pattern is uniform in only the 1/4 horizontal line amount, for example, the drive current setting circuit 124 may set the drive current to the minimum value only in the output channel corresponding to the portion in which the image pattern is uniform among all the output channels of the source driver 13. For example, in the case of the FHD panel (1920×1080), since one horizontal line is 1920 pixels, the output channel number of the analog voltage of the source driver 13 is 1920×3 (RGB) =5760 channels. 5760 channels of the source driver 13 are connected to source lines on the panel 21, respectively. Since the image data may be different for each output channel, the source driver 13 and the drive current setting circuit 124 are configured to set the drive current arbitrarily for each output channel of the source driver 13, so that the power consumption can be optimized more finely.

Next, as shown in fig. 13, in the case where the image pattern is not uniform in the front-rear horizontal lines in the non-blanking period, the drive current setting circuit 124 refers to the pattern of the image data of the past plural horizontal lines stored in the memory 122. The control herein will be described with reference to fig. 16 and 17.

In the case where the voltage levels for driving in successive horizontal lines are different, it is effective in improving the image quality of the liquid crystal panel to optimize the driving current of the source driver for driving the current horizontal line in consideration of the values of the data of the first several horizontal lines including the previous horizontal line. Here, an 8-bit 256-gradation liquid crystal panel will be described as an example. In the example shown in fig. 16, the video data of the current horizontal line is set to the fourth line in the figure, and output at the white level (255 levels). Fig. 16 shows a case where the video data from the current horizontal line to the first three lines is changed to the white level (current horizontal line) immediately after being black level three times in succession. On the other hand, in fig. 17, similarly, the image data of the current horizontal line is set to the fourth line in the figure, and the image data of the current horizontal line is set to the white level (255 levels), but this is different from the example shown in fig. 16: the video data from the current horizontal line to the first three lines is continuously changed in black level (0 level), white level (255 level), and black level (0 level).

Here, in the example shown in fig. 16 and 17, image data of four horizontal lines may be recorded in the memory 122. That is, the memory 122 sequentially records video data of the first three horizontal lines in addition to video data of the current horizontal line. In the example shown in fig. 16, since the image data from the current horizontal line to the first three lines can be stored in the memory, the driving current setting circuit 124 can detect the pattern as black, and white by referring to the memory 122. In the example shown in fig. 17, the drive current setting circuit 124 can detect black, white, black, and white patterns by referring to the memory 122. Thus, the pattern of the image data up to the previous three lines can be considered in the four-line memory.

In the example shown in fig. 16, first, the image data of the black level of the first line is stored in the memory 122. At this time, since the image data of the black level of the first line is the first data, it cannot be compared with the previous image data. In this case, the driving current of the source driver 13 for driving the first line may be set simply by referring to the image data itself of the first line. Next, the image data of the black level of the second line is stored in the memory 122. At this time, when the image data of the first line and the second line are compared, the black level (level 0) is uniform. Thus, in this case, as described above, the driving current of the source driver 13 driving the second row may be set to the minimum level. Next, the image data of the black level of the third line is stored in the memory 122. At this time, when the image data of the second line and the third line are compared, the black level (level 0) is uniform. Accordingly, in this case, as well, the driving current of the source driver 13 for driving the third row may be set to the minimum level.

Next, the white level (255 levels) image data of the fourth row is stored in the memory 122. Thus, four parallel amounts of video data are stored in the memory 122. At this time, when comparing the image data of the third line and the fourth line, the third line is at a black level and the fourth line is at a white level, so that the driving current of the source driver 13 driving the fourth line (the current horizontal line) is insufficient at the minimum level, and must be set to be larger than this level. That is, in the liquid crystal panel, even if the same transition is made from the black level to the white level, the data of the previous row may be affected. Accordingly, in the case where the current horizontal line is set to the white level (255 levels) after continuously continuing the black level (0 levels) among the three horizontal lines, in order to advance the source driver 13 driving this current horizontal line to the target desired value voltage level, it is preferable to, for example, once raise the driving current of the source driver 13 to the maximum level, or to apply the overdrive voltage and time disclosed in patent document 1 (japanese patent application laid-open No. 2018-63332) (see fig. 18).

On the other hand, in the example shown in fig. 17, first, the image data of the black level of the first line is stored in the memory 122. At this time, since the image data of the black level of the first line is the first data, it cannot be compared with the previous image data. In this case, the driving current of the source driver 13 for driving the first line may be set simply by referring to the image data itself of the first line. The above is the same as in fig. 16. Next, the image data of the white level of the second line is stored in the memory 122. At this time, if the image data of the first line and the second line are compared, they do not coincide with each other. At this time, the memory 122 stores no predetermined line amount of video data. In this case, the flow shown in fig. 13 is followed, and the driving current is adjusted according to the difference between the voltage level of the previous horizontal line and the voltage level of the current horizontal line, details of which will be described later. Basically, the driving current of the source driver 13 needs to be set large due to the transition from the black level to the white level. Next, the image data of the black level of the third line is stored in the memory 122. At this time, if the image data of the second line and the third line are compared, they do not coincide with each other. In this case, the flow shown in fig. 13 is also followed, and the driving current is adjusted according to the difference of the voltage level of the previous horizontal line and the current horizontal line. Basically, the driving current of the source driver 13 needs to be set large due to the transition from the white level to the black level.

Next, the white level (255 levels) image data of the fourth row is stored in the memory 122. Thus, four parallel amounts of video data are stored in the memory 122. At this time, when comparing the image data of the third row and the fourth row, the third row is at a black level and the fourth row is at a white level, so that the driving current of the source driver 13 driving the fourth row (the current horizontal row) must also be increased. However, in the case of comparing the example of fig. 16 and the example of fig. 17, since the second row is at the white level in the example of fig. 17, even if the third row is at the black level, the fourth row is affected by the white level of the second row when the fourth row is raised to the white level. Therefore, in the example of fig. 17, the driving current of the source driver 13 for outputting the white level of the fourth row can be suppressed, as compared with the case where three rows continue to be black and then become white as shown in the example of fig. 16. That is, the fourth row of the example of fig. 17 may be set to a smaller level of driving current of the source driver 13 than the fourth row of the example of fig. 16. For example, in the example of fig. 16, when the level of the driving current is set to the maximum level (for example, five levels), in the example of fig. 17, the level of the driving current may be set to a level smaller than the maximum level (for example, four levels). In this way, the driving current of the source driver 13 driving the current horizontal line can be controlled based on the pattern of the image data of the plurality of lines stored in the memory 122. Thus, it is expected to reduce the power consumption of the liquid crystal panel and improve the image quality.

As another example, not only the black level (0 level) and the white level (255 level) but also the intermediate gray level (e.g., 125 level) are considered for driving the liquid crystal panel. Fig. 19 shows an example of such a transition of the driving current to the black level, the white level, and the intermediate gradation level. This intermediate gray level (125 level) display is generally highly sensitive to the human eye. For example, when the image data of the current horizontal line is at the intermediate gradation level (125 levels), the driving current of the source driver 13 required for driving the intermediate gradation level (125 levels) of the current horizontal line is different between the case where all the image data from the current horizontal line to the first three horizontal lines are at the black level (0 levels) and the case where the image data from the current horizontal line to the first three horizontal lines are changed in such a manner that the image data is at the black level, the intermediate gradation level, and the black level. For example, when it is assumed that the level of the driving current of the source driver 13 can be adjusted in five levels, the driving current of the current horizontal line (intermediate gradation level) may be set as follows, taking into consideration the image pattern of the past horizontal line stored in the memory 122. The following setting examples are merely examples, and the setting of the driving current can be appropriately adjusted.

[ setting example of drive Current level ]

1) Black → black black → middle: grade five (maximum)

2) White→white→middle: grade five (maximum)

3) Middle- →white- →middle: grade four

4) Middle- →black- →middle-: grade four

5) Middle- →white- →black- →middle: grade four

6) Middle- > black- > white- > middle: grade four

7) Black→middle→black→middle: grade three

8) Black- & gt middle- & gt white- & gt middle: grade three

9) White→medium→black→medium: grade three

10 White→ middle→ white→ middle: grade three

11 Middle- & gt, black- & gt, middle- & gt: grade two

12 Middle→white→middle: grade two

13 Black→black→medium→medium: grade one (minimum)

14 White→white→medium→medium: grade one (minimum)

15 White→black→medium→medium: grade one (minimum)

16 Black- →white- →medium: grade one (minimum)

17 Black → middle → middle- & gt: grade one (minimum)

18 White → middle → middle- & gt: grade one (minimum)

The control method for setting the driving current for driving the source driver 13 of the current horizontal line based on the pattern of the image data of the plurality of previous horizontal lines is not limited to the control of the entire horizontal line, and may be applied to the control of a part of the horizontal line.

Specifically, in the case of assuming control of the entire horizontal line, the number of channels of all source drivers for driving the liquid crystal panel is 1920×3 (R/G/B) =5760 channels in the case of FHD, for example, and the driving capability of the source drivers can be reduced in all channels by comparing whether all source driver channels are identical in the current line and the previous line or not, and in the case where all source driver channels are identical. As shown in fig. 20, for example, if the current line and the previous line are identical in comparison with each other only in the region of 50% of the left half of the screen of the liquid crystal panel, and if all the source driver channels of 50% of the left half of the screen are identical, the driving current of the source driver may be reduced only in all the channels of 50% of the left half of the screen. Similarly, for example, if the comparison is made only in the region of 50% of the right half of the screen of the liquid crystal panel as to whether the source driver channels are identical in the current row and the previous row, the driving current of the source driver can be reduced only in the entire channels of 50% of the right half of the screen in the case where all the source driver channels are identical in the right half of the screen. In the example of fig. 20, the liquid crystal panel is divided into two regions of about 50%, but the liquid crystal panel may be divided into three regions or four or more regions and subjected to the same process. In this way, not only in the case where the entire screen is uniform, but also in the case where the screen of the liquid crystal panel is divided into a plurality of areas and the driving channels of the source drivers in all of the front and rear rows are unchanged, the driving power of the source drivers can be reduced. Of course, in the case where there is a change in the current row and the previous row, the driving capability of the source driver may be increased according to the amount of change thereof.

In the case where the screen of the liquid crystal panel is divided into a plurality of areas and the change in the video data is detected in each area as described above with reference to fig. 16 and 17, the driving current of the source driver driving the current horizontal line may be optimized in consideration of the influence of the video data of a plurality of horizontal lines preceding the current horizontal line. That is, fig. 21 shows a timing chart of the liquid crystal panel. For example, in the case where the number of channels of the source driver is 5760 channels, the left half of the screen is the source driver channels 1 to 2880, and the right half of the screen is the source driver channels 2881 to 5760. In fig. 21, d1 to d5760 are video data of the current horizontal line, c1 to c5760 are video data of the previous horizontal line of the current horizontal line, b1 to b5760 are video data of the horizontal line two lines before the current horizontal line, and a1 to a5760 are video data of the horizontal line three lines before the current horizontal line. These four horizontal lines of image data are stored in the memory 122. Further, d1 to d2880 are video data corresponding to the left half of the screen of the liquid crystal panel among the current horizontal lines, and c1 to c2880, b1 to b2880, and a1 to a2880 are video data corresponding to the left half of the screen of the liquid crystal panel.

In this case, when setting the driving current of the source driver outputting the video data d1 to d2880 corresponding to the left half of the screen among the current horizontal lines, the pattern of the previous horizontal line video data c1 to c2880, b1 to b2880, and a1 to a2880 corresponding to the left half of the screen may be referred to. For example, it is assumed that the image data d1 to d2880 corresponding to the left half of the fourth line and the image data c1 to c2880 corresponding to the left half of the third line do not match. In this case, the driving currents of the source drivers d1 to d2880 corresponding to the left half of the current fourth line may be determined based on the patterns (c 1 to c2880, b1 to b2880, a1 to a 2880) of the image data corresponding to the left half stored in the first to third lines of the memory 122. The drive current control is not limited to the left half of the screen, and such local drive current control may be similarly performed for the right half of the screen.

Next, the description will be returned to fig. 13 again. As shown in fig. 13, in the case where the image pattern is not uniform in the front and rear horizontal lines during the non-blanking period and the image data of the predetermined number of horizontal lines is not recorded in the memory 122, the drive current setting circuit 124 compares the voltage levels of the front and rear horizontal lines based on the detection value of the level detection circuit 121 and sets the drive current of the source driver 13 according to the difference in the voltage levels. For example, in the case where the voltage level of the previous horizontal line is the maximum value and the voltage level of the current horizontal line is the minimum value, the difference in the voltage levels of the two lines is the largest. In this case, the drive current setting circuit 124 sets the drive current of the source driver 13 to the maximum value. Alternatively, even if the voltage level of the previous horizontal line is the maximum value, in the case where the voltage level of the current horizontal line is the intermediate value, the difference in the voltage levels of the two lines is moderate. In this case, the drive current setting circuit 124 sets the drive current of the source driver 13 to a moderate value.

Fig. 14 shows an example of the setting operation of the drive current by the drive current setting circuit 124. Fig. 14 shows an example of a change in the voltage level of a certain source line. The source line has a minimum voltage level in the vertical blanking period, and then has a maximum voltage level in the first horizontal line, a maximum voltage level in the next second horizontal line, a middle voltage level in the next third horizontal line, a minimum voltage level in the next fourth horizontal line, and a maximum voltage level in the next fifth horizontal line. When the change in the voltage level in each horizontal line period is observed, the amount of change in the voltage level is largest in the first horizontal line, the voltage level is unchanged in the second horizontal line, the amount of change in the voltage level is medium in the third horizontal line, the amount of change in the voltage level is medium again in the fourth horizontal line, and the amount of change in the voltage level is largest again in the fifth horizontal line.

Then, the driving current setting circuit 124 sets the driving current of the source driver 13 according to the amount of change in the voltage level. Basically, the driving current of the source driver 13 is proportional to the amount of change in the voltage level in each horizontal line period. That is, the variation amount of the voltage level is maximum during the first horizontal line, and thus the driving current of the source driver 13 is set to the maximum value. In addition, the voltage level does not change during the second horizontal line, so the driving current of the source driver 13 is set to a minimum value. In addition, the amount of change in the voltage level during the third horizontal line is moderate, and thus the driving current of the source driver 13 is set to an intermediate value. In addition, the amount of change in the voltage level during the fourth horizontal line is again medium, so the driving current of the source driver 13 is set to the intermediate value. In addition, the variation amount of the voltage level is maximum during the fifth horizontal line, and thus the driving current of the source driver 13 is set to the maximum value. Thus, for example, during the second horizontal line in which the voltage level does not change, the driving current of the source driver 13 can be suppressed to the minimum value, and thus the power consumption amount can be suppressed. In addition, since the driving current of the source driver 13 can be set to an amount necessary to maintain the display quality of the panel 21, unnecessary power consumption can be suppressed. In particular, the driving current of the source driver 13 can be finely adjusted for each horizontal line, and thus the power consumption of the source driver 13 can be optimized.

In the above description, in order to present the content of the present invention, the embodiments of the present invention are described with reference to the drawings. However, the present invention is not limited to the above-described embodiments, and includes modifications and improvements that will be apparent to those skilled in the art based on the matters described in the present specification.

Claims

1. An image data recognition circuit for recognizing image data outputted from an image data receiving circuit to control a driving current of a source driver, comprising:

a memory that stores video data of a current horizontal line and video data of n horizontal lines preceding the current horizontal line among the video data outputted from the video data receiving circuit, wherein n is an integer of 2 or more and the same as below;

an image pattern detection circuit that compares the image data of the current horizontal line with the image data of the previous horizontal line thereof and determines whether or not the image data are identical, and in the case where the image data are not identical, reads the pattern of the image data of n horizontal line amounts stored before the current horizontal line of the memory; and

and a drive current setting circuit that sets a drive current for driving the source driver of the current horizontal line based on the pattern of the image data of the n horizontal line amounts read from the memory by the image pattern detecting circuit, and outputs a set value of the drive current to the source driver.

2. The image data recognition circuit according to claim 1, wherein the image pattern detection circuit compares image data of a specific portion which is a portion of the current horizontal line with image data of a portion corresponding to the specific portion of a previous horizontal line thereof and determines whether or not the image data are identical, and,

in the case where the image data does not match, a pattern of image data of a portion corresponding to the specific portion among image data of n horizontal lines of the image data stored before the current horizontal line of the memory is read,

the driving current setting circuit sets a driving current of the source driver for driving the specific portion of the current horizontal line based on a pattern of image data of a portion corresponding to the specific portion of the n horizontal line amounts read from the memory by the image pattern detecting circuit.

3. A panel system controller, comprising:

the image data recognition circuit of claim 1;

an image data receiving circuit that receives image data and outputs the image data to the image data identifying circuit; and

and a source driver which is driven by the driving current set by the image data recognition circuit and has a plurality of output channels for outputting the image data to the source lines of the display panel at a predetermined voltage level.

4. The panel system controller according to claim 3, wherein the image data recognition circuit and the source driver are formed of a semiconductor device of one integrated chip.

5. An image data recognition circuit for recognizing image data outputted from an image data receiving circuit to control a driving current of a source driver, comprising:

an image pattern detection circuit that compares image data of a specific portion of a current horizontal line among the image data output from the image data reception circuit with image data of a portion corresponding to the specific portion of a previous horizontal line thereof, and determines whether or not the image data are identical; and

and a drive current setting circuit that sets a drive current of the source driver for driving the specific portion of the current horizontal line to a minimum level and outputs a set value of the drive current to the source driver, in a case where image data of the specific portion of the current horizontal line and image data of a portion corresponding to the specific portion of a previous horizontal line thereof are identical.