JP2023119414A - Switching circuit, current detection circuit, switching timing control method, and control program - Google Patents

Abstract

To provide a switching circuit capable of equalizing an input/output current of a bridge circuit having a plurality of legs connected in parallel by switching timing control.SOLUTION: A switch circuit includes: a bridge circuit including a plurality of legs connected in parallel, each of the legs including a first arm having a switching element and a second arm having the switching element or a reversely connected diode connected in series; a control circuit configured to perform power conversion by performing switching control of the switching element of each of the legs; an inductor provided between a connection point of the first arm and the second arm of each leg and a coupling point for coupling the connection point of each leg; and a connection point voltage detection circuit for detecting a voltage of the connection point of each leg. The control circuit adjusts switching timing of the switching element based on a time change rate of the voltage detected by the connection point voltage detection circuit.SELECTED DRAWING: Figure 1

Description

Applied for application of Article 30, Paragraph 2 of the Patent Act. Published on pages 113-118 of Study Group-2 (https://www.bookpark.ne.jp/cm/ieej/detail/IEEJ-20210302X05701-020-PDF/ https://www.bookpark.ne.jp/cm/ieej/detail/IEEJ-20210302X05701-020-PDF/ jp/cm/ieej/detail/IEEJ-20210302X05701-PDF/) On March 2, 2021, in "Power Technology in General and Semiconductor Power Conversion in General" of the Joint Study Group on Power Technology/Power System Technology/Semiconductor Power Conversion published by

The present invention relates to a switching circuit, a current detection circuit, a switching timing control method, and a control program.

2. Description of the Related Art A power converter equipped with a half-bridge circuit configured using a power semiconductor device is used in a wide range of fields such as industry, electric power, household appliances, and mobile objects such as automobiles and railways (for example, Patent Document 1). In power converters that handle large currents, devices are generally connected in parallel because the current capacity of a single power semiconductor device is insufficient.

JP 2019-29763 A

However, due to variations in device characteristics, variations in wiring parasitic inductance, and the like, current imbalance may occur between the power semiconductor devices connected in parallel, causing problems. Measures such as selection of power semiconductor devices with uniform device characteristics and symmetrical wiring can be considered, but problems such as an increase in cost and a decrease in the degree of freedom in design arise.
The problem of current imbalance can also occur in an interleaved circuit in which bridge circuits are connected in parallel.

An object of the present disclosure is to provide a switching circuit capable of equalizing input and output currents of a bridge circuit having multiple legs connected in parallel by switching timing control, a current detection circuit used in the switching circuit, and switching timing control. It is to provide a method and a control program.

A switching circuit according to an aspect of the present disclosure includes a plurality of legs in which a first arm having a switching element and a second arm having a switching element or a reverse-connected diode are connected in series, and the plurality of legs are A bridge circuit connected in parallel, a control circuit for controlling switching of the switching elements of each leg, a connection point between the first arm and the second arm of each leg, and a connection point that connects the connection points of each leg. and a connection point voltage detection circuit that detects the voltage at the connection point of each leg, the control circuit based on the time rate of change of the voltage detected by the connection point voltage detection circuit. to adjust the switching timing of the switching element.

A current detection circuit according to an aspect of the present disclosure includes a leg in which a first arm having a switching element and a second arm having a switching element or a reverse-connected diode are connected in series to detect current in a bridge circuit. a current detection circuit comprising: an inductor connected in series to a connection point of a first arm and a second arm; a connection point voltage detection circuit for detecting voltage at the connection point of the leg; and the connection point voltage detection circuit and an arithmetic circuit for calculating the current flowing through the leg based on the time rate of change of the detected voltage.

A switching timing control method according to an aspect of the present disclosure includes a plurality of legs in which a first arm having a switching element and a second arm having a switching element or a reverse-connected diode are connected in series, and a plurality of the A switching circuit comprising a bridge circuit formed by connecting legs in parallel, and an inductor provided between a connection point of a first arm and a second arm of each leg and a connection point connecting the connection points of each leg. In the switching timing control method of 1, the voltage at the connection point of each leg is detected, and the switching timing of the switching element is adjusted based on the time rate of change of the detected voltage.

A control program according to an aspect of the present disclosure includes a plurality of legs in which a first arm having a switching element and a second arm having a switching element or a reverse-connected diode are connected in series, and the plurality of legs are A switching circuit comprising a bridge circuit connected in parallel, an inductor provided between a connecting point of a first arm and a second arm of each leg, and a connecting point connecting the connecting points of each leg. A control program for causing a computer to execute timing control, wherein the computer detects the voltage at the connection point of each leg and adjusts the switching timing of the switching element based on the time rate of change of the detected voltage. to execute the process to be performed.

According to the present disclosure, switching timing control can equalize input and output currents of a bridge circuit having a plurality of legs connected in parallel.

2 is a circuit block diagram showing a configuration example of a switching circuit according to Embodiment 1; FIG. 4 is a timing chart showing temporal changes of gate control signals and connection point voltages according to the first embodiment; FIG. 4 is an explanatory diagram showing a commutation operation from a first U-phase switching element (high-side device) to a second U-phase switching element (low-side device); 5 is a graph showing falling waveforms of a U-phase connection point voltage, a V-phase connection point voltage, and a connection point voltage; It is a graph which shows the rising waveform of a PWM signal and a U-phase connection point voltage. 4 is a flow chart showing a switching timing control method according to the first embodiment; 4 is a flow chart showing a switching timing control method according to the first embodiment; 3 is a circuit block diagram showing a configuration example of a control circuit; FIG. 2 is a circuit block diagram showing a configuration example of a switching control circuit according to Embodiment 1; FIG. 5 is a graph showing temporal changes in output voltage when control according to the first embodiment is not performed; 4 is a graph showing temporal changes in output voltage when voltage rising delay synchronization control is performed at a connection point; 7 is a graph showing temporal changes in output voltage when voltage rise delay time and fall time synchronization control is performed at a connection point; 4 is a chart showing the effects of the switching timing control method according to the first embodiment; 8 is a block diagram showing a control circuit according to Embodiment 2; FIG. FIG. 11 is a circuit block diagram showing a configuration example of a voltage converter according to Embodiment 3; 10 is a timing chart showing temporal changes in gate control signals and connection point voltages according to the third embodiment; FIG. 11 is a circuit block diagram showing a configuration example of a voltage converter according to Embodiment 4; 10 is a timing chart showing temporal changes in gate control signals and connection point voltages according to the fourth embodiment. FIG. 12 is a circuit block diagram showing a configuration example of a voltage converter according to Embodiment 5; FIG. 11 is a timing chart showing temporal changes of gate control signals and connection point voltages according to the fifth embodiment; FIG. FIG. 11 is a block diagram showing a configuration example of a switching control circuit according to a sixth embodiment; FIG. 11 is a circuit block diagram showing a configuration example of a balance inductor according to Embodiment 7; FIG. 11 is a circuit block diagram showing a configuration example of a switching circuit according to an eighth embodiment; FIG. 21 is a circuit block diagram showing a configuration example of a switching control circuit according to a ninth embodiment; FIG. 20 is a circuit block diagram showing a configuration example of a current detection circuit according to a tenth embodiment;

A switching circuit, a current detection circuit, a switching timing control method, and a control program according to embodiments of the present disclosure will be described below with reference to the drawings. The present disclosure is not limited to these examples, but is indicated by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims. Moreover, at least part of the embodiments described below may be combined arbitrarily.

(Embodiment 1)
FIG. 1 is a circuit block diagram showing a configuration example of a switching circuit 101 according to the first embodiment. A switching circuit 101 according to the first embodiment includes a half bridge circuit 10 , a control circuit 5 and a balance inductor 6 .

The half-bridge circuit 10 comprises a first leg 1 and a second leg 2 connected in parallel for shunting current. In the first embodiment, the first leg 1 is called the U phase and the second leg 2 is called the V phase as appropriate. The first leg 1 is a circuit in which a first arm having a first U-phase switching element 11a and a second arm having a second U-phase switching element 12a are connected in series. The second leg 2 is a circuit in which a first arm having a first V-phase switching element 21a and a second arm having a second V-phase switching element 22a are connected in series. The first U-phase switching element 11a, the second U-phase switching element 12a, the first V-phase switching element 21a, and the second V-phase switching element 22a are, for example, N-channel MOSFETs. Hereinafter, the first U-phase switching element 11a, the second U-phase switching element 12a, the first V-phase switching element 21a, and the second V-phase switching element 22a are collectively referred to as switching elements.

Specifically, the switching circuit 101 includes a positive input terminal INP and a negative input terminal INN to which the power supply 100 is connected, and a positive output terminal OUTP and a negative output terminal OUTN to which a load composed of a load inductor L and a resistor R is connected. , the drains of the first U-phase switching element 11a and the first V-phase switching element 21a are connected to the positive input terminal INP. The source of the first U-phase switching element 11a is connected to the drain of the second U-phase switching element 12a. The source of the first V-phase switching element 21a is connected to the drain of the second V-phase switching element 22a. The sources of the second U-phase switching element 12a and the second V-phase switching element 22a are connected to the negative input terminal INN and the negative output terminal OUTN.

Each switching element has a parasitic diode 11b, 12b, 21b, 22b formed between the source and the drain. The parasitic diodes 11b, 12b, 21b, and 22b behave as reverse-connected diodes between the source and the drain.
Although not shown in FIG. 1, there is a device output capacitance C between the source and drain of each switching element (see FIG. 3). Note that a capacitive element may be provided between the source and drain of each switching element. Capacitance elements provided for the respective switching elements have the same capacitance.

Gate drive circuits 11c, 12c, 21c, and 22c are connected to the gates of the switching elements, respectively. The gate drive circuits 11c, 12c, 21c, and 22c turn on/off each switching element by outputting a gate drive signal to each switching element in accordance with the gate control signals vgh_u, vgl_u, vgh_v, and vgl_v output from the control circuit 5. .

A connection point between the first arm and the second arm of the first leg 1 (hereinafter referred to as a U-phase connection point P1) and a connection point between the first arm and the second arm of the second leg 2 (hereinafter referred to as a V-phase connection point) P2) is connected through a balance inductor 6 to the positive output terminal OUTP. The balance inductor 6 includes a first inductor 61 and a second inductor 62 magnetically coupled via a core. The turns ratio of the first inductor 61 and the second inductor 62 is 1:1. One end of the first inductor 61 is connected to the U-phase connection point P1. One end of the second inductor 62 is connected to the V-phase connection point P2. The other end of the first inductor 61 and the other end of the second inductor 62 are connected. The connection point of the other end is called a connection point P0. The node P0 is connected to the positive output terminal OUTP. The first inductor 61 and the second inductor 62 are connected to the current output from the U-phase connection point P1 of the first leg 1 (hereinafter referred to as U-phase output current iu) and the current from the V-phase connection point P2 of the second leg 2. It has a coupling polarity that suppresses imbalance with the output current (hereinafter referred to as V-phase output current iv). In other words, when the positive U-phase output current iu and the positive V-phase output current iv flow through the first inductor 61 and the second inductor 62, magnetic fluxes are generated in directions that cancel each other out. When the U-phase output current iu and the V-phase output current iv become equal, the core magnetic flux also becomes smaller, so the balance inductor 6 can be configured using a small core.

The switching circuit 101 also includes a U-phase connection point voltage detection circuit 71 that detects the voltage at the U-phase connection point P1, a V-phase connection point voltage detection circuit 72 that detects the voltage at the V-phase connection point P2, and a connection point P0. and a junction voltage detection circuit 70 for detecting the voltage of . A U-phase connection point voltage detection circuit 71, a V-phase connection point voltage detection circuit 72, and a connection point voltage detection circuit 70 generate signals indicating the detected U-phase connection point voltage Vu, V-phase connection point voltage Vv, and connection point voltage Vc. Output to the control circuit 5 .

The control circuit 5 outputs gate control signals vgh_u, vgl_u, vgh_v, and vgl_v to the gate drive circuits 11c, 12c, 21c, and 22c, thereby switching on/off the switching elements of the first leg 1 and the second leg 2. It is a circuit that The control circuit 5 drives the load by switching control of each switching element. The control circuit 5 according to the first embodiment adjusts the switching timing of each switching element based on the U-phase connection point voltage Vu, the V-phase connection point voltage Vv, and the connection point voltage Vc. Control to equalize the output current. That is, the control circuit 5 performs control to equalize the U-phase output current iu and the V-phase output current iv. The control circuit 5 may adjust the switching timing by software, or may be partly or wholly configured by a hardware circuit. The control circuit 5 may be composed of an FPGA.

<Switching timing control method>
FIG. 2 is a timing chart showing temporal changes in gate control signals and connection point voltages according to the first embodiment. The horizontal axis indicates time. The upper diagram shows the waveform of the gate control signal for the first U-phase switching element 11a on the high-side device side, and the middle diagram shows the waveform of the gate control signal for the second U-phase switching element 12a on the low-side device side. The figure below shows the waveform of the U-phase connection point voltage Vu. The operation of the V phase is similar to that of the U phase.

FIG. 3 is an explanatory diagram showing the commutation operation from the first U-phase switching element 11a (high side device) to the second U-phase switching element 12a (low side device). The upper diagram is a graph showing the falling waveform of the U-phase connection point voltage Vu during the commutation operation. The horizontal axis indicates time, and the vertical axis indicates the U-phase connection point voltage Vu.
It is assumed that the U-phase output current iu is constant during the commutation period. In the period (A), the first U-phase switching element 11a is on and the U-phase connection point voltage Vu is equal to the power supply voltage Vdc. In the period (B), the first U-phase switching element 11a is turned off, but the U-phase connection point voltage Vu does not immediately become zero, and the U-phase connection point voltage Vu decreases as the device output capacitance C is discharged. During period (C), when the U-phase contact voltage becomes zero, current flows through the parasitic diode 12b of the second U-phase switching element 12a. In the period (D), the second U-phase switching element 12a is turned on after the dead time period, and the commutation operation is completed. The U-phase connection point voltage Vu in period (B) is expressed by the following equation.

Here, the time t is zero when the period (B) starts, that is, when the first U-phase switching element 11a is turned off. From the above equation (1), it can be seen that the slope when the U-phase connection point voltage Vu becomes zero from the power supply voltage Vdc is proportional to the U-phase output current iu. The fall time when the U-phase connection point voltage Vu falls below the first threshold voltage Vrefh and then falls below the second threshold voltage Vrefl (hereinafter referred to as U-phase fall time Tf_u) depends on the U-phase output current iu. inversely proportional.
The values of the threshold voltages Vrefh and Vrefl are not particularly limited. % voltage.

The above operation and phenomenon of the U phase are the same for the V phase, and the fall time ( hereinafter referred to as V-phase fall time Tf_v) is inversely proportional to the V-phase output current iv.
If the device output capacitances C of the first leg 1 and the second leg 2 are equal, the U-phase output current iu and the V-phase output current iv are compared by comparing the U-phase fall time Tf_u and the V-phase fall time Tf_v. can be determined.

In the switching control method according to the first embodiment, assuming that the device output capacitances C are equal, by matching the fall time of the U-phase connection point voltage Vu and the fall time of the V-phase connection point voltage Vv, , to equalize the steady-state currents.

Note that the U-phase fall time Tf_u corresponds to the time change rate of the voltage detected by the U-phase connection point voltage detection circuit 71 .

FIG. 4 is a graph showing falling waveforms of the U-phase connection point voltage Vu, the V-phase connection point voltage Vv, and the connection point voltage Vc. The horizontal axis indicates time, and the vertical axis indicates voltage. FIG. 4 shows the case where the U-phase output current iu is smaller than the V-phase output current iv. The node voltage Vc is the average of the U-phase node voltage Vu and the V-phase node voltage Vv. When U-phase fall time Tf_u is longer than the fall time of node voltage Vc (hereinafter referred to as node fall time Tf_c), U-phase output current iu is smaller than V-phase. In this case, the control circuit 5 increases the fall insertion delay of the gate signal with respect to the PWM signal, and performs control to lengthen the ON time (high side ON time) of the first U-phase switching element 11a. In the next switching cycle, the U-phase output current iu increases, and the difference between the U-phase fall time Tf_u and the node fall time Tf_c becomes smaller. When U-phase fall time Tf_u is smaller than node fall time Tf_c, U-phase output current iu is larger than V-phase. In this case, the control circuit 5 shortens the ON time (high side ON time) of the first U-phase switching element 11a to reduce the U-phase output current iu.
If the above control is performed similarly for the V-phase, the falling times of the U-phase connection point voltage Vu, the V-phase connection point voltage Vv, and the connection point voltage Vc are finally equal, and the U-phase output current iu and the V-phase output the currents iv are equal.
The above switching timing control is called fall time synchronization control.

On the other hand, when U-phase connection point voltage Vu rises, U-phase connection point voltage Vu rises at a high speed regardless of the magnitude of U-phase output current iu. The same applies to the rise of the V-phase connection point voltage Vv. This voltage rising timing is affected by variations in device characteristics.

FIG. 5 is a graph showing rising waveforms of the PWM signal and the U-phase connection point voltage Vu. The horizontal axis indicates time, and the vertical axis indicates voltage. The upper diagram shows the PWM signal waveform when the voltage rises. The figure below shows the waveform of the U-phase connection point voltage Vu. In the switching control method according to the first embodiment, the time from when the PWM signal rises until the U-phase connection point voltage Vu becomes equal to the threshold voltage Vrefh (hereinafter referred to as U-phase rising delay time Td_u), By matching the time from when the PWM signal rises to when the V-phase connection voltage becomes equal to the threshold voltage Vrefh (hereinafter referred to as V-phase rise delay time Td_v), current sharing during switching is equalized. Specifically, the control circuit 5 compares the U-phase rise delay time Td_u with a predetermined delay time command value Td_ref, and if the U-phase rise delay time Td_u is greater than the delay time command value Td_ref, the gate for the PWM signal is Decrease the rise insertion delay of the signal. When the U-phase rising delay time Td_u is smaller than the delay time command value Td_ref, the gate signal rising insertion delay is increased.
If the above control is performed similarly for the V phase, the U phase rising delay time Td_u and the V phase rising delay time Td_v will eventually become equal, and as a result of matching the switching timings of the U phase and the V phase, the current sharing during switching will occur. can be equalized.
The above switching timing control is called rise delay synchronization control.

6 and 7 are flowcharts showing the switching timing control method according to the first embodiment. A control procedure of the control circuit 5 will be described. The control flow shown in FIGS. 6 and 7 conceptually shows the contents of control, and the process control is not necessarily executed according to the procedure shown in the figure.

The control circuit 5 acquires the U-phase connection point voltage Vu and detects the U-phase fall time Tf_u (step S11). The control circuit 5 acquires the V-phase connection point voltage Vv and detects the V-phase fall time Tf_v (step S12). The control circuit 5 acquires the node voltage Vc and detects the node fall time Tf_c (step S13).

Next, the control circuit 5 determines whether or not the U-phase fall time Tf_u is longer than the node fall time Tf_c (step S14). If the U-phase fall time Tf_u is large (step S14: YES), the control circuit 5 increases the U-phase fall delay amount to increase the U-phase high-side ON time (the ON time of the first U-phase switching element 11a). time) is extended (step S15). A change control method for the U-phase fall delay amount is not particularly limited, but the fall delay amount may be adjusted by a known method such as I control, PI control, or PID control. The same applies to other delay amounts to be described later.

After step S14: NO and step S15, the control circuit 5 determines whether or not the U-phase fall time Tf_u is shorter than the node fall time Tf_c (step S16). If the U-phase fall time Tf_u is small (step S16: YES), the control circuit 5 decreases the U-phase fall delay amount to increase the U-phase high-side ON time (the ON time of the first U-phase switching element 11a). time) is shortened (step S17).

After step S16: NO and step S17, the control circuit 5 determines whether or not the V-phase fall time Tf_v is longer than the node fall time Tf_c (step S18). If the V-phase fall time Tf_v is large (step S18: YES), the control circuit 5 increases the V-phase fall delay amount to increase the V-phase high-side ON time (the ON time of the first V-phase switching element 21a). time) is extended (step S19).

Step S18: NO and following the process of step S19, the control circuit 5 determines whether or not the V-phase fall time Tf_v is shorter than the node fall time Tf_c (step S20). If the V-phase fall time Tf_v is small (step S20: YES), the control circuit 5 decreases the V-phase fall delay amount to increase the V-phase high-side ON time (the ON time of the first V-phase switching element 21a). time) is shortened (step S21).

After step S20: NO and step S21, the control circuit 5 measures the U-phase rise delay time Td_u (step S22) and measures the V-phase rise delay time Td_v (step S23).

Next, control circuit 5 determines whether or not U-phase rise delay time Td_u is greater than delay time command value Td_ref (step S24). If the U-phase rise delay time Td_u is large (step S24: YES), the control circuit 5 reduces the U-phase rise delay amount (step S25).

After step S24: NO and step S25, the control circuit 5 determines whether the U-phase rise delay time Td_u is smaller than the delay time command value Td_ref (step S26). If the U-phase rise delay time Td_u is small (step S26: YES), the control circuit 5 increases the U-phase rise delay amount (step S27).

Step S26: NO and the process of step S27, the control circuit 5 determines whether or not the V-phase rise delay time Td_v is greater than the delay time command value Td_ref (step S28). If the V-phase rise delay time Td_v is large (step S28: YES), the control circuit 5 reduces the amount of delay in the rise of the V-phase (step S29).

Step S28: NO and the process of step S29, the control circuit 5 determines whether or not the V-phase rise delay time Td_v is smaller than the delay time command value Td_ref (step S30). If the V-phase rise delay time Td_v is small (step S30: YES), the control circuit 5 increases the V-phase rise delay amount (step S31).
Thereafter, the control circuit 5 repeats the processes of steps S11 to S31 to equalize the U-phase output current iu and the V-phase output current iv.

<Hardware Configuration of Control Circuit 5>
The configuration of the control circuit 5 that implements the above control method will be described.
FIG. 8 is a circuit block diagram showing a configuration example of the control circuit 5. As shown in FIG. The control circuit 5 includes a PWM signal generation circuit 50a, a U-phase voltage comparison circuit 51, a V-phase voltage comparison circuit 52, a node voltage comparison circuit 53, a reference voltage generation circuit 54, and a switching control circuit 50. .

The reference voltage generation circuit 54 includes series-connected resistors R3, R4, and R5, and generates reference voltages Vrefh' and Vrefl' corresponding to the first threshold voltage Vrefh and the second threshold voltage Vrefl from the power supply voltage Vdc. It is a circuit that The reference voltage generation circuit 54 outputs the generated reference voltages Vrefh′ and Vrefl′ to the U-phase voltage comparison circuit 51 , the V-phase voltage comparison circuit 52 and the node voltage comparison circuit 53 .

The U-phase voltage comparison circuit 51 has a voltage dividing circuit that divides the U-phase connection point voltage Vu, a first comparison circuit 51a, and a second comparison circuit 51b. The voltage dividing circuit is composed of voltage dividing resistors R1 and R2 connected in series and capacitors C1 and C2 connected in parallel to the voltage dividing resistors R1 and R2. The first comparison circuit 51 a compares the divided voltage Vu′ and the reference voltage Vrefh′, and outputs a detection signal dethu according to the comparison result to the switching control circuit 50 . The second comparison circuit 51b compares the divided voltage Vu' with the reference voltage Vrefl' and outputs a detection signal detlu to the switching control circuit 50 according to the comparison result. That is, the U-phase voltage comparison circuit 51 is a circuit that detects whether the U-phase connection point voltage Vu is higher than the first threshold voltage Vrefh and higher than the second threshold voltage Vrefl. The configurations of the V-phase voltage comparison circuit 52 and the node voltage comparison circuit 53 are the same as those of the U-phase voltage comparison circuit 51 .

FIG. 9 is a circuit block diagram showing a configuration example of the switching control circuit 50 according to the first embodiment. The switching control circuit 50 includes a U-phase control circuit 55 , a V-phase control circuit 56 and a junction fall time detection circuit 57 . The node fall time detection circuit 57 detects the fall time of the node voltage Vc based on the detection signals dethc and detlc output from the node voltage comparison circuit 53, and outputs a signal indicating the fall time as will be described later. It is output to the U-phase delay control circuit 55c and the V-phase delay control circuit 56c.

The U-phase control circuit 55 has a U-phase rise delay time detection circuit 55a, a U-phase fall time detection circuit 55b, a U-phase delay control circuit 55c, dead time processing circuits 55d and 55e, and an inverting inverter 55f. . The U-phase rise delay time detection circuit 55a detects the U-phase rise delay time Td_u based on the PWM signal and the detection signal dethu output from the U-phase voltage comparison circuit 51, and outputs a signal indicating the delay time as U. Output to phase delay control circuit 55c. The U-phase fall time detection circuit 55b detects the U-phase fall time Tf_u based on the detection signals dethu and detlu output from the U-phase voltage comparison circuit 51, and delays the signal indicating the fall time for the U-phase. Output to the control circuit 55c. The U-phase delay control circuit 55c, as described in FIGS. 7 and 9, based on the PWM signal, the U-phase fall time Tf_u, the junction fall time Tf_c, and the U-phase rise delay time Td_u, gates the PWM signal. Adjust the rise and fall delay amounts of the control signal. Dead time is inserted into the adjusted PWM signal by the dead time processing circuit 55d, and the resulting signal is output as a gate control signal for the first U-phase switching element 11a. The adjusted PWM signal is inverted by an inverting inverter 55f, a dead time is inserted by a dead time processing circuit 55e, and output as a gate control signal for the second U-phase switching element 12a.

The V-phase control circuit 56 includes a V-phase rise delay time detection circuit 56a, a V-phase fall time detection circuit 56b, a V-phase delay control circuit 56c, dead time processing circuits 56d and 56e, and an inverting inverter circuit 56f. Each circuit constituting the V-phase control circuit 56 operates in the same manner as the U-phase control circuit 55, and outputs gate control signals for the first V-phase switching element 21a and the second V-phase switching element 22a.

<Experimental results>
An experiment was conducted by setting the design values of the circuit shown in FIG. 1 as follows. The power supply voltage Vdc is 565 V, the voltage dividing ratio of the voltage dividing circuit is 0.00885, the first threshold voltage Vrefh is 396 V, the second threshold voltage Vrefl is 170 V, and the resistance values of the voltage dividing resistors R1 and R2 are 1.68 MΩ and 15 kΩ. , the capacitances of the capacitors C1 and C2 are set to 5 pF and 560 pF, and the resistance values of the voltage dividing resistors R1, R2 and R3 are set to 1.68 MΩ, 6.8 kΩ and 3.9Ω. In order to simulate variations in device characteristics, a delay is inserted in which the V-phase voltage rises 40 ns before the U-phase voltage and falls 100 ns later.

FIG. 10 is a graph showing the time change of the output voltage when the switching timing control according to the first embodiment is not performed, and FIG. 11 is a graph showing the time change of the output voltage when the rise delay synchronization control is performed. 12 is a graph showing the time change of the output voltage when the rise delay time and fall time synchronization control is performed, and FIG. 13 is a chart showing the effects of the switching timing control method according to the first embodiment. Each figure A shows the voltage waveform at the rising time, FIG. B shows the current waveform at the rising time, FIG. C shows the voltage waveform at the falling time, and FIG. D shows the current waveform at the falling time.

It can be seen that the node voltage Vc is the average value of the U-phase node voltage Vu and the V-phase node voltage Vv. As shown in FIGS. 10A and 10B, a transient large current imbalance occurs. The V-phase output current iv increases to 10.8A and the U-phase output current iu decreases to -3.6A. As shown in FIG. 10C, since the V-phase output current iv is larger than the U-phase output current iu, the fall time of the V-phase connection point voltage Vv is shorter than the fall time of the U-phase connection point voltage Vu. The average value of the U-phase output current iu is 1.46 A, and the average value of the V-phase output current iv is 4.63 A, indicating a large current imbalance. As shown in FIG. 13, the ratio of U-phase output current iu to V-phase output current iv is 3.17.

As shown in FIG. 11A, when rising delay synchronization control is performed, the U-phase connection point voltage Vu and the V-phase connection point voltage Vv at the time of rising substantially match. The rise time difference of each voltage was 3 ns. Although the V-phase output current iv is constantly large, the transient fluctuations occurring at the rise of the U-phase output current iu and the V-phase output current iv are equal. At the time of fall, as shown in FIG. 10C, the fall time of the V-phase connection point voltage Vv is shorter than that of the U-phase connection point voltage Vu. Current imbalance is reduced compared to the case without rising delay synchronization control. The average value of the U-phase output current iu is 1.98A, and the average value of the V-phase output current iv is 3.43A. As shown in FIG. 13, the ratio of U-phase output current iu to V-phase output current iv is 1.73.

On the other hand, as shown in FIGS. 12A and 12C, when the rise delay synchronization control and the fall time synchronization control are used together, the V-phase connection point voltage Vv and the U-phase connection point voltage Vu waveforms are almost the same. As shown in FIGS. 12B and 12D, the waveforms of the U-phase output current iu and the V-phase output current iv also substantially match. The average value of the U-phase output current iu is 2.79A, and the average value of the V-phase output current iv is 2.86A. As shown in FIG. 13, the ratio of U-phase output current iu to V-phase output current iv is 1.03. The difference between the U-phase output current iu and the V-phase output current iv is 3%, and equal current sharing is achieved.

According to the first embodiment, switching timing control can equalize the U-phase output current iu and the V-phase output current iv of the half-bridge circuits 10 connected in parallel.

In addition, since the current flowing through each phase of the half-bridge circuit 10 can be equalized, a power semiconductor device having a negative temperature coefficient of resistance can also be used as each switching element constituting the half-bridge circuit 10 .

Furthermore, since the current flowing through each phase of the half bridge circuit 10 can be equalized, a SiC semiconductor device can be used as each switching element constituting the half bridge circuit 10 . Parallel-connected circuits using SiC semiconductor devices have small switching losses and are capable of high-speed switching operations, but may cause a large current imbalance during switching. According to the switching timing control of the first embodiment, it is possible to configure the switching circuit 101 capable of suppressing current imbalance and performing high-speed switching operation.

Further, even if the thermal coupling between the parallel-connected first leg 1 and the second leg 2 constituting the half-bridge circuit 10 is insufficient, current imbalance can be eliminated by switching timing control. Even if the uniformity of the device characteristics of each switching element and the symmetry of the circuit configuration such as the gate wiring are insufficient, the current imbalance can be eliminated by controlling the switching timing. Therefore, the degree of freedom in designing the half bridge circuit 10 can be improved.

In addition, although the example which comprises the half-bridge circuit 10 by two phases was demonstrated, this Embodiment 1 is applicable also to the half-bridge circuit 10 formed by connecting three or more legs in parallel.

Also, although MOSFETs have been described as switching elements, switching elements may be configured with IGBTs, bipolar transistors, and other power semiconductor devices.

Furthermore, the example of performing synchronous control of the fall time by comparing the U-phase fall time Tf_u and the node fall time Tf_c has been described, but the U-phase fall time Tf_u and the V-phase fall time Tf_v may be compared, and the switching timing may be controlled so that the U-phase and V-phase fall times are equal. Specifically, when the U-phase fall time Tf_u is longer than the V-phase fall time Tf_v, the U-phase high-side ON time is extended or the V-phase high-side ON time is shortened. When the U-phase fall time Tf_u is shorter than the V-phase fall time Tf_v, the U-phase high-side ON time is shortened or the V-phase high-side ON time is extended.

Although the U-phase fall time Tf_u and the V-phase fall time Tf_v have been described as an example of the information corresponding to the time rate of change of the U-phase connection point voltage Vu and the V-phase connection point voltage Vv, the time rate of the voltage is substantially The content and expression mode of the information are not particularly limited as long as it represents For example, the voltage difference of the U-phase connection point voltage Vu detected at intervals of a predetermined time may be used as the time rate of the U-phase connection point voltage Vu. A value obtained by applying the U-phase connection point voltage Vu to a differentiating circuit may be used as the time rate of the U-phase connection point voltage Vu.

Furthermore, although the simple circuit provided with the half bridge circuit 10 was illustrated, you may provide the two half bridge circuits 10, and may comprise a full bridge circuit. Also, a three-phase inverter or the like having three full-bridge circuits may be configured. Needless to say, a smoothing capacitor, a rectifier circuit, a transformer, and other circuit elements may be provided before or after the half bridge circuit 10 . The application range of the half bridge circuit 10 according to the first embodiment is not particularly limited, and any power conversion such as a DC-DC converter, a DC-AC converter, an AC-AC converter, an AC-DC converter, an inverter circuit, etc. It can be applied to devices, driving devices, and other electrical equipment using the half-bridge circuit 10 .

(Embodiment 2)
A switching circuit 101 according to the second embodiment differs from the first embodiment in the configuration of a control circuit 205 . The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

FIG. 14 is a block diagram showing the control circuit 205 according to the second embodiment. The control circuit 205 according to the second embodiment includes a master control circuit module 5 a provided on the first leg 1 and a slave control circuit module 5 b provided on the second leg 2 . The master control circuit module 5a and the slave control circuit module 5b are connected by a signal line 5c. When controlling the half bridge circuit 10 having three or more legs, the control circuit 205 includes a plurality of slave control circuit modules 5b.

The master control circuit module 5a includes the U-phase voltage comparison circuit 51, the reference voltage generation circuit 54, the node voltage comparison circuit 53, the U-phase control circuit 55, and the node fall time detection circuit described in the first embodiment. 57. The PWM signal generation circuit 50a is provided on the master side. The master control circuit module 5a controls the switching timing of the first leg 1 and outputs a PWM signal and a signal indicating the node fall time Tf_c to the slave control circuit module 5b via the signal line 5c.

The slave control circuit module 5b includes the V-phase voltage comparison circuit 52, the reference voltage generation circuit 54, and the V-phase control circuit 56 described in the first embodiment. The slave control circuit module 5b controls the switching timing of the second leg 2 using the PWM signal output from the master control circuit module 5a and the signal indicating the node fall time Tf_c.

According to the second embodiment, the master control circuit module 5a and the slave control circuit module 5b share the node fall time Tf_c, and by comparing the fall time of each phase with the node fall time Tf_c, The switching timing of each phase can be controlled. There is no need for two-way communication between the master control circuit module 5a and the slave control circuit module 5b, and the switching of each phase leg can be controlled by an independent controller, which is effective when the number of parallel connections is large. be.

Note that the node voltage comparison circuit 53 may be provided outside the master control circuit module 5a. The node voltage comparison circuit 53 outputs a signal indicating the node fall time Tf_c to each control circuit module.

Further, the reference voltage generation circuit 54 is provided in the master control circuit module 5a, and the master control circuit module 5a supplies the reference voltages Vrefh' and Vrefl corresponding to the first threshold voltage Vrefh and the second threshold voltage Vrefl to the slave control circuit module 5b. ' may be configured to output. In this case, the slave control circuit module 5b does not have to include the reference voltage generation circuit 54. FIG. Further, the reference voltage generation circuit 54 may be provided outside the master control circuit module 5a so that the reference voltages Vrefh' and Vrefl' are commonly input to each control circuit module.

Further, the master control circuit module 5a may be configured to output the node voltage Vc instead of outputting the node fall time Tf_c to the slave control circuit module 5b. Alternatively, the connection point voltage Vc detected by the connection point voltage detection circuit 70 may be commonly input to the master control circuit module 5a and the slave control circuit module 5b.

(Embodiment 3)
The switching circuit 101 according to the third embodiment differs from the first embodiment in the direction of output current and switching control processing. The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

FIG. 15 is a circuit block diagram showing a configuration example of a voltage conversion device according to a third embodiment; The drains of the first U-phase switching element 11a and the first V-phase switching element 21a according to the third embodiment are connected to the positive input terminal INP and the positive output terminal OUTP. The node P0 is connected to the negative output terminal OUTN. In the switching circuit 101 configured in this manner, current flows into the U-phase connection point P1 and the V-phase connection point P2.

FIG. 16 is a timing chart showing temporal changes in gate control signals and connection point voltages according to the third embodiment. Similar to FIG. 2, the waveforms of the gate control signals on the high side device side and the low side device side and the U-phase connection point voltage Vu are shown. The operation of the V phase is similar to that of the U phase. In the third embodiment, when the U-phase connection point voltage Vu and the V-phase connection point voltage Vv rise, the same process as the fall time synchronization control of the first embodiment is executed. That is, in Embodiment 3, the phenomenon shown in FIGS. 3 and 4 occurs at the time of rising. When the rise time of the U-phase connection point voltage Vu is longer than the rise time of the node voltage Vc, the control circuit 5 extends the ON time of the second U-phase switching element 12a (U-phase low side ON time). The rise time of the U-phase connection point voltage Vu is the time from when the U-phase connection point voltage Vu exceeds the second threshold voltage Vrefl to when it exceeds the first threshold voltage Vrefh (hereinafter referred to as U-phase rise time). be. The rising time of the node voltage Vc is the time measured in the same manner as the U-phase rising time (hereinafter referred to as the node rising time). When the U-phase rising time is shorter than the node rising time, the control circuit 5 shortens the ON time (U-phase low-side ON time) of the second U-phase switching element 12a.
Likewise for the V-phase, when the rise time of the V-phase connection point voltage Vv (hereinafter referred to as the V-phase rise time) is longer than the node rise time, the control circuit 5 switches the second V-phase switching element 22a to Extend the on-time (V-phase low-side on-time). When the V-phase rise time is shorter than the node rise time, the control circuit 5 shortens the ON time (V-phase low-side ON time) of the second V-phase switching element 22a.
Moreover, in the third embodiment, the phenomenon shown in FIG. 5 occurs at the falling edge. The control circuit 5 measures the fall delay time of the U-phase connection point voltage Vu (hereinafter referred to as the U-phase fall delay time), and adjusts the U-phase fall delay amount so as to match the predetermined delay time command value Td_ref. to adjust. Similarly, the control circuit 5 measures the fall delay time of the V-phase connection point voltage Vv (hereinafter referred to as the V-phase fall delay time), and adjusts the V-phase delay time so as to match the predetermined delay time command value Td_ref. Adjust fall delay amount. In this manner, the fall timing of the U-phase connection point voltage Vu and the fall timing of the V-phase connection point voltage Vv can be matched.

In the third embodiment in which the current flows into the half bridge circuit 10, the switching timing control can equalize the input and output currents of the half bridge circuits 10 connected in parallel, as in the first embodiment.

(Embodiment 4)
The switching circuit 101 according to the fourth embodiment differs from the first embodiment in the half bridge circuit 410 and switching control processing. The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

FIG. 17 is a circuit block diagram showing a configuration example of a voltage conversion device according to a fourth embodiment; A half bridge circuit 410 according to the fourth embodiment includes reversely connected diodes 12d and 22d instead of the second U-phase switching element 12a and the second V-phase switching element 22a.

FIG. 18 is a timing chart showing temporal changes in gate control signals and connection point voltages according to the fourth embodiment. Similar to FIG. 2, it shows the waveforms of the gate control signal on the high side device side and the U-phase connection point voltage Vu. The operation of the V phase is similar to that of the U phase. The control circuit 5 according to the second embodiment controls the first U-phase switching element 11a and the first V-phase switching element 21a in the same manner as in the first embodiment.

In the fourth embodiment, as in the first embodiment, the input/output currents of the half-bridge circuits 410 connected in parallel can be equalized by switching timing control.

(Embodiment 5)
The switching circuit 101 according to the fifth embodiment differs from the third embodiment in the half bridge circuit 510 and switching control processing. The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

FIG. 19 is a circuit block diagram showing a configuration example of a voltage conversion device according to a fifth embodiment; A half bridge circuit 510 according to the fifth embodiment includes reversely connected diodes 11d and 21d instead of the first U-phase switching element 11a and the first V-phase switching element 21a.

FIG. 20 is a timing chart showing temporal changes in gate control signals and connection point voltages according to the fifth embodiment. Similar to FIG. 2, it shows the waveforms of the gate control signal on the low side device side and the U-phase connection point voltage Vu. The operation of the V phase is similar to that of the U phase. The control circuit 5 according to the fifth embodiment controls the second U-phase switching element 12a and the second V-phase switching element 22a in the same manner as in the third embodiment.

In the fifth embodiment, as in the third embodiment, the input/output currents of the half-bridge circuits 510 connected in parallel can be equalized by switching timing control.

(Embodiment 6)
A switching circuit 101 according to the sixth embodiment differs from the first embodiment in the configuration of a switching control circuit 650 . The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

The half-bridge circuit 10 according to the sixth embodiment constitutes, for example, an inverter circuit, and U-phase current and V-phase current flow bidirectionally between the U-phase connection point P1 and the V-phase connection point P2 and the load. .

FIG. 21 is a block diagram showing a configuration example of a switching control circuit 650 according to the sixth embodiment. The switching control circuit 650 includes a node fall/rise time detection circuit 657 for detecting the fall time and rise time of the node voltage Vc instead of the node fall time detection circuit 57 . The U-phase control circuit 655 according to the sixth embodiment includes a U-phase current direction determination circuit 55g, and instead of the U-phase rise delay time detection circuit 55a and the U-phase fall time detection circuit 55b, the U-phase rise delay time and the U-phase A U-phase rise/fall delay time detection circuit 655a for detecting fall delay time and a U-phase fall/rise time detection circuit 655b for detecting U-phase fall time and U-phase rise time are provided. The V-phase control circuit 656 includes a V-phase current direction determination circuit 56g, which detects the V-phase rise delay time and the V-phase fall delay time instead of the V-phase rise delay time detection circuit 56a and the V-phase fall time detection circuit 56b. A V-phase rise/fall delay time detection circuit 656a for detection and a U-phase fall/rise time detection circuit 656b for detecting V-phase fall time and V-phase rise time are provided.
Since the operation of the V-phase control circuit 656 is the same as that of the U-phase control circuit 655, the configuration and operation of the U-phase control circuit 655 will be explained, and the details of the V-phase control circuit 656 will be omitted.

A gate control signal for the first U-phase switching element 11a and the second U-phase switching element 12a and a signal indicating the V-phase connection point voltage Vv are input to the U-phase current direction determination circuit 55g. The U-phase current direction determination circuit 55g determines that when the first U-phase switching element 11a is turned off from the state in which the first U-phase switching element 11a is on and the second U-phase switching element is off, the U-phase connection point voltage Vu It determines whether or not it has changed, and outputs the determination result to the U-phase delay control circuit 55c. When the first leg 1 is switched from the ON state to the OFF state as described above, the U-phase delay control circuit 55c changes the U-phase connection point voltage Vu as described in the first embodiment. Perform fall time synchronization control. If the U-phase connection point voltage Vu does not change, the switching timing adjustment control is not performed.
Similarly, the U-phase current direction determination circuit 55g determines whether the U-phase connection is made when the second U-phase switching element 12a is switched to the OFF state from the state in which the first U-phase switching element 11a is OFF and the second U-phase switching element is ON. It determines whether or not the point voltage Vu has changed, and outputs the determination result to the U-phase delay control circuit 55c. When the first leg 1 is switched from the ON state to the OFF state as described above, the U-phase delay control circuit 55c changes the U-phase connection point voltage Vu as described in the third embodiment. Perform rise time synchronization control. If the U-phase connection point voltage Vu does not change, the switching timing adjustment control is not performed.

In addition, the U-phase current direction determination circuit 55g determines that the U-phase connection point voltage It determines whether or not Vu has changed, and outputs the determination result to the U-phase delay control circuit 55c. When the first leg 1 is switched from the OFF state to the ON state as described above, the U-phase delay control circuit 55c changes the U-phase connection point voltage Vu as described in the first embodiment. Execute rising delay synchronization control. If the U-phase connection point voltage Vu does not change, the switching timing adjustment control is not performed.
Similarly, the U-phase current direction determination circuit 55g determines whether the U-phase connection is made when both the first U-phase switching element 11a and the second U-phase switching element 11a and the second U-phase switching element 12a are switched to the ON state from the OFF state. It determines whether or not the point voltage Vu has changed, and outputs the determination result to the U-phase delay control circuit 55c. When the first leg 1 is switched from the OFF state to the ON state as described above, the U-phase delay control circuit 55c changes the U-phase connection point voltage Vu as described in the third embodiment. Execute falling edge delay synchronization control. If the U-phase connection point voltage Vu does not change, the switching timing adjustment control is not performed.

According to the sixth embodiment, even if a bidirectional current flows through the half bridge circuit 10, the directions of the U-phase current and the V-phase current flowing through the U-phase connection point P1 and the V-phase connection point P2 are determined, The switching control described in the first and third embodiments can be selectively executed according to the direction, and the input/output currents of the half bridge circuits 10 connected in parallel can be equalized.

(Embodiment 7)
A switching circuit 101 according to the seventh embodiment differs from the first embodiment in the configurations of a half bridge circuit 710 and a balance inductor 706 . The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

FIG. 22 is a circuit block diagram showing a configuration example of the balance inductor 706 according to the seventh embodiment. A half bridge circuit 710 according to the seventh embodiment includes a half bridge circuit 710 in which a first leg 1, a second leg 2 and a third leg 3 are connected in parallel. In the seventh embodiment, the third leg 3 is appropriately called the W phase. The configuration of the third leg 3 is the same as that of the first leg 1 and the second leg 2, and a W-phase connection point voltage detection circuit 73 is provided at the W-phase connection point P3.

A balance inductor 706 according to the seventh embodiment includes a first balance inductor 761 , a second balance inductor 762 and a third balance inductor 763 .
The first balance inductor 761 has a primary coil 761a, one end of which is connected to the U-phase connection point P1, and a secondary coil 761b magnetically coupled via a core. A turn ratio of the primary coil 761a and the secondary coil 761b is 3:1 (number of primary turns:number of secondary turns). The winding directions of the primary coil 761a and the secondary coil 761b are the same as in the first embodiment.
Similarly, the second balance inductor 762 has a primary coil 762a one end of which is connected to the V-phase connection point P2, and a secondary coil 762b magnetically coupled via a core. The third balance inductor 763 has a primary coil 763a one end of which is connected to the W-phase connection point P3, and a secondary coil 763b magnetically coupled via a core. The turns ratio and winding direction of the second balance inductor 762 and the third balance inductor 763 are the same as those of the first balance inductor 761 .

The other ends of the primary coils 761 a , 762 a , 763 a are connected to one end of the secondary coil 761 b of the first balance inductor 761 . The other end of the secondary coil 761 b of the first balance inductor 761 is connected to one end of the secondary coil 762 b of the second balance inductor 762 . The other end of the secondary coil 762b of the second balance inductor 762 is connected to one end of the secondary coil 763b of the third balance inductor 763. The other end of the secondary coil 763b of the third balance inductor 763 is connected to the coupling point P0.

According to the seventh embodiment, in the three-phase half-bridge circuit 10 as well as in the first embodiment, the current of each phase can be balanced and the balance inductor 706 can be configured using a small core.

Although the balance inductor 706 corresponding to three phases has been described, Embodiment 7 can also be applied to the half bridge circuit 10 having four or more legs. For N legs, the turns ratio of the primary coil and the secondary coil should be N:1.

(Embodiment 8)
The switching circuit 101 according to the eighth embodiment differs from the first embodiment in that the control circuit 5 executes the method of adjusting the switching timing using software. The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.

FIG. 23 is a circuit block diagram showing a configuration example of the switching circuit 101 according to the eighth embodiment. The control circuit 5 according to the eighth embodiment is a computer having a CPU (Central Processing Unit) or a processor such as a multi-core CPU, a ROM (Read Only Memory), a RAM (Random Access Memory), an input/output interface, etc. are connected to the gate drive circuits 11c, 12c, 21c, 22c, the U-phase connection point voltage detection circuit 71, the V-phase connection point voltage detection circuit 72, the connection point voltage detection circuit 70, and the like. A storage unit 8 for storing a control program 81 is also connected to the control circuit 5 . By executing the control program 81 stored in the storage unit 8, the control circuit 5 executes processing related to the switching timing control method according to the eighth embodiment. The contents of the processing are the same as those described in the first to sixth embodiments. More specifically, the control circuit 5 may execute the processing of the flow charts shown in FIGS. The control program 81 may be readable and recorded on a recording medium 8a such as a magnetic disk, an optical disk, or a semiconductor memory, or may be read from the recording medium 8a and stored in the storage unit 8.

According to the eighth embodiment, as in the first embodiment, it is possible to equalize input and output currents of the half-bridge circuits 10 connected in parallel by switching timing control executed by software.

(Embodiment 9)
The switching circuit 101 according to the ninth embodiment differs from the first embodiment in the control circuit 5 that performs interleaved drive control and the switching timing adjustment method. The rest of the configuration of the switching circuit 101 is the same as that of the switching circuit 101 according to the first embodiment.
The circuit configuration itself formed by connecting the first leg 1 and the second leg 2 in parallel is the same as that of the first embodiment, but the driving method and operation are different. In the first embodiment, substantially the same gate drive signal is input to each leg, and the whole circuit operates like one half-bridge circuit. In other words, each leg operates in almost perfect synchronization so that the high side devices of each leg turn on and off simultaneously and the low side devices of each leg also turn on and off at the same time. On the other hand, in the interleaved method of the ninth embodiment, phase-shifted pulse signals are input to each leg. For example, gate drive signals that are 180 degrees out of phase are input to each leg. Hereinafter, in the ninth embodiment, a circuit formed by connecting the first leg 1 and the second leg 2 in parallel is simply referred to as a bridge circuit.

As in the first embodiment, the control circuit 5 according to the ninth embodiment includes a PWM signal generation circuit 50a, a U-phase voltage comparison circuit 51, a V-phase voltage comparison circuit 52, a reference voltage generation circuit 54, and a switching control circuit 950. and However, the control circuit 5 according to the ninth embodiment does not include the node voltage comparison circuit 53 .

FIG. 24 is a circuit block diagram showing a configuration example of the switching control circuit 950 according to the first embodiment. The switching control circuit 950 includes a U-phase control circuit 955 and a V-phase control circuit 956 .

The U-phase control circuit 955 has a U-phase fall time detection circuit 55b, a U-phase pulse width control circuit 955c, dead time processing circuits 55d and 55e, and an inverting inverter 55f. The U-phase fall time detection circuit 55b detects the U-phase fall time Tf_u based on the detection signals dethu and detlu output from the U-phase voltage comparison circuit 51, and outputs a signal indicating the fall time as a U-phase pulse. Output to the width control circuit 955c and the V-phase pulse width control circuit 956c.

The V-phase control circuit 956 includes a V-phase fall time detection circuit 56b, a V-phase pulse width control circuit 956c, dead time processing circuits 56d and 56e, and an inverting inverter circuit 56f. The V-phase fall time detection circuit 56b detects the V-phase fall time Tf_v based on the detection signals dethv and detlv output from the V-phase voltage comparison circuit 52, and outputs a signal indicating the fall time as a V-phase pulse. Output to the width control circuit 956c and the U-phase pulse width control circuit 955c.

The U-phase pulse width control circuit 955c adjusts the pulse width of the PWM signal according to the fall time based on the PWM signal, the U-phase fall time Tf_u and the V-phase fall time Tf_v. Specifically, when the U-phase fall time Tf_u is longer than the V-phase fall time Tf_v, the pulse width is adjusted so that the U-phase high-side ON time becomes longer. When the U-phase fall time Tf_u is shorter than the V-phase fall time Tf_v, the pulse width is adjusted so that the U-phase high-side ON time is shortened. The operation of the circuit subsequent to the U-phase pulse width control circuit 955c is the same as in the first embodiment.

The V-phase pulse width control circuit 956c adjusts the pulse width of the PWM signal according to the fall time based on the PWM signal, the V-phase fall time Tf_v and the U-phase fall time Tf_u. Specifically, when the U-phase fall time Tf_u is longer than the V-phase fall time Tf_v, the pulse width is adjusted so that the high-side ON time of the V-phase is shortened. When the U-phase fall time Tf_u is shorter than the V-phase fall time Tf_v, the pulse width is adjusted so that the U-phase high-side ON time becomes longer. The operation of the circuit subsequent to the V-phase pulse width control circuit 956c is the same as in the first embodiment.

According to the ninth embodiment, as in the first embodiment, the input/output currents of the parallel connection of the first leg 1 and the second leg 2 can be equalized.

In the case where the bridge circuit shown in the first embodiment is driven by the interleave method, an example of eliminating the imbalance of the currents flowing in each leg has been described, but the switching circuit 101 shown in another embodiment is driven by the interleave method. The invention according to the ninth embodiment can also be applied in this case.

For example, when driving a bridge circuit in which current flows into the U-phase connection point P1 and the V-phase connection point P2 in an interleaved manner as shown in the third embodiment, the U-phase pulse width control circuit 955c controls the PWM signal, the U-phase rise Based on the time and the V-phase rise time, the pulse width of the PWM signal is adjusted according to the rise time. The pulse width of the PWM signal may be adjusted accordingly.

Further, as shown in Embodiment 4 or 5, when driving a bridge circuit in which one of the first arm and the second arm is composed of diodes in an interleaved manner, the PWM signal for driving the other first arm or the second arm is controlled by the same method as above.

Furthermore, as in the sixth embodiment, when the U-phase current and the V-phase current flow bidirectionally between the U-phase connection point P1 and the V-phase connection point P2 and the load, the U-phase control circuit 955 and the V-phase The control circuit 956 may be provided with a U-phase current direction determination circuit 55g and a V-phase current direction determination circuit 56g so as to switch the control method according to the direction of the current.

(Embodiment 10)
FIG. 25 is a circuit block diagram showing a configuration example of the current detection circuit 1009 according to the tenth embodiment. A current detection circuit 1009 according to the tenth embodiment is a circuit that detects an output current from the half bridge circuit 1010 including at least the first leg 1 of the first embodiment. For convenience of explanation, terms such as U phase, U phase current, and U phase connection point P1 will be used as in the first embodiment.

The current detection circuit 1009 includes an inductor 1091 connected in series to the U-phase connection point P1, a voltage detection circuit 1092 that detects the U-phase connection point voltage Vu, and an arithmetic circuit 1093. One end of the inductor 1091 is connected to the U-phase connection point P1, and the other end of the inductor 1091 is connected to the load. Voltage detection circuit 1092 detects U-phase connection point voltage Vu and outputs a signal indicating the detected voltage to arithmetic circuit 1093 .

The arithmetic circuit 1093 includes the U-phase voltage comparison circuit 51, the reference voltage generation circuit 54, and the U-phase fall time detection circuit 55b, which are similar to those of the first embodiment. The arithmetic circuit 1093 calculates the time from when the U-phase connection point voltage Vu falls below the first threshold voltage Vrefh to when it falls below the second threshold voltage Vrefl when the first leg 1 is switched from the ON state to the OFF state. To detect. The time is a value proportional to the U-phase output current iu, and the arithmetic circuit 1093 detects the detected time as the U-phase output current iu. Note that the arithmetic circuit 1093 may convert the detected time to the U-phase output current iu.

According to the current detection circuit 1009 according to the tenth embodiment, the current of the half bridge circuit 1010 can be easily detected with a simple configuration.

Although an example of detecting the U-phase output current iu has been described, the input current to the power conversion circuit may also be detected in the same manner. Arithmetic circuit 1093 calculates the time from when U-phase connection point voltage Vu exceeds second threshold voltage Vrefl to when it exceeds first threshold voltage Vrefh when first leg 1 is switched from the ON state to the OFF state. Then, the detected time is detected as the U-phase connection point voltage Vu.

1 first leg 2 second leg 5 control circuit 6 balance inductor 10 half bridge circuit 11a first U-phase switching element 12a second U-phase switching element 21a first V-phase switching element 22a second V-phase switching element 50 switching control circuit 50a PWM signal generation Circuit 51 U-phase voltage comparison circuit 51a First comparison circuit 51b Second comparison circuit 52 V-phase voltage comparison circuit 53 Junction point voltage comparison circuit 54 Reference voltage generation circuit 55 U-phase control circuit 55a U-phase rising delay time detection circuit 55b U-phase Fall time detection circuit 55c U-phase delay control circuit 56 V-phase control circuit 56a V-phase rise delay time detection circuit 56b V-phase fall time detection circuit 56c V-phase delay control circuit 57 Junction fall time detection circuit 61 First inductor 62 second inductor 70 connection point voltage detection circuit 71 U-phase connection point voltage detection circuit 72 V-phase connection point voltage detection circuit 8 storage unit 81 control program 8a recording medium 100 power supply

Claims (17)

a bridge circuit comprising a plurality of legs in which a first arm having a switching element and a second arm having a switching element or a diode connected in reverse are connected in series, the plurality of legs being connected in parallel;
a control circuit that controls switching of the switching element of each leg;
an inductor provided between a connection point of the first arm and the second arm of each leg and a connection point that couples the connection points of each leg;
a connection point voltage detection circuit that detects the voltage at the connection point of each leg,
The control circuit is
A switching circuit that adjusts the switching timing of the switching element based on the time rate of change of the voltage detected by the connection point voltage detection circuit. The control circuit is
The switching circuit according to claim 1, wherein the switching timing of the switching element is adjusted based on the time rate of change of the voltage at the connection point that increases or decreases when the leg is switched to the OFF state. The control circuit is
If the time rate of change of the voltage at the connection point associated with the first leg is greater (or less) than the time rate of change of the voltage at the connection point associated with the second leg, then the first leg The switching circuit according to claim 2, wherein the ON time of the switching element of is shortened (longened). A coupling point voltage detection circuit that detects the voltage at the coupling point,
The control circuit is
2. The switching timing of the switching element according to claim 1, wherein the switching timing of the switching element is adjusted based on the time rate of change of the voltage detected by the node voltage detection circuit and the time rate of change of the voltage detected by the connection point voltage detection circuit. switching circuit. The control circuit is
The switching timing of the switching element is adjusted based on the time rate of change of the voltage at the connection point that increases or decreases when the leg is switched to the OFF state and the time rate of change of the voltage at the connection point. 5. The switching circuit according to 4. The control circuit is
If the time rate of change of the voltage at the connection point associated with the leg is greater (or less) than the time rate of change of the voltage at the coupling point, shortening (lengthening) the ON time of the switching element of the leg. 6. A switching circuit according to claim 5. The control circuit is
A plurality of control circuit modules provided in each of the plurality of legs and performing switching control of each leg,
The plurality of control circuit modules commonly receive the voltage at the connection point detected by the connection point voltage detection circuit or a signal indicating the time rate of change of the voltage, and the connection point of the leg to be controlled. A signal indicating the voltage of is input respectively,
Each control circuit module is
Adjusting the switching timing of the switching element of the leg to be controlled based on the input signal indicating the voltage or time rate of change at the connection point and the input signal indicating the voltage at the connection point A switching circuit according to any one of claims 4 to 6. The control circuit is
The switching elements of the first arm and the second arm are switching-controlled by an interleave method, and the switching elements of the first arm or the second arm are controlled based on the time rate of change of the voltage detected by the connection point voltage detection circuit. The switching circuit according to any one of claims 1 to 3, which adjusts a pulse width of a signal that turns on and off the . the second arm has a switching element,
The control circuit is
Determining whether or not the voltage at the connection point changes when the leg is switched to an off state when current flows bidirectionally between the leg and the load;
9. The switching timing of the switching element is adjusted based on the time rate of change of the voltage at the connection point when the leg is switched to the OFF state when it is determined that the voltage has changed. 2. The switching circuit according to item 1. The rate of change over time is
10. The switching circuit according to any one of claims 1 to 9, wherein it is the time difference between when the detected voltage crosses the first threshold and when the detected voltage crosses the second threshold. The control circuit is
After switching the switching element of the leg in the off state to the on state, detecting the point in time when the voltage at the connection point of each leg becomes a predetermined voltage or more (or a predetermined voltage or less), and the voltage becomes the predetermined voltage or more. 11. The switching circuit according to any one of claims 1 to 10, wherein the switching timing of the switching element of each leg is adjusted so that the timings of the voltage becoming (or equal to or lower than a predetermined voltage) are the same. the second arm has a switching element,
The control circuit is
Determining whether or not the voltage at the connection point changes when the switching element of the leg in the OFF state is switched to the ON state when current flows bidirectionally between the leg and the load;
When it is determined that there is a voltage change, after switching the switching element of the leg to the ON state, detecting the time when the voltage at the connection point of each leg becomes a predetermined voltage or more (or a predetermined voltage or less), 12. The switching circuit according to any one of claims 1 to 11, wherein the switching timing of the switching element of each leg is adjusted so that the timing of becoming equal to or higher than the predetermined voltage (or equal to or lower than the predetermined voltage) is the same. 13. The inductor according to any one of claims 1 to 12, wherein the inductors on the legs are magnetically coupled and have coupling polarities that inhibit current imbalance in the legs. switching circuit. A current detection circuit for detecting a current in a bridge circuit including a leg formed by connecting a first arm having a switching element and a second arm having a switching element or a reverse-connected diode in series,
an inductor connected in series to a connection point between the first arm and the second arm;
a connection point voltage detection circuit that detects the voltage at the connection point of the leg;
A current detection circuit comprising: an arithmetic circuit that calculates the current flowing through the leg based on the time rate of change of the voltage detected by the connection point voltage detection circuit. The rate of change over time is
15. The current detection circuit according to claim 14, wherein the time difference is the time when the detected voltage passes the first threshold and the time when the detected voltage passes the second threshold. A bridge circuit comprising a plurality of legs in which a first arm having a switching element and a second arm having a switching element or a reverse-connected diode are connected in series, wherein the plurality of legs are connected in parallel, each leg A switching timing control method for a switching circuit comprising a connection point between a first arm and a second arm of and an inductor provided between a connection point connecting the connection points of each leg,
detecting the voltage at said connection point of each leg;
A switching timing control method, comprising: adjusting the switching timing of the switching element based on the time rate of change of the detected voltage. A bridge circuit comprising a plurality of legs in which a first arm having a switching element and a second arm having a switching element or a reverse-connected diode are connected in series, wherein the plurality of legs are connected in parallel, each leg A control program for causing a computer to execute switching timing control of a switching circuit comprising an inductor provided between a connection point of a first arm and a second arm of and a connection point connecting the connection points of each leg and
to the computer;
detecting the voltage at said connection point of each leg;
A control program for executing a process of adjusting the switching timing of the switching element based on the time rate of change of the detected voltage.

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