JP6072645B2 - Power converter - Google Patents

Description

  The present invention relates to a power converter, and more particularly to a power converter configured by connecting semiconductor modules having MOSFETs in parallel in one phase.

  In medium- and large-capacity power converters such as elevator-drive power converters, the capacity is increased by increasing the current so that the motor as a load does not become a high voltage. For this purpose, the semiconductor switching elements are connected in parallel within one phase. In the parallel connection, not only the switching element characteristics but also the non-uniformity of the main circuit wiring inductance and the gate drive circuit becomes the cause of non-uniform current sharing.

  Here, by making the gate drive circuit common in parallel, the influence of the non-uniformity of the gate drive circuit can be eliminated.

  Further, for example, as disclosed in Patent Document 1, it is possible to reduce the current sharing unevenness by adjusting the timing of switching by delay-adjusting the signal to each gate driving circuit by using separate gate driving circuits in parallel. Are known.

  Further, by using a combination of a MOSFET using SiC (silicon carbide) and a SiC Schottky barrier diode (SBD) as a free-wheeling diode, the switching module has been reduced in loss, but the voltage change rate dv / Since dt and current change rate di / dt are increasing, there is a concern that a slight difference in wiring inductance may affect current sharing unevenly.

JP 2009-135626 A

  Here, as a countermeasure to non-uniform current sharing, in Patent Document 1, the gate drive circuits of switching elements connected in parallel are separately provided, the temperature of each switching element is compared, and the gates are set so that the temperatures are balanced. The current sharing unevenness is reduced by adjusting the signal to the drive circuit by the delay circuit.

  For example, in the three-phase inverter circuit shown in FIG. 6, the case of a power conversion device in which the switching circuit 3 of each phase is configured by parallel connection of semiconductor modules 31 and 32 will be described. 7, the drive signal GP1 of the positive side switching element 31QP of the semiconductor module 31, the drive signal GN1 of the negative side switching element 31QN, the drive signal GP2 of the positive side switching element 32QP of the semiconductor module 32 connected in parallel to the semiconductor module 31, Drive signal GN2 for negative side switching element 32QN, voltages VP1, VP2, VN1, and VN2 for switching elements 31QP, 31QN, 32QP, and 32QN, currents IP1, IP2, IN1, and IN2 for switching elements 31QP, 31QN, 32QP, and 32QN, semiconductor module Currents Iac1 and Iac2 of AC output terminals 31AC and 32AC of 31 and 32 are shown. The horizontal axis in FIG. 7 is time.

  In FIG. 7, it is assumed that the positive side switching elements 31QP and 32QP are on and the current flows evenly until time t1. A case is assumed in which when the turn-off is performed at time t1, the switching element 31QP is delayed to be turned off due to variations in the gate drive circuit or element characteristics, resulting in uneven current. In this case, since the current IP1 of the switching element 31QP that is turned off later increases, the current of the AC output terminal also satisfies Iac1> Iac2, and current non-uniformity occurs. After the time t1, the negative-side freewheeling mode is set, but until the time t2, the driving signals GN1 and GN2 of the switching elements 31QN and 32QN are turned off. Current flows through the 31QN and 32QN parasitic diodes.

  FIG. 4 shows the current Id-voltage Vds characteristics of the MOSFET, but even if the current is in the reverse direction, the current can be passed by the parasitic diode (the dotted line in FIG. 4 is only the MOSFET parasitic diode without the circulating diode, the broken line is the MOSFET parasitic) A case where an SBD (Schottky barrier diode) is combined as a diode and a free-wheeling diode is shown). Further, even when the current is in the reverse direction, the gate voltage is applied to enter the synchronous rectification mode, and the voltage (absolute value of Vds) can be reduced (solid line indicated as “MOSFET synchronous rectification” in FIG. 4). Here, in order to reduce the loss, it is preferable to bring the time t2 as close as possible to the time t1, but a period (dead time) for preventing a short circuit is necessary.

  Between time t2 and time t4, the driving signals GN1 and GN2 of the switching elements 31GN and 32GN in the circulating mode in which the circulating current flows are turned on to perform synchronous rectification. During this time, current unevenness continues.

  At time t4, the drive signals GN1 and GN2 of the negative side switching elements 31QN and 32QN are turned off and the positive side switching elements 31QP and 32QP are turned on after the dead time. At this time, the current is large (Iac1> Iac2) Drive signal GP1 is delayed. Switching element 32QP is turned on first at time t5 (driving signal GP2 is turned on), and switching element 31QP is turned on at a later time t6 (driving signal GP1 is turned on). Since current IP2 flows into 32QP, current equalization is achieved. Here, the length of time from time t5 to time t6 is increased because the greater the temperature difference between the switching elements, the greater the current non-uniformity. In the case of FIG. 7, the magnitudes of the currents Iac1 and Iac2 are reversed so as to reduce the non-uniformity of current sharing. However, the magnitudes of the currents Iac1 and Iac2 are not reversed and the difference is In this case, the current sharing unevenness can be reduced as compared with the case where nothing is done.

  However, as shown in FIG. 7, if the current sharing unevenness is reduced by shifting the timing of turning on the positive side switching elements 31 QP and 32 QP from time t 5 to time t 6 after the end of synchronous rectification, from time t 5. However, the current unevenness continues in the previous stage. While the current non-uniformity is occurring, the amount of heat generated by the two is different, so that there is a difference in the life of the switching elements between the switching elements connected in parallel. Therefore, it is desired to reduce the current sharing unevenness as early as possible after the current unevenness occurs.

  Further, as shown in FIG. 8, in the case of the configuration of the motor 52 having two systems of three-phase windings, another problem occurs. In the configuration of the motor 52 having two systems of three-phase windings shown in FIG. 8, if the turn-on timing is shifted, a large potential difference between the AC output terminals (corresponding to the DC voltage of each power converter 301 or 302 in the set parallel configuration). Will occur. That is, as shown in FIG. 9, since the switching element 32QP is turned on first at time t5, the voltage VP2 of the switching element 32QP first becomes substantially zero, and the AC output terminal 32AC of the semiconductor module 32 is substantially at the potential of the positive electrode P2 ( Potential of the positive electrode of the semiconductor module 32). On the other hand, the AC output terminal 31AC of the semiconductor module 31 remains almost at the potential of the negative electrode N1 (the potential of the negative electrode of the semiconductor module 31) because the switching element 31QP is not yet turned on. Occurs between 31AC and the AC output terminal 32AC. Then, the current circulated by this potential difference (AC output terminal 32AC → U2 phase → floating capacitance 523 → U1 phase → AC output terminal 31AC → circulating diode 31DN → DC negative electrode N1 → switching element on the converter side of the power converter 301) Or any of the switching elements on the converter side of the power converter 302 → DC negative electrode N2 → DC smoothing capacitor of the power converter 302 → DC positive electrode P2 → switching element 32QP → AC output terminal 32AC path) There is a concern that the temperature of wiring conductors and the like may increase due to.

  Accordingly, in this case as well, the length of time from time t5 to time t6 is such that the greater the temperature difference between the switching elements, the greater the current non-uniformity, so the time from time t5 to time t6 is shortened. In addition, it is desirable that the current sharing non-uniformity is reduced at the time t5, and the current sharing non-uniformity is reduced as early as possible after the current non-uniformity occurs as in the case of FIG. It is desirable.

  The problem to be solved by the present invention is to provide a power conversion device capable of reducing non-uniform current sharing between parallel circuits from the earliest possible stage.

  In order to solve the above problem, in the present invention, the length of the synchronous rectification period is made different between the parallels.

  Specifically, for example, in a power conversion device that includes a switching circuit in which a plurality of semiconductor modules having a pair of upper and lower MOSFETs are connected in parallel within one phase and converts direct current and alternating current, the alternating current side of each of the semiconductor modules And a gate control unit that controls on and off of the MOSFET according to the current detected by the current detection unit, the gate control unit being one of the MOSFETs In the period of the recirculation mode in which the recirculation current flows, the time during which the MOSFET on the side in the recirculation mode of the semiconductor module having the smaller current detected by the current detection unit is on is large in the current detected by the current detection unit The semiconductor module is characterized in that it is longer than the ON time of the MOSFET on the side of the semiconductor module in the reflux mode.

  By adopting the above configuration, it is possible to reduce non-uniform current sharing between parallels using the period of synchronous rectification, so that non-uniform current sharing between parallels is reduced from the earliest possible stage. it can.

The figure which shows the structure of Example 1 of this invention. 5 is a flowchart illustrating the operation of a gate control unit according to the first embodiment. FIG. 3 is a diagram illustrating a gate drive signal and current / voltage waveforms in the first embodiment. The figure which shows the electric current Id-voltage Vds characteristic of MOSFET. The figure which shows the structure of Example 2 of this invention. The figure which shows the circuit structure of the power converter device with which Example 1 is applied. The figure which shows the gate drive signal in the prior art example in the circuit of FIG. 6, and a current and a voltage waveform. The figure which shows the circuit structure of the power converter device with which Example 2 is applied. The figure which shows the gate drive signal in the prior art example in the circuit of FIG. 8, and a current and a voltage waveform.

  Embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention. FIG. 6 illustrates a circuit configuration of a power conversion device to which the first embodiment is applied. FIG. 1 shows a case where one phase portion of the three-phase inverter shown in FIG.

  The three-phase inverter shown in FIG. 6 includes a switching circuit 3 (3 (U) corresponding to the U phase and 3 (V) corresponding to the V phase) between the DC positive electrode (P) and the DC negative electrode (N). (V), 3 (W) corresponding to the W phase is connected, and is a power conversion device that converts direct current into alternating current and supplies it to a motor 51 that is a load. Note that the three-phase inverter shown in FIG. 6 can also convert alternating current from the motor 51 into direct current in the regeneration mode. The switching circuit 3 has a configuration in which a plurality of semiconductor modules having a pair of upper and lower MOSFETs are connected in parallel within one phase.

  The switching circuit 3 for one phase has a semiconductor module 31 and a semiconductor module 32 connected in parallel.

  The semiconductor module 31 includes a positive side switching element (MOSFET) 31QP, a freewheeling diode 31DP connected in reverse parallel to the switching element 31QP, a negative side switching element (MOSFET) 31QN, and a freewheeling connected in reverse parallel to the switching element 31QN. It is composed of a diode 31DN. As shown in FIG. 1, the semiconductor module 31 includes a positive side DC input terminal 31P, a negative side DC input terminal 31N, and an AC output terminal 31AC. Further, the positive side switching element 31QP and the negative side switching element 31QN are driven by the gate drive circuits 41P and 41N shown in FIG. 1, respectively.

  Similarly, the semiconductor module 32 is connected to the positive side switching element (MOSFET) 32QP, the freewheeling diode 32DP connected in antiparallel to the switching element 32QP, the negative side switching element (MOSFET) 32QN, and connected to the switching element 32QN in antiparallel. The freewheeling diode 32DN is configured. As shown in FIG. 1, the semiconductor module 32 includes a positive side DC input terminal 32P, a negative side DC input terminal 32N, and an AC output terminal 32AC. The positive side switching element 32QP and the negative side switching element 32QN are driven by the gate drive circuits 42P and 42N shown in FIG. 1, respectively.

  As described with reference to FIG. 4, the circulating current can be passed through the MOSFET's parasitic diode and synchronous rectification, so that the circulating diodes 31DP, 31DN, 32DP, and 32DN are not necessarily required and may be omitted. . In the first embodiment, the case of converting direct current to alternating current is described as an example, and therefore, the AC output terminals 31AC and 32AC are called. However, when alternating current is converted to direct current, an alternating current input terminal is used. You may call it a side terminal.

  As shown in FIG. 1, the power conversion apparatus according to this embodiment includes a current detection unit 2 that detects current on the AC side of the semiconductor modules 31 and 32. Specifically, the currents of the AC output terminals 31AC and 32AC are respectively detected by the current detection unit 2 using signals from the current sensors 21 and 22 provided on the AC side of the semiconductor modules 31 and 32, respectively. Is detected. The current detection unit 2 replaces the method of detecting the current on the AC side of the semiconductor modules 31 and 32 using the current sensors 21 and 22 by the method shown in FIG. The current on the AC side of the semiconductor modules 31 and 32 is detected by detecting the temperature of the MOSFET constituting the switching element using a temperature sensor (not shown), assuming that the temperature of the MOSFET constituting the element is higher. Strictly, it may be estimated and detected). Alternatively, the current on the positive electrode side and the negative electrode side of DC is measured by a current sensor (not shown), and the current on the AC side is detected by the current detector 2 in consideration of the switching timing of the switching element (strictly estimated and detected). You may make it do.

  In addition, the power conversion device includes a gate control unit 1 that controls on and off of the switching elements 31QP, 31QN, 32QP, and 32QN. Specifically, the gate control unit 1 controls on and off of the switching elements 31QP, 31QN, 32QP, and 32QN by sending gate drive signals to the gate drive circuits 41P, 41N, 42P, and 42N. The gate control unit 1 includes a delay determination unit 11 and delay circuits 121, 122, 131, and 132. The gate control unit 1 controls on and off of the switching element according to the current detected by the current detection unit 2. Specifically, the delay determination unit 11 drives each gate drive so that the current sharing unevenness can be reduced from the gate drive signal from the power converter control unit 10 and the current value detected by the current detection unit 2. The delay time to be applied to the signal (including no delay) is calculated, and each gate drive signal is delayed by the delay time calculated by the delay determination unit 11 via the delay circuits 121, 122, 131, 132, It is transmitted to the gate drive circuits 41P, 41N, 42P, and 42N.

  Note that the gate drive signal from the power converter control unit 10 is the same as the gate drive signal of a normal power converter that does not consider the current sharing unevenness. For example, the gate drive signal for PWM control of the switching element It is. In this embodiment, the power conversion device control unit 10 and the gate control unit 1 are described separately. However, the gate control unit 1 is provided in the power conversion device control unit 10, or the gate control unit 1 is provided. It is also possible to provide the power conversion device control unit 10 in the inside so as to serve as both.

  The gate control unit 1 performs control so that the lengths of the synchronous rectification periods of the switching elements 31QP, 31QN, 32QP, and 32QN are different from each other according to the current imbalance detected by the current detection unit 2. Specifically, the gate control unit 1 has a smaller current detected by the current detection unit 2 in the circulation mode period in which the circulation current flows in any of the switching elements 31QP, 31QN, 32QP, and 32QN configured by MOSFETs. In the semiconductor module of the semiconductor module, the MOSFET on the side that becomes the reflux mode of the semiconductor module with the larger current detected by the current detection unit 2 is the ON time of the MOSFET on the side that becomes the reflux mode of the semiconductor module. Control is made to be longer than the ON time (the length of the synchronous rectification period). Conventionally, as shown in FIG. 7 and FIG. 9, the period of synchronous rectification is the same for both the semiconductor modules 31 and 32, and this is greatly different from the conventional one.

  FIG. 2 is a flowchart illustrating the operation of the gate control unit according to the first embodiment. The delay setting procedure in the gate control unit 1 will be described with reference to FIG. The gate control unit 1 calculates the difference x (procedure 111) and the sum Iac (procedure 117) from the currents Iac1 and Iac2 that are AC current detection values of the semiconductor modules 31 and 32 detected by the current detection unit 2. The magnitude of the absolute value of the difference x and the set threshold value Xt is determined (procedure 112). If the absolute value x of the difference x is less than or equal to the threshold value Xt, there is no delay (procedure 119) (delay time Td1 = Td2 = 0). When the absolute value of the difference x exceeds the threshold value Xt, a delay time d having a magnitude proportional to the difference x is set (procedure 113) (d = A · x). If the absolute value of the delay time d is extremely large, the delay time d may exceed the synchronous rectification period. Therefore, a limit value is provided (step 114). The delay time d is set equal to a positive or negative limit value.

  Next, it is determined which of the semiconductor modules 31 and 32 is delayed (that is, which of the synchronous rectification periods is made longer than the other) depending on whether d is positive or negative (procedure 115).

  When d> 0, the current Iac1 is larger than the current Iac2, so that the synchronous rectification period of the semiconductor module 32 on the smaller current side is longer than the synchronous rectification period of the semiconductor module 31 on the larger current side. And delay time Td1 = d and delay time Td2 = 0 (procedures 116 and 1161). In this case, of the delay circuits 121 and 131 connected to the gate drive circuits 41P and 41N on the semiconductor module 31 side in the period of the circulation mode in which synchronous rectification is performed, the switching element on the side in the circulation mode is turned on. In order to delay the gate drive signal by the delay time Td1 = d and to turn on the switching element on the side in the circulation mode among the delay circuits 122 and 132 connected to the gate drive circuits 42P and 42N on the semiconductor module 32 side. Are delayed by the delay time Td2 = 0 (that is, not delayed). For example, FIG. 3 to be described later shows an example in the case of d> 0. When synchronous rectification is performed, the switching element 32QN is turned on at time t2, whereas the switching element 31QN has only the delay time d. It is delayed and turned on at time t3.

  On the contrary, when d <0, the current Iac1 is smaller than the current Iac2, and therefore the synchronous rectification period of the semiconductor module 31 on the smaller current side is longer than the synchronous rectification period of the semiconductor module 32 on the larger current side. Therefore, it is assumed that the delay time Td1 = 0 and the delay time Td2 = −d (procedures 116 and 1162). Here, −d is set so that the delay time Td2 is an absolute value of d. Thus, when performing synchronous rectification, the switching element on the semiconductor module 32 side is turned on by delaying by the delay time Td2, contrary to the case of d> 0, and the switching element on the semiconductor module 31 side is turned on by the delay time Td1 = Since it is 0, it is turned on without delay.

  In FIG. 2, in order to determine whether the switching element in the reflux mode is the P side or the N side, the sign of the current sum Iac calculated in step 117 is determined (step 118). The side is adjusted (procedure 120P). If it is positive, the N side is adjusted (procedure 120N). If it is 0, no delay is performed (procedure 119). For example, in FIG. 3 to be described later, since Iac is positive, the switching elements 31QN and 32QN on the N side are in the reflux mode, so adjustment is performed on the N side.

  FIG. 3 is a diagram illustrating a gate drive signal and current / voltage waveforms in the first embodiment. Since FIG. 3 is a diagram corresponding to FIG. 7, only the difference from FIG. 7 will be described. The description up to time t2 is the same as in FIG. In FIG. 3, since Iac1> Iac2, the driving signal GN1 of the switching element 31QN in the circulating mode is delayed by the delay time d from the driving signal GN2 of the switching element 32QN in the circulating mode. At time t2, only the drive signal GN2 is turned on and the switching element 32QN is synchronously rectified, so that the resistance is lowered and the current IN2 is increased (in the negative direction), so that current equalization can be achieved. At time t3, which is delayed by the delay time d from time t2, the drive signal GN1 is also turned on, so that the switching element 31QN is also synchronously rectified and the resistance is lowered. Since both synchronous rectifications are completed at time t4, as a result, the larger the current Iac1, the shorter the synchronous rectification period.

  Thereby, at the end of the synchronous rectification at time t4, the currents IN1 and IN2 and the currents Iac1 and Iac2 can be reduced, more preferably matched. In FIG. 7 and FIG. 9 of the related art, the unequal reduction of current sharing is started at time t5, whereas the unequal reduction of current sharing is already completed at the end of synchronous rectification at time t4 earlier than time t5. As a result, it is possible to reduce the non-uniform current sharing between the parallel circuits from the earliest possible stage. Thereby, the difference in the heat generation amount of the switching elements between the parallel elements can be reduced, and the difference in the life of the switching elements between the switching elements connected in parallel can be reduced. Also, unlike FIGS. 7 and 9, there is no need to shift the timings at which the drive signals GP1 and GP2 are turned on in order to reduce the current sharing unevenness at time t5, or even if they are shifted, a short time is required. can get.

  Further, in FIG. 3, the adjustment is performed at the start timing of the synchronous rectification, and the uneven current sharing is started from the time t2, and the currents are matched at the time t3, so that the current sharing is uneven. The effect of reducing is even greater. It is not always necessary to match the currents. If the difference can be reduced, the effect is reduced as compared with the case where the currents are matched, but the effect of reducing uneven current sharing can be obtained.

  FIG. 5 is a diagram showing the configuration of the second embodiment of the present invention. FIG. 8 is a diagram illustrating a circuit configuration of a power conversion device to which the second embodiment is applied. FIG. 5 shows a configuration for one phase in a power converter having a set parallel configuration for supplying alternating current to a motor 52 having two systems of three-phase windings as shown in FIG.

  In the second embodiment, description of parts common to the first embodiment will be omitted, and differences will be mainly described.

  The power conversion device shown in FIG. 8 has a set parallel configuration in which two power conversion devices 301 and 302 are connected in parallel to the power source 6 and the motor 52 that is a load. , 302 are regarded as one power conversion device. Therefore, it can be considered that the semiconductor module 31 of the power conversion device 301 and the semiconductor module 32 of the power conversion device 302 are connected in parallel within one phase. A filter 7 is provided between the power source 6 and the two power converters 301 and 302. The motor 52 includes two layers of a U1 phase, a V1 phase, and a W1 phase three-layer winding connected to the power conversion device 301, and a three-layer winding of the U2, V2, and W2 phases connected to the power conversion device 302. Has a system. The basic configuration of the semiconductor modules 31 and 32 is the same as that of the first embodiment.

  In FIG. 5, the semiconductor module 31 is connected between a direct current positive electrode (P1) and a direct current negative electrode (N1), and the semiconductor module 32 is connected between a direct current positive electrode (P2) and a direct current negative electrode (N2). . The winding 521 connected to the U1 terminal of the motor 52 and the winding 522 connected to the U2 terminal are not connected, but are electrostatically coupled by the stray capacitance 523 between the windings. For this reason, when the potential difference between the U1 terminal and the U2 terminal, that is, the AC output terminal 31AC and the AC output terminal 32AC, changes at time t5 and time t6 in FIG. There is a concern that this current may cause noise or increase the temperature of the wiring.

  Also in the present embodiment, basically the same effects as those of the first embodiment can be obtained. Further, as compared with FIG. 9, as shown in FIG. 3, the potential difference between the AC output terminal 31AC and the AC output terminal 32AC does not occur at time t5, so that the drive signal is reduced in order to reduce current sharing unevenness at time t5. It is not necessary to shift the timings when GP1 and GP2 are turned on, and the large potential difference generated from time t5 to time t6 is not generated. Alternatively, unlike FIG. 3, even when a potential difference remains between the AC output terminal 31AC and the AC output terminal 32AC, the difference can be reduced as compared with the conventional case, so that current sharing is not possible from time t5 to time t6. In order to reduce the uniformity, the period during which the drive signals GP1 and GP2 are turned on can be shortened, and the time during which the large potential difference that has occurred from time t5 to time t6 can be shortened.

  The third embodiment is a modification of the first and second embodiments.

  For example, in the delay setting procedure of the gate control unit 1 shown in FIG. 2, the delay time d is proportional to the current difference x (procedure 113), but is not proportional but is stepped according to the magnitude of the difference x. It may be a function to change.

  In the description so far, the synchronous rectification start timing is changed to change the delay time until the synchronous rectification starts. However, the present invention is not limited to this, and the length of the synchronous rectification period can be made different from each other. Therefore, it may be adjusted at the timing when the synchronous rectification is finished. In this case, the larger one of the currents Iac1 and Iac2 is adjusted so that the synchronous rectification ends first. In this case, the current can be detected until after synchronous rectification at the time t2 in FIG. Moreover, you may make it adjust by both the start timing and completion | finish timing of synchronous rectification. Therefore, the gate control unit 1 uses the semiconductor module with the larger current detected by the current detection unit 2 to turn on the MOSFET on the side in the reflux mode of the semiconductor module with the smaller current detected by the current detection unit 2. The gate control unit 1 may be earlier than the turn-on timing of the MOSFET on the side in the recirculation mode, or the gate control unit 1 of the MOSFET on the side in the recirculation mode of the semiconductor module with the smaller current detected by the current detection unit 2 The turn-off timing may be set later than the turn-off timing of the MOSFET on the side in the reflux mode of the semiconductor module with the larger current detected by the current detector 2, or both may be used in combination.

  Moreover, the loss can be reduced by using a MOSFET as the silicon carbide (SiC) device. However, it is not limited to a silicon carbide (SiC) device, and a device using other materials may be used. Similarly, a free-wheeling diode connected in reverse parallel to the MOSFET can also be reduced in loss by using a silicon carbide (SiC) Schottky barrier diode (SBD).

  In the above description, the case of converting from direct current to alternating current has been described as an example. However, the present invention can also be applied to the case of converting from alternating current to direct current in the regeneration mode.

  As mentioned above, although the Example of this invention has been described, the structure demonstrated by each Example so far is an example to the last, and this invention can be suitably changed within the range which does not deviate from a technical idea. Further, the configurations described in the respective embodiments may be used in combination as long as they do not contradict each other.

1: Gate control unit 2: Current detection unit 3: Switching circuit 31, 32: Semiconductor modules 31QP, 31QN, 32QP, 32QN: Switching elements 31DP, 31DN, 32DP, 32DN: Free-wheeling diodes 31P, 31N, 32P, 32N: DC input Terminals 31AC, 32AC: AC output terminals 41P, 41N, 42P, 42N: Gate drive circuits 51, 52: Motor 6: Power supply 7: Filter 10: Power converter control unit 11: Delay determination unit 21, 22: Current sensor 301, 302: Power converter 521, 522: Winding 523: Stray capacitance

Claims (10)

In a power conversion device having a switching circuit in which a plurality of semiconductor modules having a pair of upper and lower MOSFETs are connected in parallel within one phase, and converting direct current and alternating current,
A current detector for detecting the current on the AC side of each of the semiconductor modules;
A gate control unit that controls on and off of the MOSFET according to the current detected by the current detection unit;
The gate control unit is a time during which the MOSFET on the side that is in the reflux mode of the semiconductor module with the smaller current detected by the current detection unit is on during the period of the reflux mode in which the reflux current flows through any of the MOSFETs. Is made longer than the ON time of the MOSFET on the side in which the semiconductor module having the larger current detected by the current detection unit is in the reflux mode. In claim 1,
The current detection unit detects a current on an AC side of the semiconductor module using a current sensor provided on an AC side of the semiconductor module. In claim 1,
The current detection unit is configured to detect the current on the AC side of the semiconductor module by detecting the temperature of the MOSFET, assuming that the current is larger as the temperature of the MOSFET is higher. In any one of Claim 1 to 3,
The gate control unit determines when to turn on the MOSFET on the side of the semiconductor module with the smaller current detected by the current detection unit, and the circuit of the semiconductor module with the larger current detected by the current detection unit. A power conversion device characterized in that the power conversion device is set earlier than a timing at which a MOSFET on a mode side is turned on. In any one of Claims 1-4,
The gate control unit is configured to detect the turn-off timing of the MOSFET on the side of the semiconductor module having the smaller current detected by the current detection unit. The circulation mode of the semiconductor module having the larger current detected by the current detection unit. A power conversion device characterized in that the power conversion device is slower than the timing at which the MOSFET on the side to be turned off. In any of claims 1 to 5,
The MOSFET is a silicon carbide (SiC) device. In any one of Claim 1 to 6,
The semiconductor module includes a diode connected in reverse parallel to the MOSFET. In claim 7,
The power conversion device, wherein the diode is a silicon carbide (SiC) Schottky barrier diode. In any one of Claims 1-8,
When the direct current is converted into alternating current, the gate control unit is in the recirculation mode of the semiconductor module with the smaller current detected by the current detection unit in the recirculation mode period in which the recirculation current flows in any of the MOSFETs. A power conversion device characterized in that the time during which the side MOSFET is on is longer than the time during which the side MOSFET in the circulating mode of the semiconductor module with the larger current detected by the current detection unit is on. . In any one of Claim 1 to 9,
When the alternating current is converted into direct current, the gate control unit is set to the recirculation mode of the semiconductor module having the smaller current detected by the current detection unit in the recirculation mode period in which the recirculation current flows through any of the MOSFETs. A power conversion device characterized in that the time during which the side MOSFET is on is longer than the time during which the side MOSFET in the circulating mode of the semiconductor module with the larger current detected by the current detection unit is on. .