JP2023114456A - Flip-flop - Google Patents

Abstract

To solve the problem in which, the shift of a threshold voltage of a transistor that easily deteriorates is suppressed by applying an AC pulse to a gate of the transistor but in the case of using amorphous silicon as a semiconductor layer of the transistor, as a matter of course, a transistor that forms a circuit generating the AC pulse also results in the shift of the threshold voltage.SOLUTION: In a method, a signal is input to a gate electrode of a transistor that deteriorates easily through a transistor that is turned on, so that a shift of a threshold voltage of the transistor that deteriorates easily and a shift of a threshold voltage of the transistor that is turned on are suppressed. That is to say, an AC pulse is applied to the gate electrode of the transistor that deteriorates easily through a transistor in which a high potential (VDD) is applied to a gate electrode (or through an element with a resistor component).SELECTED DRAWING: Figure 1

Description

The present invention relates to a display device having a circuit configured using transistors. In particular, the present invention relates to a display device using an electro-optical element such as liquid crystal or a light-emitting element as a display medium, and a driving method thereof.

2. Description of the Related Art In recent years, display devices have been actively developed due to an increase in large display devices such as liquid crystal televisions. In particular, there is a technique for integrally forming a driver circuit (hereinafter also referred to as an internal circuit) including a pixel circuit and a shift register using a transistor made of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) on an insulating substrate. , low power consumption, and low cost. The internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter also referred to as an external circuit) via an FPC or the like, and its operation is controlled.

Among the internal circuits shown above, a shift register using a transistor made of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised.
FIG. 124A shows a configuration of a flip-flop included in a conventional shift register (Patent Document 1). The flip-flop in FIG. 124A includes transistors 11, 12,
having a transistor 13, a transistor 14, a transistor 15 and a transistor 17;
It is connected to the signal line 21 , the signal line 22 , the wiring 23 , the signal line 24 , the power line 25 and the power line 26 . A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. The operation period of the flip-flop in FIG. 124(A) is divided into a set period, a selection period, a reset period, and a non-selection period, as shown in the timing chart of FIG. 124(B). Selection period.

Here, the transistors 12 and 16 are on during the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layers of the transistors 12 and 16, the threshold voltage (Vth) fluctuates due to deterioration or the like. More specifically, the threshold voltage increases. In other words, in the conventional shift register, the threshold voltages of the transistors 12 and 16 rise and they cannot be turned on, so VSS cannot be supplied to the node 41 and the wiring 23, causing a malfunction.

In order to solve this problem, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3 devised a shift register capable of suppressing the shift of the threshold voltage of the transistor 12 . In Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), By inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor, the shift of the threshold voltages of the first transistor and the second transistor is suppressed.

Furthermore, in Non-Patent Document 4, a shift register is devised that can suppress the shift of the threshold voltage of not only the transistor 12 but also the transistor 16 . In Non-Patent Document 4, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and another new transistor (referred to as a third transistor) is arranged as a transistor. 16 (assumed to be the fourth transistor). Then, in the non-selection period, inverted signals are inputted to the gate electrodes of the first transistor and the gate electrode of the second transistor, respectively, and inverted signals are inputted to the gate electrodes of the third transistor and the gate electrode of the fourth transistor, respectively. By inputting the signal, the shift of the threshold voltages of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed.

Furthermore, in Non-Patent Document 5, the shift of the threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12 .

In the display devices of Non-Patent Documents 6 and 7, a shift register made up of amorphous silicon transistors is used as a scanning line driver circuit, and a single signal line is applied to the R, G, and B sub-pixels for video signal transmission. By inputting the signal, the number of signal lines is reduced to 1/3. In this way, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

Japanese Patent Application Laid-Open No. 2004-157508

Soo Young Yoon, et al. , ``Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure'', SOCIETY FOR INFORMATION DISPLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, p. 348-351 Binn Kim, et al. , ``a-Si Gate Driver Integration with Time Shared Data Driving'', Proceedings of The 12th International Display Workshops in connection with Asia Display 2005 , p. 1073-1076 Mindoo Chun, et al. , ``Integrated Gate Driver Using Highly Stable a-Si TFT's'', Proceedings of The 12th International Display Workshops in connection with Asia Display 2005, p. 1077-1080 Chun-Ching, et al. , ``Integrated Gate Driver Circuit Using a-Si TFT'', Proceedings of The 12th International Display Workshops in connection with Asia Display 2005, p. 1023-1026 Yong Ho Jang, et al. , ``A-Si TFT Integrated Gate Driver with AC-Driven Single Pull-down Structure'', SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p. 208-211 Jin Young Choi, et al. , ”A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNIC AL PAPERS, Volume XXXVII, p. 274-276 Yong Soon Lee, et al. , "Advanced TFT-LCD Data Line Reduction Method", SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p. 1083-1086

According to the conventional technology, by applying an AC pulse to the gate of a transistor that is likely to deteriorate, the shift of the threshold voltage of the transistor is suppressed. However, when amorphous silicon is used as a semiconductor layer of a transistor, a problem arises in that the threshold voltage of the transistor constituting a circuit for generating an AC pulse also shifts.
Also, it has been proposed to reduce the number of signal lines to 1/3 to reduce the number of contacts between the display panel and the driver IC (Non-Patent Document 6 and Non-Patent Document 7). There is a demand for a further reduction in the number of contacts in an IC.

In other words, a circuit technology for suppressing fluctuations in the threshold voltage of a transistor remains as a problem that cannot be solved by conventional techniques. A technique for reducing the number of contact points of the driver IC mounted on the display panel remains an issue. A remaining issue is how to reduce the power consumption of display devices. There remains a problem of increasing the size or increasing the definition of the display device.

An object of the invention disclosed in this specification is to provide an industrially useful technique by solving one or more of such problems.

In the display device according to the present invention, by inputting a signal to the gate electrode of the transistor which is easily deteriorated through the turned-on transistor, the threshold voltage of the transistor which is easily deteriorated is shifted and the threshold voltage of the transistor which is turned on is shifted. It suppresses the shift of i.e.
The present invention includes a configuration in which an AC pulse is applied to the gate electrode of a transistor that is susceptible to deterioration through a transistor (or through an element having a resistance component) to which a high potential (VDD) is applied to the gate electrode. .

Various forms of switches may be used as shown herein. Examples include electrical switches and mechanical switches. In other words, it is not limited to a specific one as long as it can control the flow of current. For example, a transistor (for example,
Bipolar transistor, MOS transistor, etc.), diodes (for example, PN diode, PIN diode, Schottky diode, MIM (MetalInsulat
or Metal) diode, MIS (Metal Insulator Semiconductor
uctor) diodes, diode-connected transistors, etc.), thyristors, and the like can be used. Alternatively, a logic circuit in which these are combined can be used as a switch.

When a transistor is used as a switch, the transistor simply operates as a switch; therefore, the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress off-state current, it is preferable to use a transistor having a polarity with a smaller off-state current. As a transistor with low off-state current, there are a transistor having an LDD region, a transistor having a multi-gate structure, and the like. Alternatively, an N-channel transistor is preferably used when the potential of the source terminal of the transistor operated as a switch operates in a state close to a low-potential power source (VSS, GND, 0 V, or the like). Conversely, the potential of the source terminal is
It is desirable to use a P-channel transistor when operating in a state close to a high-potential power supply (such as VDD). This is because when an N-channel transistor operates with its source terminal close to the low-potential power supply, and when a P-channel transistor operates with its source terminal close to the high-potential power supply, the absolute value of the gate-source voltage is Since it can be made large, the switching characteristic is improved. Also, since the source follower operation is less likely to occur, the magnitude of the output voltage is less likely to decrease.

A CMOS switch may be used as a switch by using both an N-channel transistor and a P-channel transistor. When a CMOS switch is used, current flows when either one of the P-channel transistor and the N-channel transistor is turned on, so that the switch easily functions as a switch. For example, the voltage can be output appropriately regardless of whether the voltage of the input signal to the switch is high or low. Furthermore, since the voltage amplitude value of the signal for turning on/off the switch can be reduced, power consumption can also be reduced.

When a transistor is used as a switch, the switch has an input terminal (one of the source terminal and the drain terminal), an output terminal (the other of the source terminal and the drain terminal), and a terminal for controlling conduction (gate terminal). there is On the other hand, when a diode is used as a switch, the switch may not have a terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce wiring for controlling terminals.

In this specification, when it is explicitly stated that “A and B are connected”, it means that A and B are electrically connected and that A and B are functionally connected. and A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, the configurations disclosed in this specification are not limited to predetermined connection relationships, such as the connection relationships shown in the drawings or text, and include connections other than the connection relationships shown in the drawings or text.

For example, when A and B are electrically connected, an element (for example, switch, transistor, capacitive element, inductor, resistive element, diode, etc.) that enables electrical connection between A and B is , A and B. Alternatively, when A and B are functionally connected, a circuit that enables functional connection between A and B (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (booster circuit,
step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources,
Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier,
A differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) may be arranged between A and B. Alternatively, assuming that A and B are directly connected, A and B
may be directly connected.

When we explicitly state that "A and B are directly connected", it means that A and B are directly connected (that is, there is no other element or other circuit between A and B). When A and B are electrically connected (that is, when A and B are connected by sandwiching another element or another circuit) case).

When we explicitly state that "A and B are electrically connected", it means that A and B are electrically connected (i.e., another element or device between A and B). When A and B are functionally connected (that is, when A and B are functionally connected via another circuit) case) and the case where A and B are directly connected (that is, the case where A and B are connected without interposing another element or another circuit between them). In other words, the explicit description of "electrically connected" is the same as the explicit description of "connected".

A display element, a display device having a display element, a light-emitting element, and a light-emitting device having a light-emitting element can have various modes and various elements. For example, as a display element, a display device, a light-emitting element or a light-emitting device, an EL element (organic EL element, inorganic EL element,
elements or EL elements containing organic and inorganic substances), electron-emitting devices, liquid crystal devices, electronic inks, electrophoretic devices, grating light valves (GLV), plasma displays (PDP)
, a digital micromirror device (DMD), a piezoelectric ceramic display, a carbon nanotube, and the like can be used as a display medium whose contrast, luminance, reflectance, transmittance, etc. are changed by electromagnetism. As a display device using an EL element, E
Field emission display (FED) and SED type flat display (SED: Surface-cond.
Liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct view liquid crystal displays, projection liquid crystal displays), electronic ink, electrophoresis, etc. There is electronic paper as a display device using elements.

Various types of transistors can be used as the transistors described in this specification. Therefore, there is no limitation on the type of transistor to be used. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also called microcrystalline or semi-amorphous) silicon, or the like can be used. The use of TFTs has various advantages. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, the manufacturing cost can be reduced and the size of the manufacturing apparatus can be increased. Since the manufacturing equipment can be made large, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, they can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Transistors on a transparent substrate can then be used to control the transmission of light through the display element. Alternatively, since the film thickness of the transistor is thin, part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

By using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve crystallinity and manufacture a transistor with good electrical characteristics. the result,
A gate driver circuit (scanning line driver circuit), a source driver circuit (signal line driver circuit), and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on a substrate.

By using a catalyst (such as nickel) when manufacturing microcrystalline silicon, crystallinity can be further improved, and a transistor with good electrical characteristics can be manufactured. At this time,
Crystallinity can be improved only by applying heat treatment without using a laser. As a result, the gate driver circuit (scanning line driving circuit) and part of the source driver circuit (analog switch, etc.) can be integrally formed on the substrate. Furthermore, when a laser is not used for crystallization, uneven crystallinity of silicon can be suppressed. Therefore, a clear image can be displayed.

However, it is possible to produce polycrystalline silicon and microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. As a result, it is possible to manufacture small-sized transistors with little variation in characteristics, size, shape, etc., high current supply capability, and the like. By using these transistors, a circuit with low power consumption can be formed or high integration can be achieved.

Alternatively, a transistor including a compound semiconductor or oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor obtained by thinning any of these compound semiconductors or oxide semiconductors can be used. I can. As a result, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, a transistor can be directly formed on a substrate having low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors are
It can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Furthermore, they can be deposited or formed at the same time as the transistors, reducing costs.

Alternatively, a transistor or the like formed by an inkjet method or a printing method can be used. These allow room temperature fabrication, low vacuum fabrication, or fabrication on large substrates. In addition, since it is possible to manufacture without using a mask (reticle),
The layout of transistors can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost can be reduced and the number of steps can be reduced. Furthermore, since the film is applied only to the necessary portions, the material is not wasted and the cost can be reduced as compared with the manufacturing method in which the film is formed on the entire surface and then etched.

Alternatively, a transistor including an organic semiconductor, a carbon nanotube, or the like can be used. These allow a transistor to be formed on a bendable substrate.
Therefore, it can be strongly impact-resistant.

In addition, various transistors can be used.

Various types of substrates on which transistors are formed can be used, and there is no particular limitation. Examples of substrates on which transistors are formed include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates,
Stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), leather substrates, rubber Substrates, stainless steel substrates, substrates with stainless steel foil, and the like can be used. Alternatively, the skin of animals such as humans (
The epidermis, dermis) or subcutaneous tissue may be used as a substrate. Alternatively, a transistor may be formed on one substrate, then transferred to another substrate, and placed on the other substrate. Substrates on which transistors are transferred include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates,
Cloth substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester)
Or recycled fibers (including acetate, cupra, rayon, recycled polyester), etc.)
, a leather substrate, a rubber substrate, a stainless steel substrate, a substrate having a stainless steel foil, and the like can be used. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of animals such as humans may be used as the substrate. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is hard to break, impart heat resistance, or reduce weight.

A transistor can have various configurations. Not limited to any particular configuration. For example, a multi-gate structure with two or more gate electrodes may be used. When the multi-gate structure is used, the channel regions are connected in series, resulting in a structure in which a plurality of transistors are connected in series. The multi-gate structure can reduce off-state current and improve reliability by increasing the withstand voltage of the transistor. Alternatively, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change so much, and the slope of the voltage-current characteristic can be made flat. By utilizing the flat slope of the voltage versus current characteristic, it is possible to realize an ideal current source circuit and an active load with a very high resistance value. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.
Alternatively, a structure in which gate electrodes are arranged above and below the channel may be used. The structure in which the gate electrodes are arranged above and below the channel increases the channel region, so that the current value can be increased. Alternatively, a depletion layer is easily formed, and the S value can be reduced. When the gate electrodes are arranged above and below the channel, the configuration is such that a plurality of transistors are connected in parallel.

Alternatively, a structure in which the gate electrode is arranged above the channel region or a structure in which the gate electrode is arranged below the channel region may be used. Alternatively, a staggered structure or an inverted staggered structure may be used, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. good. Also,
A source electrode or a drain electrode may overlap the channel region (or part thereof).
By forming a structure in which the source electrode and the drain electrode overlap with the channel region (or part thereof), it is possible to prevent the operation from becoming unstable due to accumulation of charge in part of the channel region. Also, an LDD region may be provided. By providing the LDD region, off-state current can be reduced, and reliability can be improved by improving the withstand voltage of the transistor. Alternatively, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and the slope of the voltage-current characteristic can be made flat.

In this specification, one pixel indicates the minimum unit of an image. Therefore, R (red) G
In the case of a full-color display device consisting of (green) and B (blue) color elements, one pixel consists of a dot of R color element, a dot of G color element, and a dot of B color element. and Note that the color elements are not limited to three colors, three or more colors may be used, and colors other than RGB may be used. For example, it may be RGBW (where W is white) by adding white. Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one color in RGB may be added to RGB. For example, it may be R, G, B1, and B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, R1, R2, G, and B may be used. By using such color elements, a more realistic display can be achieved and power consumption can be reduced. Note that one pixel may have a plurality of dots of color elements of the same color.
At that time, the plurality of color elements may have different sizes of areas that contribute to display. Further, gradation may be expressed by controlling each of a plurality of dots of color elements of the same color. This is called an area gradation method. Alternatively, a plurality of dots of the same color element may be used, and the signal supplied to each dot may be slightly different to widen the viewing angle. In other words, the potentials of the pixel electrodes of the plurality of color elements of the same color may be different. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

In this specification, one pixel indicates one element whose brightness can be controlled. Therefore, as an example, one pixel indicates one color element, and the single color element expresses brightness. Therefore, at that time, in the case of a color display device consisting of R (red), G (green) and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel and a B pixel. It shall consist of three pixels. Note that the color elements are not limited to three colors, three or more colors may be used, and colors other than RGB may be used. For example, it may be RGBW (where W is white) by adding white. Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Also, for example, a color similar to at least one color in RGB may be added to RGB. For example, it may be R, G, B1, and B2. B1 and B
2 are both blue, but have slightly different frequencies. Similarly, R1, R2, G,
It may be B. By using such color elements, a more realistic display can be achieved and power consumption can be reduced. As another example, when the brightness is controlled using a plurality of regions for one color element, one region may be used as one pixel. Therefore, as an example, when performing area gradation or having sub-pixels (sub-pixels), there are a plurality of areas for controlling brightness for each color element, and gradation is expressed by the entire area. However, one pixel may correspond to one region whose brightness is controlled. Therefore, in that case, one color element is composed of a plurality of pixels. Alternatively, even if one color element has a plurality of areas whose brightness is to be controlled, they may be grouped together and one color element may be defined as one pixel. Therefore, in that case, one color element is composed of one pixel. Further, when the brightness of one color element is controlled using a plurality of regions, the size of the region contributing to display may differ depending on the pixel. In addition, the viewing angle may be widened by slightly different signals supplied to each of the plurality of brightness control regions for each color element. That is, for one color element, the potentials of the pixel electrodes of the plurality of regions may be different. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

When one pixel (for three colors) is explicitly described, it is assumed that three pixels of R, G, and B are considered to be one pixel. When one pixel (for one color) is explicitly described, it is assumed that, when one color element has a plurality of areas, they are collectively considered as one pixel.

In this specification, pixels may be arranged (arranged) in a matrix. Here, the arrangement (arrangement) of the pixels in a matrix includes the case where the pixels are arranged in a straight line in the vertical direction or the horizontal direction, and the case where the pixels are arranged in a jagged line. For example, in the case of full-color display with three color elements (eg, RGB), a stripe arrangement and a delta arrangement of dots of three color elements are included. moreover,
Including the case of Bayer arrangement. The color elements are not limited to three colors, and may be more than three colors. For example, there are RGBW (W is white), and one or more colors such as yellow, cyan, and magenta are added to RGB. Also, the size of the display area may be different for each dot of the color element. Thereby, power consumption can be reduced. Alternatively, the life of the display element can be extended.

In this specification, an active matrix system in which pixels have active elements or a passive matrix system in which pixels do not have active elements can be used.

In the active matrix system, not only transistors but also various active elements (active elements, nonlinear elements) can be used as active elements (active elements, nonlinear elements). For example, MIM (MetalInsulatorMetal) and TFD (Th
inFilm Diode) or the like can also be used. These elements can be manufactured at low cost because of the small number of manufacturing steps. Alternatively, it is possible to increase the yield. Furthermore, since the size of the element is small, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

Active elements (active elements, non-linear elements)
It is also possible to use a passive matrix type that does not use . Since active elements (active elements, non-linear elements) are not used, the number of manufacturing processes is small and the manufacturing can be performed at low cost.
Alternatively, it is possible to increase the yield. Moreover, since an active element (active element, nonlinear element) is not used, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

A transistor is a device having at least three terminals including a gate, a drain, and a source, and having a channel region between the drain region and the source region, the drain region, the channel region, and the source region. A current can flow through it. Here, since the source and the drain vary depending on the structure of the transistor, operating conditions, etc., it is difficult to define which is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be called the source or the drain. In that case, as an example, they may be referred to as a first electrode and a second electrode, respectively.

A transistor may be a device having at least three terminals including a base, an emitter and a collector. In this case as well, the emitter and collector are sometimes referred to as the first terminal and the second terminal.

A gate means the whole including a gate electrode and a gate wiring (also called a gate line, a gate signal line, a scanning line, a scanning signal line, etc.) or a part of them. A gate electrode refers to a portion of a conductive film that overlaps a semiconductor forming a channel region with a gate insulating film interposed therebetween. Note that part of the gate electrode is LDD (Lightly Doped Dr.
ain) region or the source region and the drain region through the gate insulating film in some cases. A gate wiring is a wiring for connecting gate electrodes of transistors or connecting a gate electrode and another wiring.

However, there are portions (regions, conductive films, wirings, etc.) that function both as gate electrodes and as gate wirings. Such a portion (region, conductive film, wiring, etc.) may be called a gate electrode or a gate wiring. In other words, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a portion of a gate wiring that is extended and arranged overlaps a channel region, that portion (region, conductive film, wiring, etc.) functions as a gate wiring, but it also functions as a gate electrode. It is working. Therefore, such a portion (region, conductive film, wiring, etc.) may be called a gate electrode or a gate wiring.

A portion (a region, a conductive film, a wiring, etc.) formed of the same material as the gate electrode and connected to form the same island as the gate electrode may also be called the gate electrode. Similarly, a portion (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and connected to form the same island as the gate wiring may also be referred to as the gate wiring. A part like this (
region, conductive film, wiring, etc.) does not overlap with the channel region in a strict sense.
It may not have the function of connecting to another gate electrode. However, if the island is formed of the same material as the gate electrode or gate wiring and is the same as the gate electrode or gate wiring
There are parts (regions, conductive films, wiring, etc.) that are connected by forming Such portions (regions, conductive films, wirings, etc.) may also be called gate electrodes or gate wirings.

For example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected by a conductive film formed using the same material as the gate electrode. Such portions (regions, conductive films, wirings, etc.) are portions (regions, conductive films, wirings, etc.) for connecting gate electrodes, so they may be called gate wirings. can be regarded as one transistor, it may be called a gate electrode.
In other words, a portion (region, conductive film, wiring, etc.) that is formed of the same material as the gate electrode or the gate wiring and forms the same island as the gate electrode or the gate wiring is connected to the gate electrode or the gate wiring. You can call me Furthermore, for example, a conductive film in a portion that connects a gate electrode and a gate wiring and is formed of a material different from that of the gate electrode or the gate wiring may be called a gate electrode or a gate wiring. You can call it

A gate terminal refers to a portion of a gate electrode (region, conductive film, wiring, etc.) or a portion of a portion electrically connected to the gate electrode (region, conductive film, wiring, etc.).

When called a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, the gate line, the gate signal line, the scanning line, and the scanning signal line are wirings formed in the same layer as the gates of the transistors,
It may mean a wiring formed of the same material as the transistor gate or a wiring formed at the same time as the transistor gate. Examples include storage capacitor wiring, power supply wiring, and reference potential supply wiring.

A source means the whole including a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, etc.), or a part of them. A source region is a semiconductor region containing a large amount of P-type impurities (boron, gallium, etc.) or N-type impurities (phosphorus, arsenic, etc.). Therefore, a region containing a small amount of P-type or N-type impurities, a so-called LDD (Lightly Doped Drain) region, is not included in the source region. A source electrode is a portion of a conductive layer formed of a material different from that of a source region and electrically connected to the source region. However, the source electrode
It may be called a source electrode including the source region. A source wiring is a wiring for connecting source electrodes of pixels or connecting a source electrode and another wiring.

However, there are portions (regions, conductive films, wirings, etc.) that function both as source electrodes and as source wirings. Such a portion (region, conductive film, wiring, etc.) may be called a source electrode or a source wiring. In other words, there are regions where the source electrode and the source wiring cannot be clearly distinguished. For example, when a portion of a source wiring that is extended and arranged overlaps with a source region, that portion (region, conductive film, wiring, etc.) functions as a source wiring, but does not function as a source electrode. is also functioning. Therefore, such a portion (region, conductive film, wiring, etc.) may be called a source electrode or a source wiring.

A portion (region, conductive film, wiring, etc.) formed of the same material as the source electrode and connected by forming the same island as the source electrode, or a portion (region, conductive film, etc.) that connects the source electrode to another source electrode film, wiring, etc.) may also be called a source electrode. Furthermore, the portion overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected by forming the same island as the source wiring may also be called a source wiring. Strictly speaking, such portions (regions, conductive films, wirings, etc.) may not have the function of connecting to another source electrode. but,
There is a portion (region, conductive film, wiring, etc.) formed of the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring. Therefore, such portions (regions, conductive films, wirings, etc.) may also be called source electrodes or source wirings.

For example, a conductive film in a portion connecting a source electrode and a source wiring and formed of a material different from that of the source electrode or the source wiring may be called a source electrode.
You may call it a source wiring.

A source terminal refers to a portion of a region of a source region, a source electrode, or a portion electrically connected to the source electrode (region, conductive film, wiring, etc.).

When called source wiring, source line, source signal line, data line, data signal line, etc., the source (drain) of the transistor may not be connected to the wiring. In this case, the source wiring, the source line, the source signal line, the data line, and the data signal line are wiring formed of the same layer as the source (drain) of the transistor, and wiring formed of the same material as the source (drain) of the transistor. Alternatively, it may mean a wiring formed at the same time as the source (drain) of a transistor. Examples include storage capacitor wiring, power supply wiring, and reference potential supply wiring.

The drain is similar to the source.

A semiconductor device is a device having a circuit including semiconductor elements (transistors, diodes, thyristors, etc.). Furthermore, all devices that can function by utilizing semiconductor characteristics may be called semiconductor devices.

Display elements include optical modulation elements, liquid crystal elements, light emitting elements, EL elements (organic EL elements, inorganic EL elements,
elements or EL elements containing organic and inorganic substances), electron emitting elements, electrophoretic elements, discharge elements,
It refers to light reflection elements, light diffraction elements, digital micromirror devices (DMD), and the like. However, it is not limited to this.

A display device refers to a device having a display element. Note that the display device may be a display panel main body in which a plurality of pixels including display elements or peripheral driving circuits for driving the pixels are formed over the same substrate. The display device includes peripheral driving circuits arranged on a substrate by wire bonding, bumps, or the like, so-called chip-on-glass (COG)-connected IC chips, or TAB-connected IC chips. You can stay. Note that the display device may include a flexible printed circuit board (FPC) on which an IC chip, a resistive element, a capacitive element, an inductor, a transistor, and the like are attached. Note that the display device may include a printed wiring board (PWB) connected via a flexible printed circuit board (FPC) or the like and having an IC chip, a resistive element, a capacitive element, an inductor, a transistor, and the like mounted thereon. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include a lighting device, a housing, an audio input/output device, an optical sensor, and the like. Here, the lighting device such as the backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water cooling type, air cooling type), and the like. good.

A lighting device is a device having a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, hot cathode tube, etc.), a cooling device, and the like.

Note that a light-emitting device is a device having a light-emitting element or the like.

A reflecting device is a device having a light reflecting element, a light diffraction element, a light reflecting electrode, or the like.

A liquid crystal display device refers to a display device having a liquid crystal element. Liquid crystal displays include direct-view,
There are projection type, transmissive type, reflective type, semi-transmissive type, etc.

A driving device refers to a device having a semiconductor element, an electric circuit, or an electronic circuit. For example, a transistor that controls the input of a signal from a source signal line into a pixel (sometimes called a selection transistor or switching transistor), a transistor that supplies voltage or current to a pixel electrode, and a voltage or current to a light-emitting element is an example of a driving device. Furthermore, circuits that supply signals to gate signal lines (sometimes called gate drivers, gate line drive circuits, etc.), circuits that supply signals to source signal lines (source drivers,
is an example of a driver.

A display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflecting device, a driving device, and the like may overlap each other. For example, a display device may have a semiconductor device and a light-emitting device, or a semiconductor device may have a display device and a driving device.

In this specification, when it is explicitly stated that B is formed on A or B is formed on A, B is formed on A in direct contact with it. is not limited to A case where they are not in direct contact, that is, a case where another object intervenes between A and B shall be included. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals,
conductive films, layers, etc.).

Therefore, for example, when it is explicitly stated that layer B is formed on layer A (or on layer A), layer B is formed on layer A and in direct contact therewith. and a case where another layer (for example, layer C or layer D) is formed in direct contact with layer A, and layer B is formed in direct contact thereon. In addition, another layer (for example, layer C, layer D, etc.) may be a single layer or multiple layers.

Furthermore, the same applies to the case where it is explicitly described that B is formed above A, and is not limited to B being in direct contact with A. It shall include the case where another object intervenes. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed directly on the layer A and the case where the layer B is formed directly on the layer A and another layer (For example, layer C, layer D, etc.) are formed, and layer B is formed in direct contact thereon. In addition, another layer (for example, layer C, layer D, etc.) may be a single layer or multiple layers.

When it is explicitly stated that B is formed in direct contact with A, there is another object between A and B, including the case where B is formed in direct contact with A. If there is intervening, it shall not be included.

The same is true for B under A or B under A.

Characteristic deterioration of all the transistors included in the shift register can be suppressed. Therefore, malfunction of a semiconductor device to which the shift register is applied, such as a liquid crystal display device, can be suppressed.

1A and 1B illustrate the structure of a flip-flop described in Embodiment 1; FIG. 2 is a timing chart for explaining the operation of the flip-flop shown in FIG. 1; FIG. 2 is a diagram for explaining the operation of the flip-flop shown in FIG. 1; 1A and 1B illustrate the structure of a flip-flop described in Embodiment 1; FIG. 1A and 1B illustrate the structure of a flip-flop described in Embodiment 1; FIG. 4A and 4B are timing charts for explaining the operation of the flip-flop described in Embodiment 1; 1A and 1B illustrate the structure of a flip-flop described in Embodiment 1; FIG. 4A and 4B illustrate the structure of the display device described in Embodiment 1. FIG. FIG. 9 is a timing chart for explaining a write operation of the display device shown in FIG. 8; FIG. 1A and 1B illustrate a structure of a shift register described in Embodiment 1; FIG. 11 is a timing chart for explaining the operation of the shift register shown in FIG. 10; FIG. 11 is a timing chart for explaining the operation of the shift register shown in FIG. 10; FIG. 1A and 1B illustrate a structure of a shift register described in Embodiment 1; FIG. 1A and 1B illustrate a structure of a shift register described in Embodiment 1; FIG. 1A and 1B illustrate a structure of a shift register described in Embodiment 1; FIG. 4A and 4B illustrate the structure of a display device described in Embodiment 2; 1A and 1B illustrate a structure of a shift register described in Embodiment 1; FIG. 4A and 4B illustrate the structure of the display device described in Embodiment 1. FIG. 19 is a timing chart for explaining a write operation of the display device shown in FIG. 18; 4A and 4B illustrate the structure of the display device described in Embodiment 1. FIG. 1A and 1B illustrate the structure of a flip-flop described in Embodiment 1; FIG. 4A and 4B each illustrate a structure of a flip-flop described in Embodiment 2; FIG. 12A and 12B illustrate the structure of a flip-flop described in Embodiment 4; FIG. FIG. 24 is a timing chart for explaining the operation of the flip-flop shown in FIG. 23; FIG. FIG. 2 is a top view of the flip-flop shown in FIG. 1; FIG. 14 is a diagram for explaining the configuration of the buffer shown in FIG. 13; 12A and 12B illustrate the structure of a flip-flop described in Embodiment 3; FIG. 28 is a timing chart for explaining the operation of the flip-flop shown in FIG. 27; FIG. 4A and 4B illustrate the structure of a shift register described in Embodiment 3; FIG. 30 is a timing chart for explaining the operation of the shift register shown in FIG. 29; FIG. 4A and 4B are timing charts for explaining the operation of the flip-flop described in Embodiment 2; 4A and 4B are timing charts for explaining the operation of the flip-flop described in Embodiment 2; 4A and 4B illustrate the structure of a shift register described in Embodiment 2; 4A and 4B illustrate the structure of a shift register described in Embodiment 2; 34 is a timing chart for explaining the operation of the shift register shown in FIG. 33; 34 is a timing chart for explaining the operation of the shift register shown in FIG. 33; FIG. 10 illustrates a structure of a signal line driver circuit described in Embodiment 5; 38 is a timing chart for explaining the operation of the signal line driver circuit shown in FIG. 37; FIG. 10 illustrates a structure of a signal line driver circuit described in Embodiment 5; 40 is a timing chart for explaining the operation of the signal line driver circuit shown in FIG. 39; FIG. 10 illustrates a structure of a signal line driver circuit described in Embodiment 5; 12A and 12B illustrate a structure of a protection diode described in Embodiment 6; FIG. 12A and 12B illustrate a structure of a protection diode described in Embodiment 6; FIG. 12A and 12B illustrate a structure of a protection diode described in Embodiment 6; FIG. 12A and 12B illustrate the structure of a display device described in Embodiment 7. FIG. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; FIG. 2 is a cross-sectional view of a display element of a semiconductor device; FIG. 2 is a cross-sectional view of a display element of a semiconductor device; FIG. 2 is a cross-sectional view of a display element of a semiconductor device; FIG. 2 is a top view of a display element of a semiconductor device; FIG. 2 is a top view of a display element of a semiconductor device; FIG. 2 is a top view of a display element of a semiconductor device; FIG. 4 illustrates a peripheral circuit configuration of a semiconductor device; FIG. 4 illustrates a peripheral circuit configuration of a semiconductor device; FIG. 4 illustrates a panel circuit configuration of a semiconductor device; FIG. 4 illustrates a panel circuit configuration of a semiconductor device; Sectional drawing of a semiconductor device. FIG. 3 illustrates a peripheral circuit configuration of a semiconductor device; Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. Sectional drawing of a semiconductor device. 4A and 4B are diagrams for explaining peripheral components of a semiconductor device; FIG. 4 illustrates a peripheral circuit configuration of a semiconductor device; 4A and 4B are diagrams for explaining peripheral components of a semiconductor device; 4A and 4B are diagrams for explaining peripheral components of a semiconductor device; 4A and 4B are diagrams for explaining peripheral components of a semiconductor device; 4A and 4B illustrate a semiconductor device; 1A and 1B illustrate one driving method of a semiconductor device; FIG. 1A and 1B illustrate one driving method of a semiconductor device; FIG. 1A and 1B illustrate one driving method of a semiconductor device; FIG. 1A and 1B illustrate one driving method of a semiconductor device; FIG. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device; FIG. 2 is a cross-sectional view of a display element of a semiconductor device; 1A and 1B illustrate a device for forming a display element of a semiconductor device; 1A and 1B illustrate a device for forming a display element of a semiconductor device; 1A and 1B illustrate one driving method of a semiconductor device; FIG. 1A and 1B illustrate one driving method of a semiconductor device; FIG. 1A and 1B illustrate one pixel circuit of a semiconductor device; 1A and 1B illustrate one pixel circuit of a semiconductor device; 4A and 4B illustrate a process for manufacturing a semiconductor device; 4A and 4B illustrate a display element of a semiconductor device; 4A and 4B illustrate a display element of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 4A and 4B illustrate the structure of a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; 1A and 1B illustrate electronic devices each including a semiconductor device; FIG. 14 is a diagram for explaining the configuration of the buffer shown in FIG. 13; FIG. 4 is a diagram for explaining the configuration and timing chart of a conventional flip-flop;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. Those skilled in the art will readily appreciate, however, that the present invention may be embodied in many different forms and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. be done. Therefore, it should not be construed as being limited to the description of this embodiment.

(Embodiment 1)
In this embodiment mode, a structure and a driving method of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit will be described.

A basic configuration of the flip-flop of this embodiment will be described with reference to FIG. The flip-flop shown in FIG. 1 includes a first transistor 101, a second transistor 102, and a third transistor.
a transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, and a seventh transistor 107; In this embodiment mode, the first transistor 101, the second transistor 102, the third transistor 103, and the fourth transistor
transistor 104, fifth transistor 105, sixth transistor 106, and seventh
The transistor 107 of is an N-channel type transistor, and the voltage between the gate and the source (V
gs) exceeds the threshold voltage (Vth), it shall become conductive.

The connection relationship of the flip-flops in FIG. 1 will be described. The first transistor of the first transistor 101
(one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125 , and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to the third wiring 12 .
3. A first electrode of the second transistor 102 is connected to the fourth wiring 124 and a second electrode of the second transistor 102 is connected to the third wiring 123 . The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102, and the third transistor 103 is connected to the gate electrode of the second transistor 102.
03 is connected to the seventh wiring 127 . A first electrode of the fourth transistor 104 is connected to a ninth wiring 129, a second electrode of the fourth transistor 104 is connected to a gate electrode of the second transistor 102, and a gate of the fourth transistor 104 is connected. An electrode is connected to the gate electrode of the first transistor 101 . A first electrode of the fifth transistor 105 is connected to an eighth wiring 128, a second electrode of the fifth transistor 105 is connected to a gate electrode of the first transistor 101, and a gate of the fifth transistor 105 is connected. An electrode is connected to the first wiring 121 . The first electrode of the sixth transistor 106 is connected to the tenth wiring 1
30, the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101, and the gate electrode of the sixth transistor 106 is connected to the second transistor 1
02 gate electrode. A first electrode of the seventh transistor 107 is connected to the eleventh wiring 131, and a second electrode of the seventh transistor 107 is connected to the first transistor 101.
, and the gate electrode of the seventh transistor 107 is connected to the second wiring 122 .

Note that the gate electrode of the first transistor 101, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the second electrode of the seventh transistor 107 A node 141 is a connection point of the electrodes of . Furthermore, the second
A node 142 is a connection point of the gate electrode of the transistor 102, the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, and the gate electrode of the sixth transistor .

Note that the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 13
1 may be connected to each other or may be the same wiring. Furthermore, the seventh wiring 127 and the eighth wiring 128 may be connected to each other or may be the same wiring.

Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 are the first signal line, the second signal line, and the third signal line, respectively. , fourth signal line, and fifth signal line. Further, the fourth wiring 124, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are used as the first power supply line and the second power supply line, respectively. line, third power line, fourth power line, fifth power line, and sixth power line.

Note that the potential of V1 is supplied to each of the seventh wiring 127 and the eighth wiring 128,
A potential of V2 is supplied to the wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131, respectively. Furthermore, V1>V2.

Note that signals are input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126, respectively. A signal input to the first wiring 121 is a start signal, a signal input to the second wiring 122 is a reset signal, and a signal input to the fifth wiring 125 is a first clock signal. , the signal input to the sixth wiring 126 is the second clock signal. Further, the signals input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126, respectively, have an H signal potential of V1 (hereinafter also referred to as an H level) and an L signal potential. is a digital signal whose potential is V2 (hereinafter also referred to as L level).

Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the second wiring 122 to the eleventh wiring 131, respectively.

Note that a signal is output from the third wiring 123 . A signal output from the third wiring 123 is an output signal of the flip-flop in each stage and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop in the next stage. Further, in the signals output from the third wiring 123, the potential of the H signal is V1 (hereinafter also referred to as the H level) and the potential of the L signal is V2.
(hereinafter also referred to as L level) digital signal.

Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart of FIG. 2 and FIG. Further, the timing chart of FIG. 2 will be described by dividing it into a selection period and a non-selection period. Furthermore, the non-selection period is divided into a first non-selection period, a second non-selection period, a set period and a reset period. Furthermore, in the non-selection period, the set period,
The operation period other than the selection period and the reset period repeats the first non-selection period and the second non-selection period in order.

2, signals 221, 225, 226, potentials 241, 242,
The signal 222 and the signal 223 are the signal input to the first wiring 121, the signal input to the fifth wiring 125, the signal input to the sixth wiring 126, the potential of the node 141, and the potential of the node 142, respectively. , a signal input to the second wiring 122 , and a signal output from the third wiring 123 .

First, in the set period shown in FIGS. 2A and 3A, the fifth transistor 105 is turned on because the signal 221 is at H level, and the seventh transistor 107 is turned off because the signal 222 is at L level. The potential of the node 141 at this time is the second potential of the fifth transistor 105 .
becomes a source electrode, and the potential of the eighth wiring 128 is subtracted by the threshold voltage of the fifth transistor 105. 105 threshold voltage). Therefore, the first transistor 101 and the fourth transistor 104 are turned on, and the fifth transistor 105 is turned off. At this time, the potential of the node 142 (potential 242) is the same as that of the third transistor 103 and the fourth transistor 1
04 (L/W and applied voltage), which is V2+β (β: any positive number). Furthermore, β<Vth(102) (Vth(102): second transistor 10
2 threshold voltage) and β<Vth(106) (threshold voltage of the sixth transistor 106). That is, the potential (V2) of the ninth wiring 129 and the potential (V1) of the sixth wiring 126
) and the potential difference (V1−V2) between the third transistor 103 and the fourth transistor 104
is divided by Therefore, the second transistor 102 and the sixth transistor 106
turns off. Thus, in the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input, so that the potential of the third wiring 123 becomes V2. therefore,
An L signal is output from the third wiring 123 . In addition, node 141 has a potential of V1-Vt
It becomes a floating state while maintaining h(105).

In the selection period shown in FIGS. 2B and 3B, the signal 221 is at L level and the fifth transistor 105 is turned off, and the signal 222 remains at L level, so that the seventh transistor 10 is turned off.
7 remains off. At this time, the potential of the node 141 is maintained at V1-Vth (105). Therefore, the first transistor 101 and the fourth transistor 104 remain on. At this time, the potential of the node 142 is V because the sixth wiring 126 is at L level.
2. Therefore, the second transistor 102 and the sixth transistor 106 remain off. Here, since an H signal is input to the fifth wiring 125, the potential of the third wiring 123 starts to rise. At this time, the potential of node 141 is V
It rises from 1-Vth(105) and becomes V1+Vth(101)+α (Vth(101): threshold voltage of the first transistor 101, α: any positive number). Therefore, the third
Since the potential of the wiring 123 of 1 is equal to that of the wiring 125 of the fifth wiring 125, it becomes V1. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 101 . Thus, during the selection period, the third wiring 123
is electrically connected to the fifth wiring 125 to which an H signal is input, the potential of the third wiring 123 becomes V1. Therefore, an H signal is output from the third wiring 123 .

In the reset period shown in FIGS. 2C and 3C, the signal 221 remains at the L level, so the fifth transistor 105 remains off, the signal 222 remains at the H level, and the seventh transistor 107 is turned off. turns on. The potential of the node 141 at this time is the potential of the 11th wiring (
V2) is supplied through the seventh transistor 107, resulting in V2. Therefore, the first transistor 101 and the fourth transistor 104 are turned off. Node 142 at this time
is applied to the sixth wiring 103 with the second electrode of the third transistor 103 serving as the source electrode.
V1-Vth(103) (Vth(103): threshold voltage of third transistor 103). Therefore, the second transistor 102 and the sixth transistor 106 are turned on. Thus, in the reset period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, an L signal is output from the third wiring 123 .

In the first non-selection period shown in FIGS. 2D and 3D, the signal 221 remains at the L level, so the fifth transistor 105 remains off, and the signal 222 becomes the L level. 7
transistor 107 is turned off. The potential of the node 142 at this time is the sixth wiring 126
becomes V2 because an L signal is input to . Therefore, the second transistor 102 and the sixth transistor 106 are turned off. Since the node 141 at this time is in a floating state, the potential of the node 141 is set to V
keep at 2. Therefore, the first transistor 101 and the fourth transistor 104 remain off. As described above, the third wiring 123 is in a floating state in the first non-selection period, so that the potential of the third wiring 123 is maintained at V2.

In the second non-selection period shown in FIGS. 2E and 3E, the signal 221 remains at the L level, so the fifth transistor 105 remains off, and the signal 222 remains at the L level, so the first transistor 105 remains off. 7 transistor 107 remains off. The potential of the node 142 at this time is the sixth
An H signal is input to the wiring 126 of , and the transistor 104 is turned off, so V1-Vth
(103). Therefore, the second transistor 102 and the sixth transistor 106 are turned on. At this time, the potential of the node 141 is the sixth potential (V2) of the tenth wiring 130.
remains at V2 because it is supplied through transistor 106 of . Therefore, the first transistor 101 and the fourth transistor 104 remain off. Thus, in the second non-selected period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 remains at V2. Therefore, the L signal is connected to the third wiring 12
3 is output.

As described above, the flip-flop in FIG. 1 uses the bootstrap operation in the selection period to make the potential of the node 141 higher than V1+Vth(101), thereby setting the potential of the third wiring 123 to V1. be able to. Furthermore, the flip-flop of FIG. 1 can reduce the layout area and reduce the device size by performing this bootstrap operation using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 101 . Advantages such as a reduction in the number can be obtained.

Furthermore, in the flip-flop of FIG. 1, since the second transistor 102 and the sixth transistor 106 are turned on only during the second non-selected period, the threshold voltages of the second transistor 102 and the sixth transistor 106 are Shift can be suppressed.

Note that the flip-flop in FIG. 1 supplies V1 to the gate electrode of the third transistor 103 and inputs the second clock signal to the first electrode, thereby reducing the threshold voltage of the third transistor 103 to Shifts can also be inhibited.

Furthermore, the flip-flop of FIG.
04, since the fifth transistor 105 and the seventh transistor 107 are not turned on in the first non-selection period and the second non-selection period, the first transistor 101, the fourth transistor 104, the fifth transistor 105 and the A shift in the threshold voltage of the seventh transistor 107 can be suppressed.

Further, in the flip-flop of FIG. 1, even if the potential of the node 141 and the potential of the third wiring 123 fluctuate during the first non-selection period, the potential of the node 141 and the third wiring 123 are changed in the next second non-selection period. By supplying V2 to 123, the potential of the node 141 and the potential of the third wiring 123 can be reset to V2. Therefore, the flip-flop in FIG. 1 can suppress malfunction caused by fluctuations in the potentials of the node 141 and the third wiring 123 due to the floating state of the node 141 and the wiring 123 .

Furthermore, since the flip-flop of FIG. 1 can suppress the threshold shift of the transistor,
Malfunction caused by the threshold voltage shift of the transistor can be suppressed.

Further, in the flip-flop in FIG. 1, all of the first to seventh transistors 101 to 107 are N-channel transistors. Therefore, the flip-flop of FIG. 1 can use amorphous silicon as the semiconductor layer of the transistor, so that the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved. Furthermore, it becomes possible to manufacture a large-sized display device. However, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

Note that the flip-flop in FIG. 1 can suppress the deterioration of transistor characteristics even when amorphous silicon, which significantly deteriorates the characteristics (threshold voltage shift), is used as the semiconductor layer of the transistor, and thus has a long life. display device can be manufactured.

Here, functions of the first transistor 101 to the eighth transistor 108 are described. The first transistor 101 has a function of selecting the timing of supplying the potential of the fifth wiring 125 to the third wiring 123 and raising the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor. do. second transistor 10
2 has a function of selecting the timing of supplying the potential of the fourth wiring 124 to the third wiring 123 and functions as a switching transistor. The third transistor 103 is the sixth
and the potential of the ninth wiring 129, and functions as a resistor or a transistor having a resistance component. The fourth transistor 104 is connected to the ninth wiring 129
to the node 142, and functions as a switching transistor. The fifth transistor has a function of selecting the timing of supplying the potential of the eighth wiring to the node 141 and functions as an input transistor. The sixth transistor 106 has a function of selecting the timing of supplying the potential of the tenth wiring 130 to the node 141 and functions as a switching transistor. seventh transistor 10
7 has a function of selecting the timing of supplying the potential of the eleventh wiring 131 to the node 141 and functions as a switching transistor. However, the first to seventh transistors 101 to 107 are not limited to transistors as long as they have the functions described above. For example, the second transistor 102 functioning as a switching transistor
, the fourth transistor 104, the sixth transistor 106 and the seventh transistor 107
may be diodes, CMOS analog switches, or various logic circuits as long as they are elements having a switching function. Further, the fifth transistor 105 functioning as an input transistor only needs to have a function of increasing the potential of the node 141 to select the timing to turn it off, and a PN junction diode, a diode-connected transistor, or the like can be used. good too.

Note that the third transistor 103 and the fourth transistor 104 constitute an AC pulse generation circuit. The AC pulse generation circuit outputs a signal input from the first electrode of the third transistor 103 to the node 142 . However, the AC pulse generation circuit outputs an L signal to the node 142 regardless of the signal input from the first electrode of the third transistor 103 when the gate electrode of the fourth transistor 104 is at H level.

Note that in the flip-flop of this embodiment mode, the W/L value of the first transistor 101 is the largest among the W/L values of the first transistor 101 to the seventh transistor 107. , the fall time and rise time of the signal 223 can be shortened. Thus, the flip-flop of this embodiment can output a signal with little distortion or delay even when a large load is connected to the wiring 123 .

Furthermore, in the flip-flop of this embodiment, the W/L of the first transistor 101
is preferably 2 to 5 times the value of W/L of the fifth transistor 105, more preferably 3 to 4 times. Thus, the flip-flop in Embodiment 1 can output a signal with little distortion or delay even when a large load is connected to the wiring 123 .

Furthermore, in the flip-flop of this embodiment, the W/L of the fourth transistor 104
is larger than the value of W/L of the third transistor 103, the potential of the node 142 can be reduced during the set period. Accordingly, the flip-flop of this embodiment can reliably turn off the sixth transistor 106 during the set period, so that malfunction can be suppressed.

Furthermore, in the flip-flop of this embodiment, the L value of the third transistor 103 is preferably larger than the L value of the fourth transistor 104, more preferably 2
double to triple. Accordingly, in the flip-flop of this embodiment mode, the W/L value of the third transistor 103 is small, so that the W value of the fourth transistor 104 can be small, and the layout area can be reduced. be able to.

Note that the arrangement and number of transistors are not limited to those shown in FIG. 1 as long as the same operation as in FIG. 1 is performed. As can be seen from FIG. 3 describing the operation of the flip-flop in FIG. It suffices if there is continuity as indicated by the solid lines shown in (A) to (E). Therefore, transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic circuits, etc. can be newly arranged as long as the configuration is such that they can be arranged and operated so as to satisfy this requirement. good too.

For example, in the flip-flop illustrated in FIG. 4A, a capacitor 401 is provided between the gate electrode and the second electrode of the first transistor 101 to stabilize the bootstrap operation in the selection period. can be done. Furthermore, the flip-flop of FIG.
can reduce the parasitic capacitance between the gate electrode and the second electrode of the transistor 101 of
Each transistor can switch at high speed. Alternatively, a transistor 402 may be used as the capacitor 401 as illustrated in FIG. 4B. The transistor 402 has a gate electrode connected to the node 141 and a first electrode and a second electrode connected to the third wiring 123, so that the transistor 402 can function as a capacitor having a large capacitance component. However, the transistor 402 can function as a capacitor even when one of the first electrode and the second electrode is floating. It should be noted that common reference numerals are used for portions that are common to the configuration of FIG. 1, and description thereof will be omitted.

Note that in the capacitor 401, a gate insulating film may be used as an insulating layer and a gate electrode layer and a wiring layer may be used as conductive layers, or a gate insulating film may be used as an insulating layer and a gate electrode layer and an impurity may be used as conductive layers. An added semiconductor layer may be used, or an interlayer film (insulating film) may be used as an insulating layer.
A wiring layer and a transparent electrode layer may be used as the conductive layer. However, in the case where a gate electrode layer and a wiring layer are used as conductive films in the capacitor 401 , the gate electrode layer is connected to the gate electrode of the first transistor 101 and the wiring layer is connected to the second electrode of the first transistor 101 . should be connected. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101 and the wiring layer is directly connected to the second electrode of the first transistor 101. do it. This is because an increase in the layout area of the flip-flop due to the placement of the capacitive element 401 is small.

As another example, the flip-flop shown in FIG.
electrode to the first wiring 121 (by diode-connecting the first transistor 101), the eighth wiring 128 becomes unnecessary, and the wiring and power supply (V1) can be reduced by one. can. It should be noted that common reference numerals are used for portions that are common to the configuration of FIG. 1, and description thereof will be omitted.

As another example, the flip-flop illustrated in FIG. 4D can reduce one wiring and one power supply by using the resistor 403 instead of the third transistor 103 . moreover,
The flip-flop in FIG. 4D changes the potential of the node 142 to the sixth level during the second non-selection period.
can be made equal to the potential (V1) of the wiring 126, the driving capability can be improved.
It should be noted that common reference numerals are used for portions that are common to the configuration of FIG. 1, and description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 7A, by connecting the gate electrode of the second transistor 102 to a wiring 711 to which an arbitrary signal is input, the second transistor 10
2 can be reverse biased. Furthermore, the Vgs of the second transistor 102
can be made smaller. Therefore, threshold shift of the second transistor 102 can be further suppressed. It should be noted that common reference numerals are used for portions that are common to the configuration of FIG. 1, and description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 7B, the gate electrode of the second transistor 102 is connected to the sixth wiring 126 so that the second transistor 102 can be turned on even during the set period. , the driving ability can be improved. Furthermore, the third wiring 1
23 noise can be reduced. 1 are denoted by common reference numerals, and description thereof will be omitted.

As another example, the flip-flop illustrated in FIG. 7C uses a diode-connected transistor 701 and a diode-connected transistor 702 instead of the third transistor 103, whereby one wiring and one power supply can be reduced. . A first electrode of the transistor 701, a second electrode of the transistor 702, and a gate electrode of the transistor 701 are connected to the sixth wiring 1.
26 , and the second electrode of transistor 701 , the second electrode of transistor 702 and the gate electrode of transistor 702 are connected to node 141 . That is, the sixth wiring 1
26 and node 141 are connected in parallel. In addition, Fig. 1
The same reference numerals are used for the parts that are common with the configuration of , and the description thereof is omitted.

As another example, as shown in FIG. 21A, the sixth transistor 106 is not necessarily required. This is because the sixth transistor 106 is not necessarily required as long as the potential of the node 141 can be maintained at L level in the non-selected period. Therefore, the number of transistors in the flip-flop in FIG. 21A can be reduced, so that merits such as reduction in layout area can be obtained. 1 are denoted by common reference numerals, and description thereof will be omitted.

As another example, as shown in FIG. 21B, instead of the fourth transistor 104, the eighth
of the transistor 2108 may be used. A first electrode of the eighth transistor 2108 is connected to a twelfth wiring 2132, and a second electrode of the eighth transistor 2108 is connected to the node 14.
2, and the gate electrode of the eighth transistor 2108 is connected to the first wiring 121 . Further, V2 is supplied to the twelfth wiring 2132 . By doing this, FIG. 21 (B
), the ON/OFF of the eighth transistor 2108 is controlled by the start signal, so that the fall time of the potential of the node 142 can be shortened during the set period, and the second transistor 102 and The time at which the sixth transistor 106 is turned off can also be shortened. Furthermore, in the flip-flop in FIG. 21B, the sixth transistor 106 is turned off earlier, so that the potential rise time of the node 141 can be shortened in the set period. Thus, the flip-flop in FIG. 21B can improve the driving capability of the flip-flop. It should be noted that common reference numerals are used for portions that are common to the configuration of FIG. 1, and description thereof will be omitted.

Note that the eighth wiring 128 is the same as the fourth wiring 124, the ninth wiring 129, and the tenth wiring 130.
Alternatively, it may be connected to the eleventh wiring 131 .

As another example, an eighth transistor 2108 may be added as shown in FIG. Since the eighth transistor 2108 needs only to set the potential of the node 142 to L level when the start signal is at H level, the transistor size can be reduced. Furthermore, Fig. 22
In the flip-flop of (C), the ON/OFF state of the eighth transistor 2108 is controlled by the start signal, so that the driving capability of the flip-flop can be improved similarly to the flip-flop of FIG. 22(B). . 1 and 21(B) are denoted by common reference numerals, and the description thereof is omitted.

Note that the connection relationship of each wiring is not limited to that shown in FIG. 1 as long as it performs the same operation as in FIG.
As can be seen from FIG. 3 describing the operation of the flip-flop in FIG. It suffices if there is continuity as indicated by the solid lines shown in (A) to (E). Therefore, each wiring should be arranged or connected so as to satisfy this.

For example, the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, the first electrode of the sixth transistor 106, and the seventh transistor 107 are illustrated in FIG. may be connected to the sixth wiring 506 . Further, the first electrode of the third transistor 103 and the first electrode of the fifth transistor 105 may be connected to the seventh wiring 507 . Thus, the flip-flop of FIG. 5A can reduce the number of wirings from 11 to 7, compared with the flip-flop of FIG. Furthermore, the flip-flop in FIG. 5A can improve the yield of shift registers by reducing the number of wirings. Further, the flip-flop in FIG. 5A can reduce the wiring area and reduce the layout area of the shift register. Further, since the width of each wiring can be increased in the flip-flop in FIG. 5A, the voltage drop can be reduced and the driving capability of the shift register can be improved. It should be noted that common reference numerals are used for portions that are common to the configuration of FIG. 1, and description thereof will be omitted.

Note that a sixth wiring 506 illustrated in FIG. 5A corresponds to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 illustrated in FIG. Further, FIG. 5(A)
corresponds to the seventh wiring 127 and the eighth wiring 128 illustrated in FIG. Furthermore, a first wiring 501, a second wiring 502, and a third wiring 50 illustrated in FIG.
3. The fourth wiring 504 and the fifth wiring 505 are connected to the first wiring 121 shown in FIG.
, the second wiring 122 , the third wiring 123 , the fifth wiring 125 , and the sixth wiring 126 .

Note that the sixth wiring 506 and the seventh wiring 507 may be called a first power supply line and a second power supply line, respectively. Further, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 are used as the first signal line, the second signal line, and the third signal line, respectively. line, fourth signal line, and fifth signal line.

As another example, as shown in FIG. 5B, the first electrode of the fourth transistor 104 is the eighth
may be connected to the wiring 508 of The flip-flop in FIG. 5B can suppress malfunction due to a voltage drop in the sixth wiring 506 by passing instantaneous current generated in the fourth transistor 104 in the set period through the eighth wiring 508 . In addition, FIG. 1 and FIG. 5(A)
The same reference numerals are used for the parts that are common with the configuration of , and the description thereof is omitted.

As another example, as shown in FIG. 5C, the first electrode of the second transistor 102 is the ninth
may be connected to the wiring 509 of the In the flip-flop of FIG. 5B, an instantaneous current generated in the second transistor 102 in the reset period is caused to flow through the ninth wiring 509, thereby
malfunction due to a voltage drop in the wiring 506 can be suppressed. 1 and 5 (A
) are denoted by common reference numerals, and description thereof is omitted.

As another example, as shown in FIG. 5D, the gate electrode of the third transistor 103 is the first
0 wiring 510 . The flip-flop in FIG.
10, the potential of the gate electrode of the second transistor 102 and the potential of the gate electrode of the sixth transistor 106 decrease in the second non-selected period. Characteristic deterioration of the sixth transistor 106 can be suppressed. 1 and 5A are denoted by common reference numerals, and descriptions thereof are omitted.

Note that the power supply potential, signal amplitude, and signal timing are not limited to those shown in the timing chart of FIG. 2 as long as they perform the same operation as in FIG. As can be seen from FIG. 3 describing the operation of the flip-flop in FIG. It suffices if there is continuity as indicated by the solid lines shown in (A) to (E). Therefore, the power supply potential, signal amplitude and signal timing may be changed so as to satisfy this.

For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the fifth wiring 125
, the period during which the H signal is input to the sixth wiring 126 may be shortened. FIG. 6 shows that the timing at which the signal switches from the L level to the H level is the period Ta, compared with the timing chart of FIG.
Delayed by 1, the timing at which the signal switches from the H level to the L level is advanced by the period Ta2. In other words, in FIG. 6, compared with FIG. 2, the period during which the signal is at the H level (period Tb
) is shortened by period Ta1+period Ta2. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current of each wiring is small, so power saving, prevention of malfunction, improvement of driving capability, and the like can be achieved. Furthermore, the flip-flop to which the timing chart of FIG. 6 is applied can shorten the fall time of the signal output from the third wiring 123 in the reset period. . This is because the timing at which the potential of the node 141 becomes L level is delayed by the period Ta1+the period Ta2, so that the L signal input to the fifth wiring 125 is the first transistor 101 with large current capability (large channel width). This is because the voltage is supplied to the third wiring 123 via the . It should be noted that common reference numerals are used for portions that are common to the timing chart of FIG. 2, and description thereof will be omitted.

Note that the relationship between the period Ta1, the period Ta2, and the period Tb is ((Ta1+Tb)/(Ta1+
Ta2+Tb))×100<10[%] is desirable. More preferably, ((T
a1+Tb)/(Ta1+Ta2+Tb))×100<5[%].
Furthermore, it is desirable that period Ta1≈period Ta2.

As another example, when Va (V2<Va<V1) is supplied to the seventh wiring 127, the potential of the node 142 is Va-Vth (103) during the reset period and the second non-selection period. Threshold voltage shifts of the transistor 102 and the sixth transistor 106 can be suppressed.

As another example, when Vb (V1+Vth(103)<Vb) is supplied to the seventh wiring 127, the potential of the node 142 is V1 during the reset period and the second unselected period; The sixth transistor 106 can be easily turned on.

As another example, by setting the potential of the L signal input to the sixth wiring 126 to Vc (Vc<V2) and the potential of the H signal to Vd (V1>Vd>V2), the second transistor 102 and Sixth
threshold voltage shift of transistor 106 can be suppressed. This is because the potential of the node 142 becomes Vc during the set period and the first non-selected period, and a reverse bias is applied to the second transistor 102 and the sixth transistor 106 . Furthermore, the potential of the node 142 becomes Vd during the reset period and the second non-selection period,
This is because the Vgs of the first transistor 102 and the sixth transistor 106 are reduced.

An example of a top view of the flip-flop shown in FIG. 5A is shown in FIG. A conductive layer 2501 includes portions functioning as the gate electrode of the second transistor 102 and the gate electrode of the sixth transistor 106 , and is connected to the conductive layer 2502 through a wiring 2547 . conductive layer 25
02 includes portions that function as the second electrode of the third transistor 103 and the second electrode of the fourth transistor 104 . The conductive layer 2503 includes portions functioning as the first electrode of the second transistor 102, the first electrode of the sixth transistor 106, and the first electrode of the fourth transistor 104, and is connected to the sixth wiring 506. Connected. A conductive layer 2504 includes a portion functioning as the second electrode of the second transistor 102 and is connected to the third wiring 503 through a wiring 2548 . The conductive layer 2505 is the second electrode of the fifth transistor 105;
It includes a portion functioning as the second electrode of the seventh transistor 107 and is connected to the conductive layer 2510 through a wiring 2549 . A conductive layer 2506 includes a portion functioning as the first electrode of the seventh transistor 107 and is connected to the sixth wiring 506 . A conductive layer 2507 includes a portion functioning as the first electrode of the first transistor 101 and is connected to the fourth wiring 504 through a wiring 2541 . A conductive layer 2508 includes a portion functioning as the second electrode of the first transistor 101 and is connected to the third wiring 503 through a wiring 2548.
A conductive layer 2510 is the gate electrode of the first transistor 101 and the fourth transistor 104 .
including a portion functioning as a gate electrode of The conductive layer 2511 is connected to the seventh transistor 107
, and is connected to the second wiring 502 through a wiring 2546 . A conductive layer 2512 includes a portion functioning as the gate electrode of the third transistor 103 and is connected to the seventh wiring 507 through a wiring 2544 . The conductive layer 2513 is the third
, and is connected to the fifth wiring 505 through a wiring 2543 . A conductive layer 2514 includes a portion functioning as the gate electrode of the fifth transistor 105 and is connected to the first wiring 501 through a wiring 2545 . A conductive layer 2515 includes a portion functioning as the second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 through a wiring 2547 .

Note that the portion functioning as the gate electrode, the first electrode, and the second electrode of the first transistor 101 is a portion formed so that the conductive layer and the semiconductor layer 2581 overlap with each other. A portion functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 is a portion formed so that the conductive layer and the semiconductor layer 2582 overlap with each other. A portion functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 is a portion formed so that the conductive layer and the semiconductor layer 2583 overlap with each other. A portion functioning as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 is a portion formed so that the conductive layer and the semiconductor layer 2584 overlap with each other. A portion functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 is a portion formed so that the conductive layer and the semiconductor layer 2585 overlap with each other. A portion functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 is a portion formed so that the conductive layer and the semiconductor layer 2586 overlap with each other. Portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are portions formed so that the conductive layer and the semiconductor layer 2587 overlap with each other.

The configuration and driving method of the shift register having the flip-flops of this embodiment described above will be described.

The structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 10 has n flip-flops (flip-flop 1001_1 to flip-flop 1001_n).

The connection relationship of the shift register in FIG. 10 will be described. In the shift register of FIG. 10, the i-th flip-flop 1001_i (one of the flip-flops 1001_1 to 1001_n) is connected to the second wiring 1012, the third wiring 1013, the fourth wiring 1014, and the fifth wiring. 1015, sixth wiring 1016, eighth wiring 1018_i-1, eighth wiring 10
18_i and the eighth wiring 1018_i+1. However, the flip-flop 1001_1 in the first stage includes the first wiring 1011, the second wiring 1012, the third wiring 1013,
A fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, and an eighth wiring 1018_
1 and the eighth wiring 1018_2. Furthermore, the n-th flip-flop 100
1_n includes a second wiring 1012, a third wiring 1013, a fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, a seventh wiring 1017, an eighth wiring 1018_n−1, and an eighth wiring. It is connected to the wiring 1018 — n.

The first wiring 1011 is connected to the first wiring 121 illustrated in FIG. 1 of the flip-flop 1001_1. The second wiring 1012 is connected to the fifth wiring 125 shown in FIG. 1 in odd-numbered flip-flops, and is connected to the sixth wiring 126 shown in FIG. 1 in even-numbered flip-flops. The third wiring 1013 is connected to the sixth wiring 126 shown in FIG. 1 in odd-numbered flip-flops, and is connected to the fifth wiring 125 shown in FIG. 1 in even-numbered flip-flops. The fourth wiring 1014 corresponds to the seventh wiring 1 shown in FIG. 1 in all flip-flops.
27. The fifth wiring 1015 is connected to the eighth wiring 128 shown in FIG. 1 in all flip-flops. The sixth wiring 1016 is connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. 1 in all flip-flops. The eighth wiring 1018_i is the second wiring 122 of the flip-flop 1001_i−1 in FIG. 1, the third wiring 123 of the flip-flop 1001_i in FIG. 1, and the first wiring 121 of the flip-flop 1001_i+1 in FIG. connected to however,
The eighth wiring 1018_1 corresponds to the third wiring 12 shown in FIG. 1 of the flip-flop 1001_1.
3 and the first wiring 121 shown in FIG. 1 of the flip-flop 1001_2. Further, the eighth wiring 1018_n is connected to the second wiring 122 of the flip-flop 1001_n−1 shown in FIG. 1 and the third wiring 123 of the flip-flop 1001_n shown in FIG.

Note that the potential of V1 is supplied to each of the fourth wiring 1014 and the fifth wiring 1015.
A potential of V2 is supplied to the sixth wiring 1016 .

Note that the first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1
017 is input with a signal. The signal input to the first wiring 1011 is the start signal, the signal input to the second wiring 1012 is the first clock signal, and the signal input to the third wiring 1013 is the second clock. A signal input to the seventh wiring 1017 is a reset signal. Further, a first wiring 1011, a second wiring 1012,
Signals input to the third wiring 1013 and the seventh wiring 1017 are digital signals in which the potential of the H signal is V1 and the potential of the L signal is V2.

Note that various signals, power supply potentials, or currents may be input to the first wiring 1011 to the seventh wiring 1017 .

Note that signals are output from the eighth wirings 1018_1 to 1018_n. For example, the signal output from the eighth wiring 1018_i is the output signal of the flip-flop 1001_i. Further, the signal output from the eighth wiring 1018_i is also the start signal of the flip-flop 1001_i+1 and the reset signal of the flip-flop 1001_i−1.

Note that in the case where signals input to or voltages supplied to the first wiring 1011 to the seventh wiring 1017 are the same, the first wiring 1011 to the seventh wiring 1017 may be connected to each other or may be the same. wiring may be used.

Next, the operation of the shift register shown in FIG. 10 will be described with reference to the timing charts of FIGS. 11 and 12. FIG. Here, the timing chart of FIG. 11 is divided into a scanning period and a blanking period. The scanning period is a period from the start of output of the selection signal from the eighth wiring 1018_1 to the end of the output of the selection signal from the eighth wiring 1018_n. The blanking period is a period from the end of output of the selection signal from the eighth wiring 1018_n to the start of output of the selection signal from the eighth wiring 1018_1.

Note that in FIG. 11, the signal 1111 input to the first wiring 1011 and the second wiring 10
12, a signal 1113 input to the third wiring 1013, a signal 1117 input to the seventh wiring 1017, and a signal 1118_1 output to the eighth wiring 1018_1.
A signal 1118_n output to the wiring 1018_2 and the eighth wiring 1018_n is shown. Further, in FIG. 12, a signal 1211 input to the first wiring 1011, a signal 1218_1 output to the eighth wiring 1018_1, a signal 1218_i output to the eighth wiring 1018_i, and a signal 1218_i output to the eighth wiring 1018_i+1. 1218 — n is output to the eighth wiring 1018 — n.

As shown in FIG. 12, for example, when the flip-flop 1001_i enters the selection period, an H signal is output from the eighth wiring 1018_i.
i+1 is the set period. After that, the flip-flop 1001_i enters a reset period, and an L signal is output from the eighth wiring 1018_i. At this time, flip-flop 1
001_i+1 is a selection period. After that, the flip-flop 1001_i enters the first non-selected period, and the eighth wiring 1018_i is in a floating state and the potential is maintained at the L level. At this time, the flip-flop 1001_i+1 is in the reset period. After that, the flip-flop 1001 — i enters the second non-selection period, and the L signal is output from the eighth wiring 1018 — i. At this time, the flip-flop 1001_i+1 is in the first non-selection period. Thus, the flip-flop 1001_i repeats the first non-selection period and the second non-selection period until the next set period.

As described above, the shift register in FIG. 10 can sequentially output selection signals from the eighth wiring 1018_1 to the eighth wiring 1018_n. That is, the shift register in FIG. 10 can scan the eighth wirings 1018_1 to 1018_n. Therefore, the shift register in FIG. 10 can sufficiently obtain the function as a shift register.

Further, a reset signal input to the flip-flop 1001 — n in the final stage is input through the seventh wiring 1017 . By doing so, the shift register in FIG. 10 does not require a dummy flip-flop, so the layout area can be reduced. However, dummy flip-flops may be arranged.

Further, the shift register in FIG. 10 can freely determine the retrace period by the timing of the signal input to the first wiring 1011 .

Further, by applying the flip-flop shown in this embodiment mode to the shift register in FIG. 10, threshold shift of the transistor can be suppressed. Furthermore, the shift register in FIG. 10 can have a longer life. Furthermore, the shift register in FIG. 10 can improve the driving capability. Furthermore, suppression of malfunction can be aimed at. moreover,
The shift register in FIG. 10 can simplify the process.

Note that the configuration is not limited to that of FIG. 10 as long as it performs the same operation as that of FIG.

For example, as shown in FIG. 13, the output signal of each flip-flop may be output via a buffer. In the shift register in FIG. 13, the flip-flops 1001_1 to 1001_n are connected to the eighth wirings 1018_1 to 1018_n through the buffers 1301_1 to 1301_n, respectively, so that wide driving capability can be obtained. This is because when a large load is connected to each of the eighth wirings 1018_1 to 1018_n, signals output from each of the eighth wirings 1018_1 to 1018_n are delayed and rounded. That is, the eighth wiring 1018_1 to
This is because the delay and distortion of the signal output from each of the eight wirings 1018_n do not affect the operation of the shift register. 10 are denoted by common reference numerals, and description thereof will be omitted.

Note that each of the buffers 1301_1 to 1301_n can be a logic circuit such as NAND or NOR, an operational amplifier, or a circuit combining these. That is, inverters, analog buffers, or the like can be used. In addition, buffer 1
Each of 301_1 to buffer 1301_n is desirably composed of an N-channel transistor when the flip-flop is composed of an N-channel transistor.
Furthermore, it is desirable that each of the buffers 1301_1 to 1301_n be configured to perform a bootstrap operation. Further, the driving voltage (potential difference between the negative power supply and the positive power supply) of each of the buffers 1301_1 to 1301_n is the flip-flop 1
001_1 to flip-flop 1001_n is preferably higher than the respective drive voltages.

Buffers 1301_1 to 1301 included in the shift register shown in FIG.
An example of _n will be described with reference to FIGS. 123A and 123B. Figure 123 (
A buffer 8000 shown in A) has an inverter 8001 between a wiring 8011 and a wiring 8012 .
A, the inverters 8001b, and 8001c are connected to each other, so that an inverted signal of the signal input to the wiring 8011 is output from the wiring 8012 . However, the number of inverters connected between the wiring 8011 and the wiring 8012 is not limited.
12 and an even number of inverters, a signal having the same polarity as the signal input to the wiring 8011 is output from the wiring 8012 . Further, the buffer 810 in FIG. 123(B)
0, inverters 8002a, 8002b, and 8002c connected in series, and inverters 8003a and 8003b connected in series.
and an inverter 8003c may be connected in parallel. Buffer 81 in FIG. 123(B)
00 can average variations in transistor characteristics, so that delay and distortion of a signal output from the wiring 8012 can be reduced. Furthermore, the inverter 8002a and the inverter 8
002a and the outputs of inverter 8002b and inverter 8002b may be connected together.

Note that in FIG. 123A, it is preferable that W of the transistor included in the inverter 8001a<W of the transistor included in the inverter 8001b<W of the transistor included in the inverter 8001c. This is because the drive capability of the flip-flop (specifically, the W/L value of the transistor 101 in FIG. 1) can be reduced by reducing the W of the inverter 8001a. can be made smaller. Similarly, in FIG. 123B, it is preferable that W of the transistor included in the inverter 8002a<W of the transistor included in the inverter 8002b<W of the transistor included in the inverter 8002c. Similarly, in FIG. 123B, it is preferable that W of the transistor included in the inverter 8003a<W of the transistor included in the inverter 8003b<W of the transistor included in the inverter 8003c. Furthermore, the inverter 800
W of the transistor included in 2a=W of the transistor included in the inverter 8003a, W of the transistor included in the inverter 8002b=W of the transistor included in the inverter 8003b, and W of the transistor included in the inverter 8002c=W of the transistor included in the inverter 8003c. preferable.

Note that the inverters shown in FIGS. 123A and 123B are not particularly limited as long as they can invert and output an input signal. For example, as shown in FIG. 123C, an inverter may be configured with a first transistor 8201 and a second transistor 8202 . Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. In the inverter in FIG. 123C, when an H signal is input to the first wiring 8211, the potential obtained by dividing V1-V2 between the first transistor 8201 and the second transistor 8202 (W/L of the first transistor 8201 <W/L of the second transistor 8202)
Output from the second wiring 8212 . Furthermore, when the L signal is input to the first wiring 8211, the inverter in FIG.
(threshold voltage of the transistor 8201 of ) is output from the second wiring 8212 . moreover,
The first transistor 8201 may be a PN junction diode as long as it has a resistance component, or may simply be a resistance element.

Furthermore, as shown in FIG. 123D, an inverter may be configured with a first transistor 8301, a second transistor 8302, a third transistor 8303, and a fourth transistor 8304. FIG. Further, a signal is input to the first wiring 8311, a signal is output from the second wiring 8312, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and the fourth wiring 8314 and V2 is supplied to the sixth wiring 8316 . Figure 123
In the inverter of (D), when an H signal is input to the first wiring 8311, V2 is transferred to the second wiring 8311.
Output from 312. At this time, the potential of the node 8341 is set at L level, so that the first transistor 8301 is turned off. Furthermore, the inverter in FIG.
When an L signal is input to 11, V1 is output from the second wiring 8312. At this time, when the potential of the node 8341 reaches V1−Vth (8303) (Vth (8303): threshold voltage of the third transistor 8303), the node 8341 is in a floating state and the node 8341 is in a floating state.
potential is V1+Vth(8301) (Vth(8301)
: the threshold voltage of the first transistor 8301), the first transistor 8301 is turned on. Furthermore, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode.

Furthermore, as shown in FIG. 26A, an inverter may be configured with a first transistor 8401, a second transistor 8402, a third transistor 8403, and a fourth transistor 8404. FIG. The inverter in FIG. 26A is a two-input inverter and can perform bootstrap operation. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413.
V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. In the inverter in FIG. 26A, when an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, V2 is transferred to the third wiring 841.
Output from 3. Since the potential of the node 8441 is V2 at this time, the first transistor 8401 is turned off. Furthermore, the inverter in FIG.
When an L signal is input to the second wiring 8412, V1 is output from the third wiring 8413. At this time, the potential of the node 8441 is V1-Vth (8403) (Vth (8403)
: the threshold voltage of the third transistor 8403), the node 8441 becomes floating, and the potential of the node 8441 becomes V1+Vth (8401) by the bootstrap operation.
(Vth(8401): threshold voltage of the first transistor 8401), the first transistor 8401 is turned on. Furthermore, since the first transistor 8401 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, one of the first wiring 8411 and the second wiring 8412 is preferably connected to the third wiring 123 shown in FIG. 1, and the other is connected to the node 142 shown in FIG.

Furthermore, as shown in FIG. 26B, an inverter may be configured with a first transistor 8501, a second transistor 8502, and a third transistor 8503. FIG. Figure 2
The inverter 6(B) is a two-input inverter and is capable of bootstrap operation. Further, a signal is input to a first wiring 8511, an inverted signal is input to a second wiring 8512, a signal is output from a third wiring 8513, and a fourth wiring 8514 and a sixth wiring 8514 are connected.
V 2 is supplied to the wiring 8516 of the first and V 2 is supplied to the fifth wiring 8515 . Figure 26
The inverter in (B) outputs V2 from the third wiring 8513 when an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512 . Since the potential of the node 8541 is V2 at this time, the first transistor 8501 is turned off. Further, when an H signal is input to the first wiring 8511 and an L signal is input to the second wiring 8512, the inverter in FIG.
1 is output from the third wiring 8513 . At this time, the potential of the node 8541 is V1-Vth
(8503) (Vth(8503): threshold voltage of third transistor 8503), node 8541 enters a floating state, and the potential of node 8541 rises to V1+Vth(8501) (Vth(8501): threshold voltage of third transistor 8503) due to bootstrap operation. 1 transistor 8501
threshold voltage), the first transistor 8501 is turned on. Furthermore, since the first transistor 8501 functions as a bootstrap transistor,
A capacitive element may be arranged between the second electrode and the gate electrode. Furthermore, the first wiring 85
11 and the second wiring 8512 is preferably connected to the third wiring 123 shown in FIG. 1, and the other is connected to the node 142 shown in FIG.

Furthermore, as shown in FIG. 26C, an inverter may be configured with a first transistor 8601, a second transistor 8602, a third transistor 8603, and a fourth transistor 8604. FIG. The inverter in FIG. 26C is a two-input inverter and can perform bootstrap operation. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613.
V1 is supplied to the fourth wiring 8614, and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. The inverter in FIG. 26A has an L signal on the first wiring 8611 and a second
When an H signal is input to the wiring 8612 of , V2 is output from the third wiring 8613 . Since the potential of the node 8641 is V2 at this time, the first transistor 8601 is turned off.
Furthermore, the inverter in FIG.
2, V 1 is output from the third wiring 8613 . At this time, node 8
The potential of 641 is V1-Vth (8603) (Vth (8603): third transistor 8
603), the node 8641 becomes floating, and the potential of the node 8641 rises to V1+Vth (8601) (Vth (8601):
threshold voltage of the first transistor 8601), the first transistor 8601 is turned on. Furthermore, since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, one of the first wiring 8611 and the second wiring 8612 is preferably connected to the third wiring 123 shown in FIG. 1, and the other is connected to the node 142 shown in FIG.

As another example, the reset signal input to the flip-flop 1001_n can be another input signal or output signal of the shift register. In other words, flip-flop 100
By generating the reset signal input to 1_n inside the shift register, one wiring and one signal can be reduced. For example, if the flip-flop 1001_n is in an even-numbered stage, it may be connected to the eighth wiring 1018_1 as shown in FIG. . As another example, when the flip-flop 1001_n is an even-numbered stage, as shown in FIG.
may be connected to the wiring 1011 of the As another example, a dummy flip-flop 1001_d may be used as shown in FIG. 17 to generate a reset signal to be input to the flip-flop 1001_n. Dummy flip-flop 1001_d can be similar to flip-flop 1001_n−1. However, the second wiring 122 shown in FIG. 1 of the dummy flip-flop 1001_d is connected to the sixth wiring 1016 in FIG. 10 are denoted by common reference numerals, and description thereof will be omitted.

Next, the structure and driving method of the display device having the shift register of this embodiment described above will be described. However, the display device of this embodiment should have at least the flip-flop of this embodiment.

The structure of the display device of this embodiment mode will be described with reference to FIG. The display device in FIG. 18 includes a signal line driver circuit 1801, a scanning line driver circuit 1802, and a pixel portion 1804. In the pixel portion 1804, a plurality of signals are arranged extending from the signal line driver circuit 1801 in the column direction. Line S
1 to Sm, and a plurality of scanning lines G1 to Sm extending in the row direction from the scanning line driving circuit 1802.
It has a plurality of pixels 1803 arranged in a matrix corresponding to Gn, signal lines S1 to Sm, and scanning lines G1 to Gn. Each pixel 1803 is connected to a signal line Sj (signal lines S1 to S
m), and the scanning line Gi (any one of the scanning lines G1 to Gn). Furthermore, the scanning line driver circuit 1802 may be called a driver circuit.

Note that the shift register of this embodiment mode can be applied as the scanning line driver circuit 1802 . Of course, the shift register of this embodiment may be used for the signal line driver circuit 1801 as well.

Note that the scanning lines G1 to Gn are connected to the eighth wirings 1808_1 to 1808_n shown in FIGS.

Note that the signal lines and the scanning lines may be simply referred to as wiring. Furthermore, the signal line driver circuit 1801
and the scanning line driver circuit 1802 may also be referred to as driver circuits.

Note that the pixel 1803 has at least one switching element, one capacitor, and a pixel electrode. However, the pixel 1803 may have a plurality of switching elements or a plurality of capacitive elements. Furthermore, capacitive elements are not necessarily required. Furthermore, pixel 1803
may further include transistors operating in the saturation region. Furthermore, pixel 1803
may have a display element such as a liquid crystal element or an EL element. Here, transistors and PN junction diodes can be used as switching elements. However, when a transistor is used as a switching element, it is desirable that the transistor operates in a linear region. Furthermore, in the case where the scanning line driver circuit 1802 is composed of only N-channel transistors, it is desirable to use N-channel transistors as switching elements. Furthermore, in the case where the scanning line driver circuit 1802 is composed of only P-channel transistors, it is desirable to use P-channel transistors as switching elements.

Note that the scanning line driver circuit 1802 and the pixel portion 1804 are formed over the insulating substrate 1805 and the signal line driver circuit 1801 is not formed over the insulating substrate 1805 . The signal line driver circuit 1801 is formed over a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1805 . The signal line driving circuit 1801 is connected to the signal lines S1 to Sm via a printed circuit board such as FPC. However, the signal line driver circuit 1801 may be formed over the insulating substrate 1805 , or a circuit forming part of the functions of the signal line driver circuit 1801 may be formed over the insulating substrate 1805 .

Note that wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (T
a), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd)
, chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (C
u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn)
, Niobium (Nb), Silicon (Si), Phosphorus (P), Boron (B), Arsenic (As), Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O) One or more elements selected from, or compounds containing one or more elements selected from the group, alloy materials (e.g., indium tin oxide (ITO), indium zinc oxide (IZO ), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
Aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium (
Mo—Nb), etc.). Alternatively, wirings, electrodes, conductive layers, conductive films, terminals, and the like are preferably formed using a material obtained by combining these compounds. Alternatively, a compound (silicide) of one or more elements selected from the group and silicon (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), or a compound (silicide) of one or more elements selected from the group and nitrogen It is preferably formed of a compound (eg, titanium nitride, tantalum nitride, molybdenum nitride, etc.).

Silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron).
may contain Conductivity can be improved by including impurities in silicon. Alternatively, it becomes possible to behave like a normal conductor. Therefore, it becomes easy to use as a wiring, an electrode, and the like.

As silicon, silicon having various crystallinities such as single crystal, polycrystal (polysilicon), and microcrystal (microcrystal silicon) can be used. Alternatively, amorphous (
Amorphous silicon) or the like can also be used. By using single crystal silicon or polycrystalline silicon, the resistance of wirings, electrodes, conductive layers, conductive films, terminals, and the like can be reduced. By using amorphous silicon or microcrystalline silicon, wiring or the like can be formed through a simple process.

Note that aluminum or silver has high conductivity, so that signal delay can be reduced.
Furthermore, since it is easy to etch, patterning is easy and fine processing can be performed.

Note that since copper has high conductivity, signal delay can be reduced. When using copper,
In order to improve adhesion, it is desirable to have a laminated structure.

Note that molybdenum or titanium is desirable because it does not cause defects even when in contact with an oxide semiconductor (ITO, IZO, or the like) or silicon, is easy to etch, and has high heat resistance.

Tungsten is desirable because it has advantages such as high heat resistance.

Neodymium is desirable because it has advantages such as high heat resistance. In particular, the use of an alloy of neodymium and aluminum improves the heat resistance and prevents aluminum from forming hillocks.

Note that silicon is desirable because it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.

Note that ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
nO) has translucency and can be used for a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

Note that a wiring, an electrode, a conductive layer, a conductive film, a terminal, and the like may have a single-layer structure or a multi-layer structure. By using a single-layer structure, the manufacturing steps of wirings, electrodes, conductive layers, conductive films, terminals, etc. can be simplified, the number of process days can be reduced, and the cost can be reduced. Alternatively, by forming a multi-layer structure, it is possible to reduce the demerits of each material while taking advantage of the merits of each material, thereby forming wiring, electrodes, and the like with good performance. For example, by including a low-resistance material (aluminum, etc.) in the multilayer structure, it is possible to reduce the resistance of the wiring. Also, by forming a laminated structure in which a low heat-resistant material is sandwiched between high heat-resistant materials, the heat resistance of wiring, electrodes, and the like can be increased while taking advantage of the merits of the low heat-resistant material. For example, it is desirable to have a stacked structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like.

Moreover, when wiring, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, etc., may enter the other wiring, electrode, etc., into the material of the other, changing its properties, and failing to achieve its original purpose. Alternatively, a high resistance portion may be formed. Alternatively, a problem may arise during production, preventing normal production. In such a case, it is preferable to sandwich or cover a material that reacts readily with a layered structure with a material that does not react easily. For example, when connecting ITO and aluminum, ITO
It is desirable to sandwich a titanium, molybdenum, or neodymium alloy between and aluminum.
Further, when connecting silicon and aluminum, between ITO and aluminum,
It is desirable to sandwich titanium, molybdenum, or neodymium alloy.

Note that the wiring refers to an arrangement in which a conductor is arranged. It may extend linearly, or may be arranged short without extending. Therefore, the electrodes are included in the wiring.

Note that the wirings and electrodes described above can also be applied to other display devices, shift registers, and pixels.

Note that the signal line driver circuit 1801 inputs a voltage or current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the video signal may be inverted between positive and negative polarity for each frame (frame inversion drive), may be inverted for each row (gate line inversion drive), or may be inverted for each column. positive electrode and
The negative polarity may be inverted (source line inversion driving), or the positive and negative polarity may be inverted for each row and column (dot line inversion driving). Furthermore, the video signals may be input to the signal lines S1 to Sm by dot-sequential driving or may be input by line-sequential driving. Further, the signal line driving circuit 1801 applies not only the video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm.
can be entered in It is desirable to input a constant voltage such as a precharge voltage for each gate selection period and for each frame.

Note that the scanning line driving circuit 1802 inputs signals to the scanning lines G1 to Gn, and scans the scanning lines G1 to Gn.
are sequentially selected (hereinafter also referred to as scanning) from the first row. And the scanning line driving circuit 180
2 selects a plurality of pixels 1803 connected to the selected scan line. Here, a period in which one scanning line is selected is called one gate selection period, and a period in which the scanning line is not selected is called a non-selection period. Further, a signal output from the scanning line driver circuit 1802 to the scanning line is called a scanning signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

Note that when the pixel 1803 is selected, a video signal is input to the pixel 1803 from the signal line driver circuit 1801 through the signal line. Furthermore, when the pixel 1803 is not selected, the pixel 1803 is set to the video signal input during the selection period (potential corresponding to the video signal).
holding

Although not shown, the signal line driver circuit 1801 and the scanning line driver circuit 1802 are supplied with a plurality of potentials and a plurality of signals.

Next, the operation of the display device shown in FIG. 18 will be described with reference to the timing chart of FIG. Furthermore, FIG. 19 shows one frame period corresponding to the period for displaying an image for one screen. However, although one frame period is not particularly limited, it is preferable to set it to at least 1/60 second or less so that the viewer of the image does not perceive flicker.

In the timing chart of FIG. 19, the scanning line G1 of the first row, the scanning line Gi of the i-th row, the i-th scanning line
The +1-th scanning line Gi+1 and the n-th scanning line Gn are selected respectively.

In FIG. 19, for example, the i-th scanning line Gi is selected, and a plurality of pixels 1803 connected to the scanning line Gi are selected. A plurality of pixels 1803 connected to the scan line Gi each receives a video signal and holds a potential corresponding to the video signal. After that, the i-th scanning line Gi is deselected, the i+1-th scanning line Gi+1 is selected, and a plurality of pixels 1803 connected to the scanning line Gi+1 are selected. A plurality of pixels 1803 connected to the scan line Gi+1 each receives a video signal and holds a potential corresponding to the video signal. In this manner, the scanning lines G1 to Gn are sequentially selected in one frame period, and the pixels 1803 connected to the respective scanning lines are also sequentially selected. A plurality of pixels 1803 connected to each scan line receives a video signal and holds a potential corresponding to the video signal.

As described above, since the display device in FIG. 18 can independently input video signals to all the pixels, it can sufficiently function as an active matrix display device.

Further, since the shift register of this embodiment mode is used as the scanning line driver circuit 1802 in the display device in FIG. 18, threshold shift of the transistor can be suppressed. The display device in FIG. 18 can have a long life. The display device in FIG. 18 can improve the driving capability. The display device of FIG. 18 can suppress malfunction. The display device in FIG. 18 can simplify the process.

Further, in the display device of FIG. 18, the signal line driver circuit 1801, which requires high-speed operation, and the scanning line driver circuit 1802 and pixels 1803 are formed on separate substrates.
2 and the semiconductor layer of the transistor in the pixel 1803, amorphous silicon can be used. Therefore, the manufacturing process can be simplified, and the manufacturing cost can be reduced. Furthermore, the display device in FIG. 18 can improve the yield. Furthermore, the display device of this embodiment can be enlarged. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

Note that in the case where the signal line driver circuit 1801, the scanning line driver circuit 1802, and the pixel 1803 are formed over the same substrate, the semiconductor layer of the transistor included in the scanning line driver circuit 1802 and the transistor included in the pixel 1803 are poly. Silicon or polycrystalline silicon is preferably used.

Note that as long as pixels can be selected and video signals can be written independently to the pixels as shown in FIG. 18, the number and arrangement of the respective driver circuits are not limited to those shown in FIG.

For example, as shown in FIG. 20, scanning lines G1 to Gn are connected to the first scanning line driving circuit 2002.
a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are similar to the scanning line driving circuit 1 shown in FIG.
It has the same configuration as 802, and scans the scanning lines G1 to Gn at the same timing. Furthermore, the first scanning line driver circuit 2002a and the second scanning line driver circuit 2002b may be called a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 20 includes a first scanning line driver circuit 2002a and a second scanning line driver circuit 200
2b, the other of the scanning line driving circuit 2002a and the second scanning line driving circuit 2002b can scan the scanning lines G1 to Gn, thus providing redundancy. 20, the load of the first scanning line driving circuit 2002a (the wiring resistance of the scanning line and the parasitic capacitance of the scanning line) and the load of the second scanning line driving circuit 2002b are
, the delay and distortion of the signals input to the scanning lines G1 to Gn (output signals of the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b) can be reduced. Furthermore, in the display device of FIG. 20, since the load on the first scanning line driving circuit 2002a and the load on the second scanning line driving circuit 2002b are reduced, the scanning lines G1 to Gn can be scanned at high speed. can. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the definition of the panel. Further, the advantage of the display device in FIG. 20 is more effective when amorphous silicon is used for semiconductor layers of transistors included in the first scanning line driver circuit 2002a and the second scanning line driver circuit 2002b. 18 are denoted by common reference numerals, and description thereof will be omitted.

As another example, FIG. 8 is a display device capable of writing video signals to pixels at high speed. In the display device of FIG. 8, video signals are input to odd-numbered pixels 1803 from odd-numbered signal lines, and video signals are input to even-numbered pixels 1803 from even-numbered signal lines. Further, in the display device of FIG. 8, the odd-numbered scanning lines of the scanning lines G1 to Gn are scanned by the first scanning line driving circuit 802a, and the even-numbered scanning lines of the scanning lines G1 to Gn are scanned by the first scanning line driving circuit 802a. The scanning lines are scanned by the second scanning line driving circuit 802b. Furthermore, the first scanning line driver circuit 802
The start signal input to b is delayed by 1/4 period of the clock signal from the start signal input to the first scanning line driving circuit 802a.

Note that the display device in FIG. 8 can perform dot inversion driving only by inputting a positive video signal and a negative video signal to each signal line for each column in one frame period. moreover,
The display device in FIG. 8 can perform frame inversion driving by inverting the polarity of the video signal input to each signal line every frame period.

The operation of the display device in FIG. 8 will be described with reference to the timing chart in FIG. In the timing chart of FIG. 9, the first scanning line G1, the i−1th scanning line Gi−1, the ith scanning line Gi, the i+1th scanning line Gi+1, and the nth scanning line Gn. indicates the timing at which each is selected. Furthermore, in the timing chart of FIG. 9, one selection period is divided into a selection period a and a selection period b. Furthermore, in the timing chart of FIG.
A case where the display device performs dot inversion driving and frame inversion driving will be described.

In FIG. 9, for example, the selection period a of the i-th scanning line Gi is the i-1-th scanning line Gi-1.
, and the selection period Tb of the i-th scanning line Gi overlaps with the selection period a of the i+1-th scanning line Gi+1. Therefore, in the selection period a, row i-1
A video signal similar to the video signal input to the pixel 1803 of the j+1th column is the pixel 1 of the i-th row, j-th column.
803. Further, in the selection period b, the same video signal as the video signal input to the pixel 1803 of the i-th row and the j-th column is input to the pixel 1803 of the i+1-th row and the j+1-th column. Note that the video signal input to the pixel 1803 in the selection period b is the original video signal, and the video signal input to the pixel 1803 in the selection period a is the video signal for precharging the pixel 1803 . Therefore, each pixel 1803 has i
After precharging with the video signal input to the pixel 1803 of −1 row and j+1 column, the original (i row and j column) video signal is input in the selection period b.

As described above, since the display device in FIG. 8 can write a video signal to the pixel 1803 at high speed, a large size or high definition can be easily achieved. Furthermore, in the display device of FIG. 8, video signals of the same polarity are input to each signal line in one frame period.
Low power consumption can be achieved with less charging and discharging of each signal line. Furthermore, in the display device of FIG. 8, the load on the IC for supplying the video signal is greatly reduced, so heat generation of the IC, power consumption of the IC, and the like can be reduced. Further, in the display device of FIG. 8, the driving frequencies of the first scanning line driving circuit 802a and the second scanning line driving circuit 802b can be approximately halved.

Note that the display device of this embodiment mode can be driven by various driving methods depending on the structure and driving method of the pixel 1803 . For example, in one frame period, the scanning line driving circuit may scan the scanning lines multiple times.

Note that another wiring or the like may be added to the display devices of FIGS. 8, 18, and 20 depending on the structure of the pixel 1803. For example, a power supply line, a capacitor line, a new scanning line, and the like, which are kept at a constant potential, may be added. However, when a scan line is newly added, a scan line driver circuit to which the shift register of this embodiment mode is applied may be newly added. As another example, dummy scanning lines, signal lines, power lines, or capacitor lines may be arranged in the pixel portion.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part:
More figures can be constructed by combining other parts.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 2)
In this embodiment mode, a structure and a driving method of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit, which are different from those in Embodiment 1, will be described. The same reference numerals are used for the same parts as those in the first embodiment, and detailed description of the same parts or parts having similar functions will be omitted.

As the structure of the flip-flop of this embodiment, a flip-flop structure similar to that of the first embodiment can be used. However, the timing for driving the flip-flops is the same as in the first embodiment.
different from Therefore, in this embodiment, description of the configuration of the flip-flop is omitted.

A case where the driving timing of this embodiment is applied to the flip-flop of FIG. 1 will be described, but the driving timing of this embodiment is shown in FIGS. 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B)
7C, 21A, 21B, or 21C can be freely combined for implementation. Furthermore, the driving timing of this embodiment can be freely combined with the driving timing described in the first embodiment.

Next, the operation of the flip-flop of this embodiment will be described with reference to the flip-flop of FIG. 1 and the timing chart of FIG. Further, the timing chart of FIG. 31 is divided into a selection period and a non-selection period for explanation. Furthermore, the non-selection period is a first non-selection period,
The second non-selection period, the set period a, the set period b, and the reset period are divided for explanation.
Furthermore, the selection period is divided into a selection period a and a selection period b. Furthermore, in the non-selection period, the first non-selection period and the second non-selection period are repeated for the operation period other than the set period a, the set period b, the selection period a, the selection period b, and the reset period.

Note that in FIG. 31, signals 3121, 3125, 3126, potentials 3141, 3142, signals 3122, and 3123 are signals input to the first wiring 121 and signals input to the fifth wiring 125, respectively. , the signal input to the sixth wiring 126, the potential of the node 141, the potential of the node 142, the signal input to the second wiring 122, the third wiring 1
23 shows the signal output from 23. FIG.

Note that the signal 3121, the signal 3125, the signal 3126, the potential 3141, the potential 3142, the signal 3122, and the signal 3123 are the same as the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 illustrated in FIG. They are compatible and have similar characteristics.

Note that the flip-flop of this embodiment basically operates in the same manner as the flip-flop described in the first embodiment. However, the flip-flop of this embodiment differs from the flip-flop of the first embodiment in that the timing at which the H signal is input to the first wiring 121 is delayed by 1/4 cycle of the clock signal.

Note that in the flip-flop of this embodiment, the first non-selection period and the second non-selection period are the same as the first non-selection period and the second non-selection period of the flip-flop described in Embodiment 1. Do the same. Furthermore, the flip-flop of this embodiment performs the same operation during the set period a as during the second non-selection period. Furthermore, the flip-flop of the present embodiment performs the same operation during the reset period as that of the flip-flop described in the first embodiment. Further, the flip-flop of this embodiment performs the same operation as that of the flip-flop described in the first embodiment in the selection period a and the selection period b. However, the flip-flop of this embodiment differs from the flip-flop of Embodiment 1 in that an H signal is input to the first wiring 121 in the selection period a. However, even if an H signal is input to the first wiring 121 in the selection period a, the fifth transistor 105 is turned off, so that the operation of this embodiment mode is hardly affected. Therefore, the set period a, the set period b, the selected period a, the selected period b, the reset period, the first non-selected period and the second
A detailed description of the flip-flop of this embodiment during the non-selection period of is omitted.

Note that the layout area of the flip-flop according to the present embodiment can be reduced similarly to the flip-flop shown in the first embodiment. Further, the flip-flop of this embodiment mode can suppress threshold shift of the transistor. Furthermore, the flip-flop of this embodiment can simplify the manufacturing process.

By applying the timing chart shown in FIG. 32 to the flip-flop of this embodiment, the fall time of the output signal of the flip-flop of this embodiment can be greatly shortened. This is because an L signal can be input to the third wiring 123 through the first transistor 101 by shifting the timing at which the signal 3122 (reset signal) becomes H level.

Next, the configuration and driving method of the shift register having the flip-flops of this embodiment described above will be described.

The structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 33 has n flip-flops (flip-flops 3301_1 to 3301_n).

The connection relationship of the shift register in FIG. 33 will be described. The shift register of FIG.
The 1_4N-3 and 4N-1st stage flip-flops 3301_4N-1 are connected to the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, and the eleventh wiring. wiring 3321_i-1, eleventh wiring 3321_i, eleventh wiring 3321_i
321_i+2. Furthermore, the 4N-2nd stage flip-flop 3301_4N
The −2 and 4N-th stage flip-flops 3301_4N are connected to the third wiring 3313, the fifth wiring 3315, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, and the eleventh wiring.
, the wiring 3321_i−1, the eleventh wiring 3321_i, and the eleventh wiring 3321_i+2. However, the first-stage flip-flop 3301_1 is connected to the first wiring 3111,
a second wiring 3312, a fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317,
It is connected to the eighth wiring 3318, the eleventh wiring 3321_1, and the eleventh wiring 3321_3. Furthermore, the n-1th stage flip-flop 3101_n-1 is connected to the second wiring 3312,
A fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318,
A tenth wiring 3320, an eleventh wiring 3321_n−2, and an eleventh wiring 3321_n−1
connected to Further, the n-th stage flip-flop 3301_n is connected to the third wiring 3313
, fifth wiring 3315, sixth wiring 3316, seventh wiring 3317, eighth wiring 3318
, the ninth wiring 3319, the eleventh wiring 3321_n−1, and the eleventh wiring 3321_n.

The first wiring 3311 is connected to the first wiring 121 illustrated in FIG. 1 of the flip-flop 3301_1. The second wiring 3312 is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N-3, and is connected to the sixth wiring 126 shown in FIG. 1 in the flip-flop 3301_4N-1. A third wiring 3313 is a flip-flop 3301_4N.
−2 is connected to the fifth wiring 125 shown in FIG. 1, and the flip-flop 3301_4N is connected to the sixth wiring 126 shown in FIG. A fourth wiring 3314 connects the flip-flop 3
301_4N-3 is connected to the sixth wiring 126 shown in FIG.
1_4N-1 is connected to the fifth wiring 125 shown in FIG. The fifth wiring 3315 is connected to the sixth wiring 126 shown in FIG. 1 in the flip-flop 3301_4N-2, and is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N. Sixth wiring 3
306 is connected to the seventh wiring 127 shown in FIG. 1 in all the flip-flops. The seventh wiring 3317 is connected to the eighth wiring 128 shown in FIG. 1 in all flip-flops.
The eighth wiring 3318 is connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. 1 in flip-flops in all stages. Ninth wiring 331
9 is connected to the second wiring 122 shown in FIG. 1 of the flip-flop 3301_n. first
0 wiring 3120 is the second wiring 122 shown in FIG. 1 of the flip-flop 3301_n−1.
connected to The eleventh wiring 3321_i is the flip-flop 3301_i−2 shown in FIG.
, and the third wiring 123 of the flip-flop 3301_i shown in FIG.
, and the first wiring 121 shown in FIG. 1 of the flip-flop 3301_i+1.
However, the eleventh wiring 3321_1 is the third wiring shown in FIG. 1 of the flip-flop 3301_1.
, and the first wiring 121 shown in FIG. 1 of the flip-flop 3301_2. Further, the eleventh wiring 3321_2 is the third wiring 123 of the flip-flop 3301_2 illustrated in FIG. 1 and the first wiring 12 of the flip-flop 3301_3 illustrated in FIG.
1. Further, the eleventh wiring 3321_n is connected to the flip-flop 3301_n.
is connected to the third wiring 123 shown in FIG.

Note that the potential of V1 is supplied to each of the sixth wiring 3316 and the seventh wiring 3317.
A potential of V2 is supplied to the eighth wiring 3318 .

Note that the first wiring 3311, the second wiring 3312, the third wiring 3314, and the fifth wiring 33
15, a ninth wiring 3319, and a tenth wiring 3320 are inputted with signals. The signal input to the first wiring 3311 is the start signal, the signal input to the second wiring 3312 is the first clock signal, and the signal input to the third wiring 3313 is the second clock. A signal input to the fourth wiring 3314 is a third clock signal,
A signal input to the fifth wiring 3315 is the fourth clock signal, and a ninth wiring 3319
is the first reset signal, and the signal input to the tenth wiring 3320 is the second reset signal. Further, a first wiring 3311, a second wiring 3312, a third wiring
Signals input to the wiring 3314, the fifth wiring 3315, the ninth wiring 3319, and the tenth wiring 3320 are digital signals in which the potential of the H signal is V1 and the potential of the L signal is V2.

Note that various signals, currents, or voltages may be input to the first wiring 3311 to the tenth wiring 3320, respectively.

Note that signals are output from the eleventh wirings 3321_1 to 3321_n.
For example, the signal output from the eleventh wiring 3321_i is the flip-flop 3301_i.
It becomes the output signal of i. Further, the signal output from the eleventh wiring 3321_i is also the input signal of the flip-flop 3301_i+1 and the reset signal of the flip-flop 3301_i−2.

Next, the operation of the shift register shown in FIG. 33 will be described with reference to the timing charts of FIGS. 35 and 36. FIG. Here, the timing chart of FIG. 35 is divided into a scanning period and a blanking period. The scanning period is a period from the start of output of the selection signal from the 11th wiring 3311_1 to the end of the output of the selection signal from the 11th wiring 3311_n. The blanking period is a period from the end of output of the selection signal from the 11th wiring 3311_n to the start of output of the selection signal from the 11th wiring 3311_1.

Note that in FIG. 35, the signal 3511 input to the first wiring 3311 and the second wiring 33
12, a signal 3513 input to the third wiring 3313, a signal 3514 input to the fourth wiring 3314, and a signal 3515 input to the fifth wiring 3315.
, a signal 3519 input to a ninth wiring 3319, a signal 3520 input to a tenth wiring 3320, a signal 3521_1 output to an eleventh wiring 3321_1, and a signal 3521_n output to an eleventh wiring 3321_n. ing. Further, in FIG. 36, a signal 3611 input to the first wiring 3311, a signal 3621_1 output to the 11th wiring 3321_1, a signal 3621_i-1 output to the 11th wiring 3321_i-1, and the 11th wiring A signal 3621_i output to 3321_i and an eleventh wiring 3321_i+1
and a signal 3621_i+1 output to the 11th wiring 3321_n.
21_n.

As shown in FIG. 36, for example, when the flip-flop 3301_i-1 reaches the selection period a, an H signal is output from the eleventh wiring 3321_i-1. At this time, flip-flop 3
301 — i is set period a. After that, the flip-flop 3301_i-1 enters the selection period b and the H signal continues to be output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i is in the selection period a. After that, the flip-flop 33
01_i−1 becomes the reset period, and an H signal is output from the eleventh wiring 3321_i−1. At this time, the flip-flop 3301_i is in the selection period b. That is, in the shift register of this embodiment, the H signal is sequentially output from the flip-flop 3301_i-1, but the selection period b of the flip-flop 3301_i-1 and the flip-flop 3301_
i has a period that overlaps with the selection period a.

When the timing chart of FIG. 32 is applied to the flip-flop of this specification, the configuration of the shift register may be as shown in FIG. In the shift register of FIG. 34, for example, the wiring 122 shown in FIG.
21_i+3. Further, the second wiring 122 of the flip-flop 3301_n−2 shown in FIG. 1 is connected to the twelfth wiring 3322 to which the third reset signal is input.
33 are denoted by the same reference numerals, and description thereof will be omitted.

Note that since the flip-flop of this embodiment is applied to the shift register of this embodiment, the threshold shift of the transistor can be suppressed, the life of the transistor can be extended, the driving capability can be improved, malfunction can be suppressed, and the process can be simplified. Simplification and the like can be achieved.

Note that the shift register of this embodiment mode can be freely combined with the shift register described in Embodiment Mode 1. For example, the shift register of this embodiment is shown in FIGS.
It can be freely combined with the shift registers of FIGS. Specifically, in the shift register of this embodiment, buffers may be connected to the eleventh wirings 3321_1 to 3321_n, reset signals may be internally generated, and dummy flip-flops may be used. You may place a As already mentioned, the same reference numerals are used for the parts that are common with the first embodiment, and the explanation thereof is omitted.

Next, the structure and driving method of the display device having the shift register of this embodiment described above will be described. However, the display device of this embodiment should have at least the flip-flop of this embodiment.

A structure of the display device of this embodiment is described with reference to FIG. In the display device of FIG. 16, scanning lines G1 to Gn are scanned by a scanning line driving circuit 1602. In FIG. Furthermore, Figure 1
In the display device 6, video signals are input to odd-numbered pixels 1803 from odd-numbered signal lines, and video signals are input to even-numbered pixels 1803 from even-numbered signal lines. In addition, Fig. 1
8 are denoted by common reference numerals, and the description thereof is omitted.

By applying the shift register of this embodiment mode to the scan line driver circuit 1602, the display device in FIG. 16 can perform the same operation as the display device in FIG. 8 with one scan line driver circuit. Therefore, the display device in FIG. 16 can write video signals to pixels at high speed. Furthermore, the display device in FIG. 16 can be made larger or have higher definition. Furthermore, the display device in FIG. 16 can achieve low power consumption. Furthermore, the display device of FIG. 16 can suppress heat generation of the IC. Furthermore, the display device of FIG. 16 can achieve power saving of the IC.

As shown in FIG. 22, scanning lines G1 to Gn are connected to a first scanning line driving circuit 2202a.
and the second scanning line driving circuit 2202b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are the scanning line driving circuit 16 shown in FIG.
02, and scans the scanning lines G1 to Gn at the same timing. Further, the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b may be called a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 22 includes a first scanning line driver circuit 2202a and a second scanning line driver circuit 220
2b, the other of the scanning line driving circuit 2202a and the second scanning line driving circuit 2202b can scan the scanning lines G1 to Gn, thus providing redundancy. Furthermore, in the display device of FIG. 22, since the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b scan the scanning lines G1 to Gn, the load of the first scanning line driving circuit 2202a ( The wiring resistance of the scanning line and the parasitic capacitance of the scanning line) and the load of the second scanning line driver circuit 2202b can be halved compared to those in FIG. Therefore, in the display device of FIG. 22, since the load on the first scanning line driving circuit 2202a and the load on the second scanning line driving circuit 2202b are reduced, the signals input to the scanning lines G1 to Gn (the The delay and distortion of the output signals of the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b) can be reduced. Furthermore, in the display device of FIG. 22, since the load of the first scanning line driving circuit 2202a and the load of the second scanning line driving circuit 2202b are reduced, the scanning lines G1 to Gn are reduced.
can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the definition of the panel. Furthermore, the advantage of the display device in FIG.
It is even more effective. 16 are denoted by common reference numerals, and description thereof will be omitted.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part:
More figures can be constructed by combining other parts.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 3)
In this embodiment mode, a structure and a driving method of a flip-flop different from those in Embodiments 1 and 2, a driver circuit including the flip-flop, and a display device including the driver circuit will be described. The flip-flop of this embodiment mode is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from separate wirings by separate transistors. The same reference numerals are used for the same parts as in Embodiments 1 and 2, and detailed descriptions of the same parts or parts having similar functions are omitted.

A basic configuration of the flip-flop of this embodiment will be described with reference to FIG. Figure 2
The flip-flop shown in 7 includes a first transistor 101, a second transistor 102,
It has a third transistor 103 , a fourth transistor 104 , a fifth transistor 105 , a sixth transistor 106 , a seventh transistor 107 , an eighth transistor 108 and a ninth transistor 109 . In this embodiment mode, the eighth transistor 108 and the ninth transistor 109 are n-channel transistors which are turned on when the voltage between the gate and the source (Vgs) exceeds the threshold voltage (Vth). and

Note that the flip-flop in FIG. 27 is similar to the flip-flop in FIG.
It is the same with the addition of eight and ninth transistors 109 . Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are similar to those in FIG. can use things.

The connection relationship of the flip-flops in FIG. 27 will be described. A first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and a second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to the first electrode. 3 wiring 1
23. A first electrode of the second transistor 102 is connected to the fourth wiring 124 and a second electrode of the second transistor 102 is connected to the third wiring 123 . A first electrode of the third transistor 103 is connected to a sixth wiring 126, and the third transistor 103
A second electrode of is connected to the gate electrode of the second transistor 102 , and a gate electrode of the third transistor 103 is connected to the seventh wiring 127 . The first of the fourth transistor 104
is connected to the ninth wiring 129, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 101. Connected to the gate electrode. The first of the fifth transistor 105
A second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101 , and a gate electrode of the fifth transistor 105 is connected to the first wiring 121 . Connected. A first electrode of the sixth transistor 106 is connected to the tenth wiring 130 and a second electrode of the sixth transistor 106 is connected to the first transistor 101 .
, and the gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 102 . A first electrode of the seventh transistor 107 is connected to the eleventh wiring 131 and a second electrode of the seventh transistor 107 is connected to the first transistor 10 .
1, and the gate electrode of the seventh transistor 107 is connected to the second wiring 122 .
connected to A first electrode of the eighth transistor 108 is connected to the 13th wiring 133, a second electrode of the eighth transistor 108 is connected to the 12th wiring, and a gate electrode of the eighth transistor 108 is connected to the first wiring. is connected to the gate electrode of the transistor 101 of . A first electrode of the ninth transistor 109 is connected to the fourteenth wiring 134, and the ninth transistor 109
09 is connected to the twelfth wiring 132 , and the gate electrode of the ninth transistor 109 is connected to the gate electrode of the second transistor 102 .

Note that the twelfth wiring 132 and the third wiring 133 may be called a sixth signal line and a seventh signal line, respectively. Furthermore, the 14th wiring may be called a 7th power supply line.

Note that V2 is supplied to the fourteenth wiring 134 .

Note that a signal is input to the thirteenth wiring 133 . The signal input to the third wiring is the fifth
can be used.

Note that a signal is output from the twelfth wiring 132 . Furthermore, as described in Embodiment Mode 1, a signal is also output from the third wiring 123 .

Note that the first wiring 121, the second wiring 122, the fourth wiring 124, the fifth wiring 125, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, A signal input or a potential supplied to each of the tenth wiring 130 and the eleventh wiring 131 is shown in FIG.
is similar to

Note that the flip-flop in FIG. 27 is similar to the flip-flop in FIG.
8 and 9 transistors 109 are added, but FIGS.
B), FIG. 4(C), FIG. 4(D), FIG. 5(A), FIG. 5(B), FIG. 5(C), FIG. 5(D), FIG. 7(A), FIG. 7(B) An eighth transistor 108 and a ninth transistor 109 may be added to the flip-flops shown in FIGS. 7C, 21A, 21B and 21C.

The operation of the flip-flop shown in FIG. 1 will now be described with reference to the timing chart of FIG. Further, common reference numerals are used for portions common to the timing chart of FIG. 2, and descriptions thereof are omitted.

Note that a signal 232 indicates a signal output from the twelfth wiring 132 . Further, the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222 and the signal 22
3 is the same as in FIG. However, the signal 221, signal 225, signal 226, potential 241,
As the potential 242, the signal 222, and the signal 223, those similar to those shown in FIG. 6, FIG. 31, or FIG. 32 can also be used.

As described above, this embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from separate wirings by separate transistors. 27 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and the eighth transistor 108
and the ninth transistor outputs a signal from the twelfth wiring 132 . Furthermore, the eighth
Since the transistor 108 and the ninth transistor are connected in the same manner as the first transistor 101 and the second transistor 102, the twelfth wiring 132 is connected as shown in FIG.
The signal (signal 232) output from the third wiring 123 (signal 223
) is roughly the same waveform. Here, the signal 232 is the output signal of the flip-flop, and the signal 223 is the transfer signal of the flip-flop. However, the signal 223 may be the output signal of the flip-flop, and the signal 232 may be the transfer signal of the flip-flop.

Note that the eighth transistor 108 and the ninth transistor 109 have functions similar to those of the first transistor 101 and the second transistor 102, respectively. Furthermore, the eighth transistor 108 and the ninth transistor 109 may be called a buffer portion.

As described above, the flip-flop in FIG. 27 can prevent malfunction even when a large load is connected to the third wiring 132 and the signal 232 is delayed, dull, or the like. This is because, in the flip-flop of FIG. 27, the output signal of the flip-flop and the transfer signal of the flip-flop are output from separate wirings by separate transistors. because it has no effect.

Further, the flip-flop in FIG. 27 can reduce the layout area, suppress the threshold shift of the transistor, simplify the process, and provide a large-sized display device, like the flip-flop shown in the first and second embodiments. It is possible to obtain merits such as manufacturing of a semiconductor device such as a long-life display panel and the like.

Note that the operation timing described in Embodiment 2 can also be applied to the flip-flop of this embodiment.

The configuration and driving method of the shift register having the flip-flops of this embodiment described above will be described.

The structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 29 has n flip-flops (flip-flops 2901_1 to 2901_n).

The connection relationship of the flip-flops in FIG. 29 will be described. The flip-flop of FIG. 29 is
i-th flip-flop 2901_i (flip-flops 2901_1 to 2901_n
any one) of the second wiring 2912, the third wiring 2913, and the fourth wiring 2914
, a fifth wiring 2915, a sixth wiring 2916, an eighth wiring 2918_i−1, an eighth wiring 2918_i, an eighth wiring 2918_i+1, and a ninth wiring 2919_i.
However, the flip-flop 2901_1 at the first stage is connected to the first wiring 2911 and the second wiring 2901_1.
912, third wiring 2913, fourth wiring 2914, fifth wiring 2915, sixth wiring 2
916, eighth wiring 2918_1, eighth wiring 2918_2, and ninth wiring 2919_1. Further, the n-th flip-flop 2901_n is connected to the second wiring 2912,
a third wiring 2913, a fourth wiring 2914, a fifth wiring 2915, a sixth wiring 2916,
It is connected to the seventh wiring 2917, the eighth wiring 2918_n−1, the eighth wiring 2918_n, and the ninth wiring 2919_n.

The first wiring 2911 corresponds to the first wiring 121 shown in FIG. 27 of the flip-flop 2901_1.
connected to The second wiring 2912 is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in odd-numbered flip-flops, and is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in even-numbered flip-flops.
7 is connected to the sixth wiring 126 shown in FIG. The third wiring 2913 is connected to the sixth wiring 126 shown in FIG. 27 in the odd-numbered flip-flops, and is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the even-numbered flip-flops. be done. The fourth wiring 2914 is
All the flip-flops are connected to the seventh wiring 127 shown in FIG. fifth wiring 29
15 is connected to the eighth wiring 128 shown in FIG. 27 in all the flip-flops. The sixth wiring 2916 is connected to the fourth wiring 124, the ninth wiring 129, the twenty-ninth wiring 130, and the eleventh wiring 131 shown in FIG. 27 in all flip-flops. Eighth wire 2918
_i is the second wiring 122 shown in FIG. 27 of the flip-flop 2901_i−1, the third wiring 123 shown in FIG. 27 of the flip-flop 2901_i, and the flip-flop 2901i.
+1 is connected to the first wiring 121 shown in FIG. However, the eighth wiring 2918_1 is connected to the third wiring 123 shown in FIG. 27 of the flip-flop 2901_1 and the first wiring 121 shown in FIG. 27 of the flip-flop 2901_2. Furthermore, the eighth wiring 291
8_n is connected to the second wiring 122 shown in FIG. 27 of the flip-flop 2901_n−1 and the third wiring 123 shown in FIG. 27 of the flip-flop 2901_n. Ninth wiring 2
The 919_1 to 9th wirings 2919_n are connected to the 12th wirings 132 shown in FIG. 27 of the flip-flops 2901_1 to 2901_n, respectively.

Note that the flip-flops 2901_1 to 2901_n and the first wiring 29
11, second wiring 2912, third wiring 2913, fourth wiring 2914, fifth wiring 29
15, a fifth wiring 2916, and a seventh wiring 2907 are the flip-flops 1001_1 to 1001_n, the first wiring 1011, the second wiring 1012, the third wiring 1013, and the fourth wiring shown in FIG. They correspond to the wiring 1014, the fifth wiring 1015, the fifth wiring 1016, and the seventh wiring 1007, and are supplied with similar signals or potentials.

Next, the operation of the shift register shown in FIG. 29 will be described with reference to the timing chart of FIG.

In FIG. 30, a signal 3011 input to a first wiring 2911 and an eighth wiring 2918_
1 and a signal 3018_1 output to the eighth wiring 2918_i.
i, a signal 3018_i+1 output to the eighth wiring 2918_i+1, and the eighth wiring 291
A signal 3018_n output to 8_n and a signal 301 output to the ninth wiring 2919_1
9_1, signal 3019_i output to ninth wiring 2918_i, ninth wiring 2918_
A signal 3019_i+1 output to i+1 and a signal 3018_n output to the ninth wiring 2919_n are shown.

As shown in FIG. 30, for example, when the flip-flop 2901_i enters the selection period, the eighth
An H signal is output from the wiring 2918_i of the first wiring and the wiring 2919_i of the ninth wiring. At this time, the flip-flop 2901_i+1 is in the set period. Then flip-flop 290
1_i is a reset period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i+1 is in the selection period. After that, the flip-flop 2901_i enters the first non-selection period, and the eighth wiring 29
18 — i and the ninth wiring 2919 — i are brought into a floating state to maintain the potential at the L level. At this time, the flip-flop 2901_i+1 is in the reset period. After that, the flip-flop 2901_i enters the second non-selection period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i+1
becomes the first non-selection period. Thus, the flip-flop 2901_i repeats the first non-selection period and the second non-selection period until the next set period.

As described above, the shift register in FIG. 29 can sequentially output transfer signals from the eighth wiring 2918_1 to the eighth wiring 2918_n. Further, the shift register in FIG. 29 can sequentially output selection signals from the ninth wiring 2919_1 to the ninth wiring 2919_n. That is, the shift register in FIG. 29 can scan the ninth wirings 2919_1 to 2919_n. Therefore, the shift register of FIG. 29 can sufficiently obtain the function as a shift register.

Furthermore, the shift register in FIG.
Even if a large load (resistance, capacitance, etc.) is connected to the , it can operate without being affected by the load. Furthermore, the shift register in FIG.
19_n is short-circuited with the power line or the signal line, normal operation can continue. Therefore, the shift register in FIG. 29 can improve the driving capability. This is because the shift register of FIG. 29 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

Further, by applying the flip-flop shown in this embodiment mode, the shift register in FIG.
It is possible to obtain advantages such as manufacturing of semiconductor devices such as large display devices and manufacturing of semiconductor devices such as long-life display panels.

Note that the configuration is not limited to that shown in FIG. 29 as long as it performs the same operation as in FIG. for example,
By freely combining with the shift registers of FIGS. 13, 14, 15 and 17, advantages similar to those of FIGS. 13, 14, 15 and 17 can be obtained.

The structure and driving method of the display device having the shift register of this embodiment described above will be described. However, the display device of this embodiment should have at least the flip-flop of this embodiment.

As the display device of this embodiment, the display devices in FIGS. 8, 18, 16, 20, and 22 can be used. Therefore, the layout area of the display device of this embodiment mode can be reduced by using the shift register of this embodiment mode as the scanning line driver circuit. Further, the display device of this embodiment mode can suppress the threshold shift of the transistor. Furthermore, the display device of this embodiment mode can be simplified in manufacturing process. Further, the display device of this embodiment can be made larger or have higher definition. Furthermore, the display device of this embodiment can have a longer life. In particular, by applying the shift register of this embodiment as a scanning line driver circuit to the display devices in FIGS. Further, the display device in FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can save power. Furthermore, the display device of FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can suppress heat generation of the IC. Furthermore, the display device of FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied has I
C power saving can be achieved.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined and combined. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment, or can be combined.

(Embodiment 4)
In this embodiment mode, a case where a P-channel transistor is used as a transistor forming a flip-flop in this specification is described. Further, a driver circuit including the flip-flop, and a structure and a driving method of a display device including the driver circuit will be described.

In the flip-flop of this embodiment mode, the case where the polarity of the transistor included in the flip-flop in FIG. 1 is a P-channel type will be described. However, Fig. 4(A), Fig. 4(B), Fig. 4
(C), FIG. 4(D), FIG. 5(A), FIG. 5(B), FIG. 5(C), FIG. 5(D), FIG. 7(A),
The polarity of the transistors included in the flip-flops shown in FIGS. 7B, 7C, 21A, 21B, 21C, or 27 may be P-channel. can. Further, the flip-flop of this embodiment can be freely combined with the descriptions of Embodiments 1 to 3 for implementation.

A basic configuration of the flip-flop of this embodiment will be described with reference to FIG. Figure 2
3 includes a first transistor 2301 and a second transistor 230
2, third transistor 2303, fourth transistor 2304, fifth transistor 2
305 , a sixth transistor 2306 and a seventh transistor 2307 . In this embodiment, a first transistor 2301, a second transistor 2302, a third transistor 2303, a fourth transistor 2304, a fifth transistor 2305, and a sixth transistor
The transistor 2306 and the seventh transistor 2307 are P-channel transistors, and the absolute value of the voltage between the gate and the source (|Vgs|) is the absolute value of the threshold voltage (|Vt
h|) (when Vgs falls below Vth), it shall be in a conducting state.

The connection relationship of the flip-flops in FIG. 23 will be described. A first electrode (one of the source electrode and the drain electrode) of the first transistor 2301 is connected to a fifth wiring 2325, and a second electrode (the other of the source electrode and the drain electrode) of the first transistor 2301 is connected to the first electrode. 3 wiring 2323 . The first electrode of the second transistor 2302 is connected to the fourth wiring 23
24 , and the second electrode of the second transistor 2302 is connected to the third wiring 2323 . A first electrode of the third transistor 2303 is connected to a sixth wiring 2326, a second electrode of the third transistor 2303 is connected to a gate electrode of the second transistor 2302, and a gate of the third transistor 2303 is connected. An electrode is connected to the seventh wiring 2327 .
A first electrode of the fourth transistor 2304 is connected to a ninth wiring 2329, a second electrode of the fourth transistor 2304 is connected to a gate electrode of the second transistor 2302,
A gate electrode of the fourth transistor 2304 is connected to a gate electrode of the first transistor 2301 . A first electrode of the fifth transistor 2305 is connected to an eighth wiring 2328, a second electrode of the fifth transistor 2305 is connected to a gate electrode of the first transistor 2301, and a gate of the fifth transistor 2305 is connected. An electrode is connected to the first wiring 2321 . A first electrode of the sixth transistor 2306 is connected to a tenth wiring 2330 and a sixth
A second electrode of the transistor 2306 is connected to the gate electrode of the first transistor 2301 , and a gate electrode of the sixth transistor 2306 is connected to the gate electrode of the second transistor 2302 . A first electrode of the seventh transistor 2307 is connected to an eleventh wiring 2331, a second electrode of the seventh transistor 2307 is connected to a gate electrode of the first transistor 2301, and a gate of the seventh transistor 2307 is connected. An electrode is connected to the second wiring 2322 .

Note that the gate electrode of the first transistor 2301, the gate electrode of the fourth transistor 2304, the second electrode of the fifth transistor 2305, the second electrode of the sixth transistor 2306, and the second electrode of the seventh transistor 2307 A node 2341 is a connection point of the electrodes of .
Further, the gate electrode of the second transistor 2302 and the second electrode of the third transistor 2303
, the second electrode of the fourth transistor 2304, and the gate electrode of the sixth transistor 2306 are connected to each other as a node 2342. FIG.

A fourth wiring 2324, a ninth wiring 2329, a tenth wiring 2330, and an eleventh wiring 23
31 may be connected to each other or may be the same wiring. Furthermore, the seventh wiring 23
27 and the eighth wiring 2328 may be connected to each other or may be the same wiring.

Note that the first transistor 2301 to the seventh transistor 2307 correspond to the first transistor 101 to the seventh transistor 107 in FIG. 1, respectively, and have similar functions.

Note that the first wiring 2321 to the eleventh wiring 2331 are each the first wiring 121 in FIG.
to the eleventh wiring 131 . However, the first wiring 2321 to the eleventh wiring 23
A signal input to, a potential supplied to, or a signal output from 31 is connected to the first wiring 121 in FIG.
The H level and L level are inverted compared to the signal input to the 11th wiring 131, the potential supplied, or the signal output.

Note that a potential of V2 is supplied to each of the seventh wiring 2327 and the eighth wiring 2328.
A fourth wiring 2324, a ninth wiring 2329, a tenth wiring 2330, and an eleventh wiring 23
31 is supplied with the potential of V1.

Note that the first wiring 2321, the second wiring 2322, the fifth wiring 2325, and the sixth wiring 2
326 each receives a signal. A signal input to the first wiring 2321 is a start signal, a signal input to the second wiring 2322 is a reset signal, and a signal input to the fifth wiring 2325 is a first clock signal. , the signal input to the sixth wiring 2326 is the second clock signal. Furthermore, a first wiring 2321 and a second wiring 2322
, and the fifth wiring 2325 and the sixth wiring 2326. The potential of the H signal is V1 (hereinafter also referred to as H level), and the potential of the L signal is V2 (hereinafter also referred to as L level).
is a digital signal of

Note that the first wiring 2321, the second wiring 2322, the second wiring 2322 to the eleventh wiring 2
Various signals, currents or voltages may be input to 331 respectively.

Note that a signal is output from the third wiring 2323 . A signal output from the third wiring 2323 is an output signal of the flip-flop in each stage and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop in the next stage. Furthermore, a third wiring 2323
is a digital signal in which the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level).

Next, the operation of the flip-flop shown in FIG. 23 will be described with reference to the timing chart of FIG. Furthermore, the timing chart of FIG. 24 will be described by dividing it into a selection period and a non-selection period. Furthermore, the non-selection period is divided into a first non-selection period, a second non-selection period, a set period and a reset period. Here, as shown in the timing chart of FIG. 24, each period includes a set period, a selection period, a reset period, a first non-selection period, a second non-selection period, a first non-selection period, and a second non-selection period. They are arranged in the order of non-selected periods. That is, the set period,
The operation period other than the selection period and the reset period repeats the first non-selection period and the second non-selection period in order. Furthermore, the period before the set period is the second non-selection period.

The timing chart of FIG. 24 is the same as the timing chart of FIG. 2 with the H level and L level inverted.

Note that the flip-flops of this embodiment include not only flip-flops in which the H level and L level are inverted in FIG. You can use what you have.

Note that in FIG. 24, the signals 2421, 2425, 2426, the potential 2441, the potential 2442, the signal 2422, and the signal 2423 are the signals input to the first wiring 2321 and the signals input to the fifth wiring 2325, respectively. , a signal input to the sixth wiring 2326,
the potential of the node 2341, the potential of the node 2342, the signal input to the second wiring 2322,
A signal output from the third wiring 2323 is shown.

Note that the signal 2421, the signal 2425, the signal 2426, the potential 2441, the potential 2442, the signal 2422, and the signal 223 correspond to the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 in FIG. 2, respectively. are doing. However, as already mentioned, the H level and L level are inverted.

First, in the set period shown in FIG. 24A, the fifth transistor 2305 is turned on because the signal 2421 is at L level, and the seventh transistor 230 is turned on because the signal 2422 is at H level.
7 turns off. The potential of the node 2341 at this time is the second potential of the fifth transistor 2305 .
becomes a source electrode, the potential of the eighth wiring 2328 and the potential of the fifth transistor 2305
V2+|Vth(2305)|(Vth(23
05): Threshold voltage of the fifth transistor 2305). Therefore, the first transistor 2301 and the fourth transistor 2304 are turned on, and the fifth transistor 2305 is turned off. The potential of the node 2342 at this time (potential 2442) is the same as that of the third transistor 2
It is determined by the resistance ratio (L/W and applied voltage) between 303 and the fourth transistor 2304, and becomes V1-θ (θ: any positive number). Furthermore, θ<|Vth(2302)|(Vt
h (2302): threshold voltage of the second transistor 2302) and θ<|Vth (23
06) |(threshold voltage of the sixth transistor 2306). That is, the ninth wiring 2
A potential difference (V1−V2) between the potential (V1) of the wiring 329 and the potential (V2) of the sixth wiring 2326 is divided by the third transistor 2303 and the fourth transistor 2304. FIG. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned off. Thus, during the set period, the third wiring 2323 is connected to the fifth wiring 2325 to which the H signal is input.
, the potential of the third wiring 2323 becomes V1. Therefore, an H signal is output from the third wiring 2323 . In addition, node 2341 has a potential of V2+│Vth(23
05) It becomes a floating state while maintaining |.

In the selection period shown in FIG. 24B), the signal 2421 becomes H level and the fifth transistor 2
305 is turned off and the signal 2422 remains at H level, so the seventh transistor 2307 remains off. At this time, the node 2341 maintains the potential at V2+│Vth(2305)│. Therefore, the first transistor 2301 and the fourth transistor 2304 remain on. At this time, the potential of the node 2342 is V1 because the potential of the sixth wiring 2326 is at H level. Therefore, the second transistor 2302 and the sixth transistor 23
06 remains off. Here, since an L signal is input to the fifth wiring 2325, the third
, the potential of the wiring 2323 begins to decrease. Then, the potential of node 2341 drops from V2+|Vth(2305)| to V2-|Vth(230) by the bootstrap operation.
1) |-γ (Vth(2301): threshold voltage of the first transistor 2301, γ: any positive number). Therefore, the potential of the third wiring 2323 is the same as that of the fifth wiring 2325, which is V2. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 2301 .
Thus, during the selection period, the third wiring 2323 is connected to the fifth wiring 2 to which the L signal is input.
325, the potential of the third wiring 2323 becomes V2. Therefore, an L signal is output from the third wiring 2323 .

In the reset period shown in FIG. 24C, since the signal 2421 remains at H level, the fifth transistor 2305 remains off, and the signal 2422 becomes L level to turn on the seventh transistor 2307 . The potential of the node 2341 at this time is the potential of the 11th wiring (V
1) is supplied through the seventh transistor 2307, resulting in V1. Therefore, the first transistor 2301 and the fourth transistor 2304 are turned off. Node 2 at this time
The potential of 342 is the sixth potential with the second electrode of the third transistor 2303 serving as the source electrode.
V2+│Vth(2303)│(Vth(2303): threshold voltage of third transistor 2303) becomes. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned on. Thus, during the reset period, the third wiring 2323 is V
1 is supplied to the fourth wiring 2324, the potential of the third wiring 2323 is V.
1. Therefore, an H signal is output from the third wiring 2323 .

In the first unselected period shown in FIG. 24D, the signal 2421 remains at the H level, so the fifth transistor 2305 remains off, the signal 2422 remains at the H level, and the seventh transistor 2307 is turned off. do. The potential of the node 2342 at this time is the sixth wiring 2326
becomes V1 because an H signal is input to . Therefore, the second transistor 2302 and the sixth transistor 2306 are turned off. Since the node 2341 at this time is in a floating state, the potential is maintained at V1. Therefore, the first transistor 2301 and the fourth transistor 23
04 remains off. As described above, the third wiring 2323 is in a floating state in the first non-selection period, so that the potential of the third wiring 2323 is maintained at V1.

In the second unselected period shown in FIG. 24E, the fifth transistor 2305 remains off because the signal 2421 remains at the H level, and the seventh transistor 2307 remains off because the signal 2422 remains at the H level. remains At this time, the potential of the node 2342 is V2+|V because an L signal is input to the sixth wiring 2326 and the transistor 2304 is turned off.
th(2303)|. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned on. At this time, the potential of the node 2341 remains V1 because the potential (V1) of the tenth wiring 2330 is supplied through the sixth transistor 2306 . Therefore, the first transistor 2301 and the fourth transistor 2304 remain off. In this manner, during the second non-selection period, the third wiring 2323 is supplied with V1, which is the fourth wiring.
Therefore, the potential of the third wiring 2323 remains V1. Therefore, an H signal is output from the third wiring 2323 .

As described above, the flip-flop in FIG. 23 uses the bootstrap operation in the selection period to lower the potential of the node 2341 below V2−|Vth(2301)| can be V2. Furthermore, the flip-flop of FIG. 23 can reduce the layout area and the device by performing this bootstrap operation using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 2301 . Advantages such as a reduction in the number can be obtained.

Furthermore, the flip-flop of FIG. 23 is such that the second transistor 2302 and the sixth transistor 2306 are turned on only during the second non-selected period.
Shifts in the threshold voltages of the second and sixth transistors 2306 can be suppressed.

Note that in the flip-flop of FIG. 23, by supplying V2 to the gate electrode of the third transistor 2303 and inputting the second clock signal to the first electrode, the third transistor 230
3 threshold voltage shifts can also be suppressed.

Furthermore, the flip-flop in FIG. 23 is such that the first transistor 2301, the fourth transistor 2304, the fifth transistor 2305, and the seventh transistor 2307 are not turned on during the first non-selection period and the second non-selection period. , a first transistor 2301 , a fourth transistor 2304 , a fifth transistor 2305 and a seventh transistor 230
7 can be suppressed.

Furthermore, even if the potential of the node 2341 and the potential of the third wiring 2323 fluctuate in the first non-selected period, the flip-flop in FIG.
41 and the third wiring 2323, the potentials of the node 2341 and the third wiring 2323 can be reset to V1. Therefore, the flip-flop in FIG. 23 can suppress malfunction caused by fluctuations in the potentials of the node 2341 and the third wiring 2323 due to the floating state of the node 2341 and the wiring 2323 .

Furthermore, since the flip-flop of FIG. 23 can suppress the threshold voltage shift of the transistor, malfunction caused by the threshold voltage shift of the transistor can be suppressed.

Furthermore, the flip-flop in FIG. 23 is characterized in that the first transistor 2301 to the seventh transistor 2307 are all P-channel transistors. Therefore, the flip-flop of FIG. 23 can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

If the operation is the same as that of FIG. 24, the arrangement and number of each transistor are the same as those shown in FIG.
not limited to 4. Therefore, transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic circuits, and the like may be newly arranged in the flip-flops of FIG.

Note that the shift register of this embodiment mode can be implemented by freely combining the flip-flop of this embodiment mode with the shift registers described in Embodiment Modes 1 to 3. For example, the shift register of this embodiment is the flip-flop of this embodiment shown in FIG.
, 13, 14, 15, 17, 29, 33 and 34 can be freely combined for implementation. However, in the shift register of this embodiment, the H level and L level are inverted compared to the shift registers described in the first to third embodiments.

Note that the display device of this embodiment mode can be implemented by freely combining the shift register of this embodiment mode with the display devices described in Embodiment Modes 1 to 3. For example, the display device of this embodiment mode can be freely combined with the display devices of FIGS. However, in the display device of this embodiment mode, the H level and the L level are inverted compared to the display devices described in Embodiment Modes 1 to 3. FIG.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part:
More figures can be constructed by combining other parts.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 5)
In this embodiment mode, a signal line driver circuit included in the display device described in Embodiment Modes 1 to 4 will be described.

The signal line driving circuit of FIG. 37 will be described. The signal line driving circuit shown in FIG.
C5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M has a first switch 5603a, a second switch 5603b and a third switch 5603c.

The driver IC 5601 has a first wiring 5611, a second wiring 5612, and a third wiring 5613.
and wirings 5621_1 to 5621_M. Then, switch group 5602_1 to
Each of 5602_M includes a first wiring 5611, a second wiring 5612, and a third wiring 561.
3 and wires 5621_1 to 5 corresponding to switch groups 5602_1 to 5602_M, respectively.
621_M. The wirings 5621_1 to 5621_M are connected to the first switch 5603a, the second switch 5603b, and the third switch 5603b, respectively.
03c to three signal lines. For example, the J-th wiring 5621_J (any one of the wirings 5621_1 to 5621_M) corresponds to the first switch 5603a, the second switch 5603b, and the third switch 5603c included in the switch group 5602_J.
are connected to the signal line Sj−1, the signal line Sj, and the signal line Sj+1 via the .

Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

Note that the driver IC 5601 is desirably formed over a single crystal substrate or a glass substrate using a polycrystalline semiconductor. Further, the switch group 5602 is preferably formed over the same substrate as the pixel portion described in any of Embodiments 1 to 4. FIG. therefore,
The driver IC 5601 and the switch group 5602 are preferably connected via an FPC or the like.

Next, the operation of the signal line driver circuit shown in FIG. 37 will be described with reference to the timing chart of FIG. Note that the timing chart of FIG. 38 shows a timing chart when the i-th scanning line Gi is selected. Furthermore, the selection period of the i-th scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2 and a third sub-selection period T3. Furthermore, the signal line drive circuit in FIG. 37 operates in the same manner as in FIG. 38 even when scanning lines in other rows are selected.

Note that the timing chart of FIG. 38 shows that the wiring 5621_J of the J-th column
03a, the second switch 5603b and the third switch 5603c, the signal line Sj
−1, signal line Sj, and signal line Sj+1.

Note that the timing chart in FIG. 38 shows the timing when the i-th scanning line Gi is selected, the ON/OFF timing 5703a of the first switch 5603a, and the timing 5703a of the second switch 5603a.
b, the on/off timing 5703c of the third switch 5603c, and the signal 5721_J input to the wiring 5621_J of the J-th column.

Note that different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj. and the wiring 5621 in the third sub-selection period T3.
A video signal input to _J is input to the signal line Sj+1. Furthermore, in the selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_J are Dataj−1, Dataj, and Dataj+1, respectively.

As shown in FIG. 38, the first switch 5603a is turned on and the second switch 5603b and the third switch 5603c are turned off during the first sub-selection period T1. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time,
Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on,
The first switch 5603a and the second switch 5603b are turned off. At this time, wiring 5
621_J is input to the signal line S through the third switch 5603c.
input to j+1.

From the above, in the signal line driver circuit of FIG. 37, by dividing one gate selection period into three, a video signal can be input to three signal lines from one wiring 5621 during one gate selection period. can. Therefore, in the signal line driving circuit of FIG. 37, the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed can be reduced to about 1/3 the number of signal lines. By reducing the number of connections to about 1/3, the signal line driving circuit of FIG. 37 can improve reliability, yield, and the like.

By applying the signal line driver circuit of this embodiment to the display devices shown in Embodiments 1 to 4, the number of connections between the substrate on which the pixel portion is formed and the external substrate can be further reduced. . Therefore, the reliability of the display device of this embodiment can be improved. Further, the yield of the display device of this embodiment can be increased.

Next, the first switch 5603a, the second switch 5603b and the third switch 560
A case where an N-channel type transistor is applied to 3c will be described with reference to FIG.
37 are denoted by common reference numerals, and detailed description of the same parts or parts having similar functions will be omitted.

The first transistor 5903a corresponds to the first switch 5603a, the second transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the third switch 5603c.

For example, in the case of the switch group 5602_J, the first transistor 5903a has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj-1, and a gate electrode connected to the first wiring 5611. be done. The second transistor 5903b has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj, and a gate electrode connected to the second wiring 5612 . A first electrode of the third transistor 5903c is a wiring 5621_.
J, the second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the third wiring 561 .
3.

Note that the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as switching transistors. Further, a first transistor 5903a, a second transistor 5903b, and a third transistor 5903
c is turned on when the signal input to the gate electrode is at H level, and turned off when the signal input to the gate electrode is at L level.

Note that the first switch 5603a, the second switch 5603b, and the third switch 560
By using an N-channel transistor as 3c, amorphous silicon can be used as the semiconductor layer of the transistor, so that the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved. Because you can. Furthermore, it is also possible to manufacture a semiconductor device such as a large display panel. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

In the signal line driver circuit in FIG. 39, the first transistor 5903a and the second transistor 59
03b, the case where an N-channel transistor is used as the third transistor 5903c is described, but the first transistor 5903a, the second transistor 5903b,
A P-channel transistor may be used as the third transistor 5903c. At this time, the transistor is turned on when the signal input to the gate electrode is at L level, and turned off when the signal input to the gate electrode is at H level.

As shown in FIG. 37, if one gate selection period can be divided into a plurality of sub-selection periods and a video signal can be input from one wiring to each of a plurality of signal lines in each of the plurality of sub-selection periods, a switch can be used. are not limited in terms of arrangement, number, driving method, and the like.

For example, when inputting a video signal from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period will be shortened. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.

As another example, as shown in the timing chart of FIG. 40, one selection period is divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. may Further, the timing chart of FIG. 40 includes the timing when the i-th scanning line Gi is selected, the ON/OFF timing 5803a of the first switch 5603a, and the second switch 5603a.
ON/OFF timing 5803b of the switch 5603b of the third switch 5603c, ON/OFF timing 5803c of the third switch 5603c, and the signal 58 input to the J-th wiring 5621_J.
21_J. As shown in FIG. 40, the first switch 5603a, the second switch 5603b and the third switch 5603c are turned on during the precharge period Tp.
At this time, the precharge voltage Vp input to the wiring 5621_J is the first switch 560
3a, the second switch 5603b, and the third switch 5603c to the signal line Sj-1, the signal line Sj, and the signal line Sj+1, respectively. In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 56 are turned on.
03c is turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603a are turned on.
603c turns off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third
switch 5603c is turned on, and the first switch 5603a and the second switch 5603
b turns off. At this time, Dataj+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third switch 5603c.

As described above, the signal line driving circuit of FIG. 37 to which the timing chart of FIG. 40 is applied can precharge the signal line by providing the precharge selection period before the sub-selection period. can be written at high speed. 38 are denoted by common reference numerals, and detailed description of the same parts or parts having similar functions will be omitted.

41, one gate selection period is divided into a plurality of sub-selection periods as shown in FIG.
A video signal can be input to each of a plurality of signal lines from one wiring in each of a plurality of sub-selection periods. Note that FIG. 41 shows only the switch group 6022_J on the J-th column among the signal line driver circuits. The switch group 6022_J is the first transistor 60
01 , a second transistor 6002 , a third transistor 6003 , a fourth transistor 6004 , a fifth transistor 6005 and a sixth transistor 6006 . A first transistor 6001, a second transistor 6002, and a third transistor 6003
, fourth transistor 6004, fifth transistor 6005, sixth transistor 60
06 is an N-channel type transistor. The switch group 6022_J is connected to the first wiring 60
11, second wiring 6012, third wiring 6013, fourth wiring 6014, fifth wiring 60
15, sixth wiring 6016, wiring 5621_J, signal line Sj-1, signal line Sj, signal line S
j+1.

The first transistor 6001 has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj−1, and a gate electrode connected to the first wiring 6011 . A first electrode of the second transistor 6002 is connected to the wiring 5621_J, and a second electrode is connected to the signal line Sj.
−1, and the gate electrode is connected to the second wiring 6012 . third transistor 6
003 has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj, and a gate electrode connected to the third wiring 6013 . The fourth transistor 6004 has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj, and a gate electrode connected to the fourth wiring 6014 . A first electrode of the fifth transistor 6005 is the wiring 56
21_J, the second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the fifth wiring 6015 . The sixth transistor 6006 has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj+1, and a gate electrode connected to the sixth wiring 6016 .

Note that the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as switching transistors. Furthermore, a first transistor 6001, a second transistor 6002, a third transistor 6003, and a fourth transistor
Each of the transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 is turned on when the signal input to the gate electrode is at H level, and is turned off when the signal input to the gate electrode is at L level. .

Note that the first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. A third wiring 6013 and a fourth wiring 6014 correspond to the second wiring 5912 in FIG. The fifth wiring 6015 and the sixth wiring 6016 correspond to the third wiring 5913 in FIG.
corresponds to Note that the first transistor 6001 and the second transistor 6002 correspond to the first transistor 5903a in FIG. The third transistor 6003 and the fourth
corresponds to the second transistor 5903b in FIG. A fifth transistor 6005 and a sixth transistor 6006 correspond to the third transistor 5903c in FIG.

41, in the first sub-selection period T1 shown in FIG. 38, the first transistor 600
Either 1 or the second transistor 6002 is turned on. Either the third transistor 6003 or the fourth transistor 6004 is turned on in the second sub-selection period T2. Either the fifth transistor 6005 or the sixth transistor 6006 is turned on in the third sub-selection period T3. Furthermore, the first transistor 6001, the third transistor 6003, and the fifth transistor 60 are
05 or the second transistor 6002, the fourth transistor 6004 and the sixth transistor 6006 are turned on.

Therefore, in FIG. 41, since the on-time of each transistor can be shortened, the characteristic deterioration of each transistor can be suppressed. This is because, for example, in the first sub-selection period T1 shown in FIG. 38, the first transistor 6001 or the second transistor 60
02 is ON, the video signal can be input to the signal line Sj-1. For example, in the first sub-selection period T1 shown in FIG. 38, by simultaneously turning on the first transistor 6001 and the second transistor 6002, the video signal can be input to the signal line Sj-1 at high speed. can.

Note that FIG. 41 describes the case where two transistors are connected in parallel between the wiring 5621 and the signal line. However, the present invention is not limited to this, and three or more transistors are connected to the wiring 56.
21 and the signal line. By doing so, it is possible to further suppress deterioration of the characteristics of each transistor.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part:
More figures can be constructed by combining other parts.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 6)
In this embodiment mode, a structure for preventing defects due to electrostatic breakdown of the display devices described in Embodiment Modes 1 to 4 will be described.

Electrostatic discharge is the instantaneous discharge of positive or negative charges accumulated in the human body or other object through the device's input/output terminals when it touches the device, causing a large current to flow inside the device. Destruction caused by flow.

FIG. 42A shows a configuration for preventing electrostatic breakdown occurring in scanning lines by protective diodes. FIG. 42A shows a structure in which a protective diode is arranged between the wiring 6111 and the scanning line. Although not shown, a plurality of pixels are connected to the i-th scanning line Gi. Note that a transistor 6101 is used as a protective diode. Note that the transistor 61
01 is an N-channel type transistor. However, a p-channel transistor may be used, and the polarity of the transistor 6101 may be the same as the polarity of the transistor in the scan line driver circuit or the pixel.

Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

The transistor 6101 has a first electrode connected to the i-th scanning line Gi, a second electrode connected to the wiring 6111, and a gate electrode connected to the i-th scanning line Gi.

The operation of FIG. 42(A) will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the i-th scan line Gi. When positive or negative charge is not discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi is at H level or L level, so the transistor 6101 is off. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, the potential of the i-th scanning line Gi changes from the potential of the wiring 6111 to the potential of the transistor 61 .
01 minus the threshold voltage, the transistor 6101 is turned on and current flows through the wiring 6111 through the transistor 6101 . Therefore, the structure shown in FIG. 42A can prevent a large amount of current from flowing into the pixel, so that the pixel can be prevented from being damaged by electrostatic discharge.

Note that FIG. 42B shows a configuration for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. A transistor 6102 functioning as a protection diode is arranged between the scan line and the wiring 6112 . Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6102 is an N-channel transistor. However, a p-channel transistor may be used, and the polarity of the transistor 6102 may be the same as the polarity of the transistor in the scan line driver circuit or the pixel. A first electrode of the transistor 6102 is connected to the i-th scanning line Gi, and a second electrode is connected to the i-th scanning line Gi.
is connected to the wiring 6112 , and the gate electrode is connected to the wiring 6112 . Note that a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6112 . Therefore, the transistor 6102 is off when the charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, the i-th scanning line Gi
becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on, and the current flows through the wiring 61 through the transistor 6102.
flow to 12. Therefore, the structure shown in FIG. 42B can prevent a large amount of current from flowing into the pixel, so that the pixel can be prevented from being damaged by electrostatic discharge.

As shown in FIG. 42(C), by combining the configuration of FIG. 42(A) and FIG. , it is possible to prevent electrostatic breakdown of pixels even when negative charges are discharged to the i-th scanning line Gi. In addition, Fig. 4
2(A) and 2(B) are denoted by common reference numerals, and detailed descriptions of the same parts or parts having similar functions are omitted.

FIG. 43A shows a structure in which a transistor 6201 functioning as a protective diode is connected between the scan line and the storage capacitor line. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6201 is an N-channel transistor. However, a p-channel transistor may be used, and the polarity of the transistor 6201 may be the same as the polarity of the transistor in the scan line driver circuit or the pixel. Note that the wiring 6211 functions as a storage capacitor line. transistor 6201
is connected to the i-th scanning line Gi, the second electrode is connected to the wiring 6211,
The gate electrode is connected to the i-th scanning line Gi. Note that a potential lower than the L level of the signal input to the i-th scan line Gi is input to the wiring 6211 . Therefore, the transistor 6201 is off when the charge is not discharged to the i-th scanning line Gi. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the i-th scanning line Gi
potential drops instantaneously. At this time, when the potential of the i-th scanning line Gi becomes lower than the value obtained by subtracting the threshold voltage of the transistor 6201 from the potential of the wiring 6211, the transistor 62
01 is turned on, current flows through the wiring 6211 through the transistor 6201 . Therefore, the structure shown in FIG. 43A can prevent a large amount of current from flowing into the pixel, so that the pixel can be prevented from being damaged by electrostatic discharge. Furthermore, in the configuration shown in FIG. 43A, since the storage capacitor line is used as a wiring for releasing charges, there is no need to add a new wiring.

Note that FIG. 43B shows a configuration for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. Here, a potential higher than the H level of the signal input to the i-th scan line Gi is input to the wiring 6211 . Therefore, transistor 6201
is off when no charge is discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, the potential of the i-th scanning line Gi is the potential of the wiring 6211 and the potential of the transistor 62
01 threshold voltage, the transistor 6201 is turned on and current flows through the transistor 6201 to the wiring 6211 . Therefore, the structure shown in FIG. 43B can prevent a large amount of current from flowing into the pixel, so that the pixel can be prevented from being damaged by electrostatic discharge. Furthermore, in the configuration shown in FIG. 43B, since the storage capacitor line is used as a wiring for releasing charges, there is no need to add a new wiring. Note that FIG. 43 (
The same reference numerals are used for the same parts as in B), and detailed descriptions of the same parts or parts having similar functions are omitted.

Next, FIG. 44 shows a configuration for preventing electrostatic breakdown occurring in the signal line by the protection diode.
(A). FIG. 44A shows a structure in which a protective diode is arranged between the wiring 6411 and the signal line. Although not shown, a plurality of pixels are connected to the j-th signal line Sj. Note that a transistor 6401 is used as a protective diode. Note that the transistor 6401 is an N-channel transistor. However, a p-channel transistor may be used, and the polarity of the transistor 6401 may be the same as that of the transistor of the signal line driver circuit or the pixel.

Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

The transistor 6401 has a first electrode connected to the j-th signal line Sj, a second electrode connected to the wiring 6411, and a gate electrode connected to the j-th signal line Sj.

The operation of FIG. 44(A) will be described. A certain potential is input to the wiring 6411, and the potential is lower than the minimum value of the video signal input to the j-th signal line Sj. When positive or negative charge is not discharged to the j-th signal line Sj, the potential of the j-th signal line Sj is the same as that of the video signal, so the transistor 6401 is off. On the other hand, when negative charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj drops instantaneously.
At this time, when the potential of the j-th signal line Sj becomes lower than the value obtained by subtracting the threshold voltage of the transistor 6401 from the potential of the wiring 6411, the transistor 6401 is turned on, and the current flows through the wiring 6411 through the transistor 6401. flow to Therefore, the structure shown in FIG. 44A can prevent a large amount of current from flowing into the pixel, so that the pixel can be prevented from being damaged by electrostatic discharge.

Note that FIG. 44B shows a configuration for preventing electrostatic breakdown when positive charges are discharged to the j-th signal line Sj. A transistor 6402 functioning as a protection diode is arranged between the scan line and the wiring 6412 . Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6402 is an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6402 may be the same as that of the transistor in the scan line driver circuit or the pixel. A first electrode of the transistor 6402 is connected to the j-th signal line Sj, and a second
is connected to the wiring 6412 , and the gate electrode is connected to the wiring 6412 . Note that a potential higher than the maximum value of the video signal input to the j-th signal line Sj is input to the wiring 6412 . Therefore, the transistor 6402 is off when electric charge is not discharged to the signal line Sj of the j-th row. On the other hand, when positive charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj rises instantaneously. At this time, when the potential of the j-th signal line Sj becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on, and current flows to the wiring 6412 through the transistor 6402. flow. Therefore, the structure shown in FIG. 44B can prevent a large amount of current from flowing into the pixel, so that the pixel can be prevented from being damaged by electrostatic discharge.

As shown in FIG. 44(C), by combining the configuration of FIG. 44(A) and FIG. , electrostatic damage to pixels can be prevented even when negative charges are discharged to the j-th signal line Sj. In addition, Fig. 4
4(A) and 4(B) are denoted by common reference numerals, and detailed descriptions of the same parts or parts having similar functions are omitted.

In this embodiment mode, a structure for preventing electrostatic breakdown of pixels connected to scanning lines and signal lines is described. However, the structure of this embodiment is not applied only to the prevention of electrostatic breakdown of pixels connected to scanning lines and signal lines. For example, in the case where this embodiment is applied to a wiring to which a signal or potential is input and which is connected to the scanning line driver circuit and the signal line driver circuit described in Embodiments 1 to 4, the scanning line driver circuit Also, electrostatic damage to the signal line driver circuit can be prevented.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part:
More figures can be constructed by combining other parts.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 7)
In this embodiment mode, a new structure of a display device that can be applied to the display devices described in Embodiment Modes 1 to 4 will be described.

FIG. 45A shows a structure in which a diode-connected transistor is arranged between one scan line and another scan line. In FIG. 45A, a diode-connected transistor 6301a is arranged between the i−1 row scanning line Gi−1 and the i row scanning line Gi, and the i row scanning line Gi and the i+1 row scanning line Gi are arranged. A transistor 63 diode-connected to the eye scanning line Gi+1.
01b is arranged. Note that the transistors 6301a and 6301b are n-channel transistors. However, a P-channel transistor may be used, and the polarities of the transistors 6301a and 6301b may be the same as those of the transistors in the scan line driver circuit and the pixel.

Note that FIG. 45A representatively shows the i−1 row scanning line Gi−1, the i row scanning line Gi, and the i+1 row scanning line Gi+1, but the other scanning lines are also shown. Similarly diode-connected transistors are arranged.

A first electrode of the transistor 6301a is connected to the i-th scanning line Gi, and a second electrode is connected to the i-th scanning line Gi.
The gate electrode is connected to the scanning line Gi-1 of the -1 row, and the gate electrode is connected to the scanning line Gi-1 of the Gi-1 row. A first electrode of the transistor 6301b is connected to the i+1-th scanning line Gi+1, a second electrode is connected to the i-th scanning line Gi, and a gate electrode is connected to the i-th scanning line Gi.

The operation of FIG. 45(A) will be described. In the scanning line driving circuits shown in Embodiments 1 to 4, in the non-selection period, the scanning line Gi−1 of the i−1 row, the scanning line Gi of the i row, and the scanning line Gi+1 of the i+1 row maintains an L level. Therefore, transistor 6
301a and transistor 6301b are off. However, when the potential of the i-th scanning line Gi increases due to noise or the like, the i-th scanning line Gi selects a pixel, and an incorrect video signal is written to the pixel. Therefore, by arranging a diode-connected transistor between scanning lines as shown in FIG. 45A, it is possible to prevent an illegal video signal from being written to a pixel. This is because when the potential of the i-th scanning line Gi rises to the sum of the potential of the i-1-th scanning line Gi-1 and the threshold voltage of the transistor 6301a, the transistor 6301a is turned on, The potential of the eye scanning line Gi is lowered. Therefore, no pixel is selected by the i-th scanning line Gi.

Note that the structure of FIG. 45A is particularly advantageous when the scanning line driver circuit and the pixel portion are integrally formed over the same substrate. This is because, in a scanning line driver circuit including only N-channel transistors or P-channel transistors, the scanning lines may be in a floating state, and noise is likely to occur in the scanning lines.

Note that FIG. 45B shows a configuration in which the directions of the diode-connected transistors arranged between the scanning lines are reversed. Note that the transistor 6302a and the transistor 6302b
is an N-channel transistor. However, a P-channel transistor may be used, and the polarities of the transistors 6302a and 6302b may be the same as those of the transistors in the scan line driver circuit and the pixel. In FIG. 45B, the first electrode of the transistor 6302a is connected to the i-th scanning line Gi, the second electrode is connected to the i-1-th scanning line Gi-1, and the gate electrode is i It is connected to the row scanning line Gi. A first electrode of the transistor 6302b is connected to the i+1-th scanning line Gi+1, a second electrode is connected to the i-th scanning line Gi, and a gate electrode is connected to the i+1-th scanning line Gi+1. In FIG. 45B, similarly to FIG. 44A, the potential of the i-th scanning line Gi is higher than the sum of the potential of the i−1-th scanning line Gi+1 and the threshold voltage of the transistor 6302b. As it rises,
The transistor 6302b is turned on, and the potential of the i-th scanning line Gi is lowered. therefore,
Pixels are not selected by the i-th scanning line Gi, and it is possible to prevent illegal video signals from being written to the pixels.

Note that as shown in FIG. 45C, by combining the structure of FIGS. 45A and 45B, even if the potential of the i-th scanning line Gi increases, the transistor 6301a And the transistor 6302b is turned on, so the potential of the i-th scanning line Gi is lowered. Fig. 45
At (C), more noise can be filtered out because the current flows through two transistors. 45A and 45B are denoted by common reference numerals, and detailed description of the same parts or parts having similar functions will be omitted.

As shown in FIGS. 43A and 43B, even if a diode-connected transistor is arranged between the scanning line and the storage capacitor line, the same effect as in FIGS. effect can be obtained.

Although various drawings have been used to describe the present embodiment, the content or part of the content described in each drawing can also be applied to the content or part of the content described in another drawing. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part:
More figures can be constructed by combining other parts.

Similarly, the content or part of the content described in each drawing of this embodiment can also be applied to the content or part of the content described in the drawing of another embodiment. Alternatively, they can be combined.
Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

It should be noted that the present embodiment provides an example of a case where the contents described in other embodiments are embodied, an example of a slightly modified case, an example of a partially changed case, an example of an improved case, and details thereof. It shows an example of a stated case, an example of an applied case, an example of a related part, and so on. Therefore, the contents described in other embodiments can also be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 8)
In this embodiment, the pixel structure of the display device will be described. In particular, the pixel structure of the liquid crystal display device will be described.

FIG. 46 is a sectional view and a top view of a pixel in the case of combining a thin film transistor (TFT) with a so-called TN system pixel structure of a liquid crystal display device. FIG. 46A is a cross-sectional view of a pixel, and FIG. 46B is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 46A corresponds to line segment aa' in the top view of the pixel shown in FIG. 46B. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 46, the liquid crystal display device can be manufactured at low cost.

A pixel structure of a TN liquid crystal display device will be described with reference to FIG. A liquid crystal display device has a main part that displays an image, called a liquid crystal panel. LCD panel
It is produced by bonding two processed substrates with a gap of several micrometers and injecting a liquid crystal material between the two substrates. In FIG. 46A, the two substrates are a first substrate 10101 and a second substrate 10116. In FIG. TFTs on the first substrate
and pixel electrodes, and a light-shielding film 10114 and a color filter 1011 are formed on the second substrate.
5. A fourth conductive layer 10113, a spacer 10117 and a second alignment film 10112 may be fabricated.

Note that it can be implemented without manufacturing TFTs on the first substrate 10101 . When this embodiment mode is implemented without manufacturing a TFT, the manufacturing cost can be reduced because the number of steps is reduced. Furthermore, since the structure is simple, the yield can be improved. on the other hand,
When this embodiment mode is implemented by manufacturing TFTs, a larger display device can be obtained.

Note that the TFT shown in FIG. 46 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel using a TFT using an amorphous semiconductor has the advantage that it can be manufactured at low cost using a large-sized substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type, a channel protection type, and the like in the case of a bottom gate type TFT. Moreover, a top gate type may be used. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

Note that this embodiment mode can be implemented without forming the light shielding film 10114 on the second substrate 10116 . When this embodiment mode is implemented without forming the light shielding film 10114, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light shielding film 10114 is formed and this embodiment mode is implemented, a display device with less light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10115 on the second substrate 10116 . When this embodiment mode is implemented without manufacturing the color filter 10115, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without manufacturing the color filter 10115, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10115 is manufactured and this embodiment mode is implemented, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by scattering spherical spacers without forming the spacers 10117 on the second substrate 10116 . When carrying out this embodiment by scattering spherical spacers, the number of steps is reduced, so the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, spacer 101
17 and implementing the present embodiment, the positions of the spacers do not fluctuate.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing applied to the first substrate 10101 will be described. The first substrate 10101 is preferably a light-transmitting substrate, such as a quartz substrate, a glass substrate, or a plastic substrate. Note that the first substrate 10101 may be a light-shielding substrate, such as a semiconductor substrate or an SOI (S) substrate.
silicon on insulator) substrate.

First, the first insulating film 10102 may be formed on the first substrate 10101 . The first insulating film 10102 is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxN).
y) may be an insulating film. Alternatively, the first insulating film 10102 may be an insulating film having a laminated structure in which two or more films selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiOxNy), and the like are combined. In the case where the first insulating film 10102 is formed and this embodiment mode is implemented, it is possible to prevent impurities from the substrate from affecting the semiconductor layer and changing the properties of the TFT. In addition, since changes in the properties of the TFT can be suppressed,
A highly reliable display device can be obtained. Note that when this embodiment mode is implemented without forming the first insulating film 10102, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved.

Next, on the first substrate 10101 or the first insulating film 10102, a first conductive layer 1010 is formed.
3 is formed. Note that the first conductive layer 10103 may be formed by processing the shape. The process of processing the shape is preferably as follows. First, the first conductive layer 101
03 is deposited on the entire surface. At this time, the first conductive layer 10103 is formed by a sputtering device or C
A film may be formed using a film forming apparatus such as a VD apparatus. Next, a photosensitive resist material is formed over the entire surface of the first conductive layer deposited over the entire surface. Next, the resist material is exposed according to the desired shape by photolithography, laser direct writing, or the like. Next, either the exposed resist material or the non-exposed resist material is removed by etching to obtain a mask for shaping the first conductive layer 10103. After that, according to the formed mask pattern, the first conductive layer 10103 is formed.
is removed by etching, the first conductive layer 10103 can be shaped into a desired pattern. Note that methods for etching the first conductive layer 10103 include a chemical method (wet etching) and a physical method (dry etching). It is selected as appropriate in consideration of the properties of the material underlying the conductive layer 10103 . Note that materials used for the first conductive layer 10103 are Mo, Ti, and Al.
, Nd, Cr and the like are suitable. Alternatively, it may be a laminated structure in which two or more of Mo, Ti, Al, Nd, Cr, etc. are combined.

Next, a second insulating film 10104 is formed. At this time, the second insulating film 10104 may be deposited using a deposition apparatus such as a sputtering apparatus or a CVD apparatus. Note that a material used for the second insulating film 10104 is preferably a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Alternatively, a laminated structure in which two or more of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is combined may be used.
It is particularly preferable that the portion of the second insulating film 10104 in contact with the first semiconductor layer 10105 is a silicon oxide film. The reason is that if a silicon oxide film is used, the semiconductor layer 10
This is because the trap level at the interface with 105 is reduced. Note that the first conductive layer 10
When 103 is made of Mo, the portion of the second insulating film 1 in contact with the first conductive layer 10103 is
0104 is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo.

Next, a first semiconductor layer 10105 is formed. After that, it is preferable to continuously form the second semiconductor layer 10106 . Note that the first semiconductor layer 10105 and the second semiconductor layer 1
0106 may be formed by processing the shape. The step of processing the shape is preferably a method such as the photolithography method described above. Note that the material used for the first semiconductor layer 10105 is preferably silicon, silicon germanium (SiGe), or the like. Silicon containing phosphorus or the like is suitable for the material used for the second semiconductor layer 10106 .

Next, a second conductive layer 10107 is formed. At this time, as a method for forming the second conductive layer 10107, a sputtering method or a printing method is preferably used. Note that the second conductive layer 10
The material used for 107 may be transparent or reflective. If it has transparency, for example, indium tin oxide (IT
O) film, indium tin silicon oxide (ITSO) film in which silicon oxide is mixed with indium tin oxide (ITO), indium zinc oxide (IZO) film which is indium oxide mixed with zinc oxide, zinc oxide film or tin oxide Membranes can be used. In addition, IZO is ITO with 2 to
It is a transparent conductive material formed by sputtering using a target mixed with 20 wt % of zinc oxide (ZnO). On the other hand, when having reflectivity, Ti, Mo, Ta, Cr
, W, Al and the like can be used. Also, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, or a three-layer structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr, and W may be used. Note that the second conductive layer 10107 may be formed by processing the shape. The method for processing the shape is preferably a method such as the photolithography method described above. It should be noted that the etching method is preferably dry etching. Dry etching is ECR (Electron Cyclotron Resonance) or ICP (In
A dry etching apparatus using a high-density plasma source such as a ductive coupled plasma may be used.

Next, a channel region of the TFT is formed. At this time, as a mask for etching the second semiconductor layer 10106, the second conductive layer 10107 may be used, or a mask (resist) for etching the second conductive layer 10107 may be used. good. By doing so, the number of masks can be reduced, so the manufacturing cost can be reduced. By etching the conductive second semiconductor layer 10106, the removed portion becomes the TFT.
channel area. Note that instead of continuously forming the first semiconductor layer 10105 and the second semiconductor layer 10106, after the formation of the first semiconductor layer 10105, a film serving as a stopper is formed in a portion to be the channel region of the TFT. patterned and then the second semiconductor layer 10
106 may be formed. Note that the first semiconductor layer 10105 and the second semiconductor layer 10106
is etched using the same mask when the shape of the second conductive layer 10107 is processed by a method such as the photolithography method described above. By doing so, the second conductive layer 1010
Since the channel region of the TFT can be formed without using 7 as a mask, there is an advantage that the degree of freedom of the layout pattern increases. In addition, since the first semiconductor layer 10105 is not etched when the second semiconductor layer 10106 is etched, there is an advantage that the channel region of the TFT can be reliably formed without causing etching defects.

Next, a third insulating film 10108 is formed. It is preferable that the third insulating film has transparency. Note that the material used for the third insulating film 10108 is an inorganic material (silicon oxide,
Silicon nitride, silicon oxynitride, etc.) or low dielectric constant organic compound materials (photosensitive or non-photosensitive organic resin materials) are suitable. Alternatively, a material containing siloxane may be used. Siloxane is a material having a skeletal structure composed of bonds of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (eg, alkyl group, aromatic hydrocarbon) is used. Alternatively, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as substituents. A contact hole is selectively formed in the third insulating film 10108 by etching. Also, contact holes are formed at least on the second conductive layer 10107 . In addition,
By etching the third insulating film 10108 and the second insulating film 10104 at the same time, a contact hole with not only the second conductive layer 10107 but also the first conductive layer 10103 can be formed. Note that the surface of the third insulating film 10108 is preferably as flat as possible. This is because the alignment of the liquid crystal molecules is affected by the unevenness of the surface with which the liquid crystal is in contact.

Next, a third conductive layer 10109 is formed. At this time, as a method for forming the third conductive layer 10109, a sputtering method or a printing method is preferably used. Note that the third conductive layer 10
The material used for 109, like the second conductive layer 10107, may be transparent or reflective. Note that the material that can be used for the third conductive layer 10109 is the second
may be the same as the conductive layer 10107 of . Alternatively, the third conductive layer 10109 may be formed by processing the shape. A method for processing the shape may be the same as that for the second conductive layer 10107 .

Next, a first alignment film 10110 is formed. A polymer film such as polyimide can be used for the alignment film 10110 . After forming the first alignment film 10110, rubbing may be performed in order to control the alignment of the liquid crystal molecules. Rubbing is a process of rubbing the alignment film with a cloth to form streaks on the alignment film. By performing rubbing, the orientation film can be given orientation.

The first substrate 10101 manufactured as described above, the light shielding film 10114, and the color filter 10
115, the fourth conductive layer 10113, the spacer 10117, and the second alignment film 10112 are bonded to the second substrate 10116 with a gap of several μm by a sealing material. A liquid crystal panel can be produced by injecting a liquid crystal material between the two substrates. Note that in a TN liquid crystal panel as shown in FIG. 46, the fourth conductive layer 101
13 may be fabricated on the entire surface of the second substrate 10116 .

Next, the features of the pixel structure of the TN liquid crystal panel shown in FIG. 46 will be described. Figure 46
The liquid crystal molecules 10118 shown in (A) of 1 are long and narrow molecules having long and short axes. In order to indicate the orientation of the liquid crystal molecules 10118, they are represented by their lengths in FIG. 46(A). That is, it is assumed that the long axis of the liquid crystal molecule 10118 is parallel to the plane of the paper, and the short axis of the liquid crystal molecule 10118 is closer to the normal direction of the paper. . That is, the liquid crystal molecules 10118 shown in FIG. 46(A) have long axes that are closer to the first substrate 10101 and closer to the second substrate 10116 in 9 directions.
They are different by 0 degrees, and the orientation of the long axis of the liquid crystal molecule 10118 located in the middle of them is the orientation that connects them smoothly. That is, the liquid crystal molecules 101 shown in FIG.
18 is oriented such that it is twisted by 90 degrees between the first substrate 10101 and the second substrate 10116 .

Next, with reference to FIG. 46B, an example of the pixel layout when the present embodiment is applied to a TN liquid crystal display device will be described. Pixels of the TN liquid crystal display device to which this embodiment is applied include a scanning line 10121, a video signal line 10122, and a capacitor line 10123.
, a TFT 10124 , a pixel electrode 10125 , and a pixel capacitor 10126 .

Since the scanning line 10121 is electrically connected to the gate electrode of the TFT 10124 , it is preferable that the scanning line 10121 is formed of the first conductive layer 10103 .

Since the video signal line 10122 is electrically connected to the source electrode or the drain electrode of the TFT 10124, it is preferable that the video signal line 10122 is made of the second conductive layer 10107. FIG. Moreover, since the scanning lines 10121 and the video signal lines 10122 are arranged in a matrix, at least
It is preferably formed of different layers of conductive layers.

The capacitor line 10123 is arranged in parallel with the pixel electrode 10125 so that the pixel capacitor 1012
6 and is preferably composed of the first conductive layer 10103 . Note that, as shown in FIG. 46B, the capacitor line 10123 may extend along the video signal line 10122 so as to surround the video signal line 10122 . By doing so, it is possible to reduce so-called crosstalk, a phenomenon in which the potential of the electrode that should hold the potential changes as the potential of the video signal line 10122 changes. In order to reduce the cross capacitance with the video signal line 10122, the first semiconductor layer 10105 is formed as shown in FIG.
may be provided in the intersection region of the capacitor line 10123 and the video signal line 10122 .

The TFT 10124 operates as a switch that electrically connects the video signal line 10122 and the pixel electrode 10125 . As shown in FIG. 46B, either the source region or the drain region of the TFT 10124 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capability can be increased. Note that as shown in FIG. 46B, the TFT
A gate electrode 10124 may be arranged to surround the first semiconductor layer 10105 .

The pixel electrode 10125 is electrically connected to either the source electrode or drain electrode of the TFT 10124 . The pixel electrode 10125 is an electrode for applying the signal voltage transmitted by the video signal line 10122 to the liquid crystal element. Also, by arranging the capacitance line 10123,
A pixel capacitor 10126 may be formed. This makes it easier for the pixel electrode 10125 to hold the signal voltage transmitted by the video signal line 10122 . Note that the pixel electrode 101
25 may be rectangular as shown in FIG. 46(B). By doing so, the aperture ratio of the pixels can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0125 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. Further, when the pixel electrode 10125 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in a bright environment such as the outdoors and does not require a backlight, so power consumption can be greatly reduced. Note that when the pixel electrode 10125 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having the advantages of both can be obtained. Note that when the pixel electrode 10125 is made of a reflective material, the surface of the pixel electrode 10125 may be uneven. Alternatively, by making the surface of the third insulating film 10108 uneven, the pixel electrode 10125 can be made uneven. By doing so, the reflected light is diffusely reflected, so there is an advantage that the angular dependence of the intensity distribution of the reflected light is reduced. In other words, it is possible to obtain a reflective liquid crystal display device with constant brightness when viewed from any angle.

Next, a case where the present embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described with reference to FIG. FIG. 47 shows a so-called MVA (Multi-domain) pixel structure of a VA mode liquid crystal display device, in which alignment control protrusions are used to control liquid crystal molecules to have various orientations to increase the viewing angle. Version
1A and 1B are a cross-sectional view and a top view of a pixel when the present embodiment is applied to the optical alignment method. FIG. 47A is a cross-sectional view of a pixel, and FIG. 47B is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 47A corresponds to the line segment aa' in the top view of the pixel shown in FIG. 47B. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 47, it is possible to obtain a liquid crystal display device with a wide viewing angle, a fast response speed, and a high contrast.

The pixel structure of the MVA liquid crystal display device will be described with reference to FIG. A liquid crystal display device has a main part that displays an image, called a liquid crystal panel. The liquid crystal panel is made by bonding two processed substrates together with a gap of several micrometers.
It is produced by injecting a liquid crystal material between two substrates. In FIG. 47A, the two substrates are a first substrate 10201 and a second substrate 10216. In FIG. The first substrate has a TF
T and pixel electrodes are produced, and a light shielding film 10214 and a color filter 102 are formed on the second substrate.
15, a fourth conductive layer 10213, a spacer 10217, a second alignment film 10212, and an alignment control projection 10219 may be fabricated.

Note that this embodiment mode can be implemented without forming TFTs on the first substrate 10201 . When this embodiment mode is implemented without manufacturing a TFT, the manufacturing cost can be reduced because the number of steps is reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when TFTs are manufactured and this embodiment mode is implemented, a larger display device can be obtained.

Note that the TFT shown in FIG. 47 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel using a TFT using an amorphous semiconductor has the advantage that it can be manufactured at low cost using a large-sized substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type, a channel protection type, and the like in the case of a bottom gate type TFT. Moreover, a top gate type may be used. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

Note that this embodiment mode can be implemented without forming the light shielding film 10214 on the second substrate 10216 . When this embodiment mode is implemented without forming the light shielding film 10214, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light shielding film 10214 is formed and this embodiment mode is carried out, it is possible to obtain a display device with little light leakage during black display.

Note that this embodiment mode can be implemented without forming the color filter 10215 on the second substrate 10216 . When this embodiment mode is implemented without manufacturing the color filter 10215, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without manufacturing the color filter 10215, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10215 is manufactured and this embodiment mode is implemented, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by scattering spherical spacers without forming the spacers 10217 on the second substrate 10216 . When carrying out this embodiment by scattering spherical spacers, the number of steps is reduced, so the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, the spacer 102
17 and implementing the present embodiment, the positions of the spacers do not fluctuate.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, since the method described with reference to FIG. 46 may be used for the processing applied to the first substrate 10201, the description thereof will be omitted. Here, a first substrate 10201, a first insulating film 10202, a first conductive layer 10203, a second insulating film 10204, a first semiconductor layer 10205, a second semiconductor layer 10206, and a second conductive layer 10207. , a third insulating film 10208, and a third conductive layer 1020
9. The first alignment film 10210 is the first substrate 10101 in FIG.
insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110, respectively. Although not shown, alignment control protrusions may also be provided on the first substrate side. By doing so, the alignment of the liquid crystal molecules can be controlled more reliably. In addition, the first alignment film 10210 and the second
The alignment film 10212 may be a vertical alignment film. By doing so, the liquid crystal molecules 10218 can be aligned vertically.

The first substrate 10201 manufactured as described above, the light shielding film 10214, and the color filter 10
215, fourth conductive layer 10213, spacer 10217, and second alignment film 10212
A liquid crystal panel can be manufactured by bonding the second substrate 10216 with a sealing material with a gap of several micrometers and injecting a liquid crystal material between the two substrates. In the MVA type liquid crystal panel as shown in FIG. 47, the fourth conductive layer 102
13 may be fabricated on the entire surface of the second substrate 10216 . Also, the fourth conductive layer 10
An alignment control protrusion 10219 may be formed in contact with 213 . Note that the alignment control protrusion 1
The shape of 0219 is not limited, but a shape with a smooth curved surface is preferable. By doing so, the alignment of adjacent liquid crystal molecules 10218 becomes extremely similar, so that alignment defects are reduced. In addition, defects in the alignment film caused by the second alignment film 10212 being broken by the alignment control protrusions 10219 can be reduced.

Next, the features of the pixel structure of the MVA liquid crystal panel shown in FIG. 47 will be described. Figure 4
A liquid crystal molecule 10218 shown in (A) of 7 is an elongated molecule having a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecules 10218, they are represented by their lengths in FIG. 47(A). That is, the long axis of the liquid crystal molecule 10218 is parallel to the plane of the paper, and the shorter the liquid crystal molecule 10218 is, the closer the long axis is to the normal to the plane of the paper. . In other words, the liquid crystal molecules 10218 shown in FIG. 47A are oriented so that their long axes are directed in the normal direction of the orientation film. Therefore, the orientation control projection 1021
The liquid crystal molecules 10218 in the portion where 9 is located are radially aligned with the alignment control protrusion 10219 as the center. With this state, a liquid crystal display device with a wide viewing angle can be obtained.

Next, with reference to FIG. 47B, an example of the pixel layout when the present embodiment is applied to an MVA liquid crystal display device will be described. Pixels of the MVA liquid crystal display device to which this embodiment is applied include a scanning line 10221, a video signal line 10222, and a capacitor line 102.
23 , a TFT 10224 , a pixel electrode 10225 , a pixel capacitor 10226 , and an alignment control protrusion 10219 .

Since the scanning line 10221 is electrically connected to the gate electrode of the TFT 10224 , it is preferable that the scanning line 10221 is formed of the first conductive layer 10203 .

Since the video signal line 10222 is electrically connected to the source electrode or drain electrode of the TFT 10224, it is preferable that the video signal line 10222 is made of the second conductive layer 10207. FIG. Moreover, since the scanning lines 10221 and the video signal lines 10222 are arranged in a matrix, at least
It is preferably formed of different layers of conductive layers.

The capacitor line 10223 is arranged in parallel with the pixel electrode 10225 so that the pixel capacitor 1022
6 and is preferably composed of the first conductive layer 10203 . Incidentally, as shown in FIG. 47B, the capacitance line 10223 may extend along the video signal line 10222 so as to surround the video signal line 10222 . By doing so, it is possible to reduce so-called crosstalk, a phenomenon in which the potential of the electrode that should hold the potential changes as the potential of the video signal line 10222 changes. In order to reduce the cross capacitance with the video signal line 10222, the first semiconductor layer 10205 is formed as shown in FIG.
may be provided in the intersection region of the capacitor line 10223 and the video signal line 10222 .

The TFT 10224 operates as a switch that electrically connects the video signal line 10222 and the pixel electrode 10225 . As shown in FIG. 47B, either the source region or the drain region of the TFT 10224 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capability can be increased. Note that as shown in FIG. 47B, the TFT
A gate electrode 10224 may be arranged to surround the first semiconductor layer 10205 .

The pixel electrode 10225 is electrically connected to either the source electrode or drain electrode of the TFT 10224 . The pixel electrode 10225 is an electrode for applying the signal voltage transmitted by the video signal line 10222 to the liquid crystal element. Also, by arranging the capacitance line 10223,
A pixel capacitor 10226 may be formed. This makes it easier for the pixel electrode 10225 to hold the signal voltage transmitted by the video signal line 10222 . Note that the pixel electrode 102
25 may be rectangular as shown in FIG. 47(B). By doing so, the aperture ratio of the pixels can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0225 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. Further, when the pixel electrode 10225 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in a bright environment such as the outdoors and does not require a backlight, so power consumption can be greatly reduced. Note that when the pixel electrode 10225 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having the advantages of both can be obtained. Note that when the pixel electrode 10225 is made of a reflective material, the surface of the pixel electrode 10225 may be uneven. Alternatively, by making the surface of the third insulating film 10208 uneven, the pixel electrode 10225 can be made uneven. By doing so, the reflected light is diffusely reflected, so there is an advantage that the angular dependence of the intensity distribution of the reflected light is reduced. In other words, it is possible to obtain a reflective liquid crystal display device with constant brightness when viewed from any angle.

Next, another example in which the present embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described with reference to FIG. FIG. 48 shows a pixel structure of a VA mode liquid crystal display device in which the fourth conductive layer 10313 is patterned to control the orientation of liquid crystal molecules in various directions to increase the viewing angle. PVA (P
1A and 1B are a cross-sectional view and a top view of a pixel when the present embodiment is applied to an attenuated vertical alignment method; FIG. 48A is a cross-sectional view of a pixel, and FIG. 48B is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 48(A) corresponds to the line segment aa' in the top view of the pixel shown in FIG. 48(B). By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 48, a liquid crystal display device with a wide viewing angle, a fast response speed, and a high contrast can be obtained.

A pixel structure of a PVA liquid crystal display device will be described with reference to FIG. A liquid crystal display device has a main part that displays an image, called a liquid crystal panel. The liquid crystal panel is made by bonding two processed substrates together with a gap of several micrometers.
It is produced by injecting a liquid crystal material between two substrates. In FIG. 48A, the two substrates are a first substrate 10301 and a second substrate 10316. In FIG. The first substrate has a T
FTs and pixel electrodes are fabricated, and a light shielding film 10314, a color filter 10315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10 are formed on a second substrate.
312 may be made.

Note that this embodiment mode can be implemented without forming TFTs on the first substrate 10301 . When this embodiment mode is implemented without manufacturing a TFT, the manufacturing cost can be reduced because the number of steps is reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when TFTs are manufactured and this embodiment mode is implemented, a larger display device can be obtained.

Note that the TFT shown in FIG. 48 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel using a TFT using an amorphous semiconductor has the advantage that it can be manufactured at low cost using a large-sized substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type, a channel protection type, and the like in the case of a bottom gate type TFT. Moreover, a top gate type may be used. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

Note that this embodiment mode can be implemented without forming the light shielding film 10314 on the second substrate 10316 . When this embodiment mode is implemented without forming the light shielding film 10314, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light shielding film 10314 is formed and this embodiment mode is carried out, a display device with less light leakage can be obtained during black display.

Note that this embodiment mode can be implemented without forming the color filter 10315 on the second substrate 10316 . When this embodiment mode is implemented without manufacturing the color filter 10315, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without manufacturing the color filter 10315, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10315 is manufactured and this embodiment mode is implemented, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by scattering spherical spacers without forming the spacers 10317 on the second substrate 10316 . When carrying out this embodiment by scattering spherical spacers, the number of steps is reduced, so the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, spacer 103
17 and implementing the present embodiment, the positions of the spacers do not fluctuate.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, since the method described with reference to FIG. 46 may be used for the processing applied to the first substrate 10301, the description thereof will be omitted. Here, a first substrate 10301, a first insulating film 10302, a first conductive layer 10303, a second insulating film 10304, a first semiconductor layer 10305, a second semiconductor layer 10306, and a second conductive layer 10307. , a third insulating film 10308, and a third conductive layer 1030
9. The first alignment film 10310 is the first substrate 10101 in FIG.
insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110, respectively. Note that an electrode notch portion may be provided in the third conductive layer 10309 on the first substrate 10301 side. By doing so, the alignment of the liquid crystal molecules can be controlled more reliably. Also, the first alignment film 10
310 and the second alignment film 10312 may be vertical alignment films. By doing so, the liquid crystal molecules 10318 can be aligned vertically.

The first substrate 10301 manufactured as described above, the light shielding film 10314, and the color filter 10
315, fourth conductive layer 10313, spacer 10317, and second alignment film 10312
A liquid crystal panel can be manufactured by bonding the second substrate 10316 with a sealing material with a gap of several μm and injecting a liquid crystal material between the two substrates. In the PVA type liquid crystal panel as shown in FIG. 48, the fourth conductive layer 10313 may be patterned to form the electrode notch 10319 . Although the shape of the electrode cutout portion 10319 is not limited, it is preferable that the shape is a combination of a plurality of rectangles with different orientations. By doing so, a plurality of regions with different orientations can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. Also, the shape of the fourth conductive layer 10313 at the boundary between the electrode notch 10319 and the fourth conductive layer 10313 is preferably a smooth curve. By doing so, the alignment of adjacent liquid crystal molecules 10318 becomes extremely close, so that alignment defects are reduced. In addition, the second alignment film 10312 is the electrode notch portion 10
It is also possible to reduce defects in the alignment film due to step disconnection caused by 319 .

Next, the features of the pixel structure of the PVA type liquid crystal panel shown in FIG. 48 will be described. Figure 4
The liquid crystal molecule 10318 shown in (A) of 8 is an elongated molecule having a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecules 10318, they are represented by their lengths in FIG. 48(A). That is, the long axis of the liquid crystal molecule 10318 is parallel to the paper surface, and the short liquid crystal molecule 10318 is closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10318 shown in FIG. 48A are oriented such that the direction of the long axis is directed to the normal direction of the orientation film. Therefore, the electrode notch portion 1031
The liquid crystal molecules 10318 in the portion with 9 are connected to the electrode cutout portion 10319 and the fourth conductive layer 103
It is oriented radially around the 13 boundary. With this state, a liquid crystal display device with a wide viewing angle can be obtained.

Next, with reference to FIG. 48B, an example of the pixel layout when the present embodiment is applied to a PVA liquid crystal display device will be described. The pixels of the PVA liquid crystal display device to which this embodiment is applied include the scanning line 10321, the video signal line 10322, and the capacitor line 103.
23, a TFT 10324, a pixel electrode 10325, a pixel capacitor 10326, and an electrode notch 10319.

Since the scanning line 10321 is electrically connected to the gate electrode of the TFT 10324 , it is preferable that the scanning line 10321 is formed of the first conductive layer 10303 .

Since the video signal line 10322 is electrically connected to the source electrode or drain electrode of the TFT 10324, it is preferable that the video signal line 10322 is formed of the second conductive layer 10307. FIG. Moreover, since the scanning lines 10321 and the video signal lines 10322 are arranged in a matrix, at least
It is preferably formed of different layers of conductive layers.

The capacitor line 10323 is arranged in parallel with the pixel electrode 10325 so that the pixel capacitor 1032
6 and is preferably composed of the first conductive layer 10303 . Note that, as shown in FIG. 48B, the capacitance line 10323 may extend along the video signal line 10322 so as to surround the video signal line 10322 . By doing so, it is possible to reduce so-called crosstalk, a phenomenon in which the potential of the electrode that should hold the potential changes as the potential of the video signal line 10322 changes. In order to reduce the cross capacitance with the video signal line 10322, the first semiconductor layer 10305 is formed as shown in FIG.
may be provided in the intersection region of the capacitor line 10323 and the video signal line 10322 .

The TFT 10324 operates as a switch that electrically connects the video signal line 10322 and the pixel electrode 10325 . As shown in FIG. 48B, either the source region or the drain region of the TFT 10324 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capability can be increased. In addition, as shown in FIG. 48B, the TFT
A gate electrode 10324 may be arranged to surround the first semiconductor layer 10305 .

The pixel electrode 10325 is electrically connected to either the source electrode or drain electrode of the TFT 10324 . The pixel electrode 10325 is an electrode for applying the signal voltage transmitted by the video signal line 10322 to the liquid crystal element. Also, by arranging the capacitance line 10323,
A pixel capacitor 10326 may be formed. This makes it easier for the pixel electrode 10325 to hold the signal voltage transmitted by the video signal line 10322 . Note that the pixel electrode 103
25, as shown in FIG. 48B, the pixel electrode 103 is formed in a portion without the electrode cutout 10319 according to the shape of the electrode cutout 10319 provided in the fourth conductive layer 10313.
It is preferable to form a portion by notching 25 . By doing this, liquid crystal molecules 10318
Since a plurality of regions with different orientations can be formed, a liquid crystal display device with a wide viewing angle can be obtained. Further, when the pixel electrode 10325 is made of a transparent material,
A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. Further, when the pixel electrode 10325 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in a bright environment such as the outdoors and does not require a backlight, so power consumption can be greatly reduced. Note that when the pixel electrode 10325 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that when the pixel electrode 10325 is made of a reflective material, the surface of the pixel electrode 10325 may be uneven. Alternatively, by making the surface of the third insulating film 10308 uneven, the pixel electrode 10325 can be made uneven. By doing so, the reflected light is diffusely reflected, so there is an advantage that the angular dependence of the intensity distribution of the reflected light is reduced. In other words, it is possible to obtain a reflective liquid crystal display device with constant brightness when viewed from any angle.

Next, with reference to FIG. 49, a case where the present embodiment is applied to a horizontal electric field type liquid crystal display device will be described. FIG. 49 shows a pixel structure of a liquid crystal display device in which an electric field is applied in the lateral direction in order to perform switching so that the alignment of liquid crystal molecules is always horizontal with respect to the substrate. FIG. 10A is a cross-sectional view and a top view of a pixel when the present embodiment is applied to a method of applying an electric field in the horizontal direction by performing comb-tooth pattern processing, that is, a so-called IPS (In-Plane-Switching) method. . FIG. 49A is a cross-sectional view of a pixel, and FIG. 49B is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 49(A) corresponds to line segment aa' in the top view of the pixel shown in FIG. 49(B). By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 49, a liquid crystal display device having a wide viewing angle and a small gradation dependency of response speed can be obtained in principle.

A pixel structure of an IPS liquid crystal display device will be described with reference to FIG. A liquid crystal display device has a main part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates with a gap of several μm, and injecting a liquid crystal material between the two substrates. In FIG. 49A, the two substrates are a first substrate 10401 and a second substrate 10416. In FIG. TFTs and pixel electrodes are formed on the first substrate, and a light-shielding film 10414 and color filters 10415 are formed on the second substrate.
, a spacer 10417, and a second alignment film 10412 may be fabricated.

Note that this embodiment mode can be implemented without forming TFTs on the first substrate 10401 . When this embodiment mode is implemented without manufacturing a TFT, the manufacturing cost can be reduced because the number of steps is reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when TFTs are manufactured and this embodiment mode is implemented, a larger display device can be obtained.

Note that the TFT shown in FIG. 49 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel using a TFT using an amorphous semiconductor has the advantage that it can be manufactured at low cost using a large-sized substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type, a channel protection type, and the like in the case of a bottom gate type TFT. Moreover, a top gate type may be used. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

Note that this embodiment mode can be implemented without forming the light shielding film 10414 on the second substrate 10416 . In the case of implementing this embodiment mode without manufacturing the light shielding film 10414, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light shielding film 10414 is formed and this embodiment mode is carried out, a display device with less light leakage can be obtained during black display.

Note that this embodiment mode can be implemented without forming the color filter 10415 on the second substrate 10416 . When this embodiment mode is implemented without manufacturing the color filter 10415, the manufacturing cost can be reduced because the number of steps is reduced. However, even when this embodiment mode is implemented without manufacturing the color filter 10415, a display device capable of color display can be obtained by field sequential driving. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the color filter 10415 is manufactured and this embodiment mode is implemented, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by scattering spherical spacers without forming the spacers 10417 on the second substrate 10416 . When carrying out this embodiment by scattering spherical spacers, the number of steps is reduced, so the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, spacer 104
17 and implementing the present embodiment, the positions of the spacers do not fluctuate.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, since the method described with reference to FIG. 46 may be used for the processing performed on the first substrate 10401, the description thereof will be omitted. Here, a first substrate 10401, a first insulating film 10402, a first conductive layer 10403, a second insulating film 10404, a first semiconductor layer 10405, a second semiconductor layer 10406, and a second conductive layer 10407. , a third insulating film 10408, and a third conductive layer 1040
9. The first alignment film 10410 is respectively the first substrate 10101 in FIG.
insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110, respectively. In addition, the third conductive layer 10409 on the first substrate 10401 side is patterned to form two conductive layers that are engaged with each other.
It may be formed into a comb-like shape. Alternatively, one comb-shaped electrode may be electrically connected to one of the source electrode and the drain electrode of the TFT 10424 , and the other comb-shaped electrode may be electrically connected to the common electrode 10423 . By doing this, liquid crystal molecules 10418
can effectively apply a lateral electric field to

The first substrate 10401 manufactured as described above, the light shielding film 10414, and the color filter 10
415, spacers 10417, and second substrate 10 on which second alignment film 10412 is fabricated
A liquid crystal panel can be manufactured by bonding the substrates 416 together with a gap of several micrometers using a sealing material and injecting a liquid crystal material between the two substrates. Although not shown,
A conductive layer may be formed on the second substrate 10416 side. By forming the conductive layer on the second substrate 10416 side, the influence of electromagnetic noise from the outside can be reduced.

Next, the features of the pixel structure of the IPS liquid crystal panel shown in FIG. 49 will be described. Figure 4
A liquid crystal molecule 10418 shown in (A) of 9 is an elongated molecule having a major axis and a minor axis. In order to indicate the orientation of the liquid crystal molecules 10418, they are represented by their lengths in FIG. 49(A). That is, the long axis of the liquid crystal molecule 10418 is parallel to the plane of the paper, and the shorter the liquid crystal molecule 10418 is, the closer the long axis is to the normal to the plane of the paper. . In other words, the liquid crystal molecules 10418 shown in FIG. 49A are oriented so that their long axes are always parallel to the substrate. In FIG. 49(A),
The orientation in the absence of an electric field is shown, but when an electric field is applied to the liquid crystal molecules 10418, the direction of the major axis of the liquid crystal molecules 10418 rotates in the horizontal plane while always maintaining the direction parallel to the substrate. With this state, a liquid crystal display device with a wide viewing angle can be obtained.

Next, with reference to FIG. 49B, an example of the pixel layout when the present embodiment is applied to an IPS liquid crystal display device will be described. Pixels of the IPS liquid crystal display device to which this embodiment is applied include a scanning line 10421, a video signal line 10422, and a common electrode 10422.
423, a TFT 10424, and a pixel electrode 10425 may be provided.

Since the scanning line 10421 is electrically connected to the gate electrode of the TFT 10424 , it is preferable that the scanning line 10421 is formed of the first conductive layer 10403 .

Since the video signal line 10422 is electrically connected to the source electrode or the drain electrode of the TFT 10424, it is preferable that the video signal line 10422 is made of the second conductive layer 10407. FIG. Moreover, since the scanning lines 10421 and the video signal lines 10422 are arranged in a matrix, at least
It is preferably formed of different layers of conductive layers. Note that, as shown in FIG. 49B, the video signal line 10422 may be bent within the pixel so as to match the shapes of the pixel electrode 10425 and the common electrode 10423 . By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device can be improved.

The common electrode 10423 is an electrode for generating a horizontal electric field by being arranged in parallel with the pixel electrode 10425, and is composed of a first conductive layer 10403 and a third conductive layer 10409. preferred. Incidentally, as shown in FIG. 49B, the common electrode 1042
3 may extend along the video signal line 10422 so as to surround the video signal line 10422 . By doing so, it is possible to reduce so-called crosstalk, a phenomenon in which the potential of the electrode that should hold the potential changes as the potential of the video signal line 10422 changes.
In order to reduce the cross capacitance with the video signal line 10422, the first semiconductor layer 10405 may be provided in the cross region of the common electrode 10423 and the video signal line 10422 as shown in FIG. 49B.

The TFT 10424 operates as a switch that electrically connects the video signal line 10422 and the pixel electrode 10425 . As shown in FIG. 49B, either the source region or the drain region of the TFT 10424 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capability can be increased. Note that as shown in FIG. 49B, the TFT
A gate electrode 10424 may be arranged to surround the first semiconductor layer 10405 .

The pixel electrode 10425 is electrically connected to either the source electrode or drain electrode of the TFT 10424 . The pixel electrode 10425 is an electrode for applying the signal voltage transmitted by the video signal line 10422 to the liquid crystal element. A pixel capacitor may be formed by arranging the common electrode 10423 . By doing so, the pixel electrode 10325 is connected to the video signal line 10
422 is easier to hold. The pixel electrode 10425 and the comb-like common electrode 10423 are preferably formed in a bent comb-like shape as shown in FIG. 49B. By doing so, a plurality of regions in which the liquid crystal molecules 10418 are oriented differently can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. Further, when the pixel electrode 10425 and the comb-like common electrode 10423 are made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device
High color reproducibility and high image quality can be displayed. Further, in the transmissive liquid crystal display device, pixels have a high aperture ratio, and light efficiency can be improved. However, even if the pixel electrode 10425 and the comb-like common electrode 10423 are made of a material that is neither transparent nor reflective, a transmissive liquid crystal display device can be obtained. In the transmissive liquid crystal display device, since light is transmitted only through the liquid crystal molecules 10418 in a portion where a horizontal electric field exists, images with high color reproducibility and high image quality can be displayed. Further, when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a reflective material,
A transflective liquid crystal display device can be obtained. A transflective liquid crystal display device has high visibility in a bright environment such as outdoors, and can consume very little power. moreover,
A transflective liquid crystal display device has high color reproducibility and can display images with high image quality. However, a transflective liquid crystal display device can be obtained even when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of both a transparent material and a reflective material. Note that when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a reflective material, the pixel electrode 10425 and the comb-shaped common electrode 10423
The surface of 423 may be uneven. Alternatively, by making the surface of the third insulating film 10408 uneven, the pixel electrode 10425 and the comb-shaped common electrode 10423 can be uneven. By doing so, the reflected light is diffusely reflected, so there is an advantage that the angular dependence of the intensity distribution of the reflected light is reduced. In other words, it is possible to obtain a reflective liquid crystal display device with constant brightness when viewed from any angle.

Note that the comb-shaped pixel electrode 10425 and the comb-shaped common electrode 10423 are both formed of the third conductive layer 10409, but the pixel structure to which this embodiment can be applied is limited to this. can be selected as appropriate. For example, the comb-shaped pixel electrode 10425 and the comb-shaped common electrode 10423 may both be formed from the second conductive layer 10407, or both may be formed from the first conductive layer 10403. Either one may be formed of the third conductive layer 10409 and the other may be formed of the second conductive layer 10407, or one of them may be formed of the third conductive layer 10409 and the other the first conductive layer 10409. Either the layer 10407 may be formed, or one of them may be formed by the second conductive layer 10409 and the other may be formed by the first conductive layer 10407 .

Next, with reference to FIG. 50, a case where the present embodiment is applied to another horizontal electric field type liquid crystal display device will be described. FIG. 50 is a diagram showing another pixel structure of a liquid crystal display device in which an electric field is applied laterally in order to perform switching so that the orientation of the liquid crystal molecules is always horizontal with respect to the substrate. More specifically, one of the pixel electrode 10525 and the common electrode 10523 is subjected to comb-teeth pattern processing, and the other is uniformly formed in a region overlapping the comb-teeth shape. A method of applying an electric field in a direction, the so-called FFS (Fringe Field S
1A and 1B are a cross-sectional view and a top view of a pixel when the present embodiment is applied to a switching method. FIG. 50A is a cross-sectional view of the pixel, and FIG. 50B is a top view of the pixel.
The cross-sectional view of the pixel shown in FIG. 50(A) corresponds to line segment aa' in the top view of the pixel shown in FIG. 50(B). By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 50, a liquid crystal display device having a large viewing angle and a small gradation dependency of response speed can be obtained in principle.

The pixel structure of the FFS liquid crystal display device will be described with reference to FIG. A liquid crystal display device has a main part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates with a gap of several micrometers and injecting a liquid crystal material between the two substrates. In FIG. 50A, the two substrates are a first substrate 10501 and a second substrate 10516. In FIG. TFTs on the first substrate
and pixel electrodes, and a light shielding film 10514 and a color filter 1051 are formed on a second substrate.
5, a spacer 10517 and a second alignment film 10512 may be fabricated.

Note that this embodiment mode can be implemented without forming TFTs on the first substrate 10501 . When this embodiment mode is implemented without manufacturing a TFT, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when TFTs are manufactured and this embodiment mode is implemented, a larger display device can be obtained.

Note that the TFT shown in FIG. 50 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel using a TFT using an amorphous semiconductor has the advantage that it can be manufactured at low cost using a large-sized substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type, a channel protection type, and the like in the case of a bottom gate type TFT. Moreover, a top gate type may be used. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

Note that this embodiment mode can be implemented without forming the light shielding film 10514 on the second substrate 10516 . In the case of implementing this embodiment mode without manufacturing the light shielding film 10514, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light shielding film 10514 is formed and this embodiment mode is carried out, a display device with less light leakage can be obtained during black display.

Note that this embodiment mode can be implemented without forming the color filter 10515 on the second substrate 10516 . When this embodiment mode is implemented without manufacturing the color filter 10515, the manufacturing cost can be reduced because the number of steps is reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without manufacturing the color filter 10515, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10515 is manufactured and this embodiment mode is implemented, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by scattering spherical spacers without forming the spacers 10517 on the second substrate 10516 . When carrying out this embodiment by scattering spherical spacers, the number of steps is reduced, so the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, spacer 105
17 and implementing the present embodiment, the positions of the spacers do not fluctuate.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, since the method described with reference to FIG. 46 may be used for the processing applied to the first substrate 10501, the description thereof will be omitted. Here, a first substrate 10501, a first insulating film 10502, a first conductive layer 10503, a second insulating film 10504, a first semiconductor layer 10505, a second semiconductor layer 10506, and a second conductive layer 10507. , a third insulating film 10508, and a third conductive layer 1050
9. The first alignment film 10510 is the first substrate 10101 in FIG.
insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110, respectively.

However, the difference from FIG. 46 is that the fourth insulating film 10519 and the fourth conductive layer 10513 may be formed on the first substrate 10501 side. More specifically, after the third conductive layer 10509 is patterned, a fourth insulating film 10519 is formed, patterned to form contact holes, and then the fourth conductive layer 10513 is formed. The first alignment film 10510 may be formed after forming a film and patterning in the same manner. Note that materials and processing methods that can be used for the fourth insulating film 10519 and the fourth conductive layer 10513 are similar to those used for the third insulating film 10508 and the third conductive layer 10509 . Also, one comb-shaped electrode may be electrically connected to one of the source electrode and the drain electrode of the TFT 10524 , and the other uniform electrode may be electrically connected to the common electrode 10523 . By doing so, a lateral electric field can be effectively applied to the liquid crystal molecules 10518 .

The first substrate 10501 manufactured as described above, the light shielding film 10514, and the color filter 10
515, spacers 10517, and second substrate 10 on which second alignment film 10512 is fabricated
A liquid crystal panel can be manufactured by bonding the substrates 516 together with a gap of several micrometers using a sealing material and injecting a liquid crystal material between the two substrates. Although not shown, a conductive layer may be formed on the second substrate 10516 side. By forming the conductive layer on the second substrate 10516 side, the influence of electromagnetic noise from the outside can be reduced.

Next, the features of the pixel structure of the FFS liquid crystal panel shown in FIG. 50 will be described. Figure 5
A liquid crystal molecule 10518 shown in (A) of 0 is an elongated molecule having a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecules 10518, they are represented by their lengths in FIG. 50(A). That is, the long axis of the liquid crystal molecule 10518 is parallel to the paper surface, and the short liquid crystal molecule 10518 is closer to the normal direction of the paper surface. . In other words, the liquid crystal molecules 10518 shown in FIG. 50A are oriented so that their long axes are always parallel to the substrate. In FIG. 50(A),
The orientation in the absence of an electric field is shown, but when an electric field is applied to the liquid crystal molecules 10518, the direction of the long axis is always kept parallel to the substrate and rotates in the horizontal plane. With this state, a liquid crystal display device with a wide viewing angle can be obtained.

Next, with reference to FIG. 50B, an example of the pixel layout when the present embodiment is applied to the FFS liquid crystal display device will be described. Pixels of the FFS liquid crystal display device to which this embodiment is applied include a scanning line 10521, a video signal line 10522, a common electrode 10
523, a TFT 10524, and a pixel electrode 10525.

Since the scanning line 10521 is electrically connected to the gate electrode of the TFT 10524 , it is preferable that the scanning line 10521 is formed of the first conductive layer 10503 .

Since the video signal line 10522 is electrically connected to the source electrode or the drain electrode of the TFT 10524, it is preferable that the video signal line 10522 is made of the second conductive layer 10507. FIG. Moreover, since the scanning lines 10521 and the video signal lines 10522 are arranged in a matrix, at least
It is preferably formed of different layers of conductive layers. Note that, as shown in FIG. 50B, the video signal line 10522 may be bent within the pixel so as to match the shape of the pixel electrode 10525 . By doing so, the aperture ratio of the pixel can be increased,
The efficiency of the liquid crystal display device can be improved.

Common electrode 10523 is preferably comprised of first conductive layer 10503 and third conductive layer 10509 . In order to reduce the cross capacitance with the video signal line 10522,
As shown in FIG. 50B, the first semiconductor layer 10505 may be provided in the intersection region between the common electrode 10523 and the video signal line 10522 .

The TFT 10524 operates as a switch that electrically connects the video signal line 10522 and the pixel electrode 10525 . As shown in FIG. 50B, either the source region or the drain region of the TFT 10524 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capability can be increased. Note that as shown in FIG. 50B, the TFT
A gate electrode 10524 may be arranged to surround the first semiconductor layer 10505 .

The pixel electrode 10525 is electrically connected to either the source electrode or drain electrode of the TFT 10524 . The pixel electrode 10525 is an electrode for applying the signal voltage transmitted by the video signal line 10522 to the liquid crystal element. A pixel capacitor may be formed by arranging the common electrode 10523 . By doing so, the pixel electrode 10525 is connected to the video signal line 10
522 to help hold the signal voltage. Note that the pixel electrode 10525 is
As shown in FIG. 50(B), it is preferable to form a curved comb shape. By doing so, a plurality of regions in which the liquid crystal molecules 10518 are oriented differently can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. In addition, a comb-shaped pixel electrode 1052
5 and the common electrode 10523 are made of a transparent material, a transmissive liquid crystal display device can be obtained. However, even when the comb-shaped pixel electrode 10525 is made of a non-reflective material and the common electrode 10523 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. Further, when the comb-shaped pixel electrode 10525 and the common electrode 10523 are made of a reflective material, a reflective liquid crystal display device can be obtained. However, if at least the common electrode 10523 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in a bright environment such as the outdoors and does not require a backlight, so power consumption can be greatly reduced. Note that when the comb-shaped pixel electrode 10525 and the common electrode 10523 are formed using both a transparent material and a reflective material, a transflective liquid crystal display device having advantages of both can be obtained. Obtainable. However, the comb-shaped pixel electrode 1
Even when 0525 is made of a reflective material and the pixel electrode 10525 is made of a transmissive material, a transflective liquid crystal display device can be obtained. When the pixel electrode 10525 and the comb-shaped common electrode 10523 are made of a reflective material, the surfaces of the comb-shaped pixel electrode 10525 and the common electrode 10523 may be uneven. Alternatively, by making the surface of the third insulating film 10508 uneven, the comb-shaped pixel electrode 10525 and the common electrode 10523 can be uneven. By doing so, the reflected light is diffusely reflected, so there is an advantage that the angular dependence of the intensity distribution of the reflected light is reduced. In other words, it is possible to obtain a reflective liquid crystal display device with constant brightness when viewed from any angle.

Although the comb-shaped pixel electrode 10525 is formed of the fourth conductive layer 10513 and the uniform common electrode 10523 is formed of the third conductive layer 10509, this embodiment can be applied. The pixel configuration is not limited to this, and can be appropriately selected as long as certain conditions are satisfied. More specifically, when viewed from the first substrate 10501, the comb-shaped electrode should be positioned closer to the liquid crystal than the uniform electrode. This is because the lateral electric field always occurs in the opposite direction to the uniform electrode when viewed from the comb-shaped electrode. In other words, in order to apply a lateral electric field to the liquid crystal, the comb-shaped electrode must be positioned closer to the liquid crystal than the uniform electrode.

To satisfy this condition, for example, a comb-shaped electrode may be formed from the fourth conductive layer 10513 and a uniform electrode may be formed from the third conductive layer 10509, or a comb-shaped electrode may be formed. fourth conductive layer 1
0513 and a uniform electrode may be formed from the second conductive layer 10507, or a comb-shaped electrode may be formed from the fourth conductive layer 10513 and a uniform electrode may be formed from the first conductive layer 10507. 10503, a comb-shaped electrode may be formed from the third conductive layer 10509, and a uniform electrode may be formed from the second conductive layer 10507, or the comb-shaped electrode may be formed from the second conductive layer 10507. The third conductive layer 10509 may be used to form a uniform electrode, and the first conductive layer 10503 may be used to form a uniform electrode.
0507 and a uniform electrode may be formed of the first conductive layer 10503 . Note that the comb-shaped electrode is electrically connected to either the source region or the drain region of the TFT 10524, and the uniform electrode is electrically connected to the common electrode 10523, but this connection is reversed. It's okay. In that case, a uniform electrode may be formed independently for each pixel.

Next, various liquid crystal modes applicable to the liquid crystal display device of this embodiment will be described.

First, FIGS. 51A1 and 51A2 are schematic diagrams of a TN mode liquid crystal display device.

As in the above embodiment, a liquid crystal layer 10600 is sandwiched between a first substrate 10601 and a second substrate 10602 which are arranged to face each other. Then, the first substrate 106
A layer 10603 containing a first polarizer is laminated on the 01 side, and a layer 10604 containing a second polarizer is arranged on the second substrate 10602 side. Note that the layer 10 containing the first polarizer
603 and the second polarizer containing layer 10604 are arranged in crossed Nicols.

Although not shown, the backlight and the like are arranged outside the layer including the second polarizer. First electrodes 10605 are formed on the first substrate 10601 and the second substrate 10602, respectively.
, a second electrode 10606 is provided. The first electrode 10605, which is the electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least light-transmitting properties.

In the liquid crystal display device having the structure as shown in FIGS. 51A1 and 51A2, voltage is applied to the first electrode 10605 and the second electrode 10606 (referred to as a vertical electric field method) in the normally white mode. Then, black display is performed as shown in FIG. 51(A1). At this time, the liquid crystal molecules are aligned vertically. Then, the light from the backlight cannot pass through the substrate, resulting in black display.

Then, as shown in FIG. 51A2, a first electrode 10605 and a second electrode 10606
When no voltage is applied between , the display is white. At this time, the liquid crystal molecules are arranged side by side,
It will be rotating in a plane. As a result, light from the backlight passes through a pair of polarizer-containing layers (first polarizer-containing layer 10603 and second polarizer-containing layer 10604) arranged in crossed Nicols. and a predetermined image display is performed.

A liquid crystal display device having a structure as shown in FIGS. 51A1 and 51A2 can perform full-color display by providing a color filter. The color filters are formed on the first substrate 10
It can be provided on either the 601 side or the second substrate 10602 side. However, Figure 5
1 (A1) and (A2) can perform full-color display by field sequential driving if the light from the backlight changes over time without providing a color filter.

A known liquid crystal material may be used for the TN mode.

FIG. 51B1 shows a schematic diagram of a VA mode liquid crystal display device. The VA mode is a mode in which the liquid crystal molecules are oriented perpendicular to the substrate when no electric field is applied.

51A1 and 51A2, a first electrode 10605 and a second electrode 10606 are provided over a first substrate 10601 and a second substrate 10602, respectively. The first electrode 10605, which is the electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least light-transmitting properties. A layer 10603 including a first polarizer is laminated on the first substrate 10601 side, and a layer 10603 including a second polarizer is laminated on the second substrate 10602 side.
0604 are arranged. Note that the layer 10603 containing the first polarizer and the layer 10604 containing the second polarizer are arranged so as to form crossed Nicols.

In liquid crystal display devices having structures as shown in FIGS.
05 and the second electrode 10606 (longitudinal electric field method), FIG.
As shown in , it is turned on to display white. At this time, the liquid crystal molecules are arranged side by side. Light from the backlight then passes through a pair of polarizer-containing layers (a first polarizer-containing layer 10603 and a second polarizer-containing layer 10604) arranged in crossed Nicols.
), and a predetermined image is displayed. At this time, full-color display can be performed by providing a color filter. The color filters are formed on the first substrate 10
It can be provided on either the 601 side or the second substrate 10602 side.

Then, as shown in FIG. 51B2, a first electrode 10605 and a second electrode 10606
When no voltage is applied between , it is displayed in black, that is, it is in an off state. At this time, the liquid crystal molecules are aligned vertically. As a result, light from the backlight cannot pass through the substrate, resulting in black display.

In the OFF state, the liquid crystal molecules stand perpendicular to the substrate, resulting in black display, and in the ON state, the liquid crystal molecules fall horizontally relative to the substrate, resulting in white display. Since the liquid crystal molecules stand up in the off state, the polarized light from the backlight passes through the cell without being affected by the birefringence of the liquid crystal molecules, and is blocked by the layer containing the polarizer on the opposite substrate side. be able to.

Here, FIGS. 51C1 and 51C2 show an example in which the layer including the stacked polarizers of this embodiment mode is applied to the MVA mode in which the alignment of the liquid crystal is divided. The MVA mode is a method of mutually compensating the viewing angle dependence of each part. As shown in FIG. 51C1, in the MVA mode, projections 10607 and 10608 with triangular cross sections are provided on the first electrode 10605 and the second electrode 10606 for alignment control. A first electrode 10605 and a second
When a voltage is applied to the electrode 10606 (longitudinal electric field method), an ON state is obtained in which white display is performed as shown in FIG. 51(C1). At this time, the liquid crystal molecules form projections 10607 and 1060
It will be in a state where it falls side by side with respect to 8. Light from the backlight then passes through a pair of polarizer-containing layers (first polarizer-containing layer 10603 and second polarizer-containing layer 10604) arranged in crossed Nicols. A predetermined video display is performed. Note that the liquid crystal display devices having the structures shown in FIGS. 51C1 and 51C2 can perform full-color display by providing color filters. A color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display devices having the structures shown in FIGS. 51C1 and 51C2 can perform full-color display by field sequential driving without providing color filters.

Then, as shown in FIG. 51(C2), a first electrode 10605 and a second electrode 1060
When no voltage is applied between 6, black display is performed, ie, the off state. At this time, the liquid crystal molecules are aligned vertically. As a result, light from the backlight cannot pass through the substrate, resulting in black display.

A top view and a cross-sectional view of another example of the MVA mode are shown in FIG. As shown in FIG. 54A, the second electrodes 10606a, 10606b, and 10606c may be formed in a bent pattern like a doglegged shape. Also, insulating layers 10901 and 10902 are formed near the liquid crystal layer 10600 . Note that the insulating layers 10901 and 10902 may be alignment films. As shown in FIG. 54(B), the protrusion 1
0607 may be formed corresponding to the second electrodes 10606a, 10606b and 10606c. Projections 10607 are connected to second electrodes 10606a, 10606b, and 10606c.
by forming the second electrodes 10606a, 10606b, 10606
The c opening functions like a protrusion and can effectively orient the liquid crystal molecules. Note that the order in which the first electrode 10605 and the projection 10607 are formed may be reversed from that in FIG.

52A1 and 52A2 are schematic diagrams of an OCB mode liquid crystal display device. In the OCB mode, the alignment of liquid crystal molecules in the liquid crystal layer forms an optically compensated state, which is called bend alignment.

Similar to FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over a first substrate 10601 and a second substrate 10602, respectively. In addition, although not shown, a backlight and the like are arranged outside the layer 10604 including the second polarizer. The first electrode 10605, which is the electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least light-transmitting properties. Then, on the first substrate 10601 side, the layer 1 including the first polarizer
0603 are laminated, and a layer 10604 containing a second polarizer is arranged on the second substrate 10602 side. Note that the layer 10603 containing the first polarizer and the layer 10 containing the second polarizer
604 are arranged so as to form crossed Nicols.

In liquid crystal display devices having structures as shown in FIGS.
05 and the second electrode 10606 (longitudinal electric field method), FIG.
2 (A1), black display is performed. At this time, the liquid crystal molecules are aligned vertically. Then, light from the backlight cannot pass through the substrate, resulting in black display.

Then, as shown in FIG. 52A2, a first electrode 10605 and a second electrode 1060
When a constant OFF voltage is applied during 6, a white display is obtained. At this time, the liquid crystal molecules are in a state of bend alignment. As a result, light from the backlight passes through a pair of polarizer-containing layers (first polarizer-containing layer 10603 and second polarizer-containing layer 10604) arranged in crossed Nicols. and a predetermined image display is performed. Note that FIG.
A1) A liquid crystal display device having a structure like (A2) can perform full-color display by providing a color filter. A color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, FIG. 52 (A
1) The liquid crystal display device having the configuration (A2) can perform full-color display by field sequential driving without providing a color filter.

In the OCB mode as shown in FIGS. 52 (A1) and (A2), the alignment of the liquid crystal molecules in the liquid crystal layer can be optically compensated, so the viewing angle dependency is small. ratio can be increased.

52B1 and 52B2 are schematic diagrams of liquid crystals in the FLC mode and the AFLC mode.

Similar to FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over a first substrate 10601 and a second substrate 10602, respectively. The first electrode 10605, which is the electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least light-transmitting properties. A layer 10603 containing a first polarizer is provided on the first substrate 10601 side.
are stacked, and a layer 10604 containing a second polarizer is arranged on the second substrate 10602 side. Note that the layer 10603 containing the first polarizer and the layer 10604 containing the second polarizer are arranged so as to form crossed Nicols.

In liquid crystal display devices having structures as shown in FIGS.
05 and the second electrode 10606 (referred to as a vertical electric field method), the voltage shown in FIG.
As shown in 1), white display is obtained. At this time, the liquid crystal molecules are arranged side by side in a direction deviated from the rubbing direction. Thus, light from the backlight passes through a pair of polarizer-containing layers (first polarizer-containing layer 10603 and second polarizer-containing layer 10604) arranged in crossed Nicols. A predetermined video display is performed.

Then, as shown in FIG. 52B2, a first electrode 10605 and a second electrode 1060
When no voltage is applied between 6, black display is performed. At this time, the liquid crystal molecules are arranged horizontally along the rubbing direction. Then, the light from the backlight cannot pass through the substrate, resulting in black display.

Note that the liquid crystal display devices having the structures shown in FIGS. 52B1 and 52B2 can perform full-color display by providing color filters. A color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display devices having the structures shown in FIGS. 52B1 and 52B2 can perform full color display by field sequential driving without providing color filters.

A known liquid crystal material may be used for the FLC mode and AFLC mode.

53A1 and 53A2 are schematic diagrams of IPS mode liquid crystal display devices. The IPS mode is a mode in which the liquid crystal molecules are always rotated within a plane with respect to the substrate, and employs a lateral electric field method in which electrodes are provided only on one substrate side.

The IPS mode is characterized in that the liquid crystal is controlled by a pair of electrodes provided on one substrate. Therefore, a pair of electrodes 10801 and 10802 are provided on the second substrate 10602 . Each pair of electrodes 10801 and 10802 may have a light shielding property. A layer 10603 containing a first polarizer is laminated on the first substrate 10601 side, and a layer 10604 containing a second polarizer is arranged on the second substrate 10602 side. Note that the layer 10603 containing the first polarizer and the layer 10604 containing the second polarizer may be arranged so as to form crossed Nicols.

In a liquid crystal display device having a structure as shown in FIGS.
When a voltage is applied to 801 and 10802, the liquid crystal molecules are oriented along the electric lines of force deviated from the rubbing direction as shown in FIG. Light from the backlight then passes through a pair of polarizer-containing layers (first polarizer-containing layer 10603 and second polarizer-containing layer 10604) arranged in crossed Nicols. A predetermined video display is performed.

Note that the liquid crystal display devices having the structures shown in FIGS. 53A1 and 53A2 can perform full-color display by providing color filters. A color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display devices having the structures shown in FIGS. 53A1 and 53A2 can perform full color display by field sequential driving without providing color filters.

Then, as shown in FIG. 53A2, when no voltage is applied between the pair of electrodes 10801 and 10802, black display, that is, an off state is performed. At this time, the liquid crystal molecules are arranged horizontally along the rubbing direction. As a result, light from the backlight cannot pass through the substrate, resulting in black display.

An example of paired electrodes 10801, 10802 that can be used in IPS mode is shown in FIG. In FIGS. 55A to 55D, the electrode 10801 is an electrode 10801a and the electrode 10801a.
801b, corresponding to electrode 10801c and electrode 10801d. Moreover, the electrode 10802
correspond to electrodes 10802a, 10802b, 10802c and 10802d. 55A, the electrodes 10801a and 10802a have an undulating wave shape; in FIG. 55B, the electrodes 10801b and 10802b have concentric openings; Then, the electrode 10801c and the electrode 10802c
55(D), the electrode 10801d and the electrode 10802d have a comb-like shape and are meshed with each other.

FFS mode can also be used in addition to IPS mode. In the IPS mode, a pair of electrodes are formed on the same insulating film, whereas in the FFS mode, the electrodes shown in FIGS.
2), the paired electrodes 10803 and 10804 may be formed on insulating films of different layers.

In the liquid crystal display device having the structure shown in FIGS. 53B1 and 53B2, when a voltage is applied to the pair of electrodes 10803 and 10804, white display is performed as shown in FIG. 53B1. It turns on. Light from the backlight then passes through a pair of polarizer-containing layers (first polarizer-containing layer 10603 and second polarizer-containing layer 10604) arranged in crossed Nicols. A predetermined video display is performed.

Note that the liquid crystal display devices having the structures shown in FIGS. 53B1 and 53B2 can perform full-color display by providing color filters. A color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display devices having the structures shown in FIGS. 53B1 and 53B2 can perform full color display by field sequential driving without providing color filters.

Then, as shown in FIG. 53B2, when no voltage is applied between the pair of electrodes 10803 and 10804, black display, that is, an off state is performed. At this time, the liquid crystal molecules are aligned horizontally and rotated within the plane. As a result, light from the backlight cannot pass through the substrate, resulting in black display.

An example of paired electrodes 10803, 10804 that can be used in FFS mode is shown in FIG. In FIGS. 56A to 56D, the electrode 10803 is an electrode 10803a and the electrode 10803a.
803b, corresponding to electrode 10803c and electrode 10803d. Moreover, the electrode 10804
correspond to electrodes 10804a, 10804b, 10804c and 10804d. In FIG. 56A, the electrode 10803a has a bent dogleg shape, and the electrode 1080
4a may not be patterned within the pixel area. In FIG. 56(B), the electrode 108
03b has a concentric shape, and the electrode 10804b may not be patterned within the pixel region. In FIG. 56C, the electrode 10803c has a comb-like shape in which the electrodes are engaged with each other, and the electrode 10804c may not be patterned in the pixel region.
In FIG. 56D, the electrode 10803d has a comb-like shape, and the electrode 10804d may not be patterned within the pixel region.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
It may have translucency. By having light-transmitting properties, a transmissive display device with a high aperture ratio can be obtained.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
It may have light shielding or reflecting properties. A reflective display device that does not require a backlight and consumes low power can be obtained by having a light-shielding property or a reflective property.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
It may have both a light-transmitting region and a light-blocking or reflective region. By having both areas, transmissive display with high display quality is performed in a dark environment such as indoors, and reflective display with low power consumption is performed without a backlight in bright environments such as outdoors. , a transflective display device can be obtained.

A known liquid crystal material may be used for the IPS mode and the FFS mode.

As a liquid crystal mode applicable to the liquid crystal display device of the present embodiment, in addition to the liquid crystal mode described above, ASM (Axially Symmetrically Aligned Microscope) is also available.
cell) mode, PDLC (Polymer Dispersed Liquid C
rystal) mode.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 9)
In this embodiment, a display panel configuration and a peripheral configuration of a display device that can implement this embodiment will be described. In particular, the configuration of the display panel (also referred to as liquid crystal panel) of the liquid crystal display device and the peripheral configuration will be described.

First, a simple configuration of the liquid crystal panel will be described with reference to FIG. 57(A). In addition, Fig. 5
7A is a top view of the liquid crystal panel.

In the liquid crystal panel shown in FIG. 57A, a pixel portion 20101, scanning line input terminals 20103, and signal line input terminals 20104 are formed over a substrate 20100. In FIG. Scan line input terminal 201
03 are formed on the substrate 20100 extending in the row direction, and signal line input terminals 201 are formed on the substrate 20100.
Signal lines are formed on the substrate 20100 extending from 04 in the column direction. Also, the pixel unit 2
In 0101, pixels 20102 are arranged in a matrix at the intersections of scanning lines and signal lines. A switching element and a pixel electrode layer are arranged in the pixel 20102 .

As shown in the liquid crystal panel of FIG. 57A, the scanning line input terminal 20103
are formed on both sides in the row direction. The signal line input terminals 20104 are formed on one side of the substrate 20100 in the column direction. Scanning lines extending from one scanning line input terminal 20103 and scanning lines extending from the other scanning line input terminal 20103 are alternately formed.

In each pixel 20102 of the pixel portion 20101, the first terminal of the switching element is connected to the signal line, and the second terminal is connected to the pixel electrode layer.
02 can be independently controlled by a signal input from the outside. The on/off of the switching element is controlled by a signal supplied to the scanning line.

By arranging the scanning line input terminals 20103 in both of the row directions of the substrate 20100, the pixels 20102 can be arranged at high density. Also, the signal line side input terminal 20103
is arranged in one of the column directions of the substrate 20100 to reduce the frame of the liquid crystal panel,
The area of the pixel portion 20101 can be increased.

Note that as the substrate 20100, as already described, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate including stainless steel foil, or the like can be used. can be used.

As already described, the switching element can be a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, etc.), a thyristor, or a logic circuit combining them. .

Note that when a TFT is used as the switching element, the gate of the TFT is connected to the scanning line, the first terminal is connected to the signal line, and the second terminal is connected to the pixel electrode layer. can be independently controlled by signals input from the outside.

Note that the scanning line input terminals 20103 may be arranged on one side of the substrate 20100 in the row direction. By arranging the scanning line input terminal 20103 on one side of the substrate 20100 in the row direction, the frame of the liquid crystal panel can be reduced and the area of the pixel portion 20101 can be increased.

Note that a scanning line extending from one scanning line input terminal 20103 and the other scanning line input terminal 20103
The scanning line extending from 0103 may be shared.

Note that the scanning line input terminals 20103 may be arranged in both of the column directions of the substrate 20100 . By arranging the scanning line input terminals 20103 in both of the column directions of the substrate 20100, the pixels 20102 can be arranged at high density.

Note that a capacitor may be further formed in the pixel 20102 . A capacitor line may be formed over the substrate 20100 when a capacitor is provided in the pixel 20102 . When the capacitor line is formed over the substrate 20100, the first electrode of the capacitor is connected to the capacitor line and the second terminal is connected to the pixel electrode layer. Further, when the capacitor line is not formed over the substrate 20100, the first electrode of the capacitor is connected to a scanning line different from the pixel 20102 in which this capacitor is arranged, and the second terminal is connected to the pixel electrode layer. make sure you are

Here, the liquid crystal panel shown in FIG. 57A has a configuration in which signals supplied to scanning lines and signal lines are controlled by an external driving circuit. COG(
The driver IC 20201 may be mounted on the substrate 20100 by a Chip on Glass method. As another configuration, as shown in FIG.
Driver IC 20201 is connected to FPC 2 by Automated Bonding) method.
0200 (Flexible Printed Circuit).
Also, in FIG. 58, the driver IC 20201 is connected to the FPC 20200 .

The driver IC 20201 may be formed on a single crystal semiconductor substrate, or may be formed by forming a circuit with TFTs on a glass substrate.

Note that in the liquid crystal panel shown in FIG. 57A, the scanning line driver circuit 20105 may be formed over the substrate 20100 as shown in FIG. 57B. Alternatively, the scanning line driver circuit 20105 and the signal line driver circuit 20106 may be formed over the substrate 20100 as shown in FIG.

Note that the scanning line driver circuit 20105 and the scanning line driver circuit 20105 are composed of a large number of N-channel transistors and a large number of P-channel transistors. However, it may be composed only of a large number of N-channel type transistors, or may be composed only of a large number of P-channel type transistors.

Next, the details of the pixel 20102 will be described with reference to the circuit diagrams of FIGS. 59 and 60. FIG.

A pixel 20102 in FIG. 59A includes a transistor 20301 , a liquid crystal element 20302 , and a capacitor 20303 . A gate of the transistor 20301 is connected to the wiring 20305 and a first terminal is connected to the wiring 20304 . A first electrode of the liquid crystal element 20302 is connected to the counter electrode 20307 and a second electrode is connected to the second terminal of the transistor 20301 . A first electrode of the capacitor 20303 is connected to the capacitor line 20306 and a second electrode is connected to the second terminal of the transistor 20301 .

Note that the wiring 20304 is a signal line, the wiring 20305 is a scanning line, and the capacitor line 2030
6 is a capacitance line. Further, the transistor 20301 is a switching transistor and may be either a P-channel transistor or an N-channel transistor. Moreover, the liquid crystal element 2
0302 is a TN (Twisted Nematic) mode as an operation mode, IPS
(In-Plane-Switching) mode, FFS (Fringe Field
Switching) mode, MVA (Multi-domain Vertical)
alignment) mode, PVA (Patterned Vertical Al
signal), ASM (Axially Symmetrically aligned M
micro-cell) mode, OCB (Optical Compensated Bi
reference) mode, FLC (Ferroelectric Liquid
Crystal) mode, AFLC (Anti-Ferroelectric Liquid
id Crystal) or the like can be used.

A video signal and a scanning signal are input to the wirings 20304 and 20305, respectively. The video signal is an analog voltage signal, and the scanning signal is an H level or L level digital voltage signal. However, the video signal may be a current signal or a digital signal. Further, the H level and L level of the scanning signal may be potentials that can control on/off of the transistor 20301 .

A constant power supply voltage is supplied to the capacitance line 20306 . However, a pulsed signal may be supplied.

The operation of the pixel 20102 in FIG. 59A will be described. First, when the wiring 20305 becomes H level, the transistor 20301 is turned on, and a video signal is transmitted from the wiring 20304 to the second electrode of the liquid crystal element 20302 and the capacitor 2030 via the turned-on transistor 20301 .
3 second electrodes. Then, the capacitor 20303 holds the potential difference between the potential of the wiring 203076 and the potential of the video signal.

Next, when the wiring 20305 becomes L level, the transistor 20301 is turned off and the wiring 20305 is turned off.
304 is electrically cut off from the second electrode of the liquid crystal element 20302 and the second electrode of the capacitor 20303 . However, since the capacitor 20303 holds the potential difference between the potential of the wiring 203076 and the potential of the video signal, the potential of the second electrode of the capacitor 20303 can be maintained at the same potential as the video signal.

Thus, in the pixel 20102 in FIG. 59A, the potential of the second electrode of the liquid crystal element 20302 can be maintained at the same potential as the video signal, and the transmittance of the liquid crystal element 20302 can be maintained according to the video signal.

Note that although not shown, the capacitor element 20303 is not necessarily required if the liquid crystal element 20302 has a capacitance component that can hold a video signal.

Note that the first electrode of the liquid crystal element 20302 may be connected to the capacitor line 20306 as shown in FIG. 59B. For example, when the liquid crystal mode of the liquid crystal element 20302 is the FFS mode, the liquid crystal element 20302 has the structure shown in FIG.

Note that as shown in FIG. 60, the first electrode of the capacitor 20303 may be connected to the wiring 20305a in the previous row. Note that when the wiring 20305a is the n-th (n is a positive integer) scanning line, the wiring 20305b is the (n+1)-th scanning line. Similarly, transistor 20301a
, the pixel 20102a, and the capacitor 20303a are elements in the n-th row, the transistor 2
0301b, a pixel 20102b, and a capacitor element 20303b are elements on the (n+1)th row. By connecting the first electrode of the capacitor 20303b to the wiring 20305a in the front row in this way, wiring can be reduced. Thus, pixels 20102a and 20102 in FIG.
b can increase the aperture ratio.

Next, a more detailed configuration of the liquid crystal panel than the configuration of the liquid crystal panel described with reference to FIGS. 57 and 58 will be described with reference to FIG. Specifically, a TFT substrate, a counter substrate,
A configuration of a liquid crystal panel having a liquid crystal layer sandwiched between a counter substrate and a TFT substrate will be described. FIG. 61A is a top view of the liquid crystal panel. FIG. 61(B) corresponds to FIG. 61(
FIG. 2B is a cross-sectional view along the line CD of A). Note that FIG. 61B is a cross-sectional view of the case where a top-gate transistor is formed over the substrate 20100 using a crystalline semiconductor film (polysilicon film) as the semiconductor film.

In the liquid crystal panel shown in FIG. 61A, a pixel portion 20101, a scanning line driver circuit 20105a, a scanning line driver circuit 20105b, and a signal line driver circuit 20106 are formed over a substrate 20100. FIG. Pixel portion 20101, scanning line driver circuit 20105a, scanning line driver circuit 20105
b and the signal line driver circuit 20106 are sealed between the substrate 20100 and the counter substrate 20515 with a sealing material 20516 . In addition, by the TAB method, FPC2051
8 and an IC chip 20530 are arranged on the substrate 20100 .

A cross-sectional structure taken along line CD in FIG. 61A will be described with reference to FIG. 61B.
A pixel portion 20101 and its peripheral driving circuit portion (scanning line circuit 20105) are formed on a substrate 20100.
a, a scanning line driving circuit 20105b, and a signal line driving circuit 20106) are formed. ) are shown.

First, an insulating film 20501 is formed as a base film on a substrate 20100 . As the insulating film 20501, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Si
OxNy) or the like, or a laminated structure having at least two of these films may be used.

Note that a silicon oxide film is preferably used for a portion in contact with a semiconductor. As a result, trapping of electrons in the underlying film and hysteresis in transistor characteristics can be suppressed. Also,
It is desirable to arrange at least one film containing a large amount of nitrogen as the base film. Impurities from the glass can thereby be reduced.

Next, a semiconductor layer 20502 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like.

Next, an insulating layer 2 is formed over the insulating film 20501 and the semiconductor layer 20502 as a gate insulating film.
0503 is formed.

Note that as the insulating layer 20503, a single layer or a laminated structure of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used. semiconductor layer 20502
The insulating layer 20503 in contact with is preferably a silicon oxide film. This is because the trap levels at the interface with the semiconductor layer 20502 are reduced when the silicon oxide film is used. When the gate electrode is made of Mo, the gate insulating film in contact with the gate electrode is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo. Here the insulating layer 20503
, a silicon oxynitride film with a thickness of 115 nm (composition ratio Si=3
2%, O=59%, N=7%, H=2%).

Next, a conductive layer 20504 is formed as a gate electrode over the insulating layer 20503 by a photolithography method, an inkjet method, a printing method, or the like.

As the conductive layer 20504, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, A
g, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements. Alternatively, it may be composed of lamination of these elements or alloys of these elements. Here, Mo forms the gate electrode. Mo is suitable because it is easy to etch and is resistant to heat.

Note that the semiconductor layer 20502 is doped with an impurity element using the conductive layer 20504 or a resist as a mask to form a channel formation region and impurity regions serving as a source region and a drain region.

The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration.

Note that the conductive layer 20504 of the transistor 20521 has a dual-gate structure.
The transistor 20521 has a dual-gate structure so that the transistor 20521
off current can be reduced. Note that the dual gate structure is a structure having two gate electrodes. However, a plurality of gate electrodes may be provided over the channel region of the transistor.

Next, an insulating layer 20505 is formed as an interlayer film over the insulating layer 20503 and the conductive layer 20504 .
is formed.

Note that the insulating layer 20505 can be formed using an organic material, an inorganic material, or a layered structure thereof. For example silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, aluminum oxynitride or oxide with nitrogen content higher than oxygen content, diamond-like carbon (DLC), polysilazane, nitrogen-containing It can be made of a material selected from substances including carbon (CN), PSG (phosphorus glass), BPSG (phosphor boron glass), alumina, and other inorganic insulating materials. Also, an organic insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimideamide, resist, benzocyclobutene, siloxane resin, or the like can be used. . In addition, the siloxane resin is Si-
It corresponds to a resin containing O—Si bonds. Siloxane has a skeletal structure composed of bonds of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (eg, alkyl group, aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as substituents.

Note that contact holes are selectively formed in the insulating layer 20503 and the insulating layer 20505 . For example, a contact hole is formed on the upper surface of the impurity region of each transistor.

Next, a conductive film 20506 is formed as a drain electrode, a source electrode, and a wiring over the insulating layer 20505 by a photolithography method, an inkjet method, a printing method, or the like.

Note that the conductive film 20506 can be made of Ti, Mo, Ta, Cr, W, Al, N,
d, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements. Alternatively, a laminated structure of these elements or alloys of these elements can be used.

Note that the conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected to each other in the portions where the contact holes are formed in the insulating layer 20503 and the conductive layer 20504 .

Next, an insulating layer 20507 is formed as a planarizing film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505 .

Note that the insulating layer 20507 is preferably formed using an organic material because it preferably has good flatness and coverage. Note that the insulating layer 20507 may have a multilayer structure, and an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, or silicon oxynitride).

Contact holes are selectively formed in the insulating layer 20507 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 .

Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like.

Note that a transparent electrode that transmits light and a reflective electrode that reflects light can be used as the conductive layer 20508 .

In the case of a transparent electrode, for example, indium tin oxide (indium tin oxide mixed with tin oxide)
ITO) film, indium tin silicon oxide (ITSO) film in which silicon oxide is mixed with indium tin oxide (ITO), indium zinc oxide (IZO) film in which zinc oxide is mixed with indium oxide
) film, zinc oxide film, tin oxide film, or the like can be used. IZO stands for I
The transparent conductive material is formed by sputtering using a target in which 2 to 20 wt % of zinc oxide (ZnO) is mixed with TO, but is not limited to this.

In the case of a reflective electrode, for example, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, A
U, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys thereof can be used. In addition, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, Al is Ti,
A three-layer laminated structure sandwiched by metals such as Mo, Ta, Cr, and W may be employed.

Next, over the insulating layer 20507 and the conductive layer 20508 formed over the insulating layer 20507,
An insulating layer 20509 is formed as an alignment film.

Next, a sealing material 20516 is formed by an inkjet method or the like on the periphery of the pixel portion 20101, or the periphery of the pixel portion 20101 and the periphery of the peripheral driver circuit portion.

Next, a counter substrate 20515 on which an insulating film 20514, an insulating film 20513, a conductive film 20512, an insulating film 20511, and the like are formed, and a substrate 20100 are attached to each other with spacers 20531 interposed therebetween, and a liquid crystal layer 20510 is formed in the gap between them. are placed.

Note that the substrate 20115 may function as a counter substrate. Also, the insulating film 20514 is
It may function as a black matrix (light shielding film). Further, the insulating film 20513 may function as a color filter. The spacers 20531 may be provided by scattering particles of several μm, or may be formed by forming a resin film over the entire surface of the substrate and then etching the resin film. Further, the conductive film 20512 may function as a counter electrode. As the conductive film 20512, the same material as the conductive layer 20508 can be used.
Also, the insulating film 20511 may function as an alignment film.

Note that an insulating film 20532 may be formed as a planarizing film between the insulating films 20513 and 20514 and the conductive film 20512 . However, the insulating film 20532 is not illustrated in FIG.

Note that a known liquid crystal can be freely used as the liquid crystal layer 20510 . For example, ferroelectric liquid crystal or antiferroelectric liquid crystal may be used as the liquid crystal layer 20510 . Liquid crystal driving methods include TN (Twisted Nematic) mode, IPS (
In-Plane-Switching) mode, FFS (Fringe Field)
Switching) mode, MVA (Multi-domain Vertical)
alignment) mode, PVA (Patterned Vertical Ali
gnment), ASM (Axially Symmetrically aligned Mi
cro-cell) mode, OCB (Optical Compensated Bir
efringence) mode, FLC (Ferroelectric Liquid
Crystal) mode, AFLC (Anti-Ferroelectric Liqui
d Crystal) and the like can be freely used.

Next, a pixel portion 20101 and a conductive film 205 electrically connected to the peripheral driver circuit portion are formed.
33, an FPC 20200 is arranged with an anisotropic conductor layer 20517 interposed therebetween. An IC chip is arranged on the FPC 20200 with an anisotropic conductive layer 20517 interposed therebetween. That is, the FPC 20200, the conductive film 20533 and the IC chip 20530 are electrically connected.

Note that the conductive film 20533 has a function of transmitting signals and potentials input from the FPC 20200 to pixels and peripheral circuits. As the conductive film 20533, the same material as the conductive film 20506, the same material as the conductive layer 20504, or the same material as the impurity region of the semiconductor layer 20502 may be used. , or a combination of at least two layers of these may be used.

Note that the IC chip 20530 can effectively utilize the substrate area by forming functional circuits (memory and buffer).

The liquid crystal panel in FIGS. 61A and 61B includes a scanning line driving circuit 20105a and a scanning line driving circuit 20105a.
0105b and the signal line driver circuit 20106 are formed on the substrate 20100. As shown in the liquid crystal panel of FIG. Then, it may be configured to be mounted on a liquid crystal panel by the COG method or the like. By forming the signal line driver circuit 20106 in the driver IC 20601, power consumption can be reduced. By using a semiconductor chip such as a silicon wafer as the driver IC 20601, the liquid crystal panel in FIG. 62A can achieve higher speed and lower power consumption.

Similarly, as shown in the liquid crystal panel of FIG. 62B, driving circuits corresponding to the scanning line driving circuit 20105a, the scanning line driving circuit 20105b, and the signal line driving circuit 20106 are replaced with the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively. It may be formed and mounted on the liquid crystal panel by the COG method or the like. Further, by forming driver circuits corresponding to the scanning line driver circuit 20105a, the scanning line driver circuit 20105b, and the signal line driver circuit 20106 in the driver ICs 20602a, 20602b, and 20601, respectively, cost reduction can be achieved.

Although the transistor 20521 has a dual gate structure, the pixel region 205 in FIG.
As shown in 26, transistor 20521 may be a single gate structure. However, FIG. 63 shows only the pixel area 20526. FIG.

Next, a cross-sectional view when a bottom-gate transistor is formed over the substrate 20100 will be described with reference to FIG. However, FIG. 64 shows only the pixel area 20526. FIG.

First, an insulating film 20501 is formed as a base film on a substrate 20100 . next,
A conductive layer 20504 is formed as a gate electrode over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Note that the transistor 2052
The conductive layer 20504 of 1 has a dual gate structure. This is because, as already mentioned, the transistor 20521 has a dual-gate structure so that the transistor 2052
1 can be reduced. Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504 . Next, on the insulating layer 20503,
A semiconductor layer 20502 is formed by a photolithography method, an inkjet method, a printing method, or the like. In addition, the semiconductor layer 20502 is formed by using a resist as a mask.
The region 502 is doped with an impurity element to form a channel forming region and impurity regions that will be a source region and a drain region. The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration. Next, an insulating layer 20505 is formed as an interlayer film over the insulating layer 20503 and the semiconductor layer 20502 . Contact holes are selectively formed in the insulating layer 20505 . For example, a contact hole is formed on the upper surface of the impurity region of each transistor. Next, insulating layer 2050
5, a conductive film 20506 is formed as a drain electrode, a source electrode, and wiring by a photolithography method, an inkjet method, a printing method, or the like. Note that the insulating layer 205
In the portion where the contact hole 05 is formed, the conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected. Next, an insulating layer 20507 is formed as a planarizing film over the insulating layer 20505 and the conductive film 20506 . Contact holes are selectively formed in the insulating layer 20507 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 . Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508 . Next, the insulating film 20
514, an insulating film 20513, a conductive film 20512, an insulating film 20511, and the like are formed, and a liquid crystal layer 20510 is arranged in a gap between the substrate 20100 and a counter substrate 20515 formed thereon.

Note that the transistor 20521 has a dual-gate structure in FIG. however,
As shown in the pixel region 20526 of FIG. 65, the transistor 20521 may have a single gate structure.

Next, a cross-sectional view when a double-gate transistor is formed over the substrate 20100 will be described with reference to FIG. However, FIG. 66 shows only the pixel area 20526. FIG.

Note that a double-gate transistor has a structure in which gate electrodes are arranged above and below a semiconductor film. Further, a double-gate transistor has twice as much current as a top-gate transistor and a bottom-gate transistor if the same size and the same applied voltage are applied. In other words, a double-gate transistor can pass more current with a smaller transistor size.

First, an insulating film 20501 is formed as a base film on a substrate 20100 . next,
A conductive layer 20504a is formed as a first gate electrode over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 205
For 04a, a material and structure similar to those of the conductive layer 20504 can be used. next,
An insulating layer 2 is formed as a first gate insulating film over the insulating film 20501 and the conductive layer 20504a.
0503a is formed. Note that the insulating layer 20503a can have the same material and structure as those of the insulating layer 20503 . Next, a semiconductor layer 20502 is formed over the insulating layer 20503a by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20503b is formed on the insulating layer 20503a and the semiconductor layer 20502 as a second gate insulating film. Note that the insulating layer 20503b is
Materials and structures similar to those of 503 can be used. Next, a conductive layer 20504b is formed as a second gate electrode over the insulating layer 20503b by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 20504b is the conductive layer 2
Materials and structures similar to those of 0504 can be used. Note that the semiconductor layer 20502
, the semiconductor layer 20502 is doped with an impurity element using the conductive layer 20504b or a resist as a mask to form a channel formation region and impurity regions that serve as a source region and a drain region. The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration. Note that the insulating layer 20503 is formed on the semiconductor layer 20502 .
b and the conductive layer 20504b, the semiconductor layer 2050 is formed using a resist as a mask.
2 may be doped with an impurity element to form a channel formation region and impurity regions that will be a source region and a drain region. Next, on the insulating layer 20503b and the conductive layer 20
An insulating layer 20505 is formed as an interlayer film on 504b. Note that the insulating layer 205
03b and the insulating layer 20505 are selectively formed with contact holes. For example, a contact hole is formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed as a drain electrode, a source electrode, and a wiring over the insulating layer 20505 by a photolithography method, an inkjet method, a printing method, or the like. In addition,
In the portions of the insulating layers 20503 and 20505 where contact holes are formed,
The conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected. Next, over the insulating layer 20505 and the conductive film 20506, the insulating layer 205 is formed as a planarization film.
07 is formed. Contact holes are selectively formed in the insulating layer 20507 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 . Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508 . Next, a liquid crystal layer 20510 is arranged in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

61 and FIGS. 63 to 66, cross-sectional views in which the insulating layer 20507 is formed as a flat film on the insulating layer 20505 and the conductive film 20506 formed on the insulating layer 20505 are described. . However, the insulating layer 20507 is not necessarily required as shown in FIG.

Note that the cross-sectional view in FIG. 67 shows the case of a top-gate transistor, but the same applies to a bottom-gate transistor and a double-gate transistor.

Next, an amorphous semiconductor film (amorphous silicon film) is formed as a semiconductor film over the substrate 20100 .
A cross-sectional view in the case of forming a transistor using , will be described with reference to FIG. The cross-sectional view shown in FIG. 68 is a cross-sectional view of an inverted staggered channel-etched transistor.

First, an insulating film 20501 is formed as a base film on a substrate 20100 . next,
A conductive layer 20504 is formed as a gate electrode over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504 . Next, a semiconductor layer 20502 is formed over the insulating layer 20503 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502 includes a first semiconductor film and a second semiconductor film, and the second semiconductor film is formed over the first semiconductor film. Alternatively, the first semiconductor film and the second semiconductor film may be continuously formed and patterned by photolithography at the same time. Also, the second semiconductor film contains an impurity element. Next, a conductive film 20506 is formed over the insulating layer 20503 and the semiconductor layer 20502 by a photolithography method, an inkjet method, a printing method, or the like. In addition,
The semiconductor layer 20502 is etched using the conductive film 20506 as a mask, so that a channel formation region and impurity regions that serve as source and drain regions are formed. That is, the second semiconductor film containing the impurity element is removed from the channel region. However, the semiconductor layer 20502 may be etched using a resist for etching the conductive film 20506 as a mask. Next, an insulating layer 20507 is formed as a planarizing film over the insulating layer 20503 , the semiconductor layer 20502 and the conductive film 20506 . Contact holes are selectively formed in the insulating layer 20507 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 . Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508 . Next, insulating film 2
0514, an insulating film 20513, a conductive film 20512, an insulating film 20511, and the like are formed, and a liquid crystal layer 20510 is arranged in a gap between the substrate 20100 and a counter substrate 20515 formed thereon.

Although the channel-etched transistor has been described, an insulating film 21301 may be provided on the semiconductor layer 20502 as shown in FIG. An insulating film 21301 is formed between the first semiconductor film and the second semiconductor film. In addition, the semiconductor layer 20502 is the conductive film 20
When forming 506, it is etched at the same time.

Note that the transistor 20521 in FIG. 68 is called a channel-etch structure, and the transistor 20521 in FIG. 69 is called a channel protection structure.

Next, a cross-sectional view in the case of forming a top-gate transistor using an amorphous semiconductor film as a semiconductor film over the substrate 20100 will be described with reference to FIG.

First, an insulating film 20501 is formed as a base film on a substrate 20100 . next,
A conductive film 20506 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Next, a semiconductor layer 20502a is formed over the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like. Note that for the semiconductor layer 20502a, a material and a structure similar to those of the semiconductor layer 20502 can be used. In addition, the semiconductor layer 20502a contains an impurity element. Next, a semiconductor layer 20502b is formed over the insulating film 20501 and the semiconductor layer 20502a by a photolithography method, an inkjet method, a printing method, or the like. In addition, the semiconductor layer 2
A material and structure similar to those of the semiconductor layer 20502 can be used for 0502b.
Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501, the semiconductor layer 20502b, and the conductive film 20506. FIG. Next, a conductive layer 20504 is formed as a gate electrode over the insulating layer 20503 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20503 and the conductive layer 20504 formed over the insulating layer 20503 . Contact holes are selectively formed in the insulating layer 20507 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 . Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508 . Next, a liquid crystal layer 20510 is arranged in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

69 and 70, cross-sectional views in which the insulating layer 20507 is formed as a flat film on the insulating layer 20505 and the conductive film 20506 formed on the insulating layer 20505 have been described. However, the insulating layer 20507 is not necessarily required as shown in FIG.

Note that the cross-sectional view of FIG. 71 shows the case of a transistor with an inverted staggered channel-etch structure, but the same applies to the case of a transistor with an inverted staggered channel protection structure. FIG. 71 shows the case of an inverted staggered transistor.
A top gate type transistor may be used. 72 and 73 are cross-sectional views in the case of a top-gate type transistor.

In the case of the cross-sectional view shown in FIG. 72, a conductive layer 2 is formed as a pixel electrode on the insulating film 20501 and the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like.
0508 is formed. Further, the conductive layer 20508 is formed after forming the conductive film 20506 and before forming the insulating layer 20503 .

Note that in the case of the cross-sectional view shown in FIG. 73, a conductive layer 20508 is formed as a pixel electrode over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Also, the conductive layer 20508 is formed after the insulating film 20501 is formed.

Next, a cross-sectional view of a transflective liquid crystal panel will be described with reference to FIG.

Note that the cross-sectional view of FIG. 74 is a cross-sectional view of a liquid crystal panel in which a transistor uses a polycrystalline semiconductor as a semiconductor film. However, the transistor may be of bottom-gate type or double-gate type. Further, the gate electrode of the transistor may have a single gate structure,
A dual gate structure may be used.

Note that FIG. 74 is the same as FIG. 63 until the conductive film 20506 is formed. Therefore, the process and structure after the conductive film 20506 is formed will be described.

First, a photolithography method, an inkjet method, a printing method, or the like is formed on the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505 as a film for reducing the thickness of the liquid crystal layer 20510 (so-called cell gap). Thus, an insulating film 21801 is formed. Note that the insulating film 21801 is preferably formed using an organic material because it preferably has good flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, or silicon oxynitride) to form a multilayer structure. Contact holes are selectively formed in the insulating film 21801 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 . Next, a conductive layer 20508a is formed as a first pixel electrode over the insulating layers 20505 and 20507 by a photolithography method, an inkjet method, a printing method, or the like. As the conductive layer 20508a, a transparent electrode that transmits light, like the conductive layer 20508, can be used. Next, a conductive layer 20508b is formed as a second pixel electrode over the conductive layer 20508a by a photolithography method, an inkjet method, a printing method, or the like. As the conductive layer 20508b, a reflective electrode that reflects light like the conductive layer 20508 can be used. Note that a region where the conductive layer 20508b is formed is called a reflective region. Further, in the region where the conductive layer 20508a is formed, a region where the conductive layer 20508b is not formed over the conductive layer 20508a is called a transmissive region. Next, an insulating layer 20509 is formed as an alignment film over the insulating film 21801 and the conductive layers 20508a and 20508b. Next, a liquid crystal layer 20510 is arranged in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

In FIG. 74, the conductive layer 20508b is formed after the conductive layer 20508a is formed, but as shown in FIG.
a may be formed.

74 and 75, insulating films for adjusting the liquid crystal layer 20510 (cell gap) are formed under the conductive layers 20508a and 20508b. but,
An insulating film 22001 may be formed on the opposing substrate 20515 side as shown in FIG. The insulating film 22001, like the insulating film 21801, is an insulating film for adjusting the liquid crystal layer 20510 (cell gap).

In FIG. 76, the case where the insulating layer 20507 is formed as the planarization film has been described, but as shown in FIG. 77, the insulating layer 20507 may not be formed. In the case of FIG. 77, a conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that the insulating film 22001 may be formed between the conductive film 20512 and the insulating film 20511 or may be formed between the insulating film 20511 and the liquid crystal layer 20510 .

Next, FIG. 78 shows a cross-sectional view of a transflective liquid crystal panel in which a polycrystalline semiconductor is used as a semiconductor film of a transistor.

Note that the cross-sectional view of FIG. 78 is a cross-sectional view of a liquid crystal panel having a transistor using an inverted staggered channel-etch structure. However, the transistor may be of a top-gate type or may use an inverted staggered channel protection structure.

Note that FIG. 78 is the same as FIG. 78 until the conductive film 20506 is formed. Therefore, the process and structure after the conductive film 20506 is formed will be described.

First, a liquid crystal layer 20 is formed on the semiconductor layer 20502, the insulating layer 20503, and the conductive film 20506.
As a layer for reducing the thickness of 510 (so-called cell gap), an insulating film 22201 is formed by a photolithography method, an inkjet method, a printing method, or the like. Note that the insulating film 22201 is preferably formed using an organic material because the insulating film 22201 preferably has good flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, or silicon oxynitride) to form a multilayer structure. Note that the insulating film 22
Contact holes are selectively formed in 201 . For example, a contact hole is formed on the top surface of the drain electrode of transistor 20521 . Next, insulating layer 205
03 and the insulating film 22201, a conductive layer 20508a is formed as a first pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, a conductive layer 20508b is formed as a second pixel electrode over the conductive layer 20508a by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 20508
A region where b is formed is called a reflective region. Further, in the region where the conductive layer 20508a is formed, a region where the conductive layer 20508b is not formed over the conductive layer 20508a is called a transmissive region. Next, over the insulating film 22201, the conductive layer 20508a, and the conductive layer 20508b,
An insulating layer 20509 is formed as an alignment film. Next, insulating film 20514, insulating film 2
0513, a counter substrate 20515 on which a conductive film 20512, an insulating film 20511, and the like are formed
and the substrate 20100, a liquid crystal layer 20510 is arranged.

In FIG. 78, the conductive layer 20508b is formed after the conductive layer 20508a is formed, but as shown in FIG.
a may be formed.

78 and 79, insulating films for adjusting the liquid crystal layer 20510 (cell gap) are formed under the conductive layers 20508a and 20508b. but,
An insulating film 22001 may be formed on the counter substrate 20515 side as shown in FIG. The insulating film 22001 is, like the insulating film 22201, an insulating film for adjusting the liquid crystal layer 20510 (cell gap).

79 and 80, the case where the insulating layer 20507 is formed as the planarization film has been described, but as shown in FIG. 81, the insulating layer 20507 may not be formed. In the case of FIG. 81, a conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

61 and 63 to 81, a pair of electrodes (
An example in which the conductive layer 20508 and the conductive film 20512) are formed on different substrates is shown. However, the conductive film 20512 may be provided over the substrate 20100 . Thus, an IPS (In-Plane-Switching) mode can be used as a liquid crystal driving method. Further, depending on the liquid crystal layer 20510, one or both of the two alignment films (insulating layer 20509 and insulating film 20511) can be omitted.

61 and 63 to 81, the conductive layer 20508 (conductive layer 20508b) is formed as the reflective pixel electrode, and the shape of the conductive layer 20508 is preferably uneven. This is because the reflective pixel electrode reflects external light for display. This is because external light entering the reflective electrode can be diffusely reflected by the reflective electrode in order to efficiently utilize the external light and increase the display luminance. Note that the film under the conductive layer 20508 (the insulating layer 20
505, the insulating layer 20507, the insulating film 21801, or the insulating film 22201) is made uneven, so that the shape of the conductive layer 20508 becomes uneven.

Next, a liquid crystal display device having the liquid crystal panel described with reference to FIGS. 61 to 81 will be described with reference to FIG.

First, the liquid crystal display device shown in FIG. 82 is provided with a backlight unit 22601, a liquid crystal panel 22607, a layer 22608 containing a first polarizer, and a layer 22609 containing a second polarizer.

Note that the liquid crystal panel 22607 can be the same as that described in this embodiment. Further, although the liquid crystal panel of this embodiment has been described as having an active structure in which a switching element is provided in each pixel, the liquid crystal panel of FIG. 82 may have a passive structure.

The structure of the backlight unit 22601 will be described. backlight unit 226
01 is a diffuser plate 22602, a light guide plate 22603, a reflector plate 22604, and a lamp reflector 2.
2605 is configured to have a light source 22606 . A cold-cathode tube, a hot-cathode tube, a light-emitting diode, an inorganic EL, an organic EL, or the like is used as the light source 22606 .
6 has a function of emitting light as required. The lamp reflector 22605 is the light source 2260
It has a function of efficiently guiding the fluorescence from 6 to the light guide plate 22603 . The light guide plate 22603 has a function of totally reflecting fluorescence and guiding light over the entire surface. The diffusion plate 22602 has a function of reducing brightness unevenness. The reflecting plate 22604 extends downward from the light guide plate 22603 (liquid crystal panel 2
2607) has a function of reflecting and reusing the leaked light.

By placing a prism sheet between the diffusion plate 22602 and the layer 22609 containing the second polarizer, the liquid crystal display device of this embodiment can improve the screen brightness of the liquid crystal panel.

A control circuit for adjusting the brightness of the light source 22606 is connected to the backlight unit 22601 . The brightness of the light source 22606 can be adjusted by signal feeding from the control circuit.

A layer 22609 containing a second polarizer is provided between the liquid crystal panel 22607 and the backlight unit 22601, and the liquid crystal panel 22609 in the direction opposite to the backlight unit 22601 is provided.
2607 is also provided with a layer 22608 containing a first polarizer.

Note that the layer 22608 containing the first polarizer and the layer 22609 containing the second polarizer are arranged so as to form crossed Nicols when the liquid crystal element of the liquid crystal panel 22607 is driven in the TN mode. Further, the layer 22608 containing the first polarizer and the layer 22609 containing the second polarizer are arranged so as to form crossed nicols when the liquid crystal element of the liquid crystal panel 22607 is driven in the VA mode. In addition, the layer 22608 containing the first polarizer and the layer 226 containing the second polarizer
09, when the liquid crystal elements of the liquid crystal panel 22607 are driven in the IPS mode and the FFS mode, they may be arranged in cross Nicols or in parallel Nicols.

A retardation plate may be provided between both or one of the layer 22608 containing the first polarizer and the layer 22609 containing the second polarizer and the liquid crystal panel 22607 .

Note that, as shown in FIG. 85, the layer 22609 including the second polarizer and the backlight unit 2
2601, a slit (lattice) 22610 is arranged, so that the liquid crystal display device of this embodiment can perform three-dimensional display.

A slit 22610 having an opening disposed on the backlight unit side passes light incident from a light source in a stripe pattern, and allows the light to enter the display device. This slit 2261
With 0, a parallax can be created for both eyes of the viewer on the viewing side, and the viewer will see only right-eye pixels with the right eye and only left-eye pixels with the left eye at the same time. Therefore, the viewer can see the three-dimensional display. In other words, the light given a specific viewing angle by the slit 22610 passes through the pixels corresponding to the right-eye image and the left-eye image, respectively.
An image for the right eye and an image for the left eye are separated at different viewing angles to perform three-dimensional display.

By using the liquid crystal display device in FIG. 85 to manufacture an electronic device such as a television set or a mobile phone, it is possible to provide a highly functional electronic device capable of three-dimensional display with high image quality.

Next, the detailed configuration of the backlight will be described with reference to FIG. A backlight is provided in a liquid crystal display device as a backlight unit having a light source, and the backlight unit efficiently scatters light, so that the light source is surrounded by a reflector.

As shown in FIG. 84(A), the backlight unit 22852 uses the cold cathode tubes 2 as a light source.
2801 can be used. In addition, a lamp reflector 22832 can be provided in order to efficiently reflect the light from the cold cathode tube 22801 . The cold cathode tube 22801 is often used for large display devices. This is due to the intensity of the brightness from the cold cathode tube. Therefore, backlight units having cold-cathode tubes can be used for displays of personal computers.

As shown in FIG. 84B, the backlight unit 22852 can use a light emitting diode 22802 (LED) as a light source. For example, light-emitting diodes 22802 (W) emitting white light are arranged at predetermined intervals. Also, the light emitting diode 22802 (W) 22
A lamp reflector 22832 may be provided to efficiently reflect light from 802 .

Further, as shown in FIG. 84(C), the backlight unit 22852 has each color R as a light source.
GB light emitting diodes 22803, 22804, 22805 can be used. By using the light-emitting diodes 22803, 22804, and 22805 of each color RGB, it is possible to improve the color reproducibility as compared with only the light-emitting diode 22802 (W) emitting white light. In order to efficiently reflect the light from the light emitting diode, the lamp reflector 22
832 can be provided.

Furthermore, as shown in FIG. 84(D), light emitting diodes 2280 of each color RGB are used as light sources.
3, 22804 and 22805 need not be the same in number or arrangement.
For example, a plurality of colors with low emission intensity (for example, green) may be arranged.

Furthermore, a light-emitting diode 22802 emitting white light and light-emitting diodes 2280 of each color RGB
3, 22804, and 22805 may be used in combination.

In the case of having RGB light-emitting diodes, if a field sequential mode is applied, color display can be performed by sequentially lighting the RGB light-emitting diodes according to time.

The use of light-emitting diodes is suitable for large display devices because of their high brightness. In addition, since the color purity of each color of RGB is good, the color reproducibility is superior to that of a cold-cathode tube, and the layout area can be reduced.

Also, the light source does not necessarily need to be arranged as the backlight unit shown in FIG. For example, when mounting a backlight with light emitting diodes in a large display device, the light emitting diodes can be placed on the back surface of the substrate. At this time, the light-emitting diodes can be arranged at predetermined intervals, and the light-emitting diodes of each color can be arranged in order. Color reproducibility can be improved by arranging the light-emitting diodes.

Next, an example of a layer containing a polarizer (also referred to as a polarizing plate or a polarizing film) will be described with reference to FIGS.

A polarizing film 23000 in FIG. 86 includes a protective film 23001 and a substrate film 23002.
, a PVA polarizing film 23003 , a substrate film 23004 , an adhesive layer 23005 and a release film 23006 .

The PVA polarizing film 23003 has the function of producing light (linearly polarized light) only in a certain vibration direction. Specifically, the PVA polarizing film 23003 contains molecules (polarizers) in which electron densities are significantly different between vertical and horizontal directions. The PVA polarizing film 23003 can produce linearly polarized light by aligning the directions of the molecules whose electron densities differ greatly between vertical and horizontal directions.

As an example, the PVA polarizing film 23003 is made of polyvinyl alcohol (Poly V
Inyl Alcohol) polymer film is doped with an iodine compound, and the PVA film is pulled in a certain direction to obtain a film in which iodine molecules are aligned in a certain direction. Light parallel to the long axis of the iodine molecule is absorbed by the iodine molecule. For high durability and high heat resistance applications, a dichroic dye may be used instead of iodine. Dyes are preferably used in liquid crystal display devices such as in-vehicle LCDs and projector LCDs that require durability and heat resistance.

The PVA polarizing film 23003 has films (substrate films 23002) serving as base materials on both sides.
and substrate film 3604), the reliability can be increased. Also, the PVA polarizing film 23003 may be sandwiched between highly transparent and highly durable triacetylulose (TAC) films. Note that the substrate film and the TAC film function as a protective layer for the polarizer that the PVA polarizing film 23003 has.

On one of the substrate films (substrate film 23004), an adhesive layer 23005 is attached for attachment to the glass substrate of the liquid crystal panel. The adhesive layer 23005 is formed by applying an adhesive to the substrate film (substrate film 23004) on one side. Further, the adhesive layer 23005 is provided with a release film 23006 (separate film).

The other substrate film (substrate film 23002) is provided with a protective film.

A hard coat scattering layer (antiglare layer) may be provided on the surface of the polarizing film 23000 . The hard coat scattering layer has fine unevenness formed on the surface by AG treatment, and has an antiglare function that scatters external light, so it can prevent external light from reflecting on the liquid crystal panel and surface reflection.

In addition, a plurality of optical thin film layers having different refractive indices may be multilayered (also referred to as antireflection treatment or AR treatment) on the surface of the polarizing film 23000 . A plurality of optical thin film layers having different refractive indices can reduce the reflectance of the surface due to the interference effect of light.

Next, the operation of each circuit included in the liquid crystal display device will be described with reference to FIG.

FIG. 83 shows a system block diagram of the pixel portion 22705 and the driver circuit portion 22708 of the display device.

A pixel portion 22705 has a plurality of pixels, and includes a signal line 22712 and a scanning line 2222 which are each pixel.
A switching element is provided in the intersection region with 710 . The application of voltage for controlling the tilt of the liquid crystal molecules can be controlled by the switching element. Such a structure in which a switching element is provided in each intersection region is called an active type. The pixel portion of this embodiment is not limited to such an active type, and may have a passive type structure. The passive type has a simple process because each pixel does not have a switching element.

The driver circuit portion 22708 has a control circuit 22702 , a signal line driver circuit 22703 , and a scanning line driver circuit 22704 . A control circuit 22702 to which a video signal 22701 is input has a function of performing gradation control according to display content of the pixel portion 22705 . Therefore, the control circuit 2
A signal line driver circuit 22703 and a scanning line driver circuit 22704 receive the generated signals.
to enter. Then, when a switching element is selected via the scanning line 22710 based on the scanning line driving circuit 22704, a voltage is applied to the pixel electrode in the selected intersection area. The value of this voltage is determined based on the signal input from the signal line driver circuit 22703 through the signal line.

Furthermore, the control circuit 22702 generates a signal for controlling the power supplied to the lighting means 22706 , and the signal is input to the power source 22707 of the lighting means 22706 . The backlight unit described in the above embodiment can be used as the lighting means. In addition to the backlight, there is also a front light as a lighting means. A front light is a plate-like light unit that is attached to the front side of the pixel portion and that is composed of a light emitter and a light guide that illuminate the entire area. Such a lighting means can evenly illuminate the pixel portion with low power consumption.

As shown in FIG. 83B, the scanning line driver circuit 22704 has circuits functioning as a shift register 22741, a level shifter 22742, and a buffer 22743. FIG. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 22741 . Note that the scanning line driver circuit of this embodiment is not limited to the structure shown in FIG.

Further, as shown in FIG. 83C, the signal line driver circuit 22703 includes a shift register
, a first latch 22732 , a second latch 22733 , a level shifter 22734 and a buffer 22735 . A circuit functioning as the buffer 22735 is a circuit having a function of amplifying a weak signal, and includes an operational amplifier or the like. A signal such as a start pulse (SSP) is input to the level shifter 22734 , and data (DATA) such as a video signal is input to the first latch 22732 . The second latch 22733 has a latch (L
AT) signals can be temporarily held and input to the pixel portion 22705 all at once. This is called line sequential driving. Therefore, if the pixel is to be dot-sequentially driven instead of line-sequentially driven, the second
latch can be dispensed with. Thus, the signal line driver circuit of this embodiment is shown in FIG.
It is not limited to the configuration shown in 3(C).

The signal line driver circuit 22703, the scanning line driver circuit 22704, and the pixel portion 22705 can be formed using semiconductor elements provided over the same substrate. A semiconductor element can be formed using a thin film transistor provided over a glass substrate. In this case, a crystalline semiconductor film is preferably applied to the semiconductor element. A crystalline semiconductor film has high electrical characteristics, particularly high mobility, and thus can form a circuit included in a driver circuit portion. Also, the signal line drive circuit 2
2703 and the scanning line driving circuit 22704 are ICs (Integrated Circuits).
) chip to be mounted on the substrate. In this case, an amorphous semiconductor film can be applied to the semiconductor element of the pixel portion.

Here, the liquid crystal display module of this embodiment will be described with reference to FIGS. 87(A) and 87(B).

FIG. 87A shows an example of a liquid crystal display module, in which a TFT substrate 23100 and a counter substrate 23 are provided.
101 are fixed by a sealing material 23102, and a pixel portion 23103 including a TFT and the like is interposed therebetween.
and a liquid crystal layer 23104 are provided to form a display area. The colored layer 23105 is necessary for color display. In the case of the RGB system, colored layers corresponding to red, green, and blue colors are provided for each pixel. A layer 23106 containing a first polarizer, a layer 23107 containing a second polarizer, and a diffusion plate 23113 are provided outside the TFT substrate 23100 and the counter substrate 23101 .
are arranged. A light source is composed of a cold cathode tube 23110 and a reflector 23111. A circuit board 23112 is connected to the TFT substrate 23100 by a flexible wiring board 23109, and incorporates external circuits such as a control circuit and a power supply circuit.

A layer 2310 containing a second polarizer is provided between the TFT substrate 23100 and the backlight which is a light source.
7 is stacked, and a layer 23106 containing a first polarizer is also stacked on the counter substrate 23101 . On the other hand, the absorption axis of the layer 23107 containing the second polarizer and the absorption axis of the layer 23106 containing the first polarizer provided on the viewing side are arranged to be crossed Nicols.

A stacked layer 23107 containing the second polarizer and a stacked layer 2310 containing the first polarizer
6 is adhered to the TFT substrate 23100 and the counter substrate 23101 . Alternatively, the laminated layer containing the polarizer and the substrate may be laminated with a retardation plate interposed therebetween. Further, if necessary, the layer 23106 including the first polarizer on the viewing side may be subjected to antireflection treatment.

Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (I
n-Plane-Switching) mode, FFS (Fringe Field S
switching) mode, MVA (Multi-domain Vertical A
alignment) mode, PVA (Patterned Vertical Align
nment), ASM (Axially Symmetrically aligned Mic
ro-cell) mode, OCB (Optical Compensated Bire
fringence) mode, FLC (Ferroelectric Liquid C
rystal) mode, AFLC (Anti-Ferroelectric Liquid
Crystal), PDLC (Polymer Dispersed Liquid
Crystal) mode or the like can be used.

FIG. 87(B) shows an example in which the OCB mode is applied to the liquid crystal display module of FIG. 87(A), which is an FS-LCD (Field sequential-LCD). FS-L
A CD emits red light, green light, and blue light in one frame period, and can perform color display by synthesizing images using time division. Moreover, since each light emission is performed by a light-emitting diode, a cold cathode tube, or the like, a color filter is unnecessary. Therefore, it is not necessary to arrange color filters of three primary colors and limit the display area of each color, and all three colors can be displayed in any area. On the other hand, since three colors of light are emitted in one frame period, high-speed response of the liquid crystal is required. By applying the FLC mode and the OCB mode using the FS system to the display device of this embodiment mode, a high-performance and high-definition display device and a liquid crystal television device can be completed.

The OCB mode liquid crystal layer has a so-called π cell structure. The π-cell structure is a structure in which the pretilt angles of liquid crystal molecules are oriented in a plane-symmetrical relationship with respect to the central plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when voltage is applied. This bend orientation results in white display. When a further voltage is applied, the bend-aligned liquid crystal molecules are oriented perpendicular to both substrates, and light does not transmit. Note that the OCB mode can achieve high-speed response about ten times faster than the conventional TN mode.

In addition, as a mode corresponding to the FS method, a ferroelectric liquid crystal (FLC: Fe
HV (Half V
)-FLC, SS (Surface Stabilized)-FLC, etc. can also be used.

Further, by narrowing the cell gap of the liquid crystal display module, the optical response speed of the liquid crystal display module can be increased. Also, the speed can be increased by lowering the viscosity of the liquid crystal material. Speeding up is more effective when the pixel pitch of the pixel region of the TN mode liquid crystal display module is 30 μm or less. Also, the speed may be increased by using an overdrive in which the voltage applied to the liquid crystal layer is momentarily higher (or lower) than the original voltage.

The liquid crystal display module in FIG. 87B shows a transmissive liquid crystal display module, and is provided with a red light source 23190a, a green light source 23190b, and a blue light source 23190c as light sources. A controller 23199 is installed to control the on/off of the red light source 23190a, the green light source 23190b, and the blue light source 23190c. control unit 2319
Light emission of each color is controlled by 9, light is incident on the liquid crystal, and images are synthesized using time division to perform color display.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 10)
In this embodiment mode, a method for driving a display device that can implement this embodiment mode will be described. In particular, a method for driving a liquid crystal display device will be described.

First, overdrive will be described with reference to FIG. (A) of FIG.
It represents the temporal change of the output luminance of the display element with respect to the input voltage. The time change of the output luminance of the display element with respect to the input voltage 30121 indicated by the dashed line becomes like the output luminance 30123 similarly indicated by the dashed line. That is, the voltage to obtain the target output luminance Lo is Vi, but if Vi is input as it is as the input voltage, it takes time corresponding to the response speed of the element to reach the target output luminance Lo. end up

Overdrive is a technique for increasing this response speed. Specifically, first
In this method, a voltage Vo, which is higher than Vi, is applied to the element for a certain period of time to increase the response speed of the output luminance so that the target output luminance Lo is approached, and then the input voltage is returned to Vi.
At this time, the input voltage is represented by an input voltage 30122 and the output brightness is represented by an output brightness 30124 . The graph of the output luminance 30124 has a shorter time to reach the target luminance Lo than the graph of the output luminance 30123 .

In FIG. 88A, the case where the output luminance changes positively with respect to the input voltage has been described, but this embodiment also includes the case where the output luminance changes negatively with respect to the input voltage. I'm in.

A circuit for realizing such driving will be described with reference to FIGS. 88B and 88C. First, with reference to FIG. 88B, the case where the input video signal 30131 is an analog value (or discrete value) and the output video signal 30132 is also an analog value will be described. The overdrive circuit shown in FIG. 88B includes an encoding circuit 30101, a frame memory 30102, a correction circuit 30103, a DA conversion circuit
104.

An input video signal 30131 is first input to an encoding circuit 30101 and encoded. That is, the analog signal is converted into a digital signal with an appropriate number of bits. After that, the converted digital signal is input to the frame memory 30102 and the correction circuit 30103 respectively. The video signal of the previous frame held in the frame memory 30102 is also input to the correction circuit 30103 at the same time. Then, the correction circuit 30103 outputs a video signal corrected from the video signal of the current frame and the video signal of the previous frame according to a numerical table prepared in advance. At this time, an output switching signal 30133 may be input to the correction circuit 30103 so that the corrected video signal and the video signal of the frame can be switched and output. Next, the corrected video signal or the video signal of the frame is input to the DA conversion circuit 30104 . Then, an output video signal 30132, which is an analog signal having a value according to the corrected video signal or the video signal of the frame, is output. In this way, overdrive can be realized.

Next, the case where the input video signal 30131 is a signal having a digital value and the output video signal 30132 is also a signal having a digital value will be described with reference to FIG. 88(C). Figure 8
The overdrive circuit shown in (C) of 8 includes a frame memory 30112 and a correction circuit 301.
13.

The input video signal 30131 is a digital signal. First, a frame memory 30112,
are input to the correction circuits 30113 and 30113, respectively. The video signal of the previous frame held in the frame memory 30112 is also input to the correction circuit 30113 at the same time. Then, the correction circuit 30113 outputs a video signal corrected from the video signal of the current frame and the video signal of the previous frame according to a numerical table prepared in advance. At this time, an output switching signal 30133 may be input to the correction circuit 30113 so that the corrected video signal and the video signal of the frame can be switched and output. In this way, overdrive can be realized.

It should be noted that the overdrive circuit of this embodiment includes the case where the input video signal 30131 is an analog signal and the output video signal 30132 is a digital signal. At this time
The DA conversion circuit 30104 may be omitted from the circuit shown in FIG. 88(B). Moreover, the overdrive circuit in this embodiment includes a case where the input video signal 30131 is a digital signal and the output video signal 30132 is an analog signal. In this case, the encoding circuit 30101 may be omitted from the circuit shown in FIG. 88(B).

Next, drive for manipulating the potential of the common line will be described with reference to FIG. ( in FIG. 89)
A) shows a plurality of pixel circuits when one common line is arranged for one scanning line in a display device using a display element having capacitive properties such as a liquid crystal element. It is a diagram. The pixel circuit shown in FIG. 89A includes a transistor 30201, an auxiliary capacitor 30202, a display element 30203, a video signal line 30204, a scanning line 30205, and a common line 30206.

A gate electrode of the transistor 30201 is electrically connected to the scan line 30205, one of the source electrode and the drain electrode of the transistor 30201 is electrically connected to the video signal line 30204, and the other of the source electrode and the drain electrode of the transistor 30201 is electrically connected to the video signal line 30204. is electrically connected to one electrode of the auxiliary capacitor 30202 and one electrode of the display element 30203 . Also, the other electrode of the auxiliary capacitor 30202 is electrically connected to the common line 30206 .

First, since the transistor 30201 of the pixel selected by the scanning line 30205 is turned on, a voltage corresponding to the video signal is applied to the display element 30203 and the auxiliary capacitor 30202 via the video signal line 30204 . At this time, the video signal is transferred to the common line 3
0206 to display the lowest gradation, or all the pixels connected to the common line 30206 to display the highest gradation, the pixel , there is no need to write the video signal through the video signal line 30204 respectively.
By changing the potential of the common line 30206 instead of writing the video signal through the video signal line 30204, the voltage applied to the display element 30203 can be changed.

Next, FIG. 89B shows a display device using a display element having a capacitive property such as a liquid crystal element, in which two common lines are arranged for one scanning line. FIG. 4 is a diagram showing a plurality of pixel circuits; The pixel circuit shown in FIG. 89B includes a transistor 30211, an auxiliary capacitor 30212, a display element 30213, a video signal line 30214, a scanning line 30215, a first common line 30216, and a second common line 30217. .

A gate electrode of the transistor 30211 is electrically connected to the scan line 30215, one of the source electrode and the drain electrode of the transistor 30211 is electrically connected to the video signal line 30214, and the other of the source electrode and the drain electrode of the transistor 30211 is electrically connected to the video signal line 30214. is electrically connected to one electrode of the auxiliary capacitor 30212 and one electrode of the display element 30213 . Also, the other electrode of the auxiliary capacitor 30212 is electrically connected to the first common line 30216 . Also, in the pixel adjacent to the pixel in question, the auxiliary capacitor 30212
The other electrode of is electrically connected to the second common line 30217 .

In the pixel circuit shown in FIG. 89B, the number of pixels electrically connected to one common line is small. Alternatively, by moving the potential of the second common line 30217, the display element 30213
The frequency with which the voltage applied to can be changed is significantly increased. Also, source inversion driving or dot inversion driving becomes possible. Source inversion driving or dot inversion driving can suppress flicker while improving the reliability of the device.

Next, a scanning backlight will be described with reference to FIG. FIG. 90A is a diagram showing a scanning backlight in which cold cathode tubes are juxtaposed. The scanning backlight shown in FIG. 90A includes a diffusion plate 30301 and N cold cathode tubes 30302-1 to 30302-N. By arranging the N cold-cathode tubes 30302-1 to 30302-N side by side behind the diffusion plate 30301, the N cold-cathode tubes 30302-1 to 30302-N can be scanned while changing their brightness. can be done.

A change in luminance of each cold cathode tube during scanning will be described with reference to FIG. 90(C). First, the brightness of the cold cathode tube 30302-1 is changed for a certain period of time. Then, after that, the cold cathode tube 30
The brightness of the cold cathode tube 30302-2 arranged next to 302-1 is changed for the same period of time. In this way, the cold cathode tubes 30302-1 to 30302-N are sequentially changed in brightness. In addition, in FIG. 90C, the luminance to be changed for a certain period of time is lower than the original luminance, but it may be higher than the original luminance. In addition, cold cathode tubes 30302-1 to 3030
Although scanning is performed up to 2-N, scanning may be performed in the opposite direction from cold cathode tubes 30302-N to 30302-1.

By driving as shown in FIG. 90, the average brightness of the backlight can be reduced. Therefore, the power consumption of the backlight, which accounts for most of the power consumption of the liquid crystal display device, can be reduced.

Note that an LED may be used as the light source of the scanning backlight. The scanning backlight in that case is as shown in FIG. 90(B). The scanning backlight shown in FIG. 90B includes a diffusion plate 30311 and light sources 30312-1 to 30312-N in which LEDs are arranged side by side. When LEDs are used as the light source of the scanning backlight, the backlight is thin,
It has the advantage of being lighter. There is also the advantage that the color reproduction range can be widened. Furthermore, the LEs juxtaposed with each of the juxtaposed LED light sources 30312-1 to 30312-N
Since D can also be scanned in the same way, it can be a point scanning type backlight.
If it is of the point scanning type, the image quality of moving images can be further improved.

Even when LEDs are used as the light source of the backlight, they can be driven by changing the luminance as shown in FIG. 90(C).

Next, high frequency drive will be described with reference to FIG. FIG. 91A is a diagram when one image and one intermediate image are displayed in one frame period 30400. FIG. 3040
1 is the image of the frame, 30402 is the intermediate image of the frame, 30403 is the image of the next frame, and 30404 is the intermediate image of the next frame.

Note that the intermediate image 30402 of the current frame may be an image created based on the video signals of the current frame and the next frame. Also, the intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. Also, the intermediate image 30402 of the frame may be a black image. By doing so, it is possible to improve the image quality of the moving image of the hold-type display device. Further, when one image and one intermediate image are displayed in one frame period 30400, there is an advantage that it is easy to match with the frame rate of the video signal and the image processing circuit does not become complicated.

FIG. 91B is a diagram when one image and two intermediate images are displayed in a period (two frame periods) in which two one frame periods 30400 are consecutive. 30411 is the image of the current frame, 30412 is the intermediate image of the current frame, 30413 is the intermediate image of the next frame,
0414 is an image of the next frame.

Note that the intermediate image 30412 of the current frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the current frame, the next frame, and the subsequent frame. Also, the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame are
It may be a black image. When one image and two intermediate images are displayed in two frame periods, there is an advantage that the image quality of the moving image can be effectively improved without increasing the operating frequency of the peripheral driving circuit so much.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 11)
In this embodiment mode, a pixel structure of a display device that can implement this embodiment mode will be described. In particular, a pixel structure of a display device using an organic EL element will be described.

FIG. 92A shows an example layout of elements of a pixel having two TFTs in one pixel.
Further, FIG. 92(B) shows a cross-sectional view of a portion indicated by XX' in FIG. 92(A).

As shown in FIG. 92A, the pixel in this embodiment includes a first TFT 60105,
First wiring 60106, second wiring 60107, second TFT 60108, third wiring 6
0111, counter electrode 60112, capacitor 60113, pixel electrode 60115, partition wall 60
116, an organic conductor film 60117, an organic thin film 60118, and a substrate 60119. Note that the first TFT 60105 is used as a switching TFT, and the first wiring 601 is connected.
06 as a gate signal line, a second wiring 60107 as a source signal line, and a second TFT.
60108 is preferably used as a driving TFT, and the third wiring 60111 is preferably used as a current supply line.

As shown in FIG. 92A, the gate electrode of the first TFT 60105 is connected to the first wiring 60
106, one of the source electrode and the drain electrode of the first TFT 60105 is electrically connected to the second wiring 60107, and the other of the source electrode and the drain electrode of the first TFT 60105 is connected to the second wiring 60107. is preferably electrically connected to the gate electrode of the TFT 60108 and one electrode of the capacitor 60113 . Note that the first TFT
The gate electrode 60105 may be composed of a plurality of gate electrodes as shown in FIG. 92(A). By doing so, leakage current in the off state of the first TFT 60105 can be reduced.

One of the source electrode and the drain electrode of the second TFT 60108 is connected to the third wiring 6
0111 , and the other of the source electrode and the drain electrode of the second TFT 60108 is preferably electrically connected to the pixel electrode 60115 . By doing so, the current flowing through the pixel electrode 60115 can be controlled by the second TFT 60108 .

An organic conductive film 60117 is provided on the pixel electrode 60115, and the organic thin film 601 is further provided.
18 (organic compound layer) may be provided. A counter electrode 60112 may be provided on the organic thin film 60118 (organic compound layer). The counter electrode 60112 may be solidly formed so as to be commonly connected to all pixels, or may be patterned using a shadow mask or the like.

Light emitted from the organic thin film 60118 (organic compound layer) passes through either the pixel electrode 60115 or the counter electrode 60112 and is emitted. At this time, in FIG. 92B, the case where light is emitted to the pixel electrode side, that is, the side where TFTs and the like are formed is called bottom emission, and the case where light is emitted to the opposite electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60115 is preferably made of a transparent conductive film.
Conversely, in the case of top emission, the counter electrode 60112 is preferably made of a transparent conductive film.

In addition, in a light emitting device for color display, EL elements having respective emission colors of R, G, and B may be separately painted, or single-color EL elements may be painted in a solid manner, and R may be formed by a color filter.
• G and B light emission may be obtained.

Note that the configuration shown in FIG. 92 is merely an example, and various configurations other than the configuration shown in FIG. 92 can be employed with respect to the pixel layout, cross-sectional configuration, order of stacking of electrodes of EL elements, and the like. In addition to the illustrated organic thin film elements, various elements such as crystalline elements such as LEDs and inorganic thin film elements can be used for the light emitting layer.

Next, with reference to FIG. 93A, a layout example of elements of a pixel having three TFTs in one pixel will be described. Further, FIG. 93(B) shows a cross-sectional view of a portion indicated by XX' in FIG. 93(A).

As shown in FIG. 93A, the pixel in this embodiment mode includes a substrate 60200, a first wiring 60201, a second wiring 60202, a third wiring 60203, a fourth wiring 60204, a first TFT 60205, Second TFT 60206, third TFT 60207, pixel electrode 6
0208, partition wall 60211, organic conductor film 60212, organic thin film 60213, counter electrode 6
0214. Note that the first wiring 60201 is used as a source signal line, the second wiring 60202 is used as a writing gate signal line, the third wiring 60203 is used as an erasing gate signal line, and the fourth wiring 60204 is used as a current supply line. , the first TFT 60205 as a switching TFT, the second TFT 60206 as an erasing TFT, and the third TF
T60207 is preferably used as a driving TFT.

As shown in FIG. 93A, the gate electrode of the first TFT 60205 is connected to the second wiring 602
02, one of the source and drain electrodes of the first TFT 60205 is electrically connected to the first wiring 60201, and the other of the source and drain electrodes of the first TFT 60205 is connected to the third wiring. is preferably electrically connected to the gate electrode of the TFT 60207. Note that the gate electrode of the first TFT 60205 may be composed of a plurality of gate electrodes as shown in FIG. 93(A). By doing so, leakage current in the off state of the first TFT 60205 can be reduced.

In addition, the gate electrode of the second TFT 60206 is electrically connected to the third wiring 60203, and one of the source electrode and the drain electrode of the second TFT 60206 is connected to the fourth wiring 60.
204 , and the other of the source electrode or the drain electrode of the second TFT 60206 is preferably electrically connected to the gate electrode of the third TFT 60207 . Note that the gate electrode of the second TFT 60206 may be composed of a plurality of gate electrodes as shown in FIG. 93(A). By doing so, leakage current in the off state of the second TFT 60206 can be reduced.

One of the source electrode and the drain electrode of the third TFT 60207 is connected to the fourth wiring 6
0204 , and the other of the source electrode and the drain electrode of the third TFT 60207 is preferably electrically connected to the pixel electrode 60208 . By doing so, the current flowing through the pixel electrode 60208 can be controlled by the third TFT 60207 .

An organic conductive film 60212 is provided on the pixel electrode 60208, and the organic thin film 602 is further provided.
13 (organic compound layer) may be provided. A counter electrode 60214 may be provided on the organic thin film 60213 (organic compound layer). Note that the counter electrode 60214 may be solidly formed so as to be commonly connected to all pixels, or may be patterned using a shadow mask or the like.

Light emitted from the organic thin film 60213 (organic compound layer) passes through either the pixel electrode 60208 or the counter electrode 60214 and is emitted. At this time, in FIG. 93B, the case where light is emitted to the pixel electrode side, that is, the side where TFTs and the like are formed is called bottom emission, and the case where light is emitted to the opposite electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60208 is preferably made of a transparent conductive film.
Conversely, for top emission, the counter electrode 60214 is preferably formed of a transparent conductive film.

In addition, in a light emitting device for color display, EL elements having respective emission colors of R, G, and B may be separately painted, or single-color EL elements may be painted in a solid manner, and R may be formed by a color filter.
, G, and B may be obtained.

Note that the configuration shown in FIG. 93 is merely an example, and various configurations other than the configuration shown in FIG. 93 can be employed with respect to the pixel layout, cross-sectional configuration, order of stacking of electrodes of EL elements, and the like. In addition to the illustrated organic thin film elements, various elements such as crystalline elements such as LEDs and inorganic thin film elements can be used for the light emitting layer.

Next, with reference to FIG. 94A, a layout example of elements of a pixel having four TFTs in one pixel will be described. Further, FIG. 94B shows a cross-sectional view of a portion indicated by XX' in FIG. 94A.

As shown in FIG. 94A, the pixel in this embodiment mode includes a substrate 60300, a first wiring 60301, a second wiring 60302, a third wiring 60303, a fourth wiring 60304, a first TFT 60305, Second TFT 60306, third TFT 60307, fourth TF
A T60308, a pixel electrode 60309, a fifth wiring 60311, a sixth wiring 60312, a partition wall 60321, an organic conductor film 60322, an organic thin film 60323, and a counter electrode 60324 may be provided. Note that the first wiring 60301 serves as a source signal line, and the second wiring 60
302 serves as a writing gate signal line, a third wiring 60303 serves as an erasing gate signal line, a fourth wiring 60304 serves as a reverse bias signal line, a first TFT 60305 serves as a switching TFT, and a second wiring 60304 serves as a reverse bias signal line. A TFT 60306 is used as an erasing TFT and is a third TF.
T60307 is a driving TFT, and the fourth TFT 60308 is a reverse bias TFT.
As such, the fifth wiring 60311 is preferably used as a current supply line, and the sixth wiring 60312 is preferably used as a reverse bias power supply line.

As shown in FIG. 94A, the gate electrode of the first TFT 60305 is connected to the second wiring 603
02, one of the source and drain electrodes of the first TFT 60305 is electrically connected to the first wiring 60301, and the other of the source and drain electrodes of the first TFT 60305 is connected to the third wiring. is preferably electrically connected to the gate electrode of the TFT 60307 of . Note that the gate electrode of the first TFT 60305 may be composed of a plurality of gate electrodes as shown in FIG. 94(A). By doing so, leakage current in the off state of the first TFT 60305 can be reduced.

A gate electrode of the second TFT 60306 is electrically connected to a third wiring 60303, and one of a source electrode and a drain electrode of the second TFT 60306 is connected to a fifth wiring 60311.
and the other of the source electrode and the drain electrode of the second TFT 60306 is preferably electrically connected to the gate electrode of the third TFT 60307 . Note that the gate electrode of the second TFT 60306 may be composed of a plurality of gate electrodes as shown in FIG. 94(A). By doing so, leakage current in the off state of the second TFT 60306 can be reduced.

One of the source electrode and the drain electrode of the third TFT 60307 is connected to the fifth wiring 6031
1 and the other of the source electrode and the drain electrode of the third TFT 60307 is preferably electrically connected to the pixel electrode 60309 . By doing so, the current flowing through the pixel electrode 60309 can be controlled by the third TFT 60307 .

A gate electrode of the fourth TFT 60308 is electrically connected to a fourth wiring 60304, and one of a source electrode and a drain electrode of the fourth TFT 60308 is connected to a sixth wiring 60312.
, and the other of the source electrode and the drain electrode of the fourth TFT 60308 is preferably electrically connected to the pixel electrode 60309 . By doing so, the potential of the pixel electrode 60309 can be controlled by the fourth TFT 60308.
A reverse bias can be applied to the organic conductor film 60322 and the organic thin film 60323 . By applying a reverse bias to the light emitting element composed of the organic conductor film 60322 and the organic thin film 60323, the reliability of the light emitting element can be greatly improved.

For example, a light-emitting element whose brightness half-life time is about 400 hours when driven with a DC voltage (3.65 V) is driven with an AC voltage (forward bias: 3.7 V, reverse bias: 1.7 V, duty 50%, It is known that when driven at an AC frequency of 60 Hz, the luminance half life time is 700 hours or longer.

An organic conductive film 60322 is provided on the pixel electrode 60309, and an organic thin film 603 is further provided.
23 (organic compound layer) may be provided. A counter electrode 60324 may be provided on the organic thin film 60323 (organic compound layer). Note that the counter electrode 60324 may be solidly formed so as to be commonly connected to all pixels, or may be patterned using a shadow mask or the like.

Light emitted from the organic thin film 60323 (organic compound layer) passes through either the pixel electrode 60309 or the counter electrode 60324 and is emitted. At this time, in FIG. 94B, the case where the light is emitted to the pixel electrode side, that is, the side where the TFTs and the like are formed is called bottom emission, and the case where the light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60309 is preferably made of a transparent conductive film.
Conversely, for top emission, the counter electrode 60324 is preferably made of a transparent conductive film.

In a light-emitting device for color display, EL elements having respective emission colors of R, G, and B may be separately painted, or single-color EL elements may be coated in a solid manner and R, G, and R, G,
B light emission may be obtained.

Note that the configuration shown in FIG. 94 is merely an example, and various configurations other than the configuration shown in FIG. 94 can be employed with respect to the pixel layout, cross-sectional configuration, order of stacking of electrodes of EL elements, and the like. In addition to the illustrated organic thin film elements, various elements such as crystalline elements such as LEDs and inorganic thin film elements can be used for the light emitting layer.

Next, the structure of an EL element that can be applied to this embodiment mode will be described.

The EL element that can be applied to this embodiment includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, an electron An electron injection layer made of an injection material is not a clearly distinguished laminated structure, but a plurality of materials such as a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material. A structure having a layer (mixed layer) in which materials are mixed (hereinafter referred to as a mixed junction EL element) may also be used.

FIG. 95 shows a schematic diagram showing the structure of a mixed-junction EL element. In FIG. 95, 6040
1 is the anode of the EL element. 60402 is the cathode of the EL element. A layer sandwiched between the anode 60401 and the cathode 60402 corresponds to the EL layer.

In FIG. 95A, the EL layer includes a hole-transporting region 60403 made of a hole-transporting material and an electron-transporting region 60404 made of an electron-transporting material. mixed region 60 comprising both said hole-transporting material and said electron-transporting material, located on the side and between the hole-transporting region 60403 and the electron-transporting region 60404
405 can be provided.

Note that the concentration of the hole-transporting material in the mixed region 60405 decreases and the concentration of the electron-transporting material in the mixed region 60405 increases in the direction from the anode 60401 to the cathode 60402 .

Note that in the above structure, the hole-transporting region 60403 made of only the hole-transporting material does not exist, and the concentration ratio of each functional material changes inside the mixed region 60405 containing both the hole-transporting material and the electron-transporting material. It may be a configuration (having a concentration gradient). Further, a hole-transporting region 60403 containing only a hole-transporting material and an electron-transporting region 60404 containing only an electron-transporting material
may be absent, and the concentration ratio of each functional material changes (has a concentration gradient) inside the mixed region 60405 containing both the hole-transporting material and the electron-transporting material. Moreover, the ratio of the concentration may be configured to change depending on the distance from the anode or the cathode. Further, the change in percentage of concentration may be continuous. The method of setting the concentration gradient can be freely set.

A mixed region 60405 has a region 60406 added with a light-emitting material. The emission color of the EL element can be controlled by the luminescent material. In addition, carriers can be trapped by the light-emitting material. As the luminescent material, a metal complex containing a quinoline skeleton, a metal complex containing a benzoxazole skeleton, a metal complex containing a benzothiazole skeleton, and various fluorescent dyes can be used. By adding these luminescent materials, the luminescent color of the EL element can be controlled.

As the anode 60401, an electrode material with a large work function is preferably used in order to efficiently inject holes. For example, transparent electrodes such as tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), ZnO, SnO ₂ and In ₂ O ₃ can be used. Also, if it is not necessary to have translucency, the anode 60401 may be an opaque metal material.

An aromatic amine-based compound or the like can be used as the hole transport material.

As the electron transport material, a quinoline derivative, a metal complex having 8-quinolinol or a derivative thereof as a ligand (especially tris(8-quinolinolite)aluminum (Alq ₃ )), or the like can be used.

As the cathode 60402, an electrode material with a small work function is preferably used in order to efficiently inject electrons. Metals such as aluminum, indium, magnesium, silver, calcium, barium, and lithium can be used singly. Also, alloys of these metals or alloys of these metals and other metals may be used.

FIG. 95B shows a schematic diagram of an EL element having a structure different from that in FIG. 95A. Note that FIG. 95 (
The same reference numerals are used for the same parts as in A), and the description thereof is omitted.

FIG. 95B does not have a region added with a light-emitting material. However, the electron transport region 604
As a material added to 04, a material having both an electron-transporting property and a light-emitting property (electron-transporting light-emitting material), for example, tris(8-quinolinolite)aluminum (Alq ₃ ) can be used to emit light.

Alternatively, as a material added to the hole-transporting region 60403, a material having both a hole-transporting property and a light-emitting property (a hole-transporting light-emitting material) may be used.

FIG. 95C shows a schematic diagram of an EL element having a structure different from that of FIGS. 95A and 95B. The same parts as those in FIGS. 95A and 95B are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 95(C), a hole-blocking material having a large energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital compared to the hole-transporting material has a region 60407 added in the mixed region 60405. . By arranging the region 60407 added with the hole-blocking material closer to the cathode 60402 than the region 60406 added with the light-emitting material in the mixed region 60405, the recombination rate of carriers can be increased and the light emission efficiency can be increased. can. The configuration of providing the region 60407 to which the hole-blocking material is added is particularly effective in an EL device that utilizes light emission (phosphorescence) by triple photoexciton.

95(A), 95(B), and 95(C) are schematic diagrams of EL elements having different structures from those shown in FIGS.
5(D). 95(A), 95(B), and 95(C) are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 95(D), a region 60408 in which an electron-blocking material having a larger energy difference between the highest and lowest occupied molecular orbitals than the electron-transporting material is added in the mixed region 60405 is provided. By arranging the region 60408 to which the electron-blocking material is added closer to the anode 60401 than the region 60406 to which the light emitting material is added in the mixed region 60405, the recombination rate of carriers can be increased and the light emission efficiency can be increased. . The configuration of providing the region 60408 to which the electron-blocking material is added is particularly effective in an EL device utilizing light emission (phosphorescence) by triple photoexciton.

FIG. 95(E) is a schematic diagram showing the structure of a mixed junction EL element different from FIGS. 95(A), 95(B), 95(C) and 95(D). FIG. 95E shows an example of a structure having a region 60409 added with a metal material in the portion of the EL layer that is in contact with the electrode of the EL element. In FIG. 95(E), the same parts as those in FIGS. 95(A) to 95(D) are denoted by the same reference numerals, and description thereof is omitted. The configuration shown in FIG. 95(E) is, for example, MgA
An electron transporting region 60404 containing g (Mg—Ag alloy) and an electron transporting material added may have a region 60409 added with an Al (aluminum) alloy in a region in contact with the cathode 60402 . With the above structure, oxidation of the cathode can be prevented and the efficiency of electron injection from the cathode can be increased. Thus, the life of the mixed-junction EL device can be extended. Also, the driving voltage can be lowered.

A co-evaporation method or the like can be used as a method for manufacturing the mixed junction type EL element.

In mixed-junction EL devices as shown in FIGS. 95(A) to 95(E), there is no distinct interface between layers, and charge accumulation can be reduced. Thus, its life can be lengthened. Also, the driving voltage can be lowered.

The configurations shown in FIGS. 95(A) to 95(E) can be freely combined for implementation.

The configuration of the mixed junction EL element is not limited to this. Any known configuration can be freely used.

The organic material forming the EL layer of the EL element may be either a low-molecular-weight material or a high-molecular-weight material. Alternatively, both of these materials may be used. When a low-molecular-weight material is used as the organic compound material, the film can be formed by vapor deposition. On the other hand, when a polymer material is used for the EL layer, the polymer material can be dissolved in a solvent and formed into a film by a spin coating method or an inkjet method.

The EL layer may be composed of a middle-molecular material. In this specification, the medium-molecular-weight organic light-emitting material means an organic light-emitting material that does not have sublimability and has a degree of polymerization of about 20 or less. In the case of using a middle-molecular material for the EL layer, the film can be formed by an inkjet method or the like.

A low-molecular-weight material, a high-molecular-weight material, and a medium-molecular-weight material may be used in combination.

Further, the EL element may be one that utilizes light emission (fluorescence) from singlet excitons or one that utilizes light emission (phosphorescence) from triplet excitons, or both.

Next, a vapor deposition apparatus for manufacturing a display device to which this embodiment can be applied will be described with reference to the drawings.

A display device to which this embodiment mode can be applied may be manufactured by forming an EL layer. The EL layer is
At least a portion thereof is formed to contain a material that exhibits electroluminescence. The EL layer may be composed of a plurality of layers with different functions. In that case, the EL layer may be formed by combining layers having different functions, which are also called a hole injection transport layer, a light emitting layer, an electron injection transport layer, and the like.

FIG. 96 shows the structure of a vapor deposition apparatus for forming an EL layer on an element substrate on which transistors are formed.
shown in In this deposition apparatus, transfer chambers 60560 and 60561 are connected to a plurality of processing chambers. The processing chamber includes a load chamber 60562 for supplying substrates and an unload chamber 605 for recovering substrates.
63, a heat treatment chamber 60568, a plasma treatment chamber 60572, film formation treatment chambers 60569 to 60575 for depositing EL materials, film formation for forming a conductive film containing aluminum or aluminum as a main component as one electrode of an EL element. A processing chamber 60576 is included. Gate valves 60577a to 60577m are provided between the transfer chamber and each processing chamber, and the pressure of each processing chamber can be controlled independently to prevent mutual contamination between processing chambers.

A substrate introduced from the load chamber 60562 into the transfer chamber 60560 is carried into a predetermined processing chamber by a rotatably provided arm-type transfer means 60566 . Also, the substrate is transported from one processing chamber to another processing chamber by the transport means 60566 . The transfer chamber 60560 and the transfer chamber 60561 are connected to each other by a film formation treatment chamber 60570, where the transfer means 60566 and 60567 transfer substrates.

Each processing chamber connected to the transfer chamber 60560 and the transfer chamber 60561 is kept under reduced pressure. Therefore, in this vapor deposition apparatus, the film formation process of the EL layer is continuously performed without exposing the substrate to the air. A display panel that has completed the deposition process of the EL layer may be deteriorated by water vapor or the like. Chamber 60565 is connected to transfer chamber 60561 . Sealing processing chamber 605
65 is placed under atmospheric pressure or a reduced pressure close to it, so intermediate processing chamber 60564 is also provided between transfer chamber 60561 and sealing processing chamber 60565 . Intermediate processing chamber 60564
are provided for transferring substrates and buffering the pressure between the chambers.

The load chamber, the unload chamber, the transfer chamber, and the film formation processing chamber are equipped with exhaust means for keeping the chambers at a reduced pressure. Various vacuum pumps such as dry pumps, turbomolecular pumps, and diffusion pumps can be used as the evacuation means.

In the vapor deposition apparatus of FIG. 96, the number and configuration of processing chambers connected to the transfer chambers 60560 and 60561 can be appropriately combined according to the laminated structure of the EL element. An example of the combination is shown below.

The heat treatment chamber 60568 first heats the substrate on which the lower electrode, the insulating partition, and the like are formed to perform degassing treatment. The plasma processing chamber 60572 performs rare gas or oxygen plasma processing on the surface of the base electrode. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state (for example, work function) of the surface.

A deposition processing chamber 60569 is a processing chamber for forming an electrode buffer layer in contact with one electrode of the EL element. The electrode buffer layer has a carrier injection property (hole injection or electron injection), and E
This is a layer that suppresses the occurrence of short circuits and dark spot defects in the L element. Typically, the electrode buffer layer is an organic-inorganic mixed material with a resistivity of 5×10 ⁴ to 1×10 ⁶ Ωcm and 30 to 300 Ωcm.
It is formed with a thickness of nm. A deposition chamber 60571 is a treatment chamber for depositing a hole transport layer.

A light-emitting layer in an EL element has a different structure depending on whether it emits monochromatic light or white light. It is preferable to arrange the film formation processing chambers in the vapor deposition apparatus accordingly. for example,
In the case of forming three types of EL elements with different emission colors in a display panel, it is necessary to form light-emitting layers corresponding to the respective emission colors. In this case, the film formation processing chamber 60570 is used for film formation of the first light-emitting layer, the film formation processing chamber 60573 is used for film formation of the second light-emitting layer, and the film formation processing chamber 60574 is used for film formation of the third light-emitting layer. It can be used for membranes. By dividing the film formation processing chamber for each light emitting layer, mutual contamination by different light emitting materials can be prevented, and the throughput of the film formation processing can be improved.

Three types of EL materials with different emission colors may be sequentially deposited in each of the film formation processing chambers 60570, 60573, and 60574. FIG. In this case, a shadow mask is used and vapor deposition is performed by shifting the mask according to the region to be vapor-deposited.

In the case of forming an EL element that emits white light, light-emitting layers with different emission colors are stacked vertically. Also in this case, the element substrate can be sequentially moved in the film formation processing chamber, and the film can be formed for each light emitting layer. In addition, different light-emitting layers can be continuously formed in the same film formation processing chamber.

In the deposition treatment chamber 60576, an electrode is deposited on the EL layer. Electron beam vapor deposition or sputtering can be applied to form the electrodes, but resistance heating vapor deposition is preferably used.

The element substrate, on which electrodes have been formed, passes through an intermediate processing chamber 60564 and then into a sealing processing chamber 60565.
is brought into The sealing treatment chamber 60565 is filled with an inert gas such as helium, argon, neon, or nitrogen. stop. In the sealed state, between the element substrate and the sealing plate,
It may be filled with an inert gas, or may be filled with a resin material. Sealing processing chamber 6
The 0565 is equipped with a dispenser for drawing a sealing material, mechanical elements such as a fixed stage and an arm for fixing the sealing plate facing the element substrate, a dispenser or a spin coater for filling the resin material, and the like.

FIG. 97 shows the internal configuration of the film formation processing chamber. The film formation processing chamber is kept under reduced pressure, and in FIG. 97, the inside sandwiched between the top plate 60691 and the bottom plate 60692 is the inside of the chamber, which shows the inside of the chamber kept under reduced pressure.

One or more evaporation sources are provided in the processing chamber. This is because it is preferable to provide a plurality of evaporation sources when forming a plurality of layers having different compositions or co-evaporating different materials. In FIG. 97, evaporation sources 60681a, 60681b, 60681c are attached to evaporation source holder 60680. In FIG. Evaporation source holder 60680 is held by articulated arm 60683 . The multi-joint arm 60683 moves the evaporation source holder 60 by expanding and contracting the joint.
The position of 680 can be freely moved within its movable range. Also, evaporation source holder 606
80 is provided with a distance sensor 60682, evaporation sources 60681a to 60681c and the substrate 606
The distance from 89 may be monitored to control the optimum distance during vapor deposition. In that case, a multi-joint arm that can be displaced in the vertical direction (the Z direction) may be used as the multi-joint arm.

The substrate stage 60686 and the substrate chuck 60687 are paired to fix the substrate 60689 . The substrate stage 60686 may incorporate a heater so that the substrate 60689 can be heated. The substrate 60689 is fixed to the substrate stage 60686 and loaded/unloaded by releasing/releasing the substrate chuck 60687 . In vapor deposition, a shadow mask 60690 having openings corresponding to the pattern to be vapor deposited can be used as needed. In that case, shadow mask 60690 includes substrate 60689 and evaporation sources 60681a-60681c.
be placed between The shadow mask 60690 is fixed to the substrate 60689 by a mask chuck 60688 in close contact or with a certain gap. shadow mask 6
When alignment of 0690 is necessary, a camera is placed in the processing chamber, and the mask chuck 60688 is provided with positioning means for finely moving in the XY-θ direction, thereby performing the alignment.

The evaporation source 60681 is added with evaporation material supply means for continuously supplying the evaporation material to the evaporation source. The vapor deposition material supply means includes material supply sources 60685a, 60685b, and 60685c arranged at positions distant from the evaporation source 60681, and a material supply pipe 6068 connecting between them.
4. Typically, material supply sources 60685a, 60685b, and 60685c are provided corresponding to evaporation source 60681 . In the case of FIG. 97, the material supply source 60685a
and 606 evaporation source 81a correspond. material supply source 60685b and evaporation source 60681b,
The same applies to material supply source 60685c and evaporation source 60681c.

An airflow transport method, an aerosol method, or the like can be applied as a supply method of the vapor deposition material. In the airflow transport method, the fine powder of the vapor deposition material is placed on an airflow and transported to the evaporation source 60681 using an inert gas or the like. In the aerosol method, a raw material liquid in which a vapor deposition material is dissolved or dispersed in a solvent is conveyed, aerosolized by an atomizer, and vapor deposition is performed while the solvent in the aerosol is vaporized. In either case, the evaporation source 60681 is provided with a heating means to evaporate the transported evaporation material to form a film on the substrate 60689 . In the case of FIG. 97, the material supply pipe 60684
It is composed of thin tubes that can be flexibly bent and are rigid enough not to deform even under reduced pressure.

When the airflow transport method or the aerosol method is applied, the film formation may be performed under a reduced pressure of 133 Pa to 13300 Pa, which is preferably atmospheric pressure or less in the film formation processing chamber. The deposition treatment chamber can be filled with an inert gas such as helium, argon, neon, krypton, xenon, or nitrogen, or the pressure can be adjusted while supplying the gas (while evacuating at the same time). Further, in a film formation treatment chamber in which an oxide film is formed, a gas such as oxygen or nitrous oxide may be introduced to create an oxidizing atmosphere. Further, a reducing atmosphere may be created by introducing a gas such as hydrogen into a film formation processing chamber in which an organic material is deposited.

As another vapor deposition material supply method, a screw may be provided in the material supply pipe 60684 to continuously push out the vapor deposition material toward the evaporation source.

According to this vapor deposition apparatus, even a display panel with a large screen can be formed continuously with good uniformity. Moreover, since it is not necessary to replenish the vapor deposition material every time the vapor source runs out of the vapor deposition material, the throughput can be improved.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 12)
In this embodiment mode, a pixel circuit and a driving method of a display device that can implement this embodiment mode will be described.

First, digital time grayscale driving applicable to this embodiment will be described. First, a driving method in which a signal writing period (address period) and a light emission period (sustain period) are separated into pixels will be described with reference to FIG. Here, as an example, the case of 4-bit digital time gradation will be described.

A period for completely displaying an image for one display area is called one frame period. One frame period has a plurality of subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required to write signals to all rows of pixels, and the periods Tb1 to Tb4 indicate the time required to write signals to one row of pixels (or one pixel). Further, the sustain periods Ts1 to Ts4 indicate the time during which the lighting or non-lighting state is maintained according to the video signal written to the pixels, and the length ratio is Ts1:Ts2:Ts3:Ts4=2 ³ :2 ² : 2 ¹ :2 ⁰ =8:4:2:1. Gradation is expressed depending on which sustain period the light is emitted.

Operation will be explained. First, in the address period Ta1, pixel selection signals are input to the scanning lines in order from the first row, and the pixels are selected. Then, when the pixel is selected, a video signal is input to the pixel from the signal line. Then, when a video signal is written to the pixel, the pixel holds that signal until the signal is input again. Lighting/non-lighting of each pixel in the sustain period Ts1 is controlled by the written video signal. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3 and Ta4, and lighting and non-lighting of the pixels in the sustain periods Ts2, Ts3 and Ts4 are controlled by the video signals. Then, in each sub-frame period, the pixels which are not lit during the address period and to which the sustain period starts after the end of the address period and to which the signal for lighting is written are lit.

Here, with reference to FIG. 98B, description will be made focusing on the i-th pixel row. First, in the address period Ta1, pixel selection signals are input to the scanning lines in order from the first row, and the address period T
The i-th row pixel is selected in period Tb1(i) in a1. Then, when the i-th pixel is selected, a video signal is input from the signal line to the i-th pixel. and,
When a video signal is written to the i-th pixel, the i-th pixel holds the signal until the signal is input again. Lighting/non-lighting of the pixels in the i-th row during the sustain period Ts1 is controlled by the written video signal. Similarly, the address periods Ta2, Ta3, T
At a4, a video signal is input to the pixels in the i-th row, and the video signal controls lighting and non-lighting of the pixels in the i-th row during the sustain periods Ts2, Ts3, and Ts4. Then, in each sub-frame period, the pixels which are not lit during the address period and to which the sustain period starts after the end of the address period and to which the signal for lighting is written are lit.

Although the case of expressing 4-bit gradation has been described here, the number of bits and the number of gradations are not limited to this. Also, the order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random, or may be divided into a plurality of parts to emit light. Also, Ts1, Ts2
, Ts3, and Ts4 do not have to be powers of two, and may be of the same length, or may be slightly shifted from the powers of two.

Next, a driving method when a signal writing period (address period) to pixels and a light emission period (sustain period) are not separated will be described. In other words, the pixels in the row for which the video signal writing operation is completed hold the signal until the signal is written (or erased) to the pixels next time. A period from the write operation to the next writing of a signal to this pixel is called a data retention time. During this data retention time, the pixels are turned on or off according to the video signal written to the pixels. The same operation is performed until the last row, ending the address period. Then, the signal write operation in the next subframe period is started sequentially from the row whose data holding time has expired.

As described above, in the case of the driving method in which the pixels are turned on or off according to the video signal written to the pixels immediately after the signal writing operation is completed and the data holding time has come, it is attempted to make the data holding time shorter than the address period. However, since signals cannot be input to two rows at the same time, the address periods must not overlap, so the data retention time cannot be shortened. Therefore, as a result, it becomes difficult to perform high gradation display.

Therefore, by providing an erase period, a data retention time shorter than the address period is set. A driving method in which an erasing period is provided and a data holding time shorter than the address period is set will be described with reference to FIG.

First, in the address period Ta1, pixel scanning signals are input to the scanning lines in order from the first row,
A pixel is selected. Then, when the pixel is selected, a video signal is input to the pixel from the signal line. Then, when a video signal is written to the pixel, the pixel holds that signal until the signal is input again. The sustain period Ts1 is set by this written video signal.
lighting and non-lighting of each pixel in . In a row for which the video signal write operation has been completed, the pixels are turned on or off according to the immediately written video signal. The same operation is performed up to the last row, ending the address period Ta1. Then, the signal write operation in the next subframe period is started sequentially from the row whose data holding time has expired. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3 and Ta4, and lighting and non-lighting of the pixels in the sustain periods Ts2, Ts3 and Ts4 are controlled by the video signals. The end of the sustain period TS4 is set by the start of the erasing operation. This is because when the signal written to the pixel is erased during the erasing time Te of each row, until the signal is written to the next pixel, regardless of the video signal written to the pixel during the address period, the signal is forcibly erased. This is because the light is essentially turned off. That is, the data retention time ends from the pixels in the row where the erasing time Te started.

Here, with reference to FIG. 99B, description will be made focusing on the i-th pixel row. In the i-th pixel row, in the address period Ta1, pixel scanning signals are input to the scanning lines in order from the first row, and the pixels are selected. Then, when the i-th pixel is selected in the period Tb1(i), the video signal is input to the i-th pixel. Then, when the video signal is written to the i-th pixel, the i-th pixel holds the signal until the signal is input again. Lighting/non-lighting of the i-th row pixels in the sustain period Ts1(i) is controlled by the written video signal. That is, when the video signal write operation is completed in the i-th row,
The i-th row pixels are turned on or off according to the immediately written video signal. Similarly, a video signal is input to the pixels in the i-th row during the address periods Ta2, Ta3 and Ta4, and the video signals control the lighting and non-lighting of the pixels in the i-th row during the sustain periods Ts2, Ts3 and Ts4. The end of the sustain period Ts4(i) is set by the start of the erasing operation. This is because the pixels of the i-th row are forcibly turned off regardless of the video signal written to the pixels of the i-th row during the erasing time Ts(i) of the i-th row. That is, when the erasing time Te(i) starts, the data retention time of the i-th row pixels ends.

Therefore, without separating the address period and the sustain period, it is possible to provide a display device with a high gradation that is shorter than the address period and a high duty ratio (ratio of the lighting period in one frame period). In addition, since the instantaneous luminance can be lowered, the reliability of the display element can be improved.

Although the case of expressing 4-bit gradation has been described here, the number of bits and the number of gradations are not limited to this. Moreover, the order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random, or may be divided into a plurality of parts to emit light. Also, Ts1, Ts2,
The lighting times of Ts3 and Ts4 do not need to be powers of two, and may be the same length of lighting times, or may be slightly shifted from powers of two.

100A, 100B, 100C, 100D and 100E for the pixel configuration capable of digital time grayscale driving described in FIGS. 98A and 99A. will be described with reference to As the display elements shown in FIGS. 100(A), (B), (C), (D) and (E), EL
Devices (organic EL devices, inorganic EL devices or EL devices containing organic and inorganic substances), electron emission devices, liquid crystal devices, electronic inks, grating light valves (GLV), digital micromirror devices (DMD), carbon nanotubes, etc., electrical A display medium whose contrast is changed by a magnetic action can be applied. 100(A), (B), (
For the pixels shown in C), (D) and (E), a self-luminous element such as an EL element is suitable as a display element. Although FIGS. 100A, 100B, 100C, 100D and 100E show only one pixel, pixels are arranged in a matrix in the row and column directions in the pixel portion of the display device. A plurality of pixels are arranged.

A pixel illustrated in FIG. 100A includes a switching transistor 80301a, a driving transistor 80302a, and a capacitor 80304a. The switching transistor 80301a has a gate terminal connected to the scanning line 80312a, a first terminal (source terminal or drain terminal) connected to the signal line 80311a, and a second terminal (source terminal or drain terminal) connected to the driving transistor 80302a. Connected to the gate terminal. Further, the second terminal of the switching transistor 80301a is connected to the power supply line 8 through the capacitor 80304a.
0313a. Further, the driving transistor 80302a has a first terminal connected to the power supply line 80313a and a second terminal connected to the first electrode of the display element 80320a. A low power supply potential is set to the second electrode 80321a of the display element 80320a. Note that the low power supply potential is a potential that satisfies low power supply potential<high power supply potential with reference to the high power supply potential set to the power supply line 80313a. Also good. A display element 80320 displays the potential difference between the high power potential and the low power potential.
a to pass a current through the display element 80320a to cause the display element 80320a to emit light. Set the potential. Note that the capacitor 80304a can be omitted by substituting the gate capacitance of the driving transistor 80302a. As for the gate capacitance of the driving transistor 80302a, the capacitance may be formed in a region where a source region, a drain region, an LDD region, or the like overlaps with the gate electrode. A capacitance may be formed between

When a pixel is selected by the scanning line 80312a, that is, when the switching transistor 8
A video signal is input to the pixel from the signal line 80311a when 0301a is on. Then, a charge corresponding to a voltage corresponding to the video signal is accumulated in the capacitor 80304a,
The capacitor 80304a holds the voltage. This voltage is applied to the driving transistor 80302
a, and corresponds to the gate-source voltage Vgs of the driving transistor 80302a.

In general, the operating region of a transistor can be divided into a linear region and a saturation region. The boundary is (Vgs−Vth)=Vds, where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. (Vgs−Vth)>Vds
is a linear region, and the current value is determined by the magnitudes of Vds and Vgs. on the other hand,(
Vgs-Vth)<Vds is in the saturation region. Ideally, even if Vds changes,
The current value hardly changes. That is, the current value is determined only by the magnitude of Vgs.

Here, in the case of the voltage input voltage driving method, a video signal is input to the gate terminal of the driving transistor 80302a so that the driving transistor 80302a is sufficiently turned on or turned off. . That is, the driving transistor 80302a is operated in the linear region.

Therefore, when the video signal turns on the driving transistor 80302a, the power supply potential VDD set to the power supply line 80313a is ideally applied to the display element 80320 as it is.
Set to the first electrode of a.

That is, ideally, the voltage applied to the display element 80320a is constant, and the display element 8032a
Make the brightness obtained from 0a constant. A plurality of sub-frame periods are provided within one frame period, a video signal is written to pixels in each sub-frame period, lighting or non-lighting of the pixels is controlled in each sub-frame period, and the pixels are lit. Gray scale is expressed by the sum of subframe periods.

Next, the pixel configuration in FIG. 100B will be described. A pixel illustrated in FIG. 100B includes a switching transistor 80301a, a driving transistor 80302a, and a rectifying element
306a, a capacitor 80304a, and a display element 80320b. The switching transistor 80301b has a gate terminal connected to the first scanning line 80312b,
A terminal (source terminal or drain terminal) is connected to the signal line 80311b, and a second terminal (source terminal or drain terminal) is connected to the gate terminal of the driving transistor 80302b. Further, the gate terminal of the driving transistor 80302 is connected to the second scanning line 80314b through the rectifying element 80306a. Also, the switching transistor 80
A second terminal of 301b is connected to a power supply line 80313b through a capacitive element 80304b. Further, the driving transistor 80302b has a first terminal connected to the power supply line 80313b and a second terminal connected to the first electrode of the display element 80320b. display element 8032
A low power supply potential is set to the second electrode 80321b of 0b. Note that the low power supply potential is a potential that satisfies low power supply potential<high power supply potential with reference to the high power supply potential set to the power supply line 80313b. Also good.
By applying the potential difference between the high power supply potential and the low power supply potential to the display element 80320b, the display element 8
0320b to cause the display element 80320b to emit light, the respective potentials are set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80320b. Note that the capacitor 80304b can be omitted by substituting the gate capacitance of the driving transistor 80302b. As for the gate capacitance of the driving transistor 80302b, a capacitance may be formed in a region where a source region, a drain region, an LDD region, or the like overlaps the gate electrode, or the channel region and the gate electrode may overlap. A capacitance may be formed between

In this pixel configuration, a rectifying element 80306a and a second scanning line 8031
4b is added. Therefore, the switching transistor 80301b, the driving transistor 80302b, the capacitor 80304b, the signal line 80311b, the first scanning line 80312b, and the power supply line 80313b are connected to the switching transistor 80301b, respectively.
a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, a scanning line 80312a, and a power supply line 80313a.

An erasing operation will be described. In erasing operation, an H level signal is input to the second scanning line 80314b. Then, current flows through the rectifying element 80306a, and the gate potential of the driving transistor 80302b held by the capacitor 80304b can be set to a certain potential. In other words, the potential of the gate terminal of the driving transistor 80302b is set to a certain potential, and regardless of the video signal written to the pixel, the driving transistor 80302b
b can be forced off.

Note that the L-level signal input to the second scanning line 80314b is set to a potential such that current does not flow through the rectifying element 80306a when a video signal that turns off lighting is written in the pixel. In addition, the H-level signal input to the second scan line 80314b is a potential at which the gate terminal can be set to a potential that turns off the driving transistor 80302b regardless of the video signal written to the pixel. and

Note that a diode-connected transistor can be used for the rectifying element 80306a. Furthermore, in addition to diode-connected transistors, PN junction or PIN junction diodes, Schottky diodes, diodes made of carbon nanotubes, or the like may be used. FIG. 100C shows a case where a diode-connected N-channel transistor is applied. A first terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal of the driving transistor 80302c. Also,
A second terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal and is connected to the second scan line 80314c. Then, when the second scanning line 80314c is at the L level, the diode-connected transistor 80303c has its gate terminal and source terminal connected to each other, so that no current flows.
When an H level signal is input to c, the second terminal of the diode-connected transistor 80303c becomes the drain terminal, so that current flows through the diode-connected transistor 80303c.
Therefore, the diode-connected transistor 80303c has a rectifying effect.

Note that a switching transistor 80301c, a driving transistor 80302c, a capacitor 80304c, a signal line 80311c, a first scan line 80312c, and a power supply line 8031
3c denotes a switching transistor 80301a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, and a scanning line 8031 in FIG.
2a, which corresponds to the power line 80313a. Also, the second scanning line 80314c is shown in FIG.
B) corresponds to the second scanning line 80312d.

FIG. 100D shows a case where a diode-connected P-channel transistor is applied. A first terminal (source terminal or drain terminal) of diode-connected transistor 80303d is connected to second scan line 80313d. Also, the diode-connected transistor 803
03d is connected to the gate terminal and the gate terminal of the driving transistor 80302d. Then, the second scanning line 8031
3d is at the L level, the diode-connected transistor 80303d has its gate terminal and source terminal connected to each other, so that no current flows. Since the second terminal serves as a drain terminal, a current flows through the diode-connected transistor 80303d. Therefore, the diode-connected transistor 80303d has a rectifying effect.

Note that a switching transistor 80301d, a driving transistor 80302d, a capacitor 80304d, a signal line 80311d, a first scan line 80312d, and a power supply line 8031
3d denotes a switching transistor 80301a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, and a scanning line 8031 in FIG.
2a, which corresponds to the power line 80313a. Also, the second scanning line 80314d is shown in FIG.
B) corresponds to the second scanning line 80312d.

Further, an erasing transistor may be provided to erase the signal written to the pixel.
The pixel shown in FIG. 100E has an erasing transistor 80303e in the pixel shown in FIG. 100A.
and a second scanning line 80312e. Therefore, a switching transistor 80301e, a driving transistor 80302e, a capacitor 80304e, and a signal line 80
311e, the first scanning line 80312e, and the power supply line 80313e are shown in FIG.
, the switching transistor 80301a, the driving transistor 80302a, the capacitor 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a.

An erasing operation will be described. In erasing operation, an H level signal is input to the second scanning line 80312e. Then, the erasing transistor 80303e is turned on, and the gate terminal and the first terminal of the driving transistor 80302e can be made to have the same potential. That is, the gate-source voltage of the driving transistor 80302e can be set to 0V. The H-level potential of the second scanning line 80312e is preferably higher than the potential of the power supply line 80313e by at least the threshold voltage Vth of the erasing transistor 80303e. Thus, the driving transistor 80302e can be forcibly turned off.

Next, an example of a threshold voltage correction pixel circuit and a driving method applicable to this embodiment will be described with reference to FIG.

A pixel illustrated in FIG. 101A includes a driving transistor 80400 and a first switch 80401.
, a second switch 80402, a third switch 80403, a first capacitive element 80404,
It has a second capacitor 80405 and a display element 80420 . drive transistor 80
400 has a gate terminal connected to a signal line 80411 via a first capacitive element 80404 and a first switch 80401 in that order, a first terminal connected to a power supply line 80412, and a second terminal connected to a third switch 80403. is connected to the first electrode of the display element 80420 through the . Furthermore, the gate terminal of the driving transistor 80400 is connected to the power line 80412 through the second capacitor 80405 . Also, the gate terminal of the driving transistor 80400 is connected to the second terminal of the driving transistor 80400 via the second switch 80402 . A low power supply potential is set to the second electrode 80421 of the display element 80420 . Note that the low power supply potential is a potential that satisfies low power supply potential<high power supply potential with reference to the high power supply potential set to the power supply line 80412. As the low power supply potential, for example, GND, 0 V, or the like is set. Also good. A display element 80420 displays the potential difference between the high power potential and the low power potential.
to cause a current to flow through the display element 80420 to cause the display element 80420 to emit light.
Each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80420 . Note that the gate capacitance of the driving transistor 80400 can be substituted for the second capacitor 80405 and omitted. drive transistor 80
As for the gate capacitance 400, the capacitance may be formed in a region where the source region, the drain region, the LDD region, or the like overlaps the gate electrode, or may be formed between the channel region and the gate electrode. may form a capacitor. Note that the first switch 8
0401, the second switch 80402, and the third switch 80403 are controlled to be on/off by the first scanning line 80413, the second scanning line 80414, and the third scanning line 80415, respectively.

The pixel driving method shown in FIG. 101A can be divided into an initialization period, a data writing period, a threshold acquisition period, and a light emission period.

In the initialization period, the second switch 80402 and the third switch 80403 are turned on,
The potential of the gate terminal of the driving transistor 80400 is at least lower than the potential of the power supply line 80412 . Note that at this time, the first switch 80401 may be on or off. Note that the initialization period is not necessarily required.

During the threshold acquisition period, pixels are selected by the first scanning line 80413 . That is, the first switch 80401 is turned on and a certain constant voltage is input from the signal line 80411 . At this time, the second switch 80402 is on, and the driving transistor 80400 is diode-connected. Also, the third switch 80403 is off. Therefore, the potential of the gate terminal of the drive transistor 80400 becomes a value obtained by subtracting the threshold voltage of the drive transistor 80400 from the potential of the power supply line 80412 . The threshold voltage of the driving transistor 80400 is held in the first capacitor 80404 . In addition, the second capacitor 80405
holds the potential difference between the potential of the gate terminal of the driving transistor 80400 and the constant voltage input from the signal line 80411 .

A video signal (voltage) is input from the signal line 80411 in the data writing period. At this time, the first switch 80401 remains on, the second switch 80402 turns off, and the second switch 80402 remains off. Also, the drive transistor 80400
is in a floating state. Therefore, the potential of the gate terminal of the driving transistor 80400 changes according to the potential difference between the constant voltage input to the signal line 80411 during the threshold acquisition period and the video signal input to the signal line 80411 during the data writing period. For example, if the capacitance value of the first capacitor 80404 <<the capacitance value of the second capacitor 80405, the potential of the gate terminal of the driving transistor 80400 during the data writing period is the same as that of the signal line 80411 input during the threshold value acquisition period. The potential difference between the constant voltage applied and the video signal input to the signal line 80411 during the data write period is approximately equal to the value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80412 plus the value. That is, the potential of the gate terminal of the driving transistor 80400 is the potential obtained by correcting the threshold voltage of the driving transistor 80400 .

In the light emission period, a current flows through the display element 80420 according to the potential difference (Vgs) between the potential of the gate terminal of the driving transistor 80400 and the power supply line 80412 . At this time, the first switch 80401 is turned off, the second switch 80402 remains off, and the third switch 80403 is turned on. Note that the current flowing through the display element 80420 is
It is constant regardless of the threshold voltage of 0400.

Note that the pixel configuration shown in FIG. 101A is not limited to that in FIG. For example, Figure 1
A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01(A). Further, for example, the second switch 80402 is composed of a P-channel transistor or an N-channel transistor, the third switch 80403 is composed of a transistor with a polarity different from that of the second switch 80402, and the second switch 80402 and the third switch 80403 may be controlled by the same scanning line.

Subsequently, an example of a current-input pixel circuit and a driving method applicable to the present embodiment will be described below.
Description will be made with reference to FIG.

A pixel illustrated in FIG. 101B includes a driving transistor 80430 and a first switch 8043.
1, a second switch 80432, a third switch 80433, a capacitor 80434, and a display element 80450. The driving transistor 80430 has a gate terminal connected to the signal line 80441 through the second switch 80432 and the first switch 80431 in that order, a first terminal connected to the power supply line 80442, and a second terminal connected to the third switch. It is connected to the first electrode of the display element 80450 through the switch 80433 . Further, the gate terminal of the driving transistor 80430 is connected to the power supply line 80442 through the capacitor 80434 . Also, the gate terminal of the driving transistor 80430 is connected to the second terminal of the driving transistor 80430 through the second switch 80432 . Also, the display element 804
A low power supply potential is set to the second electrode 80451 of 50 . In addition, the low power supply potential is
It is a potential that satisfies low power supply potential<high power supply potential with reference to the high power supply potential set to the power supply line 80442. As the low power supply potential, for example, GND, 0 V, or the like may be set. By applying the potential difference between the high power supply potential and the low power supply potential to the display element 80450, the display element 8045 is displayed.
0 to cause the display element 80450 to emit light, the respective potentials are set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80450 . Note that the capacitive element 80434 can be omitted by using the gate capacitance of the driving transistor 80430 instead. Regarding the gate capacitance of the driving transistor 80430,
A capacitance may be formed in a region where a source region, a drain region, an LDD region, or the like overlaps a gate electrode, or a capacitance may be formed between a channel region and a gate electrode. good too. Note that the first switch 80431 and the second switch 804
32, the third switch 80433 switches the first scanning line 80443, the second scanning line 8, respectively.
0444, the third scanning line 80445 controls on/off.

The pixel driving method shown in FIG. 101B can be divided into a data writing period and a light emitting period.

A pixel is selected by the first scanning line 80443 in the data writing period. In other words,
The first switch 80431 is turned on, and current is input from the signal line 80441 as a video signal. At this time, the second switch 80432 is turned on and the third switch 80433 is turned off. Therefore, the potential of the gate terminal of the driving transistor 80430 becomes a potential corresponding to the video signal. That is, the driving transistor 80430 is connected to the capacitive element 80434
A voltage between the gate and the source of the driving transistor 80430 is held such that the same current as the video signal flows.

Next, in the light emission period, the first switch 80431 and the second switch 80432 are turned off, and the third switch 80433 is turned on. Therefore, a current having the same value as the video signal flows through the display element 80450 .

Note that the pixel configuration shown in FIG. 101B is not limited to that in FIG. For example, Figure 1
A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in 01B. Further, for example, the first switch 80431 is composed of a P-channel transistor or an N-channel transistor, the second switch 80432 is composed of a transistor having the same polarity as the first switch 80431, and the first switch 80431 and the 2 switches 80432 may be controlled by the same scan line. Also, the second switch 8043
2 may be arranged between the gate terminal of the driving transistor 80430 and the signal line 80441 .

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 13)
In this embodiment, a semiconductor device to which this embodiment can be applied is a thin film transistor (TF
A method for manufacturing a semiconductor device having T) as an element will be described with reference to the drawings.

FIG. 102 is a diagram showing an example of the structure and manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment can be applied. FIG. 102A is a diagram showing an example of the structure of a TFT that can be included in a semiconductor device to which this embodiment mode can be applied. Also, FIG. 102(B)
FIGS. 4A to 4G show an example of a manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment mode can be applied; FIGS.

Note that the structure and manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment mode can be applied are not limited to those shown in FIGS. 102A and 102B, and various structures and manufacturing processes can be used.

First, an example of a TFT structure that can be included in a semiconductor device to which this embodiment mode can be applied is described with reference to FIG. FIG. 102(A) shows a T having a plurality of different structures.
It is a sectional view of FT. Here, in FIG. 102(A), T having a plurality of different structures
Although the FTs are shown side by side, this is an expression for explaining the structure of the TFT that the semiconductor device to which the invention can be applied can have, and the TFT that the semiconductor device to which the invention can be applied can have Actually, they do not have to be juxtaposed as shown in FIG.

Next, the characteristics of each layer constituting a TFT that can be included in a semiconductor device to which this embodiment mode can be applied will be described.

As the substrate 110111, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET), polyethylene naphthalate (P
EN), polyethersulfone (PES), or a flexible synthetic resin such as acrylic. A flexible semiconductor device can be manufactured by using a flexible substrate. In addition, as long as the substrate is flexible, there are no major restrictions on the area and shape of the substrate. , productivity can be significantly improved. Such an advantage is a great advantage compared with the case of using a circular silicon substrate.

The insulating film 110112 functions as a base film. It is provided to prevent alkali metals such as Na or alkaline earth metals from the substrate 110111 from adversely affecting the characteristics of the semiconductor element. As the insulating film 110112, an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y). A single layer structure or a laminated structure of these layers can be provided.
For example, when the insulating film 110112 has a two-layer structure, a silicon nitride oxide film is preferably provided as the first insulating film, and a silicon oxynitride film is preferably provided as the second insulating film. Also, the insulating film 110
When 112 is provided with a three-layer structure, a silicon oxynitride film is provided as the first insulating film, a silicon nitride oxide film is provided as the second insulating film, and a silicon oxynitride film is provided as the third insulating film. Good.

The semiconductor films 110113, 110114, and 110115 can be made of an amorphous semiconductor or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor film may be used. SAS is a semiconductor that has an intermediate structure between an amorphous structure and a crystalline structure (including single crystal and polycrystal) and has a free energy stable third state, and has short-range order and a lattice structure. It contains strained crystalline regions. A crystal region of 0.5 to 20 nm can be observed in at least ^a part of the film. there is In X-ray diffraction, diffraction peaks of (111) and (220) are observed, which are believed to be derived from the silicon crystal lattice. dangling hand (
At least 1 atomic % or more of hydrogen or halogen is included as compensation for dangling bonds. SAS is formed by glow discharge decomposition (plasma CVD) of a material gas. As a material gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , S
iHCl ₃ , SiCl ₄ , SiF ₄ and the like can be used. Alternatively, _GeF4
may be mixed. This material gas may be diluted with _H2 , or _H2 and one or more rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate ranges from 2 to 1000 times. The pressure is approximately in the range of 0.1 Pa to 133 Pa, the power frequency is 1 MHz to 120 MHz,
Preferably from 13MHz to 60MHz. The substrate heating temperature may be 300° C. or lower. As impurity elements in the film, it is desirable that the concentration of impurities of atmospheric components such as oxygen, nitrogen, and carbon be 1×10 ²⁰ cm ⁻¹ or less, and in particular, the oxygen concentration be 5×10 ¹⁹ /cm ³ or less, preferably 1×10 19 cm −1 or less. × 10 ^1
9 /cm ³ or less. Here, known means (sputtering method, LPCVD method, plasma C
Materials containing silicon (Si) as the main component (eg, SixGe1-x, etc.) using the VD method, etc.)
Then, the amorphous semiconductor film is subjected to known methods such as a laser crystallization method, a thermal crystallization method using RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, and the like. crystallize by the crystallization method of

The insulating film 110116 is made of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (
An insulating film containing oxygen or nitrogen such as SiOxNy) (x>y) or silicon nitride oxide (SiNxOy) (x>y) can be provided with a single-layer structure or a laminated structure of these.

The gate electrode 110117 can have a single-layer conductive film or a laminated structure of two-layer or three-layer conductive films. As a material for the gate electrode 110117, a known conductive film can be used. For example, a simple film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), or silicon (Si), or a nitride film of the element (typically tantalum nitride film, tungsten nitride film, titanium nitride film), or an alloy film combining the above elements (typically Mo--W alloy, Mo--Ta alloy), or a silicide film of the above elements (typically tungsten silicide film, titanium silicide film, etc. can be used. Note that the above-described single film, nitride film, alloy film, silicide film, and the like may be used as a single layer, or may be used as a laminate.

The insulating film 110118 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y),
An insulating film containing oxygen or nitrogen such as silicon oxynitride (SiNxOy) (x>y) or DLC (
It can be provided with a single-layer structure of a film containing carbon such as diamond-like carbon) or a laminated structure of these.

The insulating film 110119 is made of siloxane resin, silicon oxide (SiOx), silicon nitride (S
iNx), silicon oxynitride (SiOxNy) (x>y), silicon oxynitride (SiNxOy) (
x>y) insulating films containing oxygen or nitrogen, films containing carbon such as DLC (diamond-like carbon), or epoxy, polyimide, polyamide, polyvinylphenol,
It can be provided in a single layer or laminated structure made of an organic material such as benzocyclobutene or acryl. Note that the siloxane resin corresponds to a resin containing a Si—O—Si bond. Siloxane has a skeletal structure composed of bonds of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (eg, alkyl group, aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as substituents. In addition, in the semiconductor device according to the present embodiment, it is also possible to directly provide the insulating film 110119 so as to cover the gate electrode 110117 without providing the insulating film 110118 .

The conductive film 110123 is Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, M
A single film of an element such as n, a nitride film of the element, an alloy film of a combination of the elements, a silicide film of the element, or the like can be used. For example, as an alloy containing a plurality of elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, etc. can be used. In the case of providing a laminated structure, a structure in which Al is sandwiched between Mo, Ti, or the like can be employed. By doing so, the resistance of Al to heat and chemical reaction can be improved.

Next, with reference to cross-sectional views of TFTs having a plurality of different structures shown in FIG.
The characteristics of each structure will be explained.

110101 is a single-drain TFT and can be manufactured by a simple method, so that it has the advantage of low manufacturing cost and high yield. Here, the semiconductor films 110113, 1
10115 have different impurity concentrations, semiconductor films 110113 are channel regions,
The semiconductor film 110115 is used as source and drain regions. By controlling the amount of impurities in this manner, the resistivity of the semiconductor film can be controlled. In addition, the semiconductor film and the conductive film 11
0123 can be brought closer to an ohmic connection. Note that as a method of separately forming semiconductor films with different amounts of impurities, a method of doping impurities into semiconductor films using the gate electrode 110117 as a mask can be used.

110102 is a TFT having a taper angle of a certain value or more in the gate electrode 110117, and can be manufactured by a simple method, so that it has the advantage of low manufacturing cost and high yield. Here, the semiconductor films 110113, 110114, and 110115 have different impurity concentrations.
are used as source and drain regions. By controlling the amount of impurities in this manner, the resistivity of the semiconductor film can be controlled. In addition, the electrical connection state between the semiconductor film and the conductive film 110123 can be brought closer to ohmic connection. Moreover, since it has an LDD region,
A high electric field is less likely to be applied inside the TFT, and deterioration of the element due to hot carriers can be suppressed. As a method for separately forming semiconductor films with different amounts of impurities, the gate electrode 11
A method of doping an impurity into a semiconductor film using 0117 as a mask can be used.
In 110102, since the gate electrode 110117 has a taper angle equal to or greater than a certain value, the concentration of the impurity that passes through the gate electrode 110117 and is doped into the semiconductor film can have a gradient, and the LDD region can be easily formed. can be formed.

110103 is a TFT having a gate electrode 110117 composed of at least two layers, the lower gate electrode being longer than the upper gate electrode. In this specification, the shape of the upper gate electrode and the lower gate electrode is referred to as a hat shape. Gate electrode 110117
, the LDD region can be formed without adding a photomask. Note that, like 110103, the LDD region is the gate electrode 11011.
7, especially the GOLD structure (Gate Overlapped LDD
). As a method for making the shape of the gate electrode 110117 hat-shaped, the following method may be used.

First, when the gate electrode 110117 is patterned, the lower layer gate electrode and the upper layer gate electrode are etched by dry etching to form a tapered shape on the side surface. Subsequently, anisotropic etching is performed so that the inclination of the upper gate electrode is almost vertical. As a result, a gate electrode having a hat-shaped cross section is formed. After that, twice
A semiconductor film 1101 used as a channel region is formed by doping an impurity element.
13. Semiconductor films 110114 used as LDD regions and semiconductor films 110115 used as source and drain electrodes are formed.

Note that the LDD region overlapping with the gate electrode 110117 is the Lov region, and the gate electrode 11
An LDD region that does not overlap with 0117 is called a Loff region. where Lof
The f region has a high effect of suppressing the off-current value, but has a low effect of alleviating the electric field in the vicinity of the drain to prevent deterioration of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field in the vicinity of the drain and is effective in preventing deterioration of the on-current value, but is less effective in suppressing the off-current value. Therefore, it is preferable to manufacture a TFT having a structure corresponding to required characteristics for each of various circuits. For example, when the semiconductor device of this embodiment is used as a display device, a pixel TFT
, it is preferable to use a TFT having a Loff region in order to suppress the off current value. On the other hand, it is preferable to use a TFT having an Lov region as the TFT in the peripheral circuit in order to relax the electric field in the vicinity of the drain and prevent deterioration of the ON current value.

110104 is in contact with the side surface of the gate electrode 110117 and the sidewall 110121
is a TFT having By having the sidewall 110121, a region overlapping with the sidewall 110121 can be an LDD region.

110105 is LDD (Lof
f) TFTs with formed regions. By doing so, the LDD region can be reliably formed, and the off current value of the TFT can be reduced.

110106 is LDD (Lov
) region. By doing so, the LDD region can be reliably formed, the electric field in the vicinity of the drain of the TFT can be relaxed, and deterioration of the on-current value can be reduced.

Next, with reference to FIGS. 102B to 102G, an example of a manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment mode can be applied will be described.
Note that the structure and manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment mode can be applied are not limited to those shown in FIGS. 102A and 102B, and various structures and manufacturing processes can be used.

In this embodiment, on the surface of the substrate 110111, on the surface of the insulating film 110112, on the surface of the semiconductor film 110113, on the surface of 110114, on the surface of 110115, the insulating film 1
By oxidizing or nitriding the surface of the insulating film 110118 or the surface of the insulating film 110119 using plasma treatment, the semiconductor film or the insulating film can be oxidized or nitrided. In this way, by oxidizing or nitriding the semiconductor film or the insulating film using the plasma treatment, the surface of the semiconductor film or the insulating film is modified and C
Since a denser insulating film can be formed than the insulating film formed by the VD method or the sputtering method, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved.

First, the surface of the substrate 110111 is washed with hydrofluoric acid (HF), alkali or pure water. As the substrate 110111, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET), polyethylene naphthalate (
PEN), polyether sulfone (PES), or a flexible synthetic resin such as acryl may be used as the substrate. Note that the case where a glass substrate is used as the substrate 110111 is shown here.

Here, an oxide film or a nitride film may be formed on the surface of the substrate 110111 by performing plasma treatment on the surface of the substrate 110111 to oxidize or nitride the surface of the substrate 110111 (FIG. 102B). . An insulating film such as an oxide film or a nitride film formed by subjecting a surface to plasma treatment is hereinafter also referred to as a plasma-treated insulating film. In FIG. 102B, the insulating film 110131 is the plasma-treated insulating film. In general, when a semiconductor element such as a thin film transistor is provided on a substrate such as glass or plastic, impurity elements such as alkali metals or alkaline earth metals such as Na contained in glass or plastic are mixed into the semiconductor element. Contamination can affect the properties of semiconductor devices. However, by nitriding the surface of the substrate made of glass, plastic, or the like, it is possible to prevent impurity elements such as Na contained in the substrate, such as alkali metals or alkaline earth metals, from entering the semiconductor element.

When the surface is oxidized by plasma treatment, it should be performed in an oxygen atmosphere (for example, oxygen (O ₂
) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or an atmosphere of oxygen and hydrogen (H ₂ ) and a rare gas, or an atmosphere of dinitrogen monoxide and a rare gas ) for plasma treatment. On the other hand, when the semiconductor film is nitrided by plasma treatment, the nitrogen atmosphere (for example, nitrogen (N ₂ ) and rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, or Plasma treatment is performed in a nitrogen-hydrogen-rare gas atmosphere, or NH ₃ and a rare-gas atmosphere). For example, Ar can be used as the rare gas. Alternatively, a mixed gas of Ar and Kr may be used. Therefore, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. For example, when Ar is used, the plasma-treated insulating film contains Ar.

Further, the plasma treatment has an electron density of 1×10 ¹¹ cm ⁻³ in the above gas atmosphere.
1×10 ¹³ cm ⁻³ or more, and the plasma electron temperature is 0.5 eV or more and 1.5 eV
It is preferred to do the following. Since the electron density of the plasma is high and the electron temperature near the object to be processed is low, the object to be processed can be prevented from being damaged by the plasma. In addition, since the electron density of plasma is as high as 1×10 ¹¹ cm ⁻³ or more, the oxide or nitride film formed by oxidizing or nitriding the object to be irradiated using plasma treatment is C
Compared with films formed by the VD method, the sputtering method, or the like, it is possible to form a dense film with superior uniformity in film thickness and the like. Alternatively, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation treatment can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Unless otherwise specified, the plasma treatment is performed under the above conditions.

Note that FIG. 102B shows the case where the plasma-treated insulating film is formed by subjecting the surface of the substrate 110111 to plasma treatment;
The case where the plasma-treated insulating film is not formed on the surface of 11 is also included.

Although FIGS. 102C to 102G do not show a plasma-treated insulating film formed by plasma-treating the surface of the object to be processed, in this embodiment, the substrate 1
10111, insulating film 110112, semiconductor film 110113, 110114, 110115
, the insulating film 110116, the insulating film 110118, or the insulating film 110119. This also includes the case where a plasma-treated insulating film formed by plasma processing is present.

Next, an insulating film 110112 is formed on the substrate 110111 using known means (sputtering method, LPCVD method, plasma CVD method, etc.) (FIG. 102(C)). As the insulating film 110112, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) can be used.

Here, a plasma-treated insulating film may be formed on the surface of the insulating film 110112 by subjecting the surface of the insulating film 110112 to plasma treatment and oxidizing or nitriding the insulating film 110112 . By oxidizing the surface of the insulating film 110112, the surface of the insulating film 110112 is modified and a dense film with few defects such as pinholes can be obtained. Also, the insulating film 110
By oxidizing the surface of 112, a plasma-treated insulating film having a low N atom content can be formed. improves. Also, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. In addition,
Plasma treatment can similarly be performed under the conditions described above.

Next, island-shaped semiconductor films 110113 and 110114 are formed on the insulating film 110112 (
FIG. 102(D)). The island-shaped semiconductor films 110113 and 110114 are the insulating films 110112
Silicon (
Si) as a main component (for example, SixGe1-x) or the like is used to form an amorphous semiconductor film, the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched. be able to. Crystallization of the amorphous semiconductor film is performed by a laser crystallization method, a thermal crystallization method using RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. can be carried out by the known crystallization method of Here, the end portions of the island-shaped semiconductor films are provided in a shape close to a right angle (θ=85 to 100°).
Alternatively, the semiconductor film 110114 to be the low-concentration drain region may be formed by doping impurities using a mask.

Here, the surfaces of the semiconductor films 110113 and 110114 are subjected to plasma treatment, so that the semiconductor film 1
By oxidizing or nitriding the surfaces of 10113 and 110114, the semiconductor film 1101
13, 110114 may be formed with a plasma-treated insulating film. For example, semiconductor film 1
When Si is used for 10113 and 110114, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the plasma processing insulating film. Alternatively, the semiconductor films 110113 and 110114 may be oxidized by plasma treatment and then nitrided by plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 110113 and 110114, and silicon nitride oxide (SiNxOy) (SiNxOy) is formed on the surface of the silicon oxide.
x>y) is formed. Note that in the case of oxidizing a semiconductor film by plasma treatment, an oxygen atmosphere (for example, an atmosphere containing oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or Plasma treatment is performed using oxygen, hydrogen (H ₂ ), and a rare gas atmosphere, or dinitrogen monoxide and a rare gas atmosphere). On the other hand, when the semiconductor film is nitrided by plasma treatment, nitrogen atmosphere (for example, nitrogen (N ₂ ) and rare gas (He, Ne, Ar, Kr) are used.
, Xe), or under a nitrogen, hydrogen and noble gas atmosphere or _NH3 and a noble gas atmosphere). For example, Ar can be used as the rare gas. Alternatively, a mixed gas of Ar and Kr may be used. Therefore, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. For example, when Ar is used, A
contains r.

Next, an insulating film 110116 is formed (FIG. 102(E)). The insulating film 110116 is formed by using known means (sputtering method, LPCVD method, plasma CVD method, etc.) to form silicon oxide (SiO 2 ).
x), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), silicon oxynitride (SiNxOy) (x>y), or a single-layer structure of an insulating film containing oxygen or nitrogen, or a stack of these can be provided in the structure. Note that when a plasma-treated insulating film is formed on the surfaces of the semiconductor films 110113 and 110114 by subjecting the surfaces of the semiconductor films 110113 and 110114 to plasma treatment, the plasma-treated insulating film can be used as the insulating film 110116. .

Here, a plasma-treated insulating film may be formed on the surface of the insulating film 110116 by subjecting the surface of the insulating film 110116 to plasma treatment and oxidizing or nitriding the surface of the insulating film 110116 . Note that the plasma processing insulating film is made of the rare gas (He, Ne,
, including at least one of Ar, Kr, and Xe). Also, the plasma treatment can be similarly performed under the conditions described above.

Alternatively, the insulating film 110116 may be once oxidized by plasma treatment in an oxygen atmosphere and then nitrided by plasma treatment again in a nitrogen atmosphere. In this manner, the surface of the insulating film 110116 can be reformed and a dense film can be formed by subjecting the insulating film 110116 to plasma treatment and oxidizing or nitriding the surface of the insulating film 110116 . An insulating film obtained by plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that the characteristics of a thin film transistor can be improved.

Next, a gate electrode 110117 is formed (FIG. 102(F)). Gate electrode 110117
can be formed using known means (sputtering method, LPCVD method, plasma CVD method, etc.).

In 110101, the semiconductor film 110115 used as the source region and the drain region can be formed by performing impurity doping after the gate electrode 110117 is formed.

In 110102, by performing impurity doping after forming the gate electrode 110117, 110114 used as LDD regions and semiconductor films 110115 used as semiconductor film source and drain regions can be formed.

In 110103, by performing impurity doping after forming the gate electrode 110117, 110114 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

In 110104, sidewalls 110121 are formed on the side surfaces of the gate electrode 110117 .
110114 which is used as an LDD region by performing impurity doping after forming 110114
Then, a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

Note that the sidewalls 110121 are made of silicon oxide (SiOx) or silicon nitride (SiNx).
) can be used. As a method for forming the sidewalls 110121 on the side surfaces of the gate electrode 110117, for example, after forming the gate electrode 110117, silicon oxide (SiOx) or silicon nitride (SiNx) is formed by a known method, and then an anisotropic film is formed. A method of etching a silicon oxide (SiOx) or silicon nitride (SiNx) film by etching can be used. By doing so, silicon oxide (
SiOx) or silicon nitride (SiNx) film can be left, so the gate electrode 1101
Sidewalls 110121 can be formed on the sides of 17 .

In 110105, a mask 110122 is formed so as to cover the gate electrode 110117, and then impurity doping is performed to use it as an LDD (Loff) region 11.
0114 and semiconductor films 110115 used as semiconductor film source and drain regions.
can be formed.

In 110106, impurity doping is performed after the gate electrode 110117 is formed, so that 110114 used as LDD (Lov) regions and semiconductor films 110115 used as semiconductor film source and drain regions can be formed.

Next, an insulating film 110118 is formed (FIG. 102(G)). The insulating film 110118 is formed of silicon oxide (SiOx), silicon nitride (
SiNx), silicon oxynitride (SiOxNy) (x>y), silicon oxynitride (SiNxOy)
Insulating film containing oxygen or nitrogen such as (x>y) or DLC (diamond-like carbon)
A single-layer structure of a film containing carbon, such as , or a laminated structure of these layers can be provided.

Here, a plasma-treated insulating film may be formed on the surface of the insulating film 110118 by subjecting the surface of the insulating film 110118 to plasma treatment and oxidizing or nitriding the surface of the insulating film 110118 . Note that the plasma processing insulating film is made of the rare gas (He, Ne,
, including at least one of Ar, Kr, and Xe). Also, the plasma treatment can be similarly performed under the conditions described above.

Next, an insulating film 110119 is formed. The insulating film 110119 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), silicon nitride oxide (SiNxOy) ( Insulating films containing oxygen or nitrogen such as x>y) and films containing carbon such as DLC (diamond-like carbon) can be used. In addition, epoxy, polyimide, polyamide, polyvinylphenol,
It can be provided with a single-layer structure of an organic material such as benzocyclobutene or acryl or a siloxane resin, or a laminated structure of these. Note that the siloxane resin corresponds to a resin containing a Si—O—Si bond. Siloxane has a skeletal structure composed of bonds of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (eg, alkyl group, aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as substituents. In addition, the plasma processing insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma processing. Ar is contained in the film.

When an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or the like, or a siloxane resin is used as the insulating film 110119, the insulating film 110119
By oxidizing or nitriding the surface of the insulating film by plasma treatment, the surface of the insulating film can be modified. By modifying the surface, the strength of the insulating film 110119 is improved, and it becomes possible to reduce physical damage such as cracking during formation of openings and film reduction during etching. In addition, since the surface of the insulating film 110119 is modified, adhesion to the conductive film is improved when the conductive film 110123 is formed over the insulating film 110119 .
For example, when a siloxane resin is used as the insulating film 110119 and nitridation is performed by plasma treatment, the surface of the siloxane resin is nitrided to form a plasma-treated insulating film containing nitrogen or a rare gas, which increases physical strength. improves.

Next, in order to form a conductive film 110123 electrically connected to the semiconductor film 110115,
Contact holes are formed in the insulating films 110119 , 110118 , and 110116 . Note that the shape of the contact hole may be tapered. By doing this,
Coverage of the conductive film 110123 can be improved.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 14)
In this embodiment mode, a detailed structure of a light-emitting element that can be applied to a display device that can implement this embodiment mode will be described.

Light-emitting elements utilizing electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to the element structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, while the latter has an electroluminescent layer made of a thin film of a luminescent material. They are common in that they require electrons. Mechanisms of light emission to be obtained include donor-acceptor recombination type light emission using a donor level and an acceptor level and localized type light emission using core electron transition of metal ions. In general, the donor-
In many cases, acceptor recombination type light emission and thin film type inorganic EL devices are local type light emission.

A light-emitting material that can be used in this embodiment mode is composed of a base material and an impurity element serving as a light emission center. Light emission of various colors can be obtained by changing the impurity element to be contained. Various methods such as a solid-phase method and a liquid-phase method (coprecipitation method) can be used as a method for producing a light-emitting material. Alternatively, a spray pyrolysis method, a metathesis method, a method by thermal decomposition reaction of a precursor, a reverse micelle method, a method combining these methods with high-temperature calcination, and a liquid phase method such as a freeze-drying method can be used.

In the solid-phase method, a base material and an impurity element or a compound containing an impurity element are weighed, mixed in a mortar,
In this method, an impurity element is added to the matrix material by heating and firing in an electric furnace to cause a reaction. The firing temperature is preferably 700 to 1500°C. This is because if the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the base material will decompose. It should be noted that the firing may be performed in the powder state, but it is preferable to perform the firing in the pellet state. It requires firing at a relatively high temperature, but since it is a simple method, it is highly productive and suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing the base material and an impurity element or a compound containing an impurity element are reacted in a solution, dried, and then fired. The particles of the luminescent material are uniformly distributed, and the reaction can proceed even at a low firing temperature due to the small particle size.

Sulfides, oxides, and nitrides can be used as base materials for the light-emitting material.
Sulfides include, for example, zinc sulfide ( _ZnS ), cadmium sulfide (CdS), calcium _sulfide (CaS), yttrium sulfide ( _Y2S3 ), gallium sulfide ( _Ga2S3 ), strontium sulfide (SrS), sulfide Barium (BaS) or the like can be used. As oxides, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. Further, as the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), etc. can also be used, and calcium-gallium sulfide (CaGa ₂ S ₄ ), strontium-gallium sulfide (SrGa ₂ S ₄ ), barium-gallium sulfide (BaGa ₂ S ₄ ), etc., may be a ternary mixed crystal.

Manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), and praseodymium as luminescent centers for localized luminescence (Pr) or the like can be used. A halogen element such as fluorine (F) or chlorine (Cl) may be added for charge compensation.

On the other hand, as the emission center of donor-acceptor recombination type emission, the first
and a second impurity element forming an acceptor level can be used. For example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used as the first impurity element. Examples of the second impurity element include copper (Cu),
Silver (Ag) or the like can be used.

When synthesizing a light-emitting material for donor-acceptor recombination-type light emission using a solid-phase method, a base material, a first impurity element or a compound containing the first impurity element, and a second impurity element or a second
are weighed and mixed in a mortar, then heated and fired in an electric furnace. As the base material, the base material described above can be used. Examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), aluminum sulfide (Al ₂ S ₃ ) can be used, and examples of the second impurity element or the compound containing the second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), silver sulfide (Ag _2S ) and the like can be used. The firing temperature is preferably 700 to 1500°C.
This is because if the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the base material will decompose. It should be noted that the firing may be performed in the powder state, but it is preferable to perform the firing in the pellet state.

Further, as the impurity element in the case of using a solid-phase reaction, a compound composed of the first impurity element and the second impurity element may be used in combination. In this case, the impurity element is easily diffused and the solid-phase reaction proceeds easily, so that a uniform light-emitting material can be obtained. Furthermore, since an extra impurity element is not included, a highly pure light-emitting material can be obtained. As the compound composed of the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.

The concentration of these impurity elements may be 0.01 to 10 atom %, preferably 0.05 to 5 atom %, relative to the base material.

In the case of thin-film inorganic EL, the electroluminescent layer is a layer containing the above-described light-emitting material, and the resistance heating deposition method,
Vacuum deposition methods such as electron beam deposition (EB deposition), physical vapor deposition methods such as sputtering (
PVD), metalorganic CVD, hydride transport low pressure CVD, and other chemical vapor deposition methods (CV
D), it can be formed using atomic epitaxy (ALE) or the like.

103A to 103C show an example of a thin-film inorganic EL element that can be used as a light-emitting element. 103A to 103C, the light-emitting element includes the first electrode layer 120100
, an electroluminescent layer 120102 and a second electrode layer 120103 .

The light-emitting elements shown in FIGS. 103B and 103C have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element shown in FIG. 103A. The light-emitting element shown in FIG. 103B has an insulating layer 120104 between the first electrode layer 120100 and the electroluminescent layer 120102, and the light-emitting element shown in FIG. and the electroluminescent layer 120
102, an insulating layer 120105, a second electrode layer 120103 and an electroluminescent layer 12010
2 and an insulating layer 120106. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Also,
The insulating layer may be a single layer or a laminate having multiple layers.

Note that the insulating layer 120104 is formed so as to be in contact with the first electrode layer 120100 in FIG.
is provided, but the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120103
An insulating layer 120104 may be provided so as to be in contact with the .

In the case of a dispersed inorganic EL, a particulate luminescent material is dispersed in a binder to form a film-like electroluminescent layer. Process into granules. If particles of a desired size cannot be obtained by the method for producing the luminescent material, the material may be processed into particles by pulverization with a mortar or the like. What is a binder
It is a substance for fixing the granular luminescent material in a dispersed state and maintaining the shape of the electroluminescent layer. The luminescent material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of the dispersion-type inorganic EL, the method of forming the electroluminescent layer includes a droplet ejection method that can selectively form an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as spin coating, and a dipping method. method, dispenser method, etc. can also be used. Although the film thickness is not particularly limited, it is preferably in the range of 10 to 1000 nm. Further, in the electroluminescent layer containing the luminescent material and the binder, the ratio of the luminescent material is preferably 50 wt % or more and 80 wt % or less.

104A to 104C show an example of a dispersed inorganic EL element that can be used as a light-emitting element. The light-emitting element in FIG. 104A has a stacked structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and a light-emitting material 120201 is held in the electroluminescent layer 120202 with a binder. include.

An insulating material can be used for the binder that can be used in this embodiment mode. Organic materials and inorganic materials can be used as the insulating material. Alternatively, a mixed material of organic and inorganic materials may be used. As the organic insulating material, polymers having a relatively high dielectric constant such as cyanoethyl cellulose resins, and resins such as polyethylene, polypropylene, polystyrene resins, silicone resins, epoxy resins and vinylidene fluoride can be used. Alternatively, aromatic polyamide, polybenzimidazole
A heat-resistant polymer such as midazole) or a siloxane resin may also be used. Note that the siloxane resin corresponds to a resin containing a Si—O—Si bond. Siloxane has a skeletal structure composed of bonds of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (eg, alkyl group, aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as substituents. Alternatively, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, phenol resins, novolak resins, acrylic resins, melamine resins, urethane resins, and oxazole resins (polybenzoxazole) may be used. These resins include barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO3).
) can be appropriately mixed to adjust the dielectric constant.

Examples of inorganic insulating materials contained in the binder include silicon oxide (SiOx), silicon nitride (SiNx
), silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, aluminum oxide containing oxygen and nitrogen (Al ₂ O ₃ ), titanium oxide (TiO ₂ )
, BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KN
bO ₃ ), lead niobate (PbNbO ₃ ), tantalum oxide (Ta ₂ O ₅ ), barium tantalate (BaTa ₂ O ₆ ), lithium tantalate (LiTaO ₃ ), yttrium oxide (Y
₂ O ₃ ), zirconium oxide (ZrO ₂ ), ZnS, and other inorganic insulating materials. By including (by addition, etc.) an inorganic material with a high dielectric constant in an organic material, the dielectric constant of the electroluminescent layer composed of the luminescent material and the binder can be more controlled, and the dielectric constant can be increased. .

In the fabrication process, the luminescent material is dispersed in a solution containing a binder. As a solvent of a solution containing a binder that can be used in the present embodiment, a solution having a viscosity suitable for a method of forming an electroluminescent layer (various wet processes) and a desired film thickness can be prepared by dissolving the binder material. Such a solvent may be appropriately selected. For example, an organic solvent or the like can be used as the solvent. When using a siloxane resin as the binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also called PGMEA)
, 3-methoxy-3-methyl-1-butanol (also referred to as MMB) and the like can be used as solvents.

The light-emitting elements shown in FIGS. 104B and 104C have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element shown in FIG. 104A. The light-emitting element shown in FIG. 104B has an insulating layer 120204 between the first electrode layer 120200 and the electroluminescent layer 120202, and the light-emitting element shown in FIG. and the electroluminescent layer 120
202, the insulating layer 120205, the second electrode layer 120203 and the electroluminescent layer 12020
2 and an insulating layer 120206. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Also, the insulating layer may be a single layer or a laminate having a plurality of layers.

Further, in FIG. 104B, an insulating layer 120204 is formed so as to be in contact with the first electrode layer 120200 .
is provided, but the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120203
An insulating layer 120204 may be provided so as to be in contact with the .

A material that can be used for an insulating layer such as the insulating layer 120104 in FIG. 103 and the insulating layer 120204 in FIG. 104 preferably has high dielectric strength and a dense film quality.
Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide ( _SiO2 ), yttrium oxide ( _Y2O3 ), titanium oxide ( _TiO2 ), aluminum oxide ( _Al2O3 ), hafnium oxide ( _{HfO2 ) , tantalum} oxide ( _Ta2O5 ), Barium titanate (BaTi
O ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., or mixed films or laminated films of two or more of these are used. be able to. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. Also, the insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. Although the film thickness is not particularly limited, it is preferably 10 to 10
00 nm range.

The light-emitting element described in this embodiment mode emits light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, and can operate by either DC driving or AC driving.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 15)
In the present embodiment, an example of a display device that can implement the present embodiment, particularly a case of optical handling will be described.

A rear projection type display device 130100 shown in FIGS.
In addition, a speaker 130102 and operation switches 130104 may be provided. The projector unit 130111 is the housing 130 of the rear projection display device 130100.
110, a mirror 13011 receives projection light for projecting an image based on an image signal.
Project towards 2. A rear projection display device 130100 includes a screen panel 130101.
It is configured to display an image projected from the back of the screen.

On the other hand, FIG. 106 shows a front projection display device 130200 . A front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201 . This projection optical system 130201 is configured to project an image onto a screen or the like arranged in front.

The configuration of the projector unit 130111 applied to the rear projection type display device 130100 shown in FIG. 105 and the front projection type display device 130200 shown in FIG. 106 will be described below.

FIG. 107 shows one configuration example of the projector unit 130111 . This projector unit 130111 includes a light source unit 130301 and a modulation unit 13030.
4. The light source unit 130301 includes a light source optical system 130303 including lenses and a light source lamp 130302 . The light source lamp 130302 is housed in a housing so as not to diffuse stray light. As the light source lamp 130302, a high-pressure mercury lamp, a xenon lamp, or the like, which can emit a large amount of light, is used. The light source optical system 130303 is configured by appropriately providing an optical lens, a film having a polarizing function, a film for adjusting phase difference, an IR film, and the like. And light source unit 130301
are arranged such that the emitted light is incident on the modulation unit 130304 . Modulation unit 130304 includes a plurality of display panels 130308, color filters, dichroic mirror 130305, total reflection mirror 130306, prism 130309, projection optical system 13
0310 is provided. Light emitted from the light source unit 130301 is separated into a plurality of optical paths by the dichroic mirror 130305 .

Each optical path is provided with a color filter that transmits light of a predetermined wavelength or wavelength band, and a display panel 130308 . A transmissive display panel 130308 modulates transmitted light based on a video signal. Each color of light transmitted through the display panel 130308 passes through the prism 13
0309 and passes through the projection optical system 130310 to display an image on the screen. A Fresnel lens may be arranged between the mirror and the screen. Projection light projected by the projector unit 130111 and reflected by the mirror is converted into roughly parallel light by the Fresnel lens and projected onto the screen.

A projector unit 130111 shown in FIG. 108 includes a reflective display panel 130407.
, 130408, 130409 are shown.

A projector unit 130111 shown in FIG. 108 includes a light source unit 130301 and a modulation unit 130400 . The light source unit 130301 may have the same configuration as in FIG. Light from the light source unit 130301 passes through the dichroic mirror 13
0401, 130402, total reflection mirror 130403, divided into a plurality of optical paths,
Incident into polarizing beam splitters 130404 , 130405 , and 130406 . The polarizing beam splitters 130404, 130405 and 130406 are provided corresponding to the reflective display panels 130407, 130408 and 130409 corresponding to each color. Reflective display panels 130407, 130408, and 130409 modulate reflected light based on video signals. Lights of respective colors reflected by the reflective display panels 130407 , 130408 , and 130409 are combined by being incident on the prism 130309 and projected through the projection optical system 130411 .

Of the light emitted from the light source unit 130301, the dichroic mirror 130401 transmits only light in the red wavelength region and reflects light in the green and blue wavelength regions. Furthermore, the dichroic mirror 130402 reflects only light in the green wavelength region. The light in the red wavelength region transmitted through the dichroic mirror 130401 is reflected by the total reflection mirror 130403 and enters the polarization beam splitter 130404. The light in the blue wavelength region enters the polarization beam splitter 130405 and is converted into the green wavelength region. The light in the region passes through a polarizing beam splitter 1304
06. The polarizing beam splitters 130404, 130405, 130406 are
It has a function of separating incident light into P-polarized light and S-polarized light, and a function of transmitting only P-polarized light. Reflective display panels 130407, 130408, and 130409 polarize the incident light based on the video signal.

Only S-polarized light corresponding to each color is incident on the reflective display panels 130407, 130408, and 130409 corresponding to each color. Note that the reflective display panels 130407 and 130408
, 130409 may be a liquid crystal panel. At this time, the liquid crystal panel operates in an electric field controlled birefringence mode (ECB). Also, the liquid crystal molecules are vertically aligned with a certain angle with respect to the substrate. Therefore, in the reflective display panels 130407, 130408, and 130409, the display molecules are oriented so that the incident light is reflected without changing its polarization state when the pixels are in the OFF state. Also, when the pixel is in the ON state, the orientation state of the display molecules changes, and the polarization state of the incident light changes.

The projector unit 130111 shown in FIG. 108 can be applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG.

The projector unit shown in FIG. 109 has a single-plate configuration. A projector unit 130111 shown in FIG.
30507, a projection optical system 130511, and a retardation plate 130504. The projection optical system 130511 is composed of one or more lenses. The display panel 130507 may be provided with a color filter.

FIG. 109B shows the projector unit 1 operating in the field sequential system.
30111 configuration. The field sequential system is a system in which light of each color such as red, green, and blue is temporally shifted and sequentially made incident on the display panel to perform color display without a color filter. In particular, high-definition images can be displayed when combined with a display panel that responds quickly to changes in input signals. In FIG. 109B, between the light source unit 130301 and the display panel 130508, a rotary color filter plate 130505 provided with a plurality of color filters such as red, green, and blue is provided.

A projector unit 130111 shown in FIG. 109C has a configuration of a color separation system using a macro lens as a color display system. This system is a system in which a microlens array 130506 is provided on the light incident side of the display panel 130509, and color display is realized by illuminating each color of light from each direction. The projector unit 130111 adopting this method has a feature that the light from the light source unit 130301 can be effectively used because the loss of light due to the color filter is small. Figure 10
A projector unit 130111 shown in 9(C) includes a dichroic mirror 130501, a dichroic mirror 130502, and a red light dichroic mirror 130503 so as to illuminate a display panel 130509 with light of each color from each direction.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 16)
In this embodiment, an example of an electronic device according to this embodiment will be described.

FIG. 110 shows a display panel module in which a display panel 900101 and a circuit board 900111 are combined. A display panel 900101 has a pixel portion 900102, a scanning line driver circuit 900103, and a signal line driver circuit 900104. FIG. For example, a control circuit 900112 and a signal dividing circuit 900113 are formed on the circuit board 900111 . The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114 . FPC or the like can be used for the connection wiring.

In the display panel 900101, a pixel portion 900102 and some peripheral driver circuits (driver circuits with low A driver circuit having a high operating frequency among the driver circuits) may be formed over an IC chip, and the IC chip may be mounted on the display panel 900101 by COG (Chip On Glass) or the like. By doing so, the area of the circuit board 900111 can be reduced, and a small display device can be obtained. Alternatively, the IC chip is TAB (Tape Auto B
It may be mounted on the display panel 900101 using a wiring) or a printed circuit board. By doing so, the area of the display panel 900101 can be reduced, so that a display device with a small frame size can be obtained.

For example, in order to reduce power consumption, a pixel portion is formed on a glass substrate using TFTs, all peripheral driving circuits are formed on an IC chip, and the IC chip is mounted on the display panel by COG or TAB. may

The display panel module shown in FIG. 110 completes the television receiver. FIG. 111 is a block diagram showing the main configuration of a television receiver. tuner 9002
01 receives a video signal and an audio signal. A video signal is sent to a video signal amplifier circuit 900202,
A video signal processing circuit 900203 that converts the signal output from the video signal amplifier circuit 900202 into color signals corresponding to the respective colors of red, green, and blue, and a control circuit 900212 that converts the video signal into the input specification of the drive circuit. processed by control circuit 9002
12 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 900213 may be provided on the signal line side, and the input digital signal may be divided into m (m is a positive integer) and supplied.

Of the signals received by the tuner 900201, audio signals are amplified by an audio signal amplifier circuit 900205.
, and its output is supplied to the speaker 900207 through the audio signal processing circuit 900206 . The control circuit 900208 receives the reception station (reception frequency) and volume control information through the input section 9 .
00209 and sends signals to the tuner 900201 and the audio signal processing circuit 900206 .

FIG. 112A shows a television receiver in which a display panel module having a different form from that shown in FIG. 111 is incorporated. In FIG. 112A, a display screen 900302 housed in a housing 900301 is formed of a display panel module. In addition, speaker 90030
3. An operation switch 900304 or the like may be provided as appropriate.

Further, FIG. 112B shows a television receiver in which only the display can be carried wirelessly. A battery and a signal receiver are incorporated in the housing 900312, and the display portion 900313 and the speaker portion 900317 are driven by the battery. The battery can be repeatedly charged with a charger 900310. Also, the charger 900310 can transmit and receive video signals, and can transmit the video signals to the signal receiver of the display. The housing 900312 is controlled by operation keys 900316 . Alternatively, Figure 1
12(B), the housing 9003 is operated by operating the operation key 900316.
12 to the charger 900310 can be an audiovisual two-way communication device. Alternatively, by operating the operation key 900316, the housing 9003
12 to the charger 900310, and by causing the other electronic device to receive the signal that the charger 900310 can transmit, thereby enabling communication control of the other electronic device. . This embodiment mode can be applied to the display portion 900313 .

FIG. 113A shows a module in which a display panel 900401 and a printed wiring board 900402 are combined. A display panel 900401 includes a pixel portion 900403 provided with a plurality of pixels, a first scan line driver circuit 900404, and a second scan line driver circuit 9004.
05 and a signal line driver circuit 900406 for supplying a video signal to the selected pixel.

The printed wiring board 900402 includes a controller 900407, a central processing unit (CPU
) 900408, memory 900409, power supply circuit 900410, audio processing circuit 90041
1, a transmission/reception circuit 900412, and the like. The printed wiring board 900402 and the display panel 900401 are connected by a flexible wiring board (FPC) 900413 . The printed circuit board (FPC) 900413 may be provided with a holding capacitor, a buffer circuit, and the like to prevent noise from being added to the power supply voltage and signals and slow rise of the signals. Also, the controller 900407, the audio processing circuit 900411, the memory 900409, the central processing unit (CPU) 900408, the power supply circuit 900410, and the like can be mounted on the display panel 900401 using a COG (Chip On Glass) method. The COG method can reduce the scale of the printed wiring board 900402 .

Interface (I/F) section 900414 provided on printed wiring board 900402
Input/output of various control signals is performed via the . An antenna port 900415 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 900402 .

FIG. 113B shows a block diagram of the module shown in FIG. 113A. This module includes VRAM 900416, DRAM 900417, flash memory 900418, etc. as memory 900409. FIG. The VRAM 900416 stores image data to be displayed on the panel, the DRAM 900417 stores image data or audio data, and the flash memory stores various programs.

A power supply circuit 900410 supplies power for operating a display panel 900401, a controller 900407, a central processing unit (CPU) 900408, an audio processing circuit 900411, a memory 900409, and a transmission/reception circuit 900412. Depending on the specifications of the panel, the power supply circuit 900410 may be provided with a current source.

A central processing unit (CPU) 900408 includes a control signal generation circuit 900420, a decoder 90
0421, register 900422, arithmetic circuit 900423, RAM 900424, interface 900419 for central processing unit (CPU) 900408, and the like. Various signals input to a central processing unit (CPU) 900408 via an interface 900419 are temporarily held in a register 900422 and then input to an arithmetic circuit 900423, a decoder 900421, and the like. The arithmetic circuit 900423 performs arithmetic operations based on the input signals and designates locations to which various commands are to be sent. On the other hand, the signal input to decoder 900421 is decoded and input to control signal generation circuit 900420 . Based on the input signal, the control signal generation circuit 900420 generates signals including various commands, and the arithmetic circuit 900
423, specifically memory 900409, transmission/reception circuit 90041
2. Send to the audio processing circuit 900411, the controller 900407, and the like.

The memory 900409, transmission/reception circuit 900412, audio processing circuit 900411, and controller 900407 operate according to the received instructions. The operation will be briefly described below.

A signal input from the input means 900425 is transferred to an interface (I/F) section 90041.
Central Processing Unit (CPU) 9004 mounted on printed wiring board 900402 via 4
08. The control signal generation circuit 900420 converts the image data stored in the VRAM 900416 into a predetermined format according to the signal sent from the input means 900425 such as a pointing device or keyboard, and sends it to the controller 900407 .

The controller 900407 has a central processing unit (CPU) 9004 according to the specifications of the panel.
08, the signal including the image data is subjected to data processing, and the display panel 90040
1. Further, the controller 900407 controls Hs based on the power supply voltage input from the power supply circuit 900410 and various signals input from the central processing unit (CPU) 900408.
A ync signal, a Vsync signal, a clock signal CLK, an alternating voltage (AC Cont), and a switching signal L/R are generated and supplied to the display panel 900401 .

The transmitting/receiving circuit 900412 processes signals transmitted and received as radio waves by the antenna 900428. Specifically, an isolator, a bandpass filter, a VCO (Volt
Age Controlled Oscillator), LPF (Low Pass
Filter), couplers, baluns, and other high-frequency circuits may be included. Transmission/reception circuit 90
Of the signals transmitted and received in 0412, the signal containing voice information is the central processing unit (CPU
) is sent to the audio processing circuit 900411 in accordance with the instructions from the 900408.

A signal containing audio information sent according to a command from a central processing unit (CPU) 900408 is demodulated into an audio signal in an audio processing circuit 900411 and sent to a speaker 900427 . Also, the audio signal sent from the microphone 900426 is processed by the audio processing circuit 90041.
1 and sent to transmit/receive circuit 900412 according to instructions from central processing unit (CPU) 900408 .

Controller 900407, central processing unit (CPU) 900408, power supply circuit 90041
0, an audio processing circuit 900411, and a memory 900409 can be mounted as the package of this embodiment.

Of course, the present embodiment is not limited to television receivers, and can be used for a variety of applications, particularly as large-area display media such as personal computer monitors, information display panels at railway stations and airports, and advertising display panels on the street. can be applied to

Next, a configuration example of the mobile phone according to this embodiment will be described with reference to FIG.

A display panel 900501 is detachably incorporated in a housing 900530 . The shape and dimensions of the housing 900530 can be appropriately changed according to the size of the display panel 900501 . A housing 900530 to which a display panel 900501 is fixed is fitted into a printed circuit board 900531 to be assembled as a module.

The display panel 900501 is connected to the printed circuit board 900531 via the FPC 900513 . A speaker 900532 and a microphone 90 are mounted on the printed circuit board 900531.
0533, transmission/reception circuit 900534, signal processing circuit 9 including CPU and controller, etc.
00535 is formed. Such a module, input means 900536 and battery 900537 are combined and housed in a housing 900539 . display panel 900501
is arranged so that it can be seen through an opening window formed in the housing 900539 .

In the display panel 900501, a pixel portion and some peripheral driving circuits (driving circuits with a low operating frequency among the plurality of driving A driver circuit having a high operating frequency among circuits) may be formed over an IC chip, and the IC chip may be mounted on the display panel 900501 by COG (Chip On Glass).
Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed circuit board. By adopting such a structure, the power consumption of the display device can be reduced, and the operating time of the mobile phone can be extended with one charge. Also, the cost of the mobile phone can be reduced.

The mobile phone shown in FIG. 115 includes operation switches 900604, a microphone 90
A main body (A) 900601 provided with 0605 and the like, a display panel (A) 900608,
Main body (B) 9 provided with display panel (B) 900609, speaker 900606, etc.
00602 are connected with a hinge 900610 so that they can be opened and closed. Display panel (A) 90
0608 and the display panel (B) 900609 are connected together with the circuit board 900607 to the main body (B) 9
00602 housed in housing 900603. Pixel portions of the display panel (A) 900608 and the display panel (B) 900609 are arranged so as to be visible through an opening window formed in the housing 900603 .

The display panel (A) 900608 and the display panel (B) 900609 are the mobile phone 90
Specifications such as the number of pixels can be appropriately set according to the functions of the 0600. For example, it is possible to combine the display panel (A) 900608 as a main screen and the display panel (B) 900609 as a sub-screen.

The mobile phone according to this embodiment can be transformed into various forms according to its functions and uses.
For example, an imaging device may be incorporated in the hinge 900610 to form a mobile phone with a camera. Further, the operation switches 900604, the display panel (A) 900608, and the display panel (B) 900609 can be housed in one housing to achieve the above effects. Similar effects can be obtained by applying the configuration of the present embodiment to an information display terminal having a plurality of display units.

This embodiment can be applied to various electronic devices. Specifically, it can be applied to a display portion of an electronic device. Such electronic devices include video cameras, digital cameras,
Images equipped with goggle-type displays, navigation systems, sound reproduction devices (car audio, audio components, etc.), computers, game machines, personal digital assistants (mobile computers, mobile phones, portable game machines, e-books, etc.), and recording media A playback device (specifically, playback of a recording medium such as a Digital Versatile Disc (DVD),
a device equipped with a display capable of displaying the image).

FIG. 116A shows a display including a housing 900711, a support base 900712, a display portion 900713, and the like.

FIG. 116B shows a camera including a main body 900721, a display portion 900722, and an image receiving portion 900.
723, operation keys 900724, external connection port 900725, shutter 900726
etc.

FIG. 116C shows a computer including a main body 900731, a housing 900732, and a display portion 9.
00733, keyboard 900734, external connection port 900735, pointing device 900736 and the like.

FIG. 116D shows a mobile computer including a main body 900741 and a display portion 900742.
, a switch 900743, an operation key 900744, an infrared port 900745, and the like.

FIG. 116(E) shows a portable image reproducing device (for example, a DVD reproducing device) equipped with a recording medium.
A main body 900751, a housing 900752, a display section (A) 900753, a display section (B
) 900754, recording medium (DVD etc.) reading unit 900755, operation keys 900756
, speaker unit 900757 and the like. The display section (A) 900753 can mainly display image information, and the display section (B) 900754 can mainly display character information.

FIG. 116F shows a goggle-type display including a main body 900761 and a display portion 90076.
2, including earphone 900763 and support 900764;

FIG. 116G shows a portable game machine including a housing 900771, a display portion 900772, a speaker portion 900773, operation keys 900774, a storage medium insertion portion 900775, and the like. A portable game machine using the display device of this embodiment for the display portion 900772 can express vivid colors.

FIG. 116H shows a digital camera with a TV reception function, which includes a main body 900781, a display portion 900782, operation keys 900783, a speaker 900784, and a shutter 90078.
5, an image receiving unit 900786, an antenna 900787, and the like.

As shown in FIGS. 116A to 116E, electronic devices according to this embodiment are characterized by having a display portion for displaying some information.

Next, application examples of the semiconductor device according to this embodiment will be described.

FIG. 117 shows an example in which the semiconductor device according to this embodiment is integrated with a building. FIG. 117 shows a housing 900810, a display unit 900811, and a remote control device 9 which is an operation unit.
00812, speaker unit 900813 and the like. The semiconductor device according to this embodiment is a wall-mounted type integrated with a building, and can be installed without requiring a large installation space.

FIG. 118 shows another example in which the semiconductor device according to this embodiment is integrated with a building. The display panel 900901 is attached integrally with the unit bath 900902 so that the bather can view the display panel 900901 . display panel 90
0901 has a function of displaying information by being operated by a bather, and can be used as an advertisement or an entertainment means.

The semiconductor device according to this embodiment can be installed not only on the side wall of the unit bus 900902 shown in FIG. 118, but also in various places. For example, it may be integrated with a part of the mirror surface or the bathtub itself. At this time, the shape of the display panel 900901 may be adapted to the mirror surface or the shape of the bathtub.

FIG. 119 shows another example in which the semiconductor device according to this embodiment is integrated with a building. The display panel 901002 is attached so as to be curved according to the curved surface of the columnar body 901001 . Note that the columnar body 901001 will be described here as a utility pole.

A display panel 901002 shown in FIG. 119 is provided at a position higher than the human viewpoint.
By installing the display panel 901002 on a building such as a utility pole that stands repeatedly outdoors, it is possible to advertise to an unspecified number of viewers. Here, the display panel 90100
In 2, it is easy to display the same image or to switch images instantly by external control, so that extremely efficient information display and advertising effects can be expected. In addition, it can be said that the display panel 901002 provided with a self-luminous display element is useful as a highly visible display medium even at night. Also, by installing it on a utility pole, the display panel 90
Securing the power supply means of 1002 is easy. It can also serve as a means of quickly and accurately transmitting information to disaster victims in emergency situations such as disasters.

As the display panel 901002, for example, a display panel which displays an image by providing a switching element such as an organic transistor on a film substrate and driving the display element can be used.

In this embodiment, walls, pillars, and unit baths are used as examples of buildings, but the present embodiment is not limited to these, and the semiconductor device according to this embodiment can be installed in various buildings. can be done.

Next, an example in which the semiconductor device according to this embodiment is provided integrally with a moving object will be described.

FIG. 120 is a diagram showing an example in which the semiconductor device according to this embodiment is integrated with an automobile. The display panel 901102 is attached integrally with the vehicle body 901101 of the automobile, and can display the operation of the vehicle body and information input from inside and outside the vehicle body on demand. It may also have a navigation function.

Note that the semiconductor device according to this embodiment can be installed not only in the vehicle body 901101 shown in FIG. 120, but also in various places. For example, it may be integrated with a glass window, a door, a steering wheel, a shift lever, a seat, a room mirror, or the like. At this time, the display panel 901
The shape of 102 may be adapted to the shape of the object to be installed.

FIG. 121 is a diagram showing an example in which the semiconductor device according to this embodiment is integrated with a train car.

FIG. 121(a) is a diagram showing an example in which a display panel 901202 is provided on the glass of a door 901201 of a train car. Compared to conventional paper advertisements, there is an advantage in that there is no labor cost required when switching advertisements. In addition, since the display panel 901202 can instantaneously switch images displayed on the display portion in response to a signal from the outside,
For example, the image on the display panel can be switched for each time period when the passenger class of train passengers changes, and a more effective advertising effect can be expected.

FIG. 121(b) shows a glass window 901203 in addition to the glass of the door 901201 of the train car.
, and an example in which a display panel 901202 is provided on a ceiling 901204. FIG.
As described above, the semiconductor device according to this embodiment can be easily installed in a place where it was difficult to install it in the past, so that an effective advertising effect can be obtained. In addition, since the semiconductor device according to the present embodiment can instantaneously switch images displayed on the display unit in response to a signal from the outside, the cost and time required for switching advertisements can be reduced, and the display is more flexible. Advertisement operation and information transmission become possible.

Note that the semiconductor device according to this embodiment can be installed not only in the door 901201, the glass window 901203, and the ceiling 901204 shown in FIG. 121, but also in various places. For example, it may be integrated with a strap, a seat, a railing, a floor, or the like. At this time, the shape of the display panel 901202 may be adapted to the shape of the object to be installed.

FIG. 122 shows an example in which the semiconductor device according to this embodiment is integrated with a passenger airplane.

FIG. 122(a) shows a display panel 90130 on the ceiling 901301 above the seat of a passenger airplane.
2 is a diagram showing the shape in use when 2 is provided. The display panel 901302 is
It is integrally attached to the ceiling 901301 via a hinge portion 901303, and the expansion and contraction of the hinge portion 901303 enables passengers to view the display panel 901302. The display panel 901302 can display information by being operated by a passenger. Furthermore, it has a function that can be used as an advertisement or entertainment means. Also, as shown in FIG. 122(b), by folding the hinge portion and storing it in the ceiling 901301, consideration can be given to safety during takeoff and landing. By turning on the display element of the display panel in an emergency, it can be used as information transmission means and a guide light.

Note that the semiconductor device according to this embodiment can be installed not only on the ceiling 901301 shown in FIG. 122, but also in various places. For example, seating seats, seating tables, armrests,
It may be integrated with a window or the like. Also, a large display panel that can be viewed by many people at the same time may be installed on the wall of the fuselage. At this time, the shape of the display panel 901302 may be adapted to the shape of the object to be installed.

In this embodiment, a train car body, a car body, and an airplane body are exemplified as moving bodies, but they are not limited to these.
It can be installed on various things such as trains (including monorails, railroads, etc.), ships, and the like. Since the semiconductor device according to this embodiment mode can instantaneously switch the display of the display panel in a moving object by a signal from the outside, by installing the semiconductor device according to this embodiment mode in the moving object, , the mobile body can be used as an advertisement display board for an unspecified number of customers, an information display board in the event of a disaster, and the like.

Note that this embodiment can be freely combined with any of the other embodiments.

The contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 17)
As described above, this specification includes at least the following inventions.

A liquid crystal display device having pixels each having a liquid crystal element and a driving circuit. The driver circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. At least a part of this drive circuit includes the following connection relationships. A first electrode of the first transistor is electrically connected to the fourth wiring, and a second electrode of the first transistor is electrically connected to the third wiring. A first electrode of the second transistor is electrically connected to the sixth wiring, and a second electrode of the second transistor is electrically connected to the third wiring. the first of the third transistor
is electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the gate electrode of the third transistor is connected to the seventh wiring is electrically connected to A first electrode of the fourth transistor is electrically connected to a sixth wiring, a second electrode of the fourth transistor is electrically connected to a gate electrode of the second transistor, and a A gate electrode is electrically connected to the gate electrode of the first transistor. A first electrode of the fifth transistor is electrically connected to a seventh wiring, a second electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor, and a A gate electrode is electrically connected to the first wiring. A first electrode of the sixth transistor is electrically connected to a sixth wiring, a second electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor, and a A gate electrode is electrically connected to the gate electrode of the second transistor. A first electrode of the seventh transistor is electrically connected to the sixth wiring, a second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the A gate electrode is electrically connected to the second wiring.

A liquid crystal display device having a pixel having the liquid crystal element and a driving circuit may include the following structure. Channel Length L and Channel Width W of First to Seventh Transistors
A configuration including a driving circuit in which the value of W/L of the first transistor is maximized among the values of the ratio W/L of . The W/L value of the first transistor is 2 to 5 times the W/L value of the fifth transistor.
A configuration including a double drive circuit. A configuration including a case where the channel length L of the third transistor is longer than the channel length L of the fourth transistor. A structure including a capacitive element arranged between a second electrode of a first transistor and a gate electrode of the first transistor. first
to the seventh transistor are N-channel transistors. The first to seventh transistors include those using amorphous silicon as a semiconductor layer.

A liquid crystal display device having a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit. first
and the second drive circuit at least partially include the following connection relationship.
The first driver circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. ing. A first electrode of the first transistor is electrically connected to the fourth wiring, and a second electrode of the first transistor is electrically connected to the third wiring. A first electrode of the second transistor is electrically connected to the sixth wiring, and a second electrode of the ninth transistor is electrically connected to the third wiring. A first electrode of the third transistor is electrically connected to a fifth wiring, a second electrode of the third transistor is electrically connected to a gate electrode of the second transistor, and a A gate electrode is electrically connected to the seventh wiring. A first electrode of the fourth transistor is electrically connected to the sixth wiring;
A second electrode of the transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor. A first electrode of the fifth transistor is electrically connected to a seventh wiring, a second electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor, and a A gate electrode is electrically connected to the first wiring. A first electrode of the sixth transistor is electrically connected to a sixth wiring, a second electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor, and a A gate electrode is electrically connected to the gate electrode of the second transistor. A first electrode of the seventh transistor is electrically connected to the sixth wiring, a second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the A gate electrode is electrically connected to the second wiring.
The second driver circuit has an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. ing. A first electrode of the eighth transistor is electrically connected to the eleventh wiring, and a second electrode of the eighth transistor is electrically connected to the tenth wiring. A first electrode of the ninth transistor is electrically connected to the thirteenth wiring, and a second electrode of the ninth transistor is electrically connected to the tenth wiring. A first electrode of the tenth transistor is electrically connected to a twelfth wiring, a second electrode of the tenth transistor is electrically connected to a gate electrode of the ninth transistor, and a A gate electrode is electrically connected to the fourteenth wiring. The first electrode of the eleventh transistor is the first
The second electrode of the eleventh transistor is electrically connected to the gate electrode of the ninth transistor, and the gate electrode of the eleventh transistor is electrically connected to the gate electrode of the eighth transistor. electrically connected. The first electrode of the twelfth transistor is the first
4, the second electrode of the twelfth transistor is electrically connected to the gate electrode of the eighth transistor, and the gate electrode of the twelfth transistor is electrically connected to the eighth wiring. It is A first electrode of the thirteenth transistor is electrically connected to the thirteenth wiring, a second electrode of the thirteenth transistor is electrically connected to a gate electrode of the eighth transistor, and the A gate electrode is electrically connected to the gate electrode of the ninth transistor. A first electrode of the fourteenth transistor is electrically connected to the thirteenth wiring, a second electrode of the fourteenth transistor is electrically connected to a gate electrode of the eighth transistor, and the A gate electrode is electrically connected to the ninth wiring.

A liquid crystal display device having a pixel having the liquid crystal element and a driving circuit may include the following structure. The fourth wiring and the 11th wiring are electrically connected, the fifth wiring and the 12th wiring are electrically connected, and the sixth wiring and the 13th wiring are electrically connected. , a configuration in which the seventh wiring and the fourteenth wiring are electrically connected; The fourth wiring and the 11th wiring are the same wiring, the fifth wiring and the 12th wiring are the same wiring, and the sixth wiring and the 13th wiring are the same wiring. , the seventh wiring and the fourteenth wiring are the same wiring. A configuration in which the third wiring and the tenth wiring are electrically connected. A configuration in which the third wiring and the tenth wiring are the same wiring. Among the values of the ratio W/L of the channel length L to the channel width W of the first to seventh transistors, the value of W/L of the first transistor is the largest, and the ratio W/L of the eighth to fourteenth transistors is the largest. A configuration in which the value of W/L of the eighth transistor is the largest among the values of the ratio W/L of the channel length L to the channel width W of the transistors. W/L of the first transistor
is two to five times the W/L value of the fifth transistor, and the W/L value of the eighth transistor is two to five times the W/L value of the twelfth transistor. configuration. The channel length L of the third transistor is greater than the channel length L of the fourth transistor, and the tenth
is longer than the channel length L of the eleventh transistor. A capacitive element is arranged between the second electrode of the first transistor and the gate electrode of the first transistor, and between the second electrode of the eighth transistor and the gate electrode of the eighth transistor A configuration in which capacitive elements are arranged. A structure in which the first to fourteenth transistors are N-channel transistors. The first to fourteenth transistors each have a structure in which amorphous silicon is used as a semiconductor layer.

The liquid crystal display device shown in this embodiment is described in this specification, and therefore has the same effects as those of the other embodiments.

S1 Signal line Sj Signal line VDD Power supply potential VSS Power supply potential G1 Scanning line Gi Scanning line Gn Scanning line 11 Transistor 12 Transistor 13 Transistor 14 Transistor 15 Transistor 16 Transistor 17 Transistor 21 Signal line 22 Signal line 23 Wiring 24 Signal line 25 Power line 26 Power supply line 32 Silicon oxynitride film 41 Node 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 110 Wiring 107 Transistor 112 Wiring 108 Transistor 109 Transistor 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 129 Wiring 130 Wiring 131 Wiring 132 Wiring 133 Wiring 134 Wiring 141 Node 142 Node 221 Signal 222 Signal 223 Signal 225 Signal 226 Signal 232 Signal 241 Potential 242 Potential 401 Capacitive element 402 Transistor 403 Resistive element 501 Wiring 502 Wiring 503 Wiring 504 Wiring 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Wiring 701 Transistor 702 Transistor 711 Wiring 81a Evaporation source 1001 Flip-flop 1007 Wiring 1011 Wiring 1012 Wiring 1013 Wiring 1014 Wiring 1015 Wiring 1016 Wiring 1017 Wiring 1018 Wiring 1111 Signal 1112 Signal 1113 Signal 1117 Signal 1118 Signal 1211 Signal 1218 Signal 1301 Buffer 1602 Scan line driver circuit 1801 Signal line driver circuit 1802 Scan line driver circuit 1803 Pixel 1804 Pixel portion 1805 Insulating substrate 1808 Wiring 2108 Transistor 2132 Wiring 2301 Transistor 2302 Transistor 2303 Transistor 2304 Transistor 2305 Transistor 2306 Transistor 2307 Transistor 2321 Wiring 2 322 Wiring 2323 Wiring 2324 Wiring 2325 Wiring 2326 Wiring 2327 Wiring 2328 Wiring 2329 Wiring 2330 Wiring 2331 Wiring 2341 Node 2342 Node 2421 Signal 2422 Signal 2423 Signal 2425 Signal 2426 Signal 2441 Potential 2442 Potential 2501 Conductive layer 2502 Conductive layer 2 503 conductive layer 2504 conductive layer 2505 conductive Layer 2506 Conductive layer 2507 Conductive layer 2508 Conductive layer 2510 Conductive layer 2511 Conductive layer 2512 Conductive layer 2513 Conductive layer 2514 Conductive layer 2515 Conductive layer 2541 Wiring 2542 Wiring 2543 Wiring 2544 Wiring 2545 Wiring 2546 Wiring 2547 Wiring 2548 Wiring 2549 Wiring 258 1 semiconductor layer 2582 Semiconductor layer 2583 Semiconductor layer 2584 Semiconductor layer 2585 Semiconductor layer 2586 Semiconductor layer 2587 Semiconductor layer 2901 Flip-flop 2907 Wiring 2911 Wiring 2912 Wiring 2913 Wiring 2914 Wiring 2915 Wiring 2916 Wiring 2917 Wiring 2918 Wiring 2919 Wiring 3011 Signal 3018 Signal 3019 Signal 3101 Flip-flop 3111 Wiring 3120 Wiring 3121 Signal 3122 Signal 3123 Signal 3125 Signal 3126 Signal 3141 Potential 3142 Potential 3301 Flip-flop 3301 Wiring 3306 Wiring 3311 Wiring 3312 Wiring 3313 Wiring 3314 Wiring 3315 Wiring 3316 Wiring 3317 Wiring 3318 Wiring 3319 Wiring 3320 Wiring 3321 Wiring 3322 Wiring 3511 Signal 3512 Signal 3513 Signal 3514 Signal 3515 Signal 3519 Signal 3520 Signal 3521 Signal 3604 Substrate film 3611 Signal 3621 Signal 5601 Driver IC
5602 switch group 5611 wiring 5612 wiring 5613 wiring 5621 wiring 5721 signal 5821 signal 5911 wiring 5912 wiring 5913 wiring 6001 transistor 6002 transistor 6003 transistor 6004 transistor 6005 transistor 6006 transistor 6011 wiring 6012 wiring 6013 wiring 6014 wiring 6 015 wiring 6016 wiring 6022 switch group 6101 transistor 6102 transistor 6111 wiring 6112 wiring 6201 transistor 6211 wiring 6401 transistor 6402 transistor 6411 wiring 6412 wiring 8000 buffer 8011 wiring 8012 wiring 802a scanning line driver circuit 802b scanning line driver circuit 8100 buffer 8201 transistor 8202 transistor 8211 wiring 8212 wiring 8 213 Wiring 8214 Wiring 8301 Transistor 8302 transistor 8303 transistor 8304 transistor 8311 wiring 8312 wiring 8313 wiring 8314 wiring 8315 wiring 8316 wiring 8341 node 8401 transistor 8402 transistor 8403 transistor 8404 transistor 8411 wiring 8412 wiring 8413 wiring 8414 wiring 8415 wiring 8416 wiring 84 17 Wiring 8441 Node 8501 Transistor 8502 Transistor 8503 Transistor 8511 Wiring 8512 Wiring 8513 Wiring 8514 Wiring 8515 Wiring 8516 Wiring 8541 Node 8601 Transistor 8602 Transistor 8603 Transistor 8604 Transistor 8611 Wiring 8612 Wiring 8613 Wiring 8614 Wiring 8615 Wiring 8616 Wiring 8641 Node 10101 Substrate 10102 Insulating film 10103 Conductive layer 10104 Insulating film 10105 Semiconductor layer 10106 semiconductor layer 10107 conductive layer 10108 insulating film 10109 conductive layer 10110 alignment film 10112 alignment film 10113 conductive layer 10114 light shielding film 10115 color filter 10116 substrate 10117 spacer 10118 liquid crystal molecule 10121 scanning line 10122 video signal line 10123 capacitor line 101 24 TFTs
10125 pixel electrode 10126 pixel capacitor 10201 substrate 10202 insulating film 10203 conductive layer 10204 insulating film 10205 semiconductor layer 10206 semiconductor layer 10207 conductive layer 10208 insulating film 10209 conductive layer 10210 alignment film 10212 alignment film 10213 conductive layer 10214 light shielding film 10 215 color filter 10216 substrate 10217 Spacers 10218 Liquid crystal molecules 10219 Alignment control protrusions 10221 Scanning lines 10222 Video signal lines 10223 Capacitance lines 10224 TFTs
10225 pixel electrode 10226 pixel capacitor 10301 substrate 10302 insulating film 10303 conductive layer 10304 insulating film 10305 semiconductor layer 10306 semiconductor layer 10307 conductive layer 10308 insulating film 10309 conductive layer 10310 alignment film 10312 alignment film 10313 conductive layer 10314 light shielding film 10 315 color filter 10316 substrate 10317 Spacer 10318 Liquid crystal molecule 10319 Electrode notch 10321 Scanning line 10322 Video signal line 10323 Capacitance line 10324 TFT
10325 pixel electrode 10326 pixel capacitor 10401 substrate 10402 insulating film 10403 conductive layer 10404 insulating film 10405 semiconductor layer 10406 semiconductor layer 10407 conductive layer 10408 insulating film 10409 conductive layer 10410 alignment film 10412 alignment film 10414 light shielding film 10415 color filter 104 16 substrate 10417 spacer 10418 liquid crystal molecule 10421 scanning line 10422 video signal line 10423 common electrode 10424 TFT
10425 pixel electrode 10501 substrate 10502 insulating film 10503 conductive layer 10504 insulating film 10505 semiconductor layer 10506 semiconductor layer 10507 conductive layer 10508 insulating film 10509 conductive layer 10510 alignment film 10512 alignment film 10513 conductive layer 10514 light shielding film 10515 color filter 105 16 substrate 10517 spacer 10518 liquid crystal molecule 10519 insulating film 10521 scanning line 10522 video signal line 10523 common electrode 10524 TFT
10525 pixel electrode 10600 liquid crystal layer 10601 substrate 10602 substrate 10603 layer 10604 layer 10605 electrode 10606 electrode 10607 projection 10801 electrode 10802 electrode 10803 electrode 10804 electrode 10901 insulating layer 2002a scanning line driving circuit 2002b scanning line driving circuit 20100 substrate 20101 pixel portion 20102 pixel 20103 Scanning line input terminal 20104 Signal line input terminal 20105 Scanning line driving circuit 20106 Signal line driving circuit 20115 Substrate 20200 FPC
20201 Driver IC
20301 transistor 20302 liquid crystal element 20303 capacitor element 20304 wiring 20305 wiring 20306 capacitor line 20307 counter electrode 20501 insulating film 20502 semiconductor layer 20503 insulating layer 20504 conductive layer 20505 insulating layer 20506 conductive film 20507 insulating layer 20508 conductive layer 2050 9 insulating layer 20510 liquid crystal layer 20511 insulation Film 20512 Conductive film 20513 Insulating film 20514 Insulating film 20515 Counter substrate 20516 Sealing material 20517 Anisotropic conductor layer 20518 FPC
20521 transistor 20525 driver circuit region 20526 pixel region 20530 IC chip 20531 spacer 20532 insulating film 20533 conductive film 20601 driver IC
21301 insulating film 21801 insulating film 22001 insulating film 2202a scanning line driving circuit 2202b scanning line driving circuit 22201 insulating film 22601 backlight unit 22602 diffusion plate 22603 light guide plate 22604 reflector plate 22605 lamp reflector 22606 light source 22607 liquid crystal panel 22608 layer 2260 9 layer 22610 slit 22701 Video signal 22702 Control circuit 22703 Signal line driving circuit 22704 Scanning line driving circuit 22705 Pixel section 22706 Illumination means 22707 Power supply 22708 Driving circuit section 22710 Scanning line 22712 Signal line 22731 Shift register 22732 Latch 22733 Latch 22734 Level shifter 22735 Buffer 22741 Shift Register 22742 Level shifter 22743 Buffer 22801 Cold cathode tube 22802 Light emitting diode 22803 Light emitting diode 22832 Lamp reflector 22852 Backlight unit 23000 Polarizing film 23001 Protective film 23002 Substrate film 23002 Substrate film 23003 PVA polarizing film 23004 Substrate film 23005 Adhesive layer 23006 Release film 23100 TFT substrate 23101 opposite Substrate 23102 Sealing material 23103 Pixel portion 23104 Liquid crystal layer 23105 Colored layer 23106 Layer 23107 Layer 23109 Flexible wiring board 23110 Cold cathode tube 23111 Reflector 23112 Circuit board 23113 Diffusion plate 23199 Controller 2901i Flip-flop 30101 Coding circuit 30102 Frame Memory 30103 Correction circuit 30104 DA conversion circuit 30112 frame memory 30113 correction circuit 30113 input voltage 30121 input voltage 30123 Output brightness 30124 Output brightness 30131 input video signal 30131 Output video signal 30133 Output switching signal 30201 Transistor 30202 Capacity 30203 display element 30204 Video signal line 30205 scanning line 30206 Common line 30211 Transistor 30212 Auxiliary capacitor 30213 Display element 30214 Video signal line 30215 Scanning line 30216 Common line 30217 Common line 30301 Diffusion plate 30302 Cold cathode tube 30311 Diffusion plate 30312 Light source 30400 Frame period 30401 Image 30402 Intermediate image 30412 Intermediate image 3 0413 Intermediate image 5603a Switch 5603b Switch 5603c Switch 5703a Timing 5703b Timing 5703c Timing 5803a Timing 5803b Timing 5803c Timing 5903a Transistor 5903b Transistor 5903c Transistor 60105 TFT
60106 Wiring 60107 Wiring 60108 TFT
60111 Wiring 60112 Counter electrode 60113 Capacitor 60115 Pixel electrode 60116 Partition wall 60117 Organic conductor film 60118 Organic thin film 60119 Substrate 60200 Substrate 60201 Wiring 60202 Wiring 60203 Wiring 60204 Wiring 60205 TFT
60206 TFT
60207 TFT
60208 pixel electrode 60211 partition wall 60212 organic conductor film 60213 organic thin film 60214 counter electrode 60300 substrate 60301 wiring 60302 wiring 60303 wiring 60304 wiring 60305 TFT
60306 TFT
60307 TFT
60308 TFT
60309 pixel electrode 60311 wiring 60312 wiring 60321 partition wall 60322 organic conductor film 60323 organic thin film 60324 counter electrode 60401 anode 60402 cathode 60403 hole transport region 60404 electron transport region 60405 mixed region 60406 region 60407 region 60408 region 6040 9 area 60560 transfer chamber 60561 transfer chamber 60562 Loading chamber 60563 Unloading chamber 60564 Intermediate processing chamber 60565 Sealing processing chamber 60566 Transfer means 60567 Transfer device 60568 Heating chamber 60569 Film formation processing chamber 60570 Film formation processing chamber 60571 Film formation chamber 60572 Plasma processing chamber 60573 Film formation processing chamber 60574 Film formation processing chamber 60576 Film formation processing chamber 60680 Evaporation source holder 60681 Evaporation source 60682 Distance sensor 60683 Articulated arm 60684 Material supply pipe 60686 Substrate stage 60687 Substrate chuck 60688 Mask chuck 60689 Substrate 60690 Shadow mask 60691 Top plate 60692 Bottom plate 6301a Transistor 630 1b transistor 6302a Transistor 6302b Transistor 8001a Inverter 8001b Inverter 8001c Inverter 8002a Inverter 8002b Inverter 8002c Inverter 8003a Inverter 8003b Inverter 8003c Inverter 80302 Drive transistor 80400 Drive transistor 80401 Switch 80402 Switch 80403 Switch 80404 Capacitive element 80 405 capacitive element 80411 signal line 80412 power supply line 80413 first Scanning line 80414 Second scanning line 80415 Third scanning line 80420 Display element 80421 Electrode 80430 Driving transistor 80431 Switch 80432 Switch 80433 Switch 80434 Capacitive element 80441 Signal line 80442 Power supply line 80443 First scanning line 80444 Second scanning line 80445 Third scanning line 80450 Display element 80451 Electrode 80454 Scanning line 10606a Electrode 10801a Electrode 10801b Electrode 10801c Electrode 10801d Electrode 10802a Electrode 10802b Electrode 10802c Electrode 10802d Electrode 10803a Electrode 10803b Electrode 10803c electrode 10803d electrode 10804a electrode 10804b electrode 10804c electrode 10804d electrode 110111 substrate 110112 insulating film 110113 semiconductor film 110114 semiconductor film 110115 semiconductor film 110116 insulating film 110117 gate electrode 110118 insulating film 110119 insulating film 110121 sidewall 110122 mask 110123 conductive film 110131 insulating film 120100 electrode layer 12010 2 Electroluminescent layer 120103 Electrode layer 120104 Insulating layer 120105 Insulation Layer 120106 Insulating layer 120200 Electrode layer 120201 Luminescent material 120202 Electroluminescent layer 120203 Electrode layer 120204 Insulating layer 120205 Insulating layer 120206 Insulating layer 130100 Rear projection display device 130101 Screen panel 130102 Speaker 130104 Operation switches 130110 Housing 130111 projector unit 130112 mirror 130200 Front projection type display device 130201 Projection optical system 130301 Light source unit 130301 Light source unit 130302 Light source lamp 130303 Light source optical system 130304 Modulation unit 130305 Dichroic mirror 130306 Total reflection mirror 130308 Display panel 130309 Prism 130310 Projection optical system 130400 Modulation unit 1 30401 dichroic mirror 130402 dichroic mirror 130403 Total reflection mirror 130404 Polarizing beam splitter 130405 Polarizing beam splitter 130406 Polarizing beam splitter 130407 Reflective display panel 130411 Projection optical system 130501 Dichroic mirror 130502 Dichroic mirror 130503 Dichroic mirror for red light 130504 Phase plate 13050 5 Color filter plate 130506 Microlens array 130507 Display panel 130508 Display panel 130509 Display panel 130511 Projection optical system 20102a Pixel 20102b Pixel 20105a Scanning line driver circuit 20105b Scanning line driver circuit 20301a Transistor 20301b Transistor 20303a Capacitor 20303b Capacitor 20305a Wiring 20305b Wiring 20 3076 Wiring 20502a Semiconductor layer 20502b Semiconductor layer 20503a Insulation Layer 20503b Insulating layer 20504a Conductive layer 20504b Conductive layer 20508a Conductive layer 20508b Conductive layer 20602a Driver IC
20602b Driver IC
23190a red light source 23190b green light source 23190c blue light source 60577a gate valve 60681a evaporation source 60681b evaporation source 60681c evaporation source 60685a material supply source 60685b material supply source 60685c material supply source 80301a switching transistor 80301b switching transistor 80301c switching switching transistor 80301d switching transistor 80301e Switching transistor 80302a Driving transistor 80302b Driving transistor 80302c Driving transistor 80302d Driving transistor 80302e Driving transistor 80303c Diode-connected transistor 80303d Diode-connected transistor 80303e Erasing transistor 80304a Capacitance element 80304b Capacitance element 80304c Capacitance element 80304d Capacitance element 80 304e capacitive element 80306a rectifying element 80311a signal line 80311b signal line 80311c signal line 80311d signal line 80311e signal line 80312a first scanning line 80312b first scanning line 80312c first scanning line 80312d first scanning line 80312e first scanning line 80313a power supply Line 80313b Power line 80313c Power line 80313d Power line 80313e Power line 80314b Second scanning line 80314c Second scanning line 80314d Second scanning line 80320a Display element 80320b Display element 80321a Electrode 80321b Electrode 900101 Display panel 900102 Pixel portion 900 103 scanning lines Drive circuit 900104 Signal line drive circuit 900111 Circuit board 900112 Control circuit 900113 Signal division circuit 900114 Connection wiring 900201 Tuner 900202 Video signal amplifier circuit 900203 Video signal processing circuit 900205 Audio signal amplifier circuit 900206 Audio signal processing circuit 900207 Speaker 900208 Control circuit 90 0209 input section 900212 Control circuit 900213 Signal dividing circuit 900301 Housing 900302 Display screen 900303 Speaker 900304 Operation switch 900310 Charger 900312 Housing 900313 Display section 900316 Operation keys 900317 Speaker section 900401 Display panel 900402 Printed wiring board 900403 Pixel portion 900404 Scanning line driver circuit 900405 Scanning Line drive circuit 900406 Signal line drive circuit 900407 Controller 900408 Central processing unit (CPU)
900409 memory 900410 power supply circuit 900411 audio processing circuit 900412 transmission/reception circuit 900413 flexible printed circuit board (FPC)
900414 Interface (I/F) section 900415 Antenna port 900416 VRAM
900417 DRAM
900418 flash memory 900419 interface 900420 control signal generation circuit 900421 decoder 900422 register 900423 arithmetic circuit 900424 RAM
900425 Input means 900426 Microphone 900427 Speaker 900428 Antenna 900501 Display panel 900513 FPC
900530 housing 900531 printed circuit board 900532 speaker 900533 microphone 900534 transmission/reception circuit 900535 signal processing circuit 900536 input means 900537 battery 900539 housing 900600 mobile phone 900601 main body (A)
900602 Body (B)
900603 Housing 900604 Operation switches 900605 Microphone 900606 Speaker 900607 Circuit board 900608 Display panel (A)
900609 Display panel (B)
900610 hinge 900711 housing 900712 support base 900713 display unit 900721 main body 900722 display unit 900723 image receiving unit 900724 operation keys 900725 external connection port 900726 shutter 900731 main unit 900732 housing 900733 display unit 900734 keyboard 900735 External connection port 900736 Pointing device 900741 Main unit 900742 Display unit 900743 Switch 900744 Operation key 900745 Infrared port 900751 Main body 900752 Housing 900753 Display (A)
900754 display unit (B)
900755 Part 900756 Operation key 900757 Speaker part 900761 Main body 900762 Display part 900763 Earphone 900764 Support part 900771 Housing 900772 Display part 900773 Speaker part 900774 Operation key 900775 Storage medium insertion part 900781 Main body 900782 Display section 900783 Operation keys 900784 Speaker 900785 Shutter 900786 Image receiving section 900787 Antenna 900810 Housing 900811 Display 900812 Remote controller 900813 Speaker 900901 Display panel 900902 Unit bus 901001 Column 901002 Display panel 901101 Body 901102 Display panel 901201 Door 901202 Display panel 901203 Glass Window 901204 Ceiling 901301 Ceiling 901302 Display panel 901303 Hinge portion

Claims (1)

having first to seventh transistors,
one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor;
one of the source or drain of the third transistor is electrically connected to the gate of the second transistor;
one of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor;
the gate of the fourth transistor is electrically connected to the gate of the first transistor;
one of the source and drain of the fifth transistor is electrically connected to the gate of the first transistor;
one of the source or drain of the sixth transistor is electrically connected to the gate of the first transistor;
the gate of the sixth transistor is electrically connected to the gate of the second transistor;
A flip-flop in which one of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor.

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