JP6154445B2 - Display device - Google Patents

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JP6154445B2
JP6154445B2 JP2015177352A JP2015177352A JP6154445B2 JP 6154445 B2 JP6154445 B2 JP 6154445B2 JP 2015177352 A JP2015177352 A JP 2015177352A JP 2015177352 A JP2015177352 A JP 2015177352A JP 6154445 B2 JP6154445 B2 JP 6154445B2
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transistor
wiring
electrode
source
signal
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JP2016028368A (en
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敦司 梅崎
敦司 梅崎
三宅 博之
博之 三宅
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株式会社半導体エネルギー研究所
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Description

The present invention relates to a display device having a circuit formed using transistors. In particular, the present invention relates to a display device using an electro-optic element such as liquid crystal or a light emitting element as a display medium, and a driving method thereof.

In recent years, display devices have been actively developed due to an increase in large display devices such as liquid crystal televisions. In particular, a technique for integrally forming a driver circuit (hereinafter also referred to as an internal circuit) including a pixel circuit and a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) on an insulating substrate is described. In order to greatly contribute to the reduction of power consumption and cost, development is being actively promoted. An internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter also referred to as an external circuit) via an FPC or the like, and its operation is controlled.

Among the internal circuits shown above, a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised.
A structure of a flip-flop included in a conventional shift register is illustrated in FIG. The flip-flop in FIG. 30A includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, and a transistor 17, and includes a signal line 21, a signal line 22, a wiring 23, a signal line 24, a power supply line 25, The power supply line 26 is connected. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively.
The operation period of the flip-flop in FIG. 30A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in the timing chart of FIG. Selection period.

Here, the transistor 12 and the transistor 16 are on in the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layers of the transistors 12 and 16, the threshold voltage (Vth) varies due to deterioration or the like. More specifically, the threshold voltage increases. That is, the conventional shift register cannot be turned on because the threshold voltages of the transistors 12 and 16 are increased, so that VSS cannot be supplied to the node 41 and the wiring 23 and malfunction occurs.

In order to solve this problem, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3 devise shift registers that can suppress the shift of the threshold voltage of the transistor 12. In Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor). By inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor, the threshold voltage shift of the first transistor and the second transistor is suppressed.

Further, Non-Patent Document 4 devises a shift register that can suppress the shift of the threshold voltage of the transistor 16 as well as the transistor 12. In Non-Patent Document 4, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and another new transistor (referred to as a third transistor) is provided as a transistor. 16 (referred to as a fourth transistor) is arranged in parallel. In the non-selection period, inverted signals are input to the gate electrode of the first transistor and the gate electrode of the second transistor, respectively, and inverted to the gate electrode of the third transistor and the gate electrode of the fourth transistor, respectively. By inputting a signal, a shift in threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed.

Further, in Non-Patent Document 5, the shift of the threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12.

Note that the display devices of Non-Patent Document 6 and Non-Patent Document 7 use a shift register formed of an amorphous silicon transistor as a scanning line driving circuit, and further video from one signal line to R, G, and B subpixels. By inputting signals, the number of signal lines is reduced to 1/3. Thus, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

JP 2004-157508 A

Soo Young Yoon, et al. , "Highly Stable Integrated Gate Driver A-Si TFT with Dual Pull-down STRUCTURE", SICIETY FOR INFORMATION DISPLAY. 348-351 Binn Kim, et al. , "A-Si Gate Driver Integration with Time Shared Data Driving", Proceedings of The 12th International Display Workshops in Conjunction. 1073-1076 Mindoo Chun, et al. , "Integrated Gate Driver Using Highly Stable a-Si TFT's", Proceedings of The 12th International Display Workshops in junction with Asp. 1077-1080 Chun-Ching, et al. , "Integrated Gate Driver Using a-Si TFT", Processeds of The 12th International Display Workshops in junction with Asia Disp. 5, 1023-1026 Yong Ho Jang, et al. , "A-Si TFT Integrated Gate Driver with AC-Driving Single Pull-Down Structure X, SOCIETY FOR INFORMATION DISPLAY TECHNO TECHNO TECHNO TECHN 208-211 Jin Young Choi, et al. , "A Compact and Cost-Efficient TFT-LCD through the Triple-Gate Pixel Structure II XOPIC TECHN TECHN TECHNO TECHN TECHN 274-276 Yong Soon Lee, et al. , "Advanced TFT-LCD Data Line Reduction Method", SOCIETY FOR INFORMATION DISPLAY 2006 INTERNIONAL SYMPOSIUM DIGITAL OF TECHNICAL PAPERS, X. 1083-1086

According to the conventional technique, the shift of the threshold voltage of the transistor is suppressed by applying an AC pulse to the gate of the transistor that is easily deteriorated. However, when amorphous silicon is used as the semiconductor layer of the transistor, it is a problem that the transistor constituting the circuit that generates the AC pulse also causes a threshold voltage shift.

In addition, although it has been proposed to reduce the number of contact points between the display panel and the driver IC by reducing the number of signal lines to 1/3 (Non-Patent Document 6 and Non-Patent Document 7), the driver is practically used. There is a need to further reduce the number of IC contacts.

That is, as a problem that cannot be solved by the conventional technique, a circuit technique that suppresses the fluctuation of the threshold voltage of the transistor remains as a problem. A technique for reducing the number of contact points of a driver IC mounted on a display panel remains as a problem. Lowering power consumption of display devices remains a problem. There remains a problem of enlargement or high definition of the display device.

An object of the invention disclosed in this specification is to provide an industrially useful technique by solving one or more of the above problems.

The display device according to the present invention can suppress the shift of the threshold voltage of the transistor by alternately applying a positive power source and a negative power source to the gate electrode of the transistor which is likely to deteriorate.

Further, the display device according to the present invention alternately supplies a high potential (VDD) or a low potential (VSS) through a switch to a gate electrode of a transistor that is likely to deteriorate, whereby the transistor The threshold voltage shift can be suppressed.

Specifically, the gate electrode of the transistor that is easily deteriorated is connected to a wiring to which a high potential is supplied via the first switching transistor and a wiring to which a low potential is supplied via the second switching transistor, By inputting a clock signal to the gate electrode of the first switching transistor and inputting an inverted clock signal to the gate electrode of the second switching transistor, a high potential or a low potential is alternately applied to the gate electrode of the transistor that is likely to deteriorate. Supply.

Note that a variety of switches can be used as a switch described in this document (specification, claims, drawings, or the like). Examples include electrical switches and mechanical switches. That is, it is only necessary to be able to control the current flow, and is not limited to a specific one. For example, as a switch, a transistor (eg, bipolar transistor, MOS transistor, etc.), diode (eg, PN diode, PIN diode, Schottky diode, MIM (Metal Insulator Metal) diode, MIS (M
etalInsulatorSemiconductor), a diode-connected transistor, or the like), a thyristor, or the like can be used. Alternatively, a logic circuit combining these can be used as a switch.

In the case where a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress off-state current, it is desirable to use a transistor having a polarity with smaller off-state current. As a transistor with low off-state current, a transistor having an LDD region, a transistor having a multi-gate structure, and the like can be given. Alternatively, an N-channel transistor is preferably used in the case where the transistor operates as a switch when the potential of the source terminal of the transistor is close to a low potential power source (Vss, GND, 0 V, or the like). On the other hand, the potential of the source terminal is
In the case of operating in a state close to a high potential side power source (Vdd or the like), it is desirable to use a P-channel transistor. This is because when the N-channel transistor operates with the source terminal close to the low-potential side power supply, and the P-channel transistor operates with the source terminal close to the high-potential side power supply, the absolute value of the gate-source voltage is This is because it can be made larger, so that it operates more reliably as a switch. Moreover, since the source follower operation is rarely performed, the output voltage is rarely reduced.

Note that both N-channel and P-channel transistors are used for CMOS.
A type of switch may be used as the switch. When a CMOS switch is used, a current flows when one of the P-channel transistor and the N-channel transistor is turned on, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Furthermore, since the voltage amplitude value of the signal for turning on / off the switch can be reduced, the power consumption can be reduced.

Note that when a transistor is used as a switch, the switch has an input terminal (one of a source terminal or a drain terminal), an output terminal (the other of the source terminal or the drain terminal), and a terminal for controlling conduction (a gate terminal). doing. On the other hand, when a diode is used as the switch, the switch may not have a terminal for controlling conduction. Therefore, the use of a diode as a switch rather than a transistor can reduce the wiring for controlling the terminal.

In this specification, when A and B are explicitly described as being connected, A and B are electrically connected and A and B are functionally connected. And the case where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, the configuration disclosed in this specification is not limited to a predetermined connection relationship, for example, the connection relationship illustrated in the drawing or text, and includes other than the connection relationship illustrated in the drawing or text.

For example, when A and B are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistance element, a diode, or the like) that enables electrical connection between A and B is provided. 1 or more may be arranged between A and B. Alternatively, when A and B are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit that enables functional connection between A and B (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit,
Step-down circuit), level shifter circuit that changes signal potential level), voltage source, current source,
Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current, etc., operational amplifier,
One or more differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) may be arranged between A and B. Alternatively, when A and B are directly connected, A and B without interposing other elements or other circuits between A and B.
And may be directly connected.

Note that in the case where it is explicitly described that A and B are directly connected, when A and B are directly connected (that is, another element or other circuit between A and B). ) And A and B are electrically connected (that is, A and B are connected with another element or another circuit sandwiched between them). ).

Note that in the case where it is explicitly described that A and B are electrically connected, another element is connected between A and B (that is, between A and B). Or when A and B are functionally connected (that is, they are functionally connected with another circuit between A and B). And a case where A and B are directly connected (that is, a case where another element or another circuit is not connected between A and B). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

Note that a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element can have various modes or have various elements. For example, as a display element, a display device, a light-emitting element, or a light-emitting device, an EL element (an organic EL element, an inorganic EL element, or an EL element including an organic substance and an inorganic substance), an electron-emitting element, a liquid crystal element, electronic ink, an electrophoretic element, Grating light valve (GLV), plasma display (P
DP, a digital micromirror device (DMD), a piezoelectric ceramic display, a carbon nanotube, and other display media whose contrast, luminance, reflectance, transmittance, and the like change due to an electromagnetic action can be used. An EL display is used as a display device using an EL element, and a field emission display (FED) or a SED type flat display (SED: Surface-c) is used as a display device using an electron-emitting device.
Liquid crystal displays (transmission type liquid crystal display, transflective type liquid crystal display, reflective type liquid crystal display, direct view type liquid crystal display, projection type liquid crystal display), electronic ink, and electrophoresis as display devices using liquid crystal elements such as an inductance Electron-emitter Display There is electronic paper as a display device using an element.

Note that various types of transistors can be used as the transistor described in this document (the specification, the claims, the drawings, or the like). Thus, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as semi-amorphous) silicon, or the like can be used. When using TFT, there are various advantages. For example, since manufacturing can be performed at a lower temperature than that of single crystal silicon, manufacturing cost can be reduced or a manufacturing apparatus can be increased in size. Since the manufacturing apparatus can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Then, light transmission through the display element can be controlled using a transistor over a transparent substrate. Alternatively, since the thickness of the transistor is small, part of the film included in the transistor can transmit light. Therefore, the aperture ratio can be improved.

Note that by using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve crystallinity and to manufacture a transistor with favorable electrical characteristics. As a result, a gate driver circuit (scan line driver circuit) and a source driver circuit (signal line driver circuit)
The signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on the substrate.

Note that when a microcrystalline silicon is manufactured, by using a catalyst (such as nickel), crystallinity can be further improved and a transistor with favorable electrical characteristics can be manufactured. At this time, crystallinity can be improved only by applying heat treatment without using a laser. As a result, a part of the gate driver circuit (scanning line driver circuit) and the source driver circuit (analog switch or the like) can be integrally formed on the substrate. Further, when a laser is not used for crystallization, unevenness in crystallinity of silicon can be suppressed. Therefore, a beautiful image can be displayed.

However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. Accordingly, a transistor with small variations in characteristics, size, shape, and the like, high current supply capability, and small size can be manufactured. When these transistors are used, low power consumption of the circuit or high integration of the circuit can be achieved.

Alternatively, a transistor having a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor in which these compound semiconductor or oxide semiconductor is thinned can be used. I can do it. Accordingly, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, the transistor can be formed directly on a substrate having low heat resistance, such as a plastic substrate or a film substrate. These compound semiconductors or oxide semiconductors are
It can be used not only for the channel portion of the transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Furthermore, since these can be formed or formed simultaneously with the transistor, cost can be reduced.

Alternatively, a transistor formed using an inkjet method or a printing method can be used. By these, it can manufacture at room temperature, manufacture at a low vacuum degree, or can manufacture on a large sized board | substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost is reduced and the number of processes can be reduced. Further, since a film is formed only on a necessary portion, the material is not wasted and cost can be reduced as compared with a manufacturing method in which etching is performed after film formation on the entire surface.

Alternatively, a transistor including an organic semiconductor or a carbon nanotube can be used. Thus, a transistor can be formed over a substrate that can be bent.
Therefore, it can be strong against impact.

In addition, various transistors can be used.

Note that various types of substrates on which transistors are formed can be used and are not limited to specific types. As a substrate on which a transistor is formed, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp) ), Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foil, etc. Can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. Alternatively, a transistor may be formed over a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed over another substrate. As a substrate to which the transistor is transferred, a single crystal substrate, an SOI substrate,
Glass substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, cloth substrate (natural fiber (silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (acetate, A plastic substrate, a rubber substrate, a stainless steel substrate, a stainless steel substrate, a foil substrate, and the like. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, or reduce weight.

Note that the structure of the transistor can take a variety of forms. It is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is employed, the channel regions are connected in series, so that a plurality of transistors are connected in series. With the multi-gate structure, the off-state current can be reduced and the reliability can be improved by improving the withstand voltage of the transistor. Or, when operating in the saturation region, the drain-source current does not change much even when the drain-source voltage changes, and the slope of the voltage / current characteristic is flat due to the multi-gate structure. it can. By using the characteristic that the slope of the voltage / current characteristic is flat, an ideal current source circuit and an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. With the structure in which the gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased or the S value can be reduced due to the easy formation of a depletion layer. When gate electrodes are provided above and below a channel, a structure in which a plurality of transistors are connected in parallel is obtained.

Alternatively, a structure in which a gate electrode is disposed over a channel region may be employed, or a structure in which a gate electrode is disposed under a channel region may be employed. Alternatively, a normal stagger structure or an inverted stagger structure may be used, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. Good. Also,
A source electrode or a drain electrode may overlap with the channel region (or a part thereof).
With the structure in which the source electrode or the drain electrode overlaps with the channel region (or part thereof), it is possible to prevent electric charges from being accumulated in part of the channel region and unstable operation. Further, an LDD region may be provided. By providing the LDD region, the off-state current can be reduced or the reliability can be improved by improving the withstand voltage of the transistor. Or L
By providing a DD region, when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change so much and the slope of the voltage / current characteristic is flat. Can do.

Note that various types of transistors can be used in this specification, and the transistor can be formed over various substrates. Therefore, all of the circuits necessary for realizing a predetermined function may be formed on the same substrate. For example, all circuits necessary for realizing a predetermined function may be formed over a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, or may be formed over various substrates. . Since all the circuits necessary to realize a given function are formed on the same board, the number of parts can be reduced to reduce costs, and the number of connection points with circuit parts can be reduced to improve reliability. can do. Alternatively, a part of the circuit necessary for realizing the predetermined function is formed on a certain substrate, and another part of the circuit necessary for realizing the predetermined function is formed on another substrate. It may be. That is, not all of the circuits necessary for realizing a predetermined function may be formed on the same substrate. For example, a part of a circuit necessary for realizing a predetermined function is formed using a transistor over a glass substrate, and another part of a circuit required for realizing a predetermined function is a single crystal substrate. The IC chip formed on the single crystal substrate and formed of a transistor may be connected to the glass substrate by COG (Chip On Glass), and the IC chip may be arranged on the glass substrate. Alternatively, the IC chip is TAB (Tape A
(automated Bonding) or a printed circuit board may be used to connect to the glass substrate. As described above, since a part of the circuit is formed on the same substrate, the number of parts can be reduced to reduce the cost, and the number of connection points with the circuit parts can be reduced to improve the reliability. In addition, since the power consumption of a circuit having a high driving voltage or a high driving frequency is large, such a circuit is not formed on the same substrate. Instead, for example, on a single crystal substrate. If the circuit of that portion is formed and an IC chip constituted by the circuit is used, an increase in power consumption can be prevented.

Note that in this specification, one pixel represents one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, at that time, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel, and a B pixel. It is assumed to be composed of three pixels. Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, and the like may be added to RGB. Further, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1, and B2 may be used. B
1 and B2 are both blue, but have slightly different frequencies. Similarly, R1, R2
, G, and B may be used. By using such color elements, it is possible to perform display closer to the real thing or to reduce power consumption. As another example, when brightness is controlled using a plurality of areas for one color element, one area may be used as one pixel. Therefore, as an example, when area gradation is performed or when sub-pixels (sub-pixels) are provided, there are a plurality of brightness control areas for one color element, and the gradation is expressed as a whole. However, one pixel for controlling the brightness may be one pixel. Therefore,
In that case, one color element is composed of a plurality of pixels. Alternatively, even if there are a plurality of areas for controlling the brightness in one color element, they are combined into one color element.
It may be a pixel. Therefore, in that case, one color element is composed of one pixel. When brightness is controlled using a plurality of areas for one color element, the size of the area contributing to display may be different depending on the pixel. In addition, in a plurality of brightness control areas for one color element, a signal supplied to each may be slightly different to widen the viewing angle. That is, for one color element, the potentials of the pixel electrodes in each of a plurality of regions may be different from each other. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

In addition, when it is explicitly described as one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered as one pixel. When it is explicitly described as one pixel (for one color), it is assumed that when there are a plurality of areas for one color element, they are considered as one pixel.

Note that in this document (the specification, the claims, the drawings, or the like), the pixels may be arranged (arranged) in a matrix. Here, the pixel being arranged (arranged) in the matrix includes a case where the pixels are arranged in a straight line or a jagged line in the vertical direction or the horizontal direction. Thus, for example, three color elements (for example, R
When full-color display is performed in GB), this includes the case where stripes are arranged and the case where dots of three color elements are arranged in delta. Furthermore, the case where a Bayer is arranged is included. Note that the color elements are not limited to three colors, and may be more than that, for example, RGBW (W is white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added.
Further, the size of the display area may be different for each dot of the color element. Thereby, it is possible to reduce power consumption or extend the life of the display element.

Note that in this document (the specification, the claims, the drawings, or the like), an active matrix method in which an active element is included in a pixel or a passive matrix method in which an active element is not included in a pixel can be used.

In the active matrix system, not only transistors but also various active elements (active elements and nonlinear elements) can be used as active elements (active elements and nonlinear elements). For example, MIM (Metal Insulator Metal) or TFD (Th
inFilmDiode) or the like can also be used. Since these elements have few manufacturing steps, manufacturing cost can be reduced or yield can be improved. Furthermore, since the size of the element is small, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

Note that as a method other than the active matrix method, a passive matrix type that does not use active elements (active elements, nonlinear elements) can be used. Since no active element (active element or nonlinear element) is used, the number of manufacturing steps is small, and manufacturing cost can be reduced or yield can be improved. In addition, since an active element (an active element or a non-linear element) is not used, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

Note that a transistor is an element having at least three terminals including a gate, a drain, and a source. The transistor has a channel region between the drain region and the source region, and the drain region, the channel region, and the source region. A current can be passed through. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in this specification,
A region functioning as a source and a drain may not be referred to as a source or a drain. In that case, as an example, there are cases where they are referred to as a first terminal and a second terminal, respectively. Alternatively, they may be referred to as a first electrode and a second electrode, respectively. Alternatively, they may be referred to as a source region and a drain region.

Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly, in this case, the emitter and collector are connected to the first terminal and the second terminal.
Sometimes referred to as a terminal.

Note that a gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line, a gate signal line, a scan line, a scan signal line, or the like). A gate electrode refers to a portion of a conductive film that overlaps with a semiconductor forming a channel region with a gate insulating film interposed therebetween. Note that part of the gate electrode is an LDD (Lightly Dope
dDrain) region or the source region and the drain region may overlap with the gate insulating film. A gate wiring is a wiring for connecting the gate electrodes of each transistor, a wiring for connecting the gate electrodes of each pixel, or a wiring for connecting the gate electrode to another wiring. Say.

However, there are portions (regions, conductive films, wirings, etc.) that also function as gate electrodes and function as gate wirings. Such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a part of the gate wiring extended and the channel region overlap, the portion (region, conductive film, wiring, etc.) functions as the gate wiring, but also as the gate electrode It is functioning. Therefore, such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring.

Note that a portion (a region, a conductive film, a wiring, or the like) formed using the same material as the gate electrode and connected to form the same island (island) as the gate electrode may be called a gate electrode. Similarly, a portion (a region, a conductive film, a wiring, or the like) formed using the same material as the gate wiring and connected by forming the same island (island) as the gate wiring may be referred to as a gate wiring. In a strict sense, such a portion (region, conductive film, wiring, or the like) may not overlap with the channel region or may not have a function of being connected to another gate electrode. However, due to conditions in the manufacturing process, etc., a portion (region, conductive film, wiring, etc.) that is formed of the same material as the gate electrode or gate wiring and forms the same island (island) as the gate electrode or gate wiring. ) Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a gate electrode or a gate wiring.

Note that, for example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected to each other with a conductive film formed using the same material as the gate electrode. Such a portion (region, conductive film, wiring, or the like) is a portion (region, conductive film, wiring, or the like) for connecting the gate electrode to the gate electrode, and may be called a gate wiring. These transistors can be regarded as a single transistor, and may be referred to as a gate electrode. That is, a portion (region, conductive film, wiring, or the like) that is formed using the same material as the gate electrode or gate wiring and is connected to form the same island (island) as the gate electrode or gate wiring is connected to the gate electrode or gate wiring. You can call it. Further, for example, a conductive film in a portion where the gate electrode and the gate wiring are connected and formed of a material different from the gate electrode or the gate wiring may be referred to as a gate electrode. You may call it.

Note that a gate terminal means a part of a part of a gate electrode (a region, a conductive film, a wiring, or the like) or a part electrically connected to the gate electrode (a region, a conductive film, a wiring, or the like). .

Note that in the case of calling a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, the gate line, the gate signal line, the scanning line, and the scanning signal line are simultaneously formed with the wiring formed in the same layer as the gate of the transistor, the wiring formed of the same material as the gate of the transistor, or the gate of the transistor. It may mean a deposited wiring. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

Note that a source refers to the whole or part of a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, or the like). The source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a little P-type impurity or N-type impurity, that is, a so-called LDD (Lightly Doped Drain) region is not included in the source region. A source electrode refers to a portion of a conductive layer which is formed using a material different from that of a source region and is electrically connected to the source region. However, the source electrode may be referred to as a source electrode including the source region. The source wiring is a wiring for connecting the source electrodes of the transistors, a wiring for connecting the source electrodes of each pixel, or a wiring for connecting the source electrode to another wiring. Say.

However, there are portions (regions, conductive films, wirings, and the like) that also function as source electrodes and function as source wirings. Such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, in the case where a part of a source wiring that is extended and the source region overlap with each other, the portion (region, conductive film, wiring, etc.) functions as a source wiring, but as a source electrode Will also work. Thus, such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring.

Note that a portion (region, conductive film, wiring, or the like) that is formed using the same material as the source electrode and forms the same island (island) as the source electrode, or a portion (region) that connects the source electrode and the source electrode , Conductive film, wiring, etc.) may also be referred to as source electrodes. Further, a portion overlapping with the source region may be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected by forming the same island as the source wiring may be called a source wiring. Such a portion (region, conductive film, wiring, or the like) may not have a function of connecting to another source electrode in a strict sense. However, there is a portion (a region, a conductive film, a wiring, or the like) that is formed using the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring due to conditions such as conditions in the manufacturing process. Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a source electrode or a source wiring.

Note that, for example, a conductive film in a portion where the source electrode and the source wiring are connected and formed using a material different from that of the source electrode or the source wiring may be referred to as a source electrode or a source wiring. You may call it.

Note that a source terminal refers to a part of a source region, a source electrode, or a portion (region, conductive film, wiring, or the like) electrically connected to the source electrode.

In addition, when calling a source wiring, a source line, a source signal line, a data line, a data signal line, etc.
In some cases, the source (drain) of the transistor is not connected to the wiring. In this case, the source wiring, the source line, the source signal line, the data line, and the data signal line are the wiring formed in the same layer as the source (drain) of the transistor and the wiring formed of the same material as the source (drain) of the transistor. Alternatively, it may mean a wiring formed simultaneously with the source (drain) of the transistor. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

The drain is the same as the source.

Note that a semiconductor device refers to a device having a circuit including a semiconductor element (a transistor, a diode, a thyristor, or the like). Furthermore, a device that can function by utilizing semiconductor characteristics may be called a semiconductor device.

Note that a display element means an optical modulation element, a liquid crystal element, a light emitting element, an EL element (an organic EL element, an inorganic EL element or an EL element containing an organic substance and an inorganic substance), an electron-emitting element, an electrophoretic element, a discharge element, and a light reflection element. An element, a light diffraction element, a digital micromirror device (DMD), etc. are said. However, it is not limited to this.

Note that a display device refers to a device having a display element. Note that the display device may be a display panel body in which a plurality of pixels including display elements or a peripheral drive circuit for driving the pixels is formed over the same substrate. Note that the display device includes a peripheral drive circuit arranged on the substrate by wire bonding or bumps, an IC chip connected by so-called chip on glass (COG), or an IC chip connected by TAB or the like. May be. Note that the display device may include a flexible printed circuit (FPC) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, and the like are attached. Note that the display device may include a printed wiring board (PWB) connected via a flexible printed circuit (FPC) or the like to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, or the like is attached. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include a lighting device, a housing, a voice input / output device, an optical sensor, and the like. Here, the illumination device such as the backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water cooling type, air cooling type) and the like. good.

Note that the lighting device refers to a device including a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source (such as an LED, a cold cathode tube, a hot cathode tube), a cooling device, and the like.

Note that a light-emitting device refers to a device having a light-emitting element or the like.

The reflection device refers to a device having a light reflection element, a light diffraction element, a light reflection electrode, and the like.

Note that a liquid crystal display device refers to a display device having a liquid crystal element. Liquid crystal display devices include direct view type, projection type, transmission type, reflection type, and transflective type.

Note that a driving device refers to a device including a semiconductor element, an electric circuit, and an electronic circuit. For example, a transistor that controls input of a signal from a source signal line into a pixel (sometimes referred to as a selection transistor or a switching transistor), a transistor that supplies voltage or current to a pixel electrode, or a voltage or current to a light-emitting element A transistor that supplies the voltage is an example of a driving device. Further, a circuit for supplying a signal to the gate signal line (sometimes referred to as a gate driver or a gate line driver circuit) and a circuit for supplying a signal to the source signal line (sometimes referred to as a source driver or source line driver circuit). ) Is an example of a driving device.

Note that a display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflecting device, a driving device, and the like may overlap with each other. For example, the display device may include a semiconductor device and a light-emitting device. Alternatively, the semiconductor device may include a display device and a driving device.

In addition, in this document (specifications, claims or drawings, etc.), if it is explicitly stated that B is formed on A or B is formed on A, B on A
Is not limited to being formed in direct contact. If not in direct contact, that is, A
And a case where another object is interposed between B and B. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Therefore, for example, when it is explicitly described that the layer B is formed on the layer A (or on the layer A), the layer B is formed in direct contact with the layer A. And the case where another layer (for example, layer C or layer D) is formed in direct contact with the layer A, and the layer B is formed in direct contact therewith. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

Furthermore, the same applies to the case where B is explicitly described as being formed above A, and is not limited to the direct contact of B on A. This includes the case where another object is interposed in. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed in direct contact with the layer A and the case where another layer is formed in direct contact with the layer A. (For example, the layer C or the layer D) is formed, and the layer B is formed in direct contact therewith. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

In addition, when it is explicitly described that B is formed in direct contact with A, it includes a case in which B is formed in direct contact with A. It shall not be included when an object is present.

The same applies to the case where B is below A or B is below A.

According to this specification, deterioration of characteristics of all transistors included in the shift register can be suppressed. Therefore, malfunction of a semiconductor device to which the shift register such as a liquid crystal display device is applied can be suppressed.

3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 2 is a timing chart illustrating the operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3 is a timing chart illustrating operation of the flip-flop described in Embodiment 1; 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a shift register described in Embodiment 1. 12 is a timing chart illustrating operation of the shift register illustrated in FIG. 11. 12 is a timing chart illustrating operation of the shift register illustrated in FIG. 11. 3A and 3B illustrate a structure of a shift register described in Embodiment 1. FIG. 15 is a diagram illustrating the configuration of the buffer illustrated in FIG. 14. FIG. 15 is a diagram illustrating the configuration of the buffer illustrated in FIG. 14. 3A and 3B illustrate a structure of a display device described in Embodiment 1. 18 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 3A and 3B illustrate a structure of a display device described in Embodiment 1. 3A and 3B illustrate a structure of a display device described in Embodiment 1. FIG. 21 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 20. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. FIG. 5 illustrates a structure of a shift register shown in Embodiment 2; 25 is a timing chart illustrating operation of the shift register illustrated in FIG. 25 is a timing chart illustrating operation of the shift register illustrated in FIG. 3A and 3B illustrate a structure of a display device described in Embodiment 2. 3A and 3B illustrate a structure of a display device described in Embodiment 2. FIG. 8 is a top view of the flip-flop in FIG. The figure which shows the structure of the conventional flip-flop. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. FIG. 32 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 31. FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 34 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 8A and 8B illustrate a structure of a display device described in Embodiment 7. FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 3; 41 is a timing chart illustrating operation of the flip-flop illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 3; 43 is a timing chart illustrating operation of the shift register illustrated in FIG. FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 4; 45 is a timing chart illustrating operation of the flip-flop illustrated in FIG. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. FIG. 6 is a top view of a display element of a semiconductor device according to the present invention. FIG. 6 is a top view of a display element of a semiconductor device according to the present invention. FIG. 6 is a top view of a display element of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 6A and 6B illustrate a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. 8A and 8B illustrate a device for forming a display element of a semiconductor device according to the present invention. 8A and 8B illustrate a device for forming a display element of a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 6A and 6B illustrate one pixel circuit of a semiconductor device according to the present invention. 6A and 6B illustrate one pixel circuit of a semiconductor device according to the present invention. 8A and 8B illustrate a process for manufacturing a semiconductor device according to the present invention. 8A and 8B illustrate a display element of a semiconductor device according to the present invention. 8A and 8B illustrate a display element of a semiconductor device according to the present invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
In this embodiment, a structure and a driving method of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit are described.

A basic structure of the flip-flop of this embodiment is described with reference to FIG.
The flip-flop illustrated in FIG. 1A includes a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, and a fifth transistor 1.
05, sixth transistor 106, seventh transistor 107, and eighth transistor 1
08. In this embodiment, the first transistor 101 to the eighth transistor 108 are N-channel transistors and are turned on when a gate-source voltage (Vgs) exceeds a threshold voltage (Vth). And

Note that the flip-flop of this embodiment is characterized in that the first transistor 101 to the eighth transistor 108 are all N-channel transistors. Therefore, in the flip-flop of this embodiment, amorphous silicon can be used as a semiconductor layer of a transistor, so that a manufacturing process can be simplified, manufacturing cost can be reduced, and yield can be improved. . However, as the semiconductor layer of the transistor,
Even when polysilicon or polycrystalline silicon is used, the manufacturing process can be simplified.

A connection relation of the flip-flop of FIG. The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is the first electrode. 3 wiring 123. The first electrode of the second transistor 102 is the fourth wiring 1
24, the second electrode of the second transistor 102 is connected to the third wiring 123,
A gate electrode of the second transistor 102 is connected to the eighth wiring 128. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the sixth transistor 106, and the third transistor 1
The gate electrode 03 is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the tenth wiring 130, the second electrode of the fourth transistor 104 is connected to the gate electrode of the sixth transistor 106, and the gate of the fourth transistor 104 The electrode is connected to the eighth wiring 128. The first electrode of the fifth transistor 105 is connected to the ninth wiring 1
29, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate electrode of the fifth transistor 105 is connected to the first wiring 121. The first electrode of the sixth transistor 106 is connected to the twelfth wiring 132, and the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101. The first electrode of the seventh transistor 107 is connected to the thirteenth wiring 133, the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 101,
A gate electrode of the seventh transistor 107 is connected to the second wiring 122. The first electrode of the eighth transistor 108 is connected to the eleventh wiring 131, and the eighth transistor 108
The second electrode is connected to the gate electrode of the sixth transistor 106, and the gate electrode of the eighth transistor 108 is connected to the gate electrode of the first transistor 101.

Note that a connection position of the gate electrode of the first transistor 101, the second electrode of the sixth transistor 106, the second electrode of the seventh transistor 107, and the gate electrode of the eighth transistor 108 is a node 141. Further, the second electrode of the third transistor 103, the fourth electrode
A connection portion of the second electrode of the transistor 104, the gate electrode of the sixth transistor 106, and the second electrode of the eighth transistor 108 is a node 142.

Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, the seventh wiring 127, and the eighth wiring 128 are respectively connected to the first signal line and the second signal 128. May be called a line, a third signal line, a fourth signal line, a fifth signal line, or a sixth signal line. Furthermore, the fourth wiring 124, the sixth wiring 126, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 1
31, the 12th wiring 132, and the 13th wiring 133 are respectively connected to the first power supply line, the second power supply line, the third power supply line, the fourth power supply line, the fifth power supply line, and the sixth power supply. May be referred to as a power line or a seventh power line.

Next, operation of the flip-flop illustrated in FIG. 1A is described with reference to a timing chart of FIG. 2 and FIGS. 3 and 4. Furthermore, the timing chart of FIG.
The description will be divided into a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

Note that the potential of V1 is supplied to the sixth wiring 126 and the ninth wiring 129, and the fourth wiring 1
24, the potential of V2 is supplied to the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133. Here, V1> V2.

Note that the first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 are respectively provided with a signal 221, a signal 225, a signal 228, and a signal 227 shown in FIG. , A signal 222 is input. Then, the signal 2 shown in FIG.
23 is output. Here, signal 221, signal 225, signal 228, signal 227, signal 2
22 and the signal 223 are digital signals in which the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level). Furthermore, signal 221 and signal 2
25, signal 228, signal 227, signal 222 and signal 223, respectively, start signal,
You may call a power clock signal (PCK), a 1st control clock signal (CCK1), a 2nd control clock signal (CCK2), a reset signal, and an output signal.

However, the first wiring 121, the second wiring 122, the fourth wiring 124 to the thirteenth wiring 133 are used.
Various signals, potentials, and currents may be input to each.

First, in the set period shown in FIGS. 2A and 3A, the signal 221 becomes H level, the fifth transistor 105 is turned on, and the signal 222 is L level, so that the seventh transistor 107 is turned off. 228 becomes H level, the second transistor 102 and the fourth transistor 104 are turned on, the signal 227 becomes L level, and the third transistor 103 is turned off. At this time, the potential of the node 141 (the potential 241) is changed from the potential of the ninth wiring 129 to the fifth transistor 105 with the second electrode of the fifth transistor 105 serving as a source electrode.
Therefore, V1-Vth105 (Vth105: threshold voltage of the fifth transistor 105) is obtained. Accordingly, the first transistor 101 and the eighth transistor 108 are turned on, and the fifth transistor 105 is turned off. Node 1 at this time
The potential 42 (potential 242) becomes V2, and the sixth transistor 106 is turned off. In this manner, in the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input and the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 is V2. It becomes. Therefore, the L signal is output from the third wiring 123. Further, the node 141 is in a floating state with the potential maintained at V1−Vth105.

Note that as shown in FIG. 5A, the flip-flop of this embodiment mode is similar to the above-described set period even when the first electrode of the fifth transistor 105 is connected to the first wiring 121. Operation can be performed. In the flip-flop in FIG. 5A, the ninth wiring 129 is unnecessary, so that the yield can be improved. Further, the flip-flop in FIG. 5A can reduce the layout area.

Note that the flip-flop of this embodiment includes a transistor 50 as illustrated in FIG.
1 may be newly arranged. The transistor 501 has a first electrode connected to the wiring 511 to which V2 is supplied, a second electrode connected to the node 141, and a gate electrode connected to the first wiring 1
21. In the flip-flop in FIG. 5C, the time during which the potential of the node 142 is decreased by the transistor 501 can be shortened, so that the sixth transistor 106 can be quickly turned off. Therefore, in the flip-flop in FIG. 5C, the potential of the node 141 is V1-V.
Since the time to reach th105 can be shortened, high-speed operation is possible, and the invention can be applied to a larger display device or a higher definition display device.

In the selection period illustrated in FIGS. 2B and 3B, the signal 221 is at the L level, the fifth transistor 105 is turned off, and the signal 222 remains at the L level.
Remains off, the signal 228 becomes L level, the second transistor 102 and the fourth transistor 104 are turned off, the signal 227 becomes H level, and the third transistor 103 is turned on. At this time, the node 141 maintains the potential at V1−Vth105. Therefore, the first transistor 101 and the eighth transistor 108 are kept on. At this time, the potential of the node 142 is such that the potential difference (V1−V2) between the potential (V2) of the eleventh wiring 131 and the potential (V1) of the sixth wiring 126 is the third transistor 103 and the eighth transistor 108. Is divided into V2 + β (β: an arbitrary positive number). Furthermore, β <Vth
106 (the threshold voltage of the sixth transistor 106). Accordingly, the sixth transistor 106 remains off. Here, since the H signal is input to the fifth wiring 125, the third wiring 125
The potential of the wiring 123 starts to rise. Then, the potential of the node 141 rises from V1−Vth105 by the bootstrap operation, and V1 + Vth101 + α (Vth101:
The threshold voltage of the first transistor 101, α: an arbitrary positive number). Therefore, the potential of the third wiring 123 is equal to that of the fifth wiring 125 and thus becomes V1. In this manner, in the selection period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the H signal is input, so that the potential of the third wiring 123 is V1. Therefore, the H signal is the third wiring 1
23.

Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 101. However, as shown in FIG. 1B, by disposing the capacitor 151 between the gate electrode and the second electrode of the first transistor 101, a bootstrap operation can be stably performed. The parasitic capacitance of the first transistor 101 can be reduced. Here, the capacitor 151 may use a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as a conductive layer, or use a gate insulating film as an insulating layer and a gate electrode layer and an impurity as a conductive layer. May be used, or an interlayer film (insulating film) may be used as an insulating layer, and a wiring layer and a transparent electrode layer may be used as a conductive layer.
However, in the capacitor 151, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101, and the wiring layer is connected to the second electrode of the first transistor 101. It is good to connect. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is directly connected to the second electrode of the first transistor 101. Good. Because
This is because the increase in the layout area of the flip-flop due to the arrangement of the capacitor 151 is reduced.

Further, a transistor 152 may be used as the capacitor 151 as illustrated in FIG. The transistor 152 can function as a capacitor having a large capacitance component by connecting the gate electrode to the node 141 and connecting the first electrode and the second electrode to the third wiring 123. Note that the transistor 152 can function as a capacitor even when one of the first electrode and the second electrode is floated.

Note that the first transistor 101 must supply an H signal to the third wiring 123. Therefore, in order to shorten the fall time and the rise time of the signal 223, the W / L value of the first transistor 101 is set to the W / L value of each of the first transistor 101 to the eighth transistor 108. It is desirable to make it the maximum.

Further, in the fifth transistor 105, the potential of the node 142 (the gate electrode of the first transistor 101) must be V1−Vth105 in the set period. Therefore, the value of W / L of the fifth transistor 105 is The W / L value of the first transistor 101 is ½ times to 5 times, more preferably 1 / times to ¼ times.

Note that in order to set the potential of the node 142 to V2 + β, the ratio W / L of the channel width W to the channel length L of the eighth transistor 108 is larger than the value of W / L of the third transistor 103. It is preferable to make it at least 10 times or more. Therefore, the eighth transistor 10
8 transistor size (W × L) becomes large. Here, the value of the channel length L of the third transistor 103 is larger than the value of the channel length L of the eighth transistor 108, more preferably 2 to 3 times, so that the transistor of the eighth transistor 108 Since the size can be reduced, the layout area can be reduced.

In the reset period illustrated in FIGS. 2C and 3C, since the signal 221 remains at the L level, the fifth transistor 105 remains off, the signal 222 becomes the H level, and the seventh transistor 107 is turned on. Then, the signal 228 becomes H level, the second transistor 102 and the fourth transistor 104 are turned on, the signal 227 becomes L level, and the third transistor 10
3 turns off. The potential of the node 141 at this time is V 2 because the potential (V 2) of the thirteenth wiring 133 is supplied through the seventh transistor 107. Accordingly, the first transistor 101 and the eighth transistor 108 are turned off. The potential of the node 142 at this time is V2 because the fourth transistor 104 is turned on. Accordingly, the sixth transistor 106 is turned off. Thus, in the reset period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

Note that the signal 223 is delayed by delaying the timing at which the seventh transistor 107 is turned on.
The fall time can be shortened. This is because the L signal input to the fifth wiring 125 is W
This is because the voltage can be supplied to the third wiring 123 through the first transistor 101 having a large / L value.

Alternatively, even if the W / L value of the seventh transistor 107 is reduced and the fall time until the potential of the node 141 becomes V2 is increased, the fall time of the signal 223 can be shortened. In this case, the value of the seventh transistor W / L is set to 1/10 to 1/40 times, more preferably 1/20 to 1/30 times the value of W / L of the first transistor 101.

Note that as shown in FIG. 5B, the operation similar to that in the set period described above can be performed without the seventh transistor 107. In the flip-flop in FIG. 5B, the number of transistors and wirings can be reduced, so that the layout area can be reduced.

In the first non-selection period shown in FIGS. 2D and 4D, since the signal 221 remains at the L level, the fifth transistor 105 remains off, and the signal 222 becomes the L level. The transistor 107 is turned off, the signal 228 becomes L level, and the second transistor 10
The second and fourth transistors 104 are turned off, the signal 227 becomes H level, and the third transistor 103 is turned on. The potential of the node 142 at this time is obtained by subtracting the threshold voltage of the third transistor 103 from the potential (V1) of the seventh wiring 127 with the second electrode of the third transistor 103 serving as a source electrode. Therefore, V1−Vth103 (Vth103: threshold voltage of the third transistor 103). Accordingly, the sixth transistor 106 is turned on. Since the sixth transistor 106 is turned on at this time, the potential of the node 141 is turned on.
V2. Accordingly, the first transistor 101 and the eighth transistor 108 remain off. Thus, in the first non-selection period, the third wiring 123 is in a floating state and maintains the potential at V2.

Note that the flip-flop of this embodiment can suppress a shift in threshold voltage of the second transistor 102 by turning off the second transistor 102.

Note that the threshold voltage shift of the third transistor 103 can be suppressed by setting the potential of the signal 227 to be equal to or lower than V1 and decreasing the potential of the gate electrode of the third transistor 103. Further, the threshold voltage of the fourth transistor 104 and the second transistor 102 is shifted by applying a reverse bias to the fourth transistor 104 and the second transistor 102 by setting the potential of the signal 228 to V2 or less. Can be suppressed.

Note that as illustrated in FIG. 9A, V2 can be supplied to the third wiring 123 by newly arranging the transistor 901. Since the transistor 901 has a first electrode connected to the fourth wiring 124, a second electrode of the transistor 901 is connected to the third wiring 123, and a gate electrode is connected to the node 142, the sixth transistor On at the same timing as 106
Off is controlled. Therefore, the flip-flop in FIG. 9A can be resistant to noise because the third wiring 123 does not enter a floating state. Further, as shown in FIG.
Instead of the transistor 102, a transistor 901 can be provided.

In the second non-selection period shown in FIGS. 2E and 4E, since the signal 221 remains at the L level, the fifth transistor 105 remains off and the signal 222 remains at the L level. 7 transistor 107 remains off, the signal 228 becomes H level, the second transistor 102 and the fourth transistor 104 are turned on, the signal 227 becomes L level, and the third transistor 103 is turned off. At this time, the potential of the node 142 is V2 because the fourth transistor 104 is turned on. Accordingly, the sixth transistor 106 is turned off.
Since the node 141 at this time is in a floating state, the potential is maintained at V2. Accordingly, the first transistor 101 and the eighth transistor 108 remain off. Thus, the second
In the non-selection period, since the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, the potential of the third wiring 123 is V2. Therefore, the L signal is output from the third wiring 123.
Is output from.

Note that the flip-flop in this embodiment can suppress a shift in threshold voltage of the sixth transistor 106 by turning off the sixth transistor 106.

Note that the flip-flop of this embodiment includes the third wiring 12 in the second non-selection period.
Even if the potential of 3 fluctuates due to noise, the potential of the third wiring 123 can be set to V2. Further, in the flip-flop of this embodiment, even when the potential of the node 141 varies due to noise, the potential of the node 141 can be set to V2 in the first non-selection period.

Note that the threshold voltage shift of the third transistor 103 can be suppressed by setting the potential of the signal 227 to V2 or less and applying a reverse bias to the third transistor 103. Further, the potential of the signal 228 is set to V1 or lower so that the gate electrode of the fourth transistor 104 and the second
By reducing the potential of the electrode of the transistor 102, the fourth transistor 104 and the second transistor
The shift of the threshold voltage of the transistor 102 can be suppressed.

From the above, the flip-flop of this embodiment can suppress a threshold shift of the second transistor 102 and the sixth transistor 106, and thus can have a long lifetime. Further, the flip-flop of this embodiment can suppress a shift in threshold voltage of all transistors, so that the lifetime can be extended. Further, since the flip-flop of this embodiment is resistant to noise, reliability can be improved.

Here, functions of the first transistor 101 to the eighth transistor 108 are described. The first transistor 101 has a function of selecting the timing at which the potential of the fifth wiring 125 is supplied to the third wiring 123 and increasing the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor. To do. Second transistor 10
2 has a function of selecting timing for supplying the potential of the fourth wiring 124 to the third wiring 123 and functions as a switching transistor. The third transistor 103 is the sixth transistor
The wiring 126 has a function of selecting the timing for supplying the potential of the wiring 126 to the node 142 and functions as a switching transistor. The fourth transistor 104 includes a tenth wiring 130.
Has a function of selecting the timing of supplying the potential to the node 124 and functions as a switching transistor. The fifth transistor 105 has a function of selecting timing for supplying the potential of the ninth wiring 129 to the node 141 and functions as an input transistor. The sixth transistor 106 has a function of selecting timing for supplying the potential of the twelfth wiring 132 to the node 141 and functions as a switching transistor. The seventh transistor 107 has a function of selecting timing for supplying the potential of the thirteenth wiring 133 to the node 141 and functions as a switching transistor. Eighth transistor 10
8 has a function of selecting the timing at which the potential of the eleventh wiring 131 is supplied to the node 142 and functions as a switching transistor.

Note that the first transistor 101 to the eighth transistor 108 are not limited to transistors as long as they have the functions described above. For example, the second transistor 102, the fourth transistor 104, the third transistor 103, the fourth transistor 104, the sixth transistor 106, and the seventh transistor 1 functioning as switching transistors.
As long as the 07 and the eighth transistors 108 are elements having a switching function, diodes, CMOS analog switches, various logic circuits, or the like may be applied. Further, the fifth transistor 105 that functions as an input transistor only needs to have a function of selecting the timing of turning off by increasing the potential of the node 141. A PN junction diode or a diode-connected transistor is used as the fifth transistor 105. Also good.

Note that the arrangement and the number of transistors are not limited to those in FIG. 1 as long as the operation similar to that in FIG. 1 is performed. As can be seen from FIGS. 3 and 4 describing the operation of the flip-flop of FIG. 1, in this embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are It suffices that the continuity is taken as indicated by solid lines in FIGS. 3A to 3C, 4D, and 4E. Therefore, transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic circuits, etc. are newly arranged if the transistor can be arranged and operated to satisfy this requirement. Also good.

For example, the potential of the node 142 is determined depending on whether the third transistor 103 is turned on or the fourth transistor 104 is turned on. However, as shown in FIG.
Between the seventh wiring 127 and the eighth wiring 128, the resistance element 1011 and the resistance element 1012
Even if they are connected, the same operation as in FIG. 1A is possible. The flip-flop in FIG. 10A can reduce the number of transistors and the number of wirings, so that the layout area can be reduced, the yield can be improved, and the like.

Further, as shown in FIG. 10B, a diode-connected transistor 1021 and a diode-connected transistor 1022 are arranged between the seventh wiring 127 and the node 142 instead of the resistance element 1011, and the eighth wiring 128. Instead of the resistance element 1012, the diode-connected transistor 1023 and the diode-connected transistor 10 are connected between the node 142 and the node 142.
24 may be arranged. The seventh wiring 127 is connected to the first electrode of the transistor 1021, the gate electrode of the transistor 1021, and the first electrode of the transistor 1022. The eighth wiring 128 is connected to the first electrode of the transistor 1023 and the transistor 1024. And the gate electrode of the transistor 1024 are connected to each other. The node 142 has a second electrode of the transistor 1021, a second electrode of the transistor 1022, a gate electrode of the transistor 1022, a second electrode of the transistor 1023, and a transistor The gate electrode of 1023 and the second electrode of the transistor 1024 are connected. That is, the seventh wiring 127 and the node 1
42, and between the eighth wiring 128 and the node 142, two diodes are connected in opposite directions and in parallel, respectively.

Note that as long as the operation similar to that in FIG. 1 is performed, the driving timing of the flip-flop of this embodiment is not limited to the timing chart in FIG.

For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the second wiring 122 are used.
The period during which the H signal is input to the fifth wiring 125, the seventh wiring 127, and the eighth wiring 128 may be shortened. In FIG. 6, the timing at which the signal switches from the L level to the H level is delayed by the period Ta1, and the timing at which the signal switches from the H level to the L level is advanced by the period Ta2, as compared with the timing chart of FIG. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, since the instantaneous current of each wiring becomes small, power saving,
It is possible to suppress malfunctions and improve the range of operating conditions. Further, the flip-flop to which the timing chart of FIG. 6 is applied has the third wiring 12 in the reset period.
The fall time of the signal output from 3 can be shortened. This is because the timing at which the potential of the node 141 becomes L level is delayed by the period Ta1 + the period Ta2, so that the fifth wiring 12
This is because the L signal input to 5 is supplied to the third wiring 123 through the first transistor 101 having a large current capability (a channel width is large). Note that portions common to the timing chart of FIG. 2 are denoted by common reference numerals, and description thereof is omitted.

Note that the relationship between the period Ta1, the period Ta2, and the period Tb is ((Ta1 + Tb) / (Ta1 +
Ta2 + Tb)) × 100 <10 [%] is desirable. More preferably, ((T
a1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <5 [%] is desirable.
Further, it is desirable that the period Ta1≈the period Ta2.

Note that the first wiring 121 to the thirteenth wiring 131 can be freely connected as long as the operation similar to that in FIG. 1 is performed. For example, as shown in FIG. 7A, the second transistor 1
02 first electrode, first electrode of the fourth transistor 104, sixth transistor 106
The first electrode of the seventh transistor 107, the first electrode of the seventh transistor 107, and the first electrode of the eighth transistor 108 may be connected to the seventh wiring 707. Further, the fifth transistor 105
The first electrode and the first electrode of the third transistor 103 may be connected to the sixth wiring 706. Further, the first electrode of the first transistor 101 and the third transistor 10
3 gate electrodes may be connected to the fourth wiring 704. Note that the first electrode of the first transistor 101 may be connected to the eighth wiring 708 as illustrated in FIG. Further, as shown in FIG. 8A, the first electrode of the third transistor 103 is connected to the ninth wiring 7.
09 may be connected. Further, as shown in FIG. 8B, the fourth transistor 104
The first electrode may be connected to the tenth wiring 710. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

In the flip-flop in FIG. 7A, the number of wirings can be reduced; thus, yield, reduction in layout area, improvement in reliability, or improvement in a range of operating conditions can be achieved. Further, since the flip-flop in FIG. 7B can reduce the potential applied to the third transistor 103 and apply a reverse bias, the shift of the threshold voltage of the third transistor 103 can be further suppressed. Further, since the potential supplied to the ninth wiring 709 can be reduced in the flip-flop in FIG. 8A, the shift of the threshold voltage of the seventh transistor 107 can be further suppressed. Further, since the flip-flop in FIG. 8B can prevent the current flowing through the third transistor 103 and the fourth transistor 104 from operating as other transistors, the range of operating conditions can be improved. it can.

FIG. 29 illustrates an example of a top view of the flip-flop illustrated in FIG. The conductive layer 2901 includes a portion functioning as the first electrode of the first transistor 101 and is connected to the fourth wiring 704 through the wiring 2951. The conductive layer 2902 functions as the second electrode of the first transistor 101 and is connected to the third wiring 703 through the wiring 2952. The conductive layer 2903 includes the gate electrode of the first transistor 101 and the eighth transistor 10.
8 function as a gate electrode. The conductive layer 2904 includes a portion functioning as the second electrode of the second transistor 102 and is connected to the third wiring 703 through the wiring 2952. The conductive layer 2905 includes the first electrode of the second transistor 102 and the fourth transistor 1.
The first electrode of 04 and the first electrode of the eighth transistor 108 are connected to the seventh wiring 707. The conductive layer 2906 functions as the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104 and is connected to the fifth wiring 705 through the wiring 2953. The conductive layer 2907 includes the first transistor 103 of the third transistor 103.
And is connected to a sixth wiring 706 through a wiring 2954. The conductive layer 2908 functions as the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, and the second electrode of the eighth transistor 108. Conductive layer 29
09 includes a function as the gate electrode of the third transistor 103 and is connected to the fourth wiring 704 through the wiring 2955. The conductive layer 2910 functions as the first electrode of the fifth transistor 105 and is connected to the sixth wiring 706 through the wiring 2956. The conductive layer 2911 functions as the second electrode of the fifth transistor 105 and the second electrode of the seventh transistor 107 and is connected to the conductive layer 2903 through the wiring 2957. The conductive layer 2912 includes a function as a gate electrode of the fifth transistor 105 and includes the wiring 29
It is connected to the first wiring 701 through 58. The conductive layer 2913 is the sixth transistor 1
06 includes a function as the second electrode of 06 and is connected to the conductive layer 2903 through the wiring 2595. The conductive layer 2914 includes a function as a gate electrode of the sixth transistor 106 and is connected to the conductive layer 2908 through a wiring 2954. The conductive layer 2915 has a function as the second electrode of the seventh transistor 107 and is connected to the wiring 707. The conductive layer 2916 includes a function as the gate electrode of the seventh transistor 107 and is connected to the second wiring 702 through the wiring 2960.

Note that portions functioning as the gate electrode, the first electrode, and the second electrode of the first transistor 101 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2981. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2982. The portions functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2983. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2984. The portion functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 is a portion where the conductive layer including each of them overlaps with the semiconductor layer 2985. The portion functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 is a portion where the conductive layer including each of them overlaps with the semiconductor layer 2986. The portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2987. Eighth transistor 10
The portions functioning as the eight gate electrodes, the first electrode, and the second electrode are portions where a conductive layer including each of them overlaps with the semiconductor layer 2988.

Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 11 includes n flip-flops (flip-flops 1101_1 to 1101_n).

Connection relations of the shift register in FIG. 11 are described. In the shift register in FIG. 11, the i-th flip-flop 1101_i (any one of the flip-flops 1101_1 to 1101_n) has the first wiring 121 illustrated in FIG.
1A, the second wiring 122 illustrated in FIG. 1A is connected to the seventh wiring 1117_i + 1, the third wiring 123 illustrated in FIG. 1A is connected to the seventh wiring 1117_i, FIG.
The fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 shown in FIG. 1A are connected to the fifth wiring 1115, and FIG. Are connected to the second wiring 1112 in the odd-numbered flip-flops, and are connected to the third wiring 1113 in the even-numbered flip-flops.
If the eighth wiring 128 shown in FIG. 1A is an odd-numbered flip-flop, the third wiring 11
13 is connected to the second wiring 1112 in the even-numbered flip-flops.
The sixth wiring 126 and the ninth wiring 129 shown in FIG. 9A are connected to the fourth wiring 1114. However, the first wiring 12 shown in FIG. 1A of the first-stage flip-flip 1101_1.
1 is connected to the first wiring 1111 and the n-th flip-flop 1101_n in FIG.
) Is connected to the sixth wiring 1116.

Note that the first wiring 1111, the second wiring 1112, the third wiring 1113, and the sixth wiring 11 are used.
16 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fourth wiring 1114 and the fifth wiring 1115 may be referred to as a first power supply line and a second power supply line, respectively.

Next, operation of the shift register illustrated in FIG. 11 is described with reference to a timing chart of FIG. 12 and a timing chart of FIG. Here, the timing chart of FIG. 12 is divided into a scanning period and a blanking period. The scan period is a period from when the selection signal is output from the seventh wiring 1117_1 to when the selection signal is output from the seventh wiring 1117_n. The blanking period is a period from when the output of the selection signal from the seventh wiring 1117 — n is finished until the output of the selection signal from the seventh wiring 1117 — 1 is started.

Note that the potential of V 1 is supplied to the fourth wiring 1114 and the potential of V 2 is supplied to the fifth wiring 1115.

Note that the first wiring 1111, the second wiring 1112, the third wiring 1113, and the sixth wiring 11 are used.
16, signal 1211, signal 1212, signal 1213, signal 12 shown in FIG.
16 is input. Here, the signal 1211, the signal 1212, the signal 1213, and the signal 1216
Is a digital signal in which the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level). Furthermore, the signal 1211, the signal 1212, and the signal 12
13 and signal 1216 may be referred to as a start signal, a first clock signal, a second clock signal (inverted clock signal), and a reset signal, respectively.

Note that various signals, potentials, and currents may be input to the first wiring 1111 to the sixth wiring 1116, respectively.

Note that from the seventh wiring 1117_1 to the seventh wiring 1117_n, digital signals having an H signal potential of V1 (hereinafter also referred to as H level) and an L signal potential of V2 (hereinafter also referred to as L level) are received. Is output. However, as shown in FIG. 14, signals are output from the seventh wiring 1117_1 to the seventh wiring 1117_n through the buffers 1401_1 to 1401_n, respectively, and the output signal of the shift register and the transfer signal of each flip-flop are divided. As a result, the range of operating conditions can be increased.

Here, the buffers 1401_1 to 1401 included in the shift register illustrated in FIG.
An example of _n will be described with reference to FIGS. In the buffer 8000 illustrated in FIG. 15A, an inverter 8001a, an inverter 8001b, and an inverter 8001c are connected between the wiring 8011 and the wiring 8012, so that an inverted signal of the signal input to the wiring 8011 is output from the wiring 8012. The However, the wiring 8011 and the wiring 801
There is no limitation on the number of inverters connected to 2; for example, when an even number of inverters are connected between the wiring 8011 and the wiring 8012, a signal having the same polarity as the signal input to the wiring 8011 Is output from. Further, as shown in a buffer 8100 in FIG. 15B, an inverter 8002a, an inverter 8002b, and an inverter 8002c connected in series, and an inverter 8003a, an inverter 8003b, and an inverter 8003c arranged in series are connected in parallel. Also good. The buffer 8100 in FIG. 15B can average variation in transistor characteristics, so that delay and rounding of a signal output from the wiring 8012 can be reduced. Further, the outputs of the inverter 8002a and the inverter 8002a and the outputs of the inverter 8002b and the inverter 8002b may be connected.

Note that in FIG. 15A, it is preferable that W of a transistor included in the inverter 8001a <W of a transistor included in the inverter 8001b <W of a transistor included in the inverter 8001c. This is because when the inverter 8001a has a small W, the driving capability of the flip-flop (specifically, the W / L value of the transistor 101 in FIG. 1) can be reduced, so that the shift register of the present invention can reduce the layout area. . Similarly, FIG.
5B, the transistor W included in the inverter 8002a <the inverter 800
It is preferable that W of the transistor included in 2b <W of the transistor included in the inverter 8002c. Similarly, in FIG. 15B, it is preferable that W of the transistor included in the inverter 8003a <W of the transistor included in the inverter 8003b <W of the transistor included in the inverter 8003c. Further, W of the transistor included in the inverter 8002a = W of the transistor included in the inverter 8003a, and the inverter 800
It is preferable that W of the transistor included in 2b = W of the transistor included in the inverter 8003b, W of the transistor included in the inverter 8002c = W of the transistor included in the inverter 8003c.

Note that there is no particular limitation on the inverter illustrated in FIGS. 15A and 15B as long as it can output an inverted signal. For example, an inverter may be formed using the first transistor 8201 and the second transistor 8202 as illustrated in FIG. Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V 1 is supplied to the third wiring 8213, and V 2 is supplied to the fourth wiring 8214. When an H signal is input to the first wiring 8211, the inverter in FIG.
A potential obtained by dividing V2 by the first transistor 8201 and the second transistor 8202 (the first transistor
(W / L of the transistor 8201 <W / L of the second transistor 8202) is output from the second wiring 8212. Further, in the inverter in FIG. 15C, when an L signal is input to the first wiring 8211, V1−Vth8201 (Vth8201: the first transistor 82).
01 threshold voltage) is output from the second wiring 8212. Further, the first transistor 8201 may be a PN junction diode as long as it is an element having a resistance component, or may simply be a resistance element.

Further, as illustrated in FIG. 15D, an inverter may be formed using the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, and the second wiring 8
A signal is output from 312, V 1 is supplied to the third wiring 8313 and the fifth wiring 8315, and V 2 is supplied to the fourth wiring 8314 and the sixth wiring 8316. FIG. 15 (D
When the H signal is input to the first wiring 8311, the inverter of (2) converts V2 into the second wiring 831.
2 is output. At this time, since the potential of the node 8341 is set to the L level, the first transistor 8301 is turned off. Further, when the L signal is input to the first wiring 8311, the inverter in FIG. 15D outputs V1 from the second wiring 8312. At this time, the node 834
When the potential of 1 becomes V1−Vth8303 (Vth8303: threshold voltage of the third transistor 8303), the node 8341 is in a floating state, and the potential of the node 8341 is V1 + Vth8301 (Vth8301: the first transistor 8) by bootstrap operation.
301, the first transistor 8301 is turned on.
Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode.

Further, as illustrated in FIG. 16A, an inverter may be formed using the first transistor 8401, the second transistor 8402, the third transistor 8403, and the fourth transistor 8404. The inverter in FIG. 16A is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413.
V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. In the inverter illustrated in FIG. 16A, when an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, V2 is supplied to the third wiring 841.
3 is output. At this time, since the potential of the node 8441 is V2, the first transistor 8401 is turned off. Further, the inverter in FIG. 16A is connected to the first wiring 8411 with H
When an L signal is input to the signal and the second wiring 8412, V 1 is output from the third wiring 8413. At this time, when the potential of the node 8441 becomes V1−Vth8403 (Vth8403: threshold voltage of the third transistor 8403), the node 8441 is in a floating state, and the potential of the node 8441 is V1 + Vth8401 (Vth84) by the bootstrap operation.
01: threshold voltage of the first transistor 8401), the first transistor 8401 is turned on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, one of the first wiring 8411 and the second wiring 8412 is connected to FIG.
A third wiring 123 shown in A) is connected, and a node 142 shown in FIG.

Further, as illustrated in FIG. 16B, an inverter may be formed using the first transistor 8501, the second transistor 8502, and the third transistor 8503. FIG.
The inverter 6 (B) is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8511, an inverted signal is input to the second wiring 8512, a signal is output from the third wiring 8513, and the fourth wiring 8514 and the sixth wiring
The second wiring 8516 is supplied with V2, and the fifth wiring 8515 is supplied with V2. FIG.
When an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512, the inverter of FIG. 5B outputs V2 from the third wiring 8513. At this time, since the potential of the node 8541 is V2, the first transistor 8501 is turned off. Further, when the H signal is input to the first wiring 8511 and the L signal is input to the second wiring 8512, the inverter in FIG.
1 is output from the third wiring 8513. At this time, the potential of the node 8541 is V1−Vth.
When 8503 (Vth8503: threshold voltage of the third transistor 8503) is reached, the node 8541 is in a floating state, and the potential of the node 8541 is V1 + Vth8501 (Vth8501: threshold voltage of the first transistor 8501) by bootstrap operation.
Therefore, the first transistor 8501 is turned on. Further, since the first transistor 8501 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, one of the first wiring 8511 and the second wiring 8512 is connected to the third wiring 123 illustrated in FIG. 1A, and the other is connected to FIG.
The node 142 shown in FIG.

Further, as illustrated in FIG. 16C, an inverter may be formed using the first transistor 8601, the second transistor 8602, the third transistor 8603, and the fourth transistor 8604. The inverter in FIG. 16C is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613.
V1 is supplied to the fourth wiring 8614 and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. In the inverter in FIG. 16A, an L signal is supplied to the first wiring 8611, the second
When an H signal is input to the second wiring 8612, V 2 is output from the third wiring 8613. At this time, since the potential of the node 8641 becomes V2, the first transistor 8601 is turned off.
Further, in the inverter in FIG. 16C, the first wiring 8611 has an H signal and the second wiring 861.
When an L signal is input to 2, V 1 is output from the third wiring 8613. At this time, node 8
When the potential of 641 becomes V1−Vth8603 (Vth8603: threshold voltage of the third transistor 8603), the node 8641 is in a floating state, and the potential of the node 8641 becomes V1 + Vth8601 (Vth8601: the first transistor 8601 of the first transistor 8601). Therefore, the first transistor 8601 is turned on. Further, since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. In addition, the first
One of the second wiring 8611 and the second wiring 8612 includes the third wiring 1 illustrated in FIG.
23 is connected, and a node 142 shown in FIG.

Note that the seventh wiring 1117 — i−1 is used as a start signal of the flip-flop 1101 — i.
The signal output from the seventh wiring 1117 — i + 1 is used as the reset signal. Here, the start signal of the flip-flop 1101_1 is input from the first wiring 1111 and the reset signal of the flip-flop 1101_n is the sixth wiring 11.
16 is input. Note that as the reset signal of the flip-flop 1101_n, a signal output from the seventh wiring 1117_1 or a signal output from the seventh wiring 1117_2 may be used. Alternatively, a dummy flip-flop may be newly disposed and the output signal of the dummy flip-flop may be used. By doing so, the number of wirings and the number of signals can be reduced.

As shown in FIG. 13, for example, when the flip-flop 1101_i enters the selection period,
H signal (selection signal) is output from the wiring 1117_i. At this time, the flip-flop 1101_i + 1 is in the set period. After that, the flip-flop 1101_i enters a reset period, and an L signal is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 is in a selection period. After that, the flip-flop 1101_i enters the first non-selection period, the seventh wiring 1117_i becomes floating, and the potential is maintained at V2. At this time, the flip-flop 1101_i + 1 is in the reset period. After that, the flip-flop 1101_i enters the second non-selection period, and the L signal is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 is in the first non-selection period.

In this manner, the shift register in FIG. 11 transmits the selection signal from the seventh wiring 1117_1 to the seventh wiring in order.
The wiring 1117_n can be output. That is, the shift register of FIG.
117_1 to the seventh wiring 717_n can be scanned.

Further, the shift register to which the flip-flop of this embodiment is applied can suppress a shift in threshold voltage of the transistor, so that the lifetime can be extended. Further, the shift register to which the flip-flop of this embodiment is applied can improve reliability. Further, the shift register to which the flip-flop of this embodiment is applied can suppress malfunction.

Further, the shift register to which the flip-flop of this embodiment is applied can operate at high speed, and thus can be applied to a higher-definition display device or a larger display device. Further, the shift register to which the flip-flop of this embodiment is applied can simplify the process. Further, a shift register to which the flip-flop of this embodiment is applied can reduce manufacturing costs. Further, the shift register to which the flip-flop of this embodiment is applied can improve yield.

Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

The structure of the display device of this embodiment will be described with reference to FIG. The display device in FIG. 17 includes a signal line driver circuit 1701, a scan line driver circuit 1702, and a pixel portion 1704, and the pixel portion 1704 includes a plurality of signals that extend from the signal line driver circuit 1701 in the column direction. Line S
1 to Sm, a plurality of scanning lines G1 to G1 arranged extending in the row direction from the scanning line driving circuit 1702
A plurality of pixels 1703 are arranged in a matrix corresponding to Gn, signal lines S1 to Sm, and scanning lines G1 to Gn. Each pixel 1703 includes a signal line Sj (signal lines S1 to S1).
any one of m) and the scanning line Gi (any one of the scanning lines G1 to Gn). Further, the scan line driver circuit 1702 may be referred to as a driver circuit.

Note that as the scan line driver circuit 1702, the shift register of this embodiment can be used. Needless to say, the shift register of this embodiment may also be used for the signal line driver circuit 1701.

Note that the scan lines G1 to Gn are connected to the seventh wiring 1117_1 to the seventh wiring 1117_n illustrated in FIGS.

Note that the signal line and the scanning line may be simply referred to as wiring. Further, the signal line driver circuit 1701
The scan line driver circuit 1702 may be called a driver circuit.

Note that the pixel 1703 includes at least one switching element, one capacitor element, and a pixel electrode. Note that the pixel 1703 may include a plurality of switching elements or a plurality of capacitor elements. Furthermore, a capacitive element is not always necessary. Further, the pixel 1703
May further include a transistor operating in a saturation region. Further, the pixel 1703
May have a display element such as a liquid crystal element or an EL element. Here, a transistor and a PN junction diode can be used as the switching element. However, when a transistor is used as the switching element, it is preferable that the transistor operates in a linear region. Further, in the case where the scan line driver circuit 1702 includes only N-channel transistors, it is preferable to use N-channel transistors as switching elements. Further, in the case where the scan line driver circuit 1702 includes only P-channel transistors, it is preferable to use P-channel transistors as switching elements.

Note that the scan line driver circuit 1702 and the pixel portion 1704 are formed over the insulating substrate 1705, and the signal line driver circuit 1701 is not formed over the insulating substrate 1705. The signal line driver circuit 1701 is formed over a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1705. The signal line driving circuit 1701 is connected to the signal line S via a printed circuit board such as an FPC.
1 to Sm. However, the signal line driver circuit 1701 may be formed on the insulating substrate 1705, and a circuit constituting a part of the function of the signal line driver circuit 1701 is the insulating substrate 17.
05 may be formed.
Note that wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (T
a), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd)
, Chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (C
u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn)
, Niobium (Nb), Silicon (Si), Phosphorus (P), Boron (B), Arsenic (As), Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O) Or one or more elements selected from the above, or a compound or alloy material (for example, indium tin oxide (ITO), indium zinc oxide (IZO) containing one or more elements selected from the above group as a component) ), Indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
It is desirable to be formed of tin oxide (SnO), tin cadmium oxide (CTO), aluminum neodymium (Al—Nd), magnesium silver (Mg—Ag), molybdenum niobium (Mo—Nb), or the like. Alternatively, the wiring, the electrode, the conductive layer, the conductive film, the terminal, and the like are preferably formed using a substance in which these compounds are combined. Or one or more elements selected from the group and a silicon compound (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), one or more elements selected from the group and nitrogen It is desirable to form with a compound (eg, titanium nitride, tantalum nitride, molybdenum nitride, or the like).

Note that silicon (Si) includes n-type impurities (such as phosphorus) or p-type impurities (such as boron).
May be included. When silicon contains impurities, the conductivity is improved and the same behavior as a normal conductor can be achieved. Therefore, it becomes easy to use as wiring, electrodes, and the like.

Silicon is monocrystalline, polycrystalline (polysilicon), or amorphous (amorphous silicon).
Silicon having various crystallinity such as microcrystal (microcrystal silicon) can be used. By using single crystal silicon or polycrystalline silicon, wiring, electrodes,
Resistance of a conductive layer, a conductive film, a terminal, or the like can be reduced. By using amorphous silicon or microcrystalline silicon, a wiring or the like can be formed by a simple process.

Note that since aluminum or silver has high conductivity, signal delay can be reduced.
Further, since etching is easy, patterning is easy and fine processing can be performed.

Note that since copper has high conductivity, signal delay can be reduced. When using copper,
In order to improve adhesion, it is desirable to have a laminated structure.

Molybdenum or titanium is preferable because it has advantages such as no defects, easy etching, and high heat resistance even when in contact with an oxide semiconductor (ITO, IZO, or the like) or silicon.

Tungsten is desirable because it has advantages such as high heat resistance.

Neodymium is desirable because it has advantages such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, the heat resistance is improved, and aluminum does not easily cause hillocks.

Silicon is preferable because it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.

In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
nO) and tin cadmium oxide (CTO) have a light-transmitting property, and thus can be used for a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

Note that IZO is desirable because it is easy to etch and process. It is difficult for IZO to leave a residue when it is etched. Therefore, when IZO is used as the pixel electrode, it is possible to reduce the occurrence of defects (short circuit, alignment disorder, etc.) in the liquid crystal element and the light emitting element.

Note that a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like may have a single-layer structure or a multilayer structure. With a single-layer structure, a manufacturing process of wiring, electrodes, conductive layers, conductive films, terminals, and the like can be simplified, the number of process days can be reduced, and cost can be reduced. Alternatively, by using a multilayer structure, it is possible to reduce the demerits while making use of the merits of each material, and to form wirings, electrodes, and the like with good performance. For example, by including a low resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. In addition, by using a laminated structure in which a low heat resistant material is sandwiched between high heat resistant materials, the heat resistance of a wiring, an electrode, or the like can be increased while taking advantage of the low heat resistant material. For example, a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like is preferable.

In addition, when wires, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, etc. is contained in the other wiring, electrode, etc. material, changing its properties, making it impossible to achieve its original purpose, forming a high resistance part, and manufacturing Occasionally, problems may occur that prevent successful manufacture. In such a case,
It is preferable to sandwich or cover a material that easily reacts by a laminated structure with a material that does not easily react. For example, when ITO and aluminum are connected, it is desirable to sandwich titanium, molybdenum, or a neodymium alloy between ITO and aluminum. When silicon and aluminum are connected, it is desirable to sandwich titanium, molybdenum, or a neodymium alloy between ITO and aluminum.

In addition, wiring means what the conductor is arrange | positioned. It may extend linearly or may be arranged short without extending. Therefore, the electrode is included in the wiring.

Note that the wirings and electrodes described above can also be applied to other display devices, shift registers, and pixels.

Note that the signal line driver circuit 1701 inputs voltage or current as video signals to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the positive / negative polarity of the video signal may be inverted every frame (frame inversion driving), or the positive / negative polarity may be inverted every row (gate line inversion driving). Positive electrode
The negative electrode may be inverted (source line inversion driving), and the positive electrode and the negative electrode may be inverted for each row and column (dot line inversion driving). Further, the video signal may be input to the signal lines S1 to Sm by dot sequential driving or may be input by line sequential driving. Further, the signal line driver circuit 1701 applies not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm.
May be entered. It is desirable to input a constant voltage such as a precharge voltage for each gate selection period and for each frame.

Note that the scan line driver circuit 1702 inputs signals to the scan lines G1 to Gn, and scan lines G1 to Gn.
Are selected in order from the first line (hereinafter also referred to as scanning). Then, the scanning line driving circuit 170
2 selects a plurality of pixels 1703 connected to the selected scanning line. Here, a period in which one scanning line is selected is referred to as one gate selection period, and a period in which the scanning line is not selected is referred to as a non-selection period. Further, a signal output from the scanning line driver circuit 1702 to the scanning line is referred to as a scanning signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

Note that when the pixel 1703 is selected, a video signal is input from the signal line driver circuit 1701 to the pixel 1703 through the signal line. Further, when the pixel 1703 is not selected, the pixel 1703 holds a video signal (a potential corresponding to the video signal) input in the selection period.

Note that although not illustrated, the signal line driver circuit 1701 and the scan line driver circuit 1702 are supplied with a plurality of potentials and a plurality of signals.

Next, operation of the display device illustrated in FIG. 17 will be described with reference to a timing chart of FIG. Further, FIG. 18 shows one frame period corresponding to a period for displaying an image for one screen. However, the period of one frame is not particularly limited, but is preferably set to at least 1/60 second or less so that a person viewing the image does not feel flicker.

In the timing chart of FIG. 18, the first scanning line G1 and the i-th scanning line Gi, i
The timing at which the + 1st scanning line Gi + 1 and the nth scanning line Gn are selected is shown.

In FIG. 18, for example, the i-th scanning line Gi is selected, and a plurality of pixels 1703 connected to the scanning line Gi are selected. The plurality of pixels 1703 connected to the scanning line Gi each input a video signal and hold a potential corresponding to the video signal. Thereafter, the i-th scanning line Gi is deselected, the i + 1-th scanning line Gi + 1 is selected, and the plurality of pixels 1703 connected to the scanning line Gi + 1 are selected. The plurality of pixels 1703 connected to the scanning line Gi + 1 each input a video signal and hold a potential corresponding to the video signal. Thus, in one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1703 connected to the respective scanning lines are also selected in order. A plurality of pixels 1703 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal.

Further, a display device using the shift register of this embodiment as the scan line driver circuit 1702 can operate at high speed, and thus can have higher definition or larger size. Further, the display device of this embodiment can simplify the process. Furthermore, the display device of this embodiment can reduce manufacturing costs. Further, the display device in this embodiment can improve yield.

Further, since the display device in FIG. 17 forms the signal line driver circuit 1701, which requires high-speed operation, the scan line driver circuit 1702, and the pixel portion 1703 on different substrates, the scan line driver circuit 17
As the semiconductor layer of the transistor included in 02 and the semiconductor layer of the transistor included in the pixel 1703, amorphous silicon can be used. Accordingly, the display device of FIG. 17 can simplify the manufacturing process. Further, the display device of FIG. 17 can reduce the manufacturing cost. Further, the display device in FIG. 17 can improve yield. Furthermore, the display device in FIG. 17 can be increased in size. Alternatively, the display device in FIG. 17 can simplify the manufacturing process even when polysilicon or polycrystalline silicon is used for the semiconductor layer of the transistor.

Note that in the case where the signal line driver circuit 1701, the scan line driver circuit 1702, and the pixel 1703 are formed over the same substrate, a semiconductor layer of a transistor included in the scan line driver circuit 1702 and a semiconductor layer of a transistor included in the pixel 1703 are used as a polycrystal. Silicon or polycrystalline silicon may be used.

Note that as shown in FIG. 17, the number and arrangement of the driver circuits are not limited to those in FIG. 17 as long as a pixel can be selected and a video signal can be written to the pixel independently.

For example, as shown in FIG. 19, the scanning lines G1 to Gn are converted into the first scanning line driving circuit 1902.
Scanning may be performed by a and the second scanning line driving circuit 1902b. The first scan line driver circuit 1902a and the second drive circuit 1902b are the same as the scan line driver circuit 1702 shown in FIG.
The scanning lines G1 to Gn are scanned at the same timing. Further, the first scan line driver circuit 1902a and the second driver circuit 1902b may be referred to as a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 19 includes a first scan line driver circuit 1902a and a second scan line driver circuit 190.
Even if a defect occurs in one of 2b, the other of the scanning line driving circuit 1902a and the second scanning line driving circuit 1902b can scan the scanning lines G1 to Gn, so that redundancy can be provided. Further, in the display device of FIG. 19, the load of the first scan line driver circuit 1902a (the wiring resistance of the scan line and the parasitic capacitance of the scan line) and the load of the second scan line driver circuit 1902b are shown in FIG.
Therefore, the delay and rounding of signals input to the scanning lines G1 to Gn (output signals of the first scanning line driver circuit 1902a and the second driving circuit 1902b) can be reduced. Further, the display device in FIG. 19 includes a load of the first scan line driver circuit 1902a and a second
Since the load on the scanning line driving circuit 1902b is reduced, the scanning lines G1 to Gn can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, the panel can be enlarged or the panel can be made high definition. Note that portions common to the configuration in FIG. 17 are denoted by common reference numerals and description thereof is omitted.

As another example, FIG. 20 illustrates a display device capable of writing video signals to pixels at high speed. In the display device of FIG. 20, a video signal is input to the odd-numbered pixel 1703 from the odd-numbered signal line, and a video signal is input to the even-numbered pixel 1703 from the even-numbered signal line. Further, in the display device of FIG. 20, the odd-numbered scanning lines among the scanning lines G1 to Gn are scanned by the first scanning line drive circuit 2002a, and the even-numbered scanning lines G1 to Gn. The scan line is scanned by the second scan line driver circuit 2002b. Further, the start signal input to the first scan line driver circuit 2002b is input with a delay of ¼ period of the clock signal from the start signal input to the first scan line driver circuit 2002a.

Note that the display device i