JP2020076964A - Semiconductor device - Google Patents

Abstract

To suppress the shift of threshold voltage of an easily degradable transistor and the shift of threshold voltage of a turned-on transistor.SOLUTION: The present invention is the one for inputting a signal to the gate electrode of an easily degradable transistor via a turned-on transistor and thereby suppressing the shift of threshold voltage of the easily degradable transistor and the shift of threshold voltage of the turned-on transistor. Therefore, the present invention includes a structure for adding an AC pulse to the gate electrode of the easily degradable transistor via a transistor to which a high potential (VDD) is applied to its gate electrode (or via an element having a resistive component).SELECTED DRAWING: Figure 1

Description

The present invention relates to a display device having a circuit including a transistor. In particular, the present invention relates to a display device using an electro-optical element such as liquid crystal or a light emitting element as a display medium, and a driving method thereof.

In recent years, display devices have been actively developed due to the increase in large-sized display devices such as liquid crystal televisions. In particular, a technique for integrally forming a driver circuit (hereinafter also referred to as an internal circuit) including a pixel circuit, a shift register, and the like using a transistor formed of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) over an insulating substrate is available. In order to greatly contribute to low power consumption and low cost, development is actively underway. The internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter, also referred to as an external circuit) via an FPC or the like, and the operation thereof is controlled.

Among the internal circuits shown above, a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised.
A structure of a flip-flop included in a conventional shift register is illustrated in FIG. 124A (Patent Document 1). The flip-flop in FIG. 124A includes the transistor 11, the transistor 12,
It has a transistor 13, a transistor 14, a transistor 15 and a transistor 17,
It is connected to the signal line 21, the signal line 22, the wiring 23, the signal line 24, the power supply line 25, and the power supply line 26. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. The operation period of the flip-flop in FIG. 124A is divided into a set period, a selection period, a reset period, and a non-selection period, as shown in the timing chart in FIG. 124B, and most of the operation periods are non-operational. It will be the selection period.

Here, the transistor 12 and the transistor 16 are on in the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layers of the transistors 12 and 16, the threshold voltage (Vth) varies due to deterioration or the like. More specifically, the threshold voltage increases. That is, in the conventional shift register, since the threshold voltages of the transistors 12 and 16 are increased and the shift registers cannot be turned on, VSS cannot be supplied to the node 41 and the wiring 23, which causes a malfunction.

In order to solve this problem, Non-Patent Document 1, Non-Patent Document 2 and Non-Patent Document 3 have devised a shift register capable of suppressing the shift of the threshold voltage of the transistor 12. In Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and in a non-selection period, By inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor, the threshold voltage shifts of the first transistor and the second transistor are suppressed.

Further, Non-Patent Document 4 devises a shift register capable of suppressing the shift of the threshold voltage of not only the transistor 12 but also the transistor 16. In Non-Patent Document 4, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and another new transistor (referred to as a third transistor) is referred to as a transistor. 16 (which is the fourth transistor) is arranged in parallel. Then, in the non-selection period, inverted signals are input to the gate electrode of the first transistor and the gate electrode of the second transistor, and inverted to the gate electrode of the third transistor and the gate electrode of the fourth transistor, respectively. By inputting a signal, shifts in threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor are suppressed.

Further, in Non-Patent Document 5, shift of the threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12.

Note that the display devices of Non-Patent Document 6 and Non-Patent Document 7 use a shift register composed of amorphous silicon transistors as a scanning line driving circuit, and further, a video signal from one signal line to R, G, and B sub-pixels. By inputting signals, the number of signal lines is reduced to 1/3. Thus, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

JP 2004-157508 A

Soo Young Youon, et al. , "Highly Stable Integrated Gate Driver Circulating using a-Si TFT with Dual Pull-down Structure, SOCIET EQUIPE DIRECTION FORM INITU FORM EYE DIRECTION FORM IN FORM EQUIPMENT FORM EQUIP FORM EQUIPE DIRECT FORM IN FORM EYE DIRECTION FORM EQUIPMENT CONFIGURATION FORM EQUIP FORM EYE POINT EQUIPMENT FORM EQUIP FORM EQUIPMENT FORM EQUIPPED. 348-351 Binn Kim, et al. , "A-Si Gate Driver Integration with with Time Shared Data Driving", Proceedings of the 12th International Display Workshops in connection with 5,200,000. 1073-1076 Mindhoo Chun, et al. , "Integrated Gate Driver Using Highly Stable a-Si TFT's", Proceedings of the 12th International Display Workshops in junction with 200, Asi. 1077-1080 Chun-Ching, et al. , "Integrated Gate Driver Circuit Using a-Si TFT", Proceedings of the 12th International Display Workshops in connection with Asap, 200, Display. 1023-1026 Yong Ho Yang, et al. , "A-Si TFT integrated gate driver with AC-Driven Single Pull-down Structure", SOCIETY FOR INFORMATION PRODUCTION, INSPECTION DIRECTIONS, 2006 INTERNATION PRODUCTION FORMULATION PICTURES. 208-211 Jin Young Choi, et al. , "A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure", SOCIETY FOR INFORMATION PRODUCTION, EXPRESSION FORMATION, DISC TYPE 2006, INTERFACE EXPRESSION TYPE, PRINT TYPE, PACKAGE STRUCTURE TYPE, PACKAGE STRUCTURE TYPE, PACKAGE STRUCTURE TYPE, PACKAGE STRUCTURE TYPE, PACKAGE PIXEL STRUCTURE TYPES 274-276 Yong Soon Lee, et al. , "Advanced TFT-LCD Data Line Reduction Method", SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGES OF TECHNICAL UM. 1083-1086

According to the conventional technology, the shift of the threshold voltage of the transistor is suppressed by applying an AC pulse to the gate of the transistor which is easily deteriorated. However, when amorphous silicon is used as a semiconductor layer of a transistor, naturally, a transistor forming a circuit for generating an AC pulse also has a problem that the threshold voltage shifts.
Further, it has been proposed to reduce the number of signal lines to 1/3 to reduce the number of contact points between a display panel and a driver IC (Non-Patent Document 6 and Non-Patent Document 7). There is a demand to further reduce the number of IC contacts.

That is, a circuit technique for suppressing the variation in the threshold voltage of the transistor remains as an issue, which is not solved by the conventional technique. A technique for reducing the number of contact points of the driver IC mounted on the display panel remains as an issue. Reducing the power consumption of display devices remains an issue. Increasing the size or increasing the definition of the display device remains an issue.

An object of the invention disclosed in this specification is to provide an industrially useful technique by solving one or more of such problems.

In the display device according to the present invention, by inputting a signal to the gate electrode of a transistor that is easily deteriorated through the transistor that is turned on, the threshold voltage of the transistor that is easily deteriorated and the threshold voltage of the transistor that is turned on are changed. It suppresses the shift of. That is,
The present invention includes a configuration in which an AC pulse is applied to the gate electrode of a transistor that easily deteriorates via a transistor in which a high potential (VDD) is applied to the gate electrode (or via an element having a resistance component). .

Various types of switches can be used as the switches shown in this specification. Examples include electrical switches and mechanical switches. That is, it is not limited to a specific one as long as it can control the flow of current. For example, as a switch, a transistor (for example,
Bipolar transistor, MOS transistor, etc., diode (eg, PN diode, PIN diode, Schottky diode, MIM (MetalInsulator)
or Metal) diode, MIS (Metal Insulator Semiconductor)
For example, a diode, a diode-connected transistor, or the like, a thyristor, or the like can be used. Alternatively, a logic circuit in which these are combined can be used as a switch.

When a transistor is used as a switch, the transistor operates as a simple switch, and therefore the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress the off current, it is desirable to use a transistor having a polarity with a smaller off current. As a transistor with low off-state current, a transistor having an LDD region, a transistor having a multi-gate structure, or the like can be given. Alternatively, when the source terminal of a transistor which operates as a switch operates in a state where the potential of the source terminal is close to a low potential power source (VSS, GND, 0V, or the like), it is preferable to use an N-channel transistor. On the contrary, the potential of the source terminal is
It is desirable to use a P-channel type transistor when operating in a state close to a high potential side power source (VDD or the like). This is because the absolute value of the gate-source voltage is calculated when the source terminal of the N-channel type transistor operates in the state close to the low-potential side power supply and when the source terminal of the P-channel type transistor operates in the state close to the high-potential side power supply. Since the size can be increased, the switching characteristics are improved. Also, since the source follower operation is rarely performed, the output voltage is unlikely to be small.

A CMOS switch may be used as a switch by using both the N-channel transistor and the P-channel transistor. When a CMOS type switch is used, a current flows if either one of the P-channel type transistor and the N-channel type transistor becomes conductive, and therefore, the switch easily functions. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Furthermore, since the voltage amplitude value of the signal for turning the switch on and off can be reduced, the power consumption can be reduced.

When a transistor is used as a switch, the switch has an input terminal (one of a source terminal and a drain terminal), an output terminal (the other of the source terminal and the drain terminal), and a terminal for controlling conduction (a gate terminal). There is. On the other hand, when a diode is used as the switch, the switch may not have a terminal for controlling conduction. Therefore, when a diode is used as a switch rather than a transistor, wiring for controlling a terminal can be reduced.

In the present specification, when it is explicitly described that "A and B are connected", A and B are electrically connected and A and B are functionally connected. And the case where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, the structure disclosed in this specification is not limited to a predetermined connection relationship, for example, a connection relationship shown in a drawing or a text, and includes a connection relationship other than the connection relationship shown in a drawing or a text.

For example, when A and B are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, etc.) that enables the A and B to be electrically connected is , A and B may be arranged one or more. Alternatively, when A and B are functionally connected, a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), or a signal conversion circuit that enables the functional connection between A and B. (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boosting circuit,
Step-down circuit, etc.), level shifter circuit that changes the potential level of the signal, etc.), voltage source, current source,
Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier,
One or more differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) may be arranged between A and B. Alternatively, in the case where A and B are directly connected, A and B need not be sandwiched between A and B, and other elements and circuits are not sandwiched.
And may be directly connected.

When it is explicitly described that “A and B are directly connected”, when A and B are directly connected (that is, another element or another circuit is connected between A and B). When it is connected without intervening) and when A and B are electrically connected (that is, they are connected with another element or another circuit sandwiched between A and B). Case) and are included.

When it is explicitly described that “A and B are electrically connected”, when A and B are electrically connected (that is, another element or a device is connected between A and B). A case where another circuit is sandwiched and connected, and a case where A and B are functionally connected (that is, another circuit is sandwiched between A and B and functionally connected). Case) and the case where A and B are directly connected (that is, the case where they are connected without sandwiching another element or another circuit between A and B). That is, the explicit description of being electrically connected is the same as the explicit description of only being connected.

A display element, a display device which is a device having a display element, a light-emitting element, and a light-emitting device which is a device having a light-emitting element can have various modes or can have various elements. For example, as a display element, a display device, a light emitting element or a light emitting device, an EL element (organic EL element, inorganic EL
Element or EL element containing organic and inorganic substances), electron-emitting element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP)
, A digital micromirror device (DMD), a piezoelectric ceramic display, a carbon nanotube, or the like, which can be used as a display medium whose contrast, luminance, reflectance, transmittance, or the like changes due to an electromagnetic effect. In addition, as a display device using an EL element, E
As a display device using an L display or an electron-emitting device, a field emission display (FED) or a SED type flat display (SED: Surface-cond) is used.
A liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), electronic ink or electrophoresis is used as a display device using a liquid crystal element such as an action electron-emitter display. There is electronic paper as a display device using an element.

Various types of transistors can be used as the transistor described in this specification. Therefore, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) having a non-single crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as semi-amorphous) silicon, or the like can be used. There are various advantages when using a TFT. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, the manufacturing cost can be reduced and the manufacturing apparatus can be enlarged. Since the manufacturing apparatus can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, the manufacturing cost can be reduced. Further, since the manufacturing temperature is low, a substrate having low heat resistance can be used. Therefore, the transistor can be manufactured on the transparent substrate. Then, the transmission of light in the display element can be controlled by using the transistor on the transparent substrate. Alternatively, since the thickness of the transistor is thin, part of the film included in the transistor can transmit light. Therefore, the aperture ratio can be improved.

By using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve the crystallinity and manufacture a transistor having good electric characteristics. as a result,
A gate driver circuit (scanning line driver circuit), a source driver circuit (signal line driver circuit), and a signal processing circuit (a signal generation circuit, a gamma correction circuit, a DA conversion circuit, or the like) can be formed over a substrate.

By using a catalyst (such as nickel) when manufacturing microcrystalline silicon, it becomes possible to further improve the crystallinity and manufacture a transistor having good electric characteristics. At this time,
The crystallinity can be improved only by applying heat treatment without using a laser. As a result, part of the gate driver circuit (scanning line driver circuit) or the source driver circuit (analog switch or the like) can be integrally formed over the substrate. Furthermore, when a laser is not used for crystallization, it is possible to suppress unevenness in the crystallinity of silicon. Therefore, a beautiful image can be displayed.

However, it is possible to manufacture polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, the transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. As a result, it is possible to manufacture a transistor with small variations in characteristics, size, shape, etc., high current supply capability, and small size. By using these transistors, a circuit with low power consumption can be formed or high integration can be achieved.

Alternatively, a transistor including a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor in which the compound semiconductor or the oxide semiconductor is thinned can be used. I can. With these, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, the transistor can be formed directly on a substrate having low heat resistance, for example, a plastic substrate or a film substrate. In addition, these compound semiconductors or oxide semiconductors,
It can be used not only for the channel portion of the transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as a resistance element, a pixel electrode, and a transparent electrode. Further, they can be formed or formed at the same time as the transistor, and the cost can be reduced.

Alternatively, a transistor or the like formed using an inkjet method or a printing method can be used. With these, manufacturing at room temperature, manufacturing at a low degree of vacuum, or manufacturing on a large substrate can be performed. Further, since it becomes possible to manufacture without using a mask (reticle),
The layout of the transistors can be easily changed. Further, since it is not necessary to use a resist, the material cost can be reduced and the number of steps can be reduced. Further, since the film is formed only on the necessary portion, the material is not wasted and the cost can be reduced as compared with the manufacturing method of etching after forming the film on the entire surface.

Alternatively, a transistor or the like including an organic semiconductor or a carbon nanotube can be used. With these, a transistor can be formed over a bendable substrate.
Therefore, it can withstand shock.

In addition, various transistors can be used.

Various types of substrates can be used as the substrate on which the transistors are formed, and the types are not limited to particular ones. As a substrate on which a transistor is formed, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate,
Stone substrate, wood substrate, cloth substrate (including natural fiber (silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled polyester), leather substrate, rubber) A substrate, a stainless steel substrate, a substrate having a stainless steel foil, or the like can be used. Alternatively, the skin of animals such as humans (
The epidermis, dermis) or subcutaneous tissue may be used as the substrate. Alternatively, the transistor may be formed over one substrate, and then the transistor may be transferred to another substrate and the transistor may be arranged over another substrate. The substrate on which the transistor is transferred includes a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate,
Cloth substrate (natural fiber (silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester)
Or recycled fiber (including acetate, cupra, rayon, recycled polyester) etc.)
A leather substrate, a rubber substrate, a stainless steel substrate, a substrate having a stainless steel foil, or the like can be used. Alternatively, the skin (dermis, dermis) or subcutaneous tissue of animals such as humans may be used as the substrate. By using these substrates, formation of a transistor with excellent characteristics, formation of a transistor with low power consumption, manufacture of a device that is not easily broken, heat resistance, or weight reduction can be achieved.

The structure of the transistor can be various modes. It is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. With the multi-gate structure, since the channel regions are connected in series, a plurality of transistors are connected in series. With the multi-gate structure, off current can be reduced and reliability can be improved by improving the withstand voltage of the transistor. Alternatively, when operating in the saturation region, even if the drain-source voltage changes, the current between the drain and the source does not change much, and the slope of the voltage-current characteristic can be made flat. By utilizing the characteristic that the slope of the voltage-current characteristic is flat, it is possible to realize an ideal current source circuit and an active load having a very high resistance value. As a result, a differential circuit and a current mirror circuit having good characteristics can be realized.
Further, a structure in which gate electrodes are arranged above and below the channel may be used. With the structure in which the gate electrodes are provided above and below the channel, the channel region is increased, so that the current value can be increased. Alternatively, a depletion layer is easily formed, and the S value can be reduced. When the gate electrodes are arranged above and below the channel, a structure in which a plurality of transistors are connected in parallel is formed.

Alternatively, the gate electrode may be arranged above the channel region, or the gate electrode may be arranged below the channel region. Alternatively, the structure may be a normal stagger structure or an inverted stagger structure, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. Good. Also,
The source electrode and the drain electrode may overlap with the channel region (or part thereof).
With the structure in which the source electrode and the drain electrode overlap with the channel region (or part thereof), charge can be prevented from being accumulated in part of the channel region and unstable operation can be prevented. Further, an LDD region may be provided. By providing the LDD region, the off current can be reduced and the withstand voltage of the transistor can be improved to improve reliability. Alternatively, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and the slope of the voltage-current characteristic can be made flat.

In the present specification, one pixel means the minimum unit of an image. Therefore, R (red) G
In the case of a full-color display device composed of (green) B (blue) color elements, one pixel is composed of dots of R color elements, dots of G color elements, and dots of B color elements. And The color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, one or more colors of yellow, cyan, magenta, emerald green, vermilion, etc. may be added to RGB. Alternatively, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1 and B2 may be used. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, R1, R2, G, and B may be used. By using such color elements, it is possible to perform a display closer to a real thing and reduce power consumption. Note that one pixel may have a plurality of dots of the same color element.
At this time, the plurality of color elements may have different sizes of regions contributing to display. Further, gradation may be expressed by controlling a plurality of dots of the same color element. This is called an area gradation method. Alternatively, a plurality of dots of the same color element may be used, and the signals supplied to the respective dots may be slightly different to widen the viewing angle. That is, the plurality of pixel electrodes of the same color element may have different pixel electrode potentials. As a result, the voltage applied to the liquid crystal molecules differs depending on each pixel electrode. Therefore, the viewing angle can be widened.

In the present specification, one pixel means one element whose brightness can be controlled. Therefore, as an example, one pixel indicates one color element, and the brightness is expressed by the one color element. Therefore, in that case, in the case of a color display device including color elements of R (red), G (green), and B (blue), the minimum unit of the image is the R pixel, the G pixel, and the B pixel. It is composed of three pixels. The color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, one or more colors of yellow, cyan, magenta, emerald green, vermilion, etc. may be added to RGB. Further, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1 and B2 may be used. B1 and B
Both 2 are blue, but their frequencies are slightly different. Similarly, R1, R2, G,
It may be B. By using such color elements, it is possible to perform a display closer to a real thing and reduce power consumption. Further, as another example, in the case of controlling the brightness of one color element using a plurality of areas, one area may be one pixel. Therefore, as an example, when performing area gradation or having sub-pixels (sub-pixels), there are a plurality of regions for controlling brightness for one color element, and gradations are expressed as a whole. However, one pixel of the area for controlling the brightness may be one pixel. Therefore, in that case, one color element is composed of a plurality of pixels. Alternatively, even if there are a plurality of regions for controlling the brightness in one color element, they may be grouped together and one color element may be one pixel. Therefore, in that case, one color element is composed of one pixel. When controlling the brightness of one color element using a plurality of regions, the size of the region contributing to display may differ depending on the pixel. Further, in a plurality of areas for controlling brightness, one color element, the signals supplied to the respective areas may be slightly different to widen the viewing angle. That is, with respect to one color element, the potentials of the pixel electrodes included in a plurality of regions may be different from each other. As a result, the voltage applied to the liquid crystal molecules differs depending on each pixel electrode. Therefore, the viewing angle can be widened.

The case where one pixel (for three colors) is explicitly described is a case where three pixels of R, G, and B are considered as one pixel. The case where one pixel (for one color) is explicitly described is a case where one color element has a plurality of regions and they are collectively considered as one pixel.

In this specification, the pixels may be arranged (arranged) in a matrix. Here, the pixels being arranged (arranged) in a matrix include the case where the pixels are arranged in a straight line in the vertical direction or the horizontal direction, and the case where they are arranged in a jagged line. For example, when full-color display is performed with three color elements (for example, RGB), a case where stripes are arranged and a case where dots of three color elements are arranged in delta are also included. further,
Includes cases where Bayer is placed. Note that the color elements are not limited to three colors and may be more than three colors. For example, RGBW (W is white), RGB with one or more colors such as yellow, cyan, and magenta added thereto can be used. Further, the size of the display area may be different for each dot of the color element. Thereby, power consumption can be reduced. Alternatively, the life of the display element can be extended.

In this specification, an active matrix method in which an active element is included in a pixel or a passive matrix method in which an active element is not included in a pixel can be used.

In the active matrix system, not only transistors but also various active elements (active elements, nonlinear elements) can be used as active elements (active elements, nonlinear elements). For example, MIM (Metal Insulator Metal) and TFD (Th
inFilmDiode) or the like can also be used. Since these elements have few manufacturing steps, they can be manufactured at low cost. Alternatively, it is possible to increase the yield. Furthermore, since the size of the element is small, the aperture ratio can be improved and low power consumption and high brightness can be achieved.

Active devices (active devices, non-linear devices) other than the active matrix system
It is also possible to use a passive matrix type without using. Since no active element (active element, non-linear element) is used, the number of manufacturing steps is small and the manufacturing can be performed at low cost.
Alternatively, it is possible to increase the yield. Further, since no active element (active element or non-linear element) is used, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

A transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and has a drain region, a channel region, and a source region. Current can be passed through. Here, since the source and the drain are changed depending on the structure of the transistor, operating conditions, and the like, it is difficult to determine which is the source or the drain. Therefore, in this specification, a region functioning as a source and a drain may not be called a source or a drain. In that case, as an example, they may be referred to as a first electrode and a second electrode, respectively.

The transistor may be a device having at least three terminals including a base, an emitter and a collector. In this case as well, the emitter and the collector may be referred to as the first terminal and the second terminal.

A gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line, a gate signal line, a scan line, a scan signal line, or the like), or part of them. The gate electrode refers to a part of a conductive film which overlaps with a semiconductor which forms a channel region with a gate insulating film interposed therebetween. In addition, a part of the gate electrode is an LDD (Lightly Doped Dr).
In some cases, it may overlap with the ain) region or the source region and the drain region via the gate insulating film. The gate wiring refers to a wiring for connecting the gate electrodes of the transistors or connecting the gate electrode and another wiring.

However, there is a portion (region, conductive film, wiring, or the like) which also functions as a gate electrode and also as a gate wiring. Such a portion (a region, a conductive film, a wiring, or the like) may be called either a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, in the case where a part of extended gate wiring and a channel region overlap with each other, the portion (region, conductive film, wiring, or the like) functions as a gate wiring, but also as a gate electrode. It's working. Therefore, such a portion (region, conductive film, wiring, or the like) may be referred to as a gate electrode or a gate wiring.

A portion (region, conductive film, wiring, or the like) formed of the same material as the gate electrode and forming a connection with the same island as the gate electrode may be referred to as a gate electrode. Similarly, a portion (a region, a conductive film, a wiring, or the like) formed of the same material as the gate wiring and forming and connecting with the same island as the gate wiring may be referred to as a gate wiring. Such a part (
(A region, a conductive film, a wiring, etc.) does not overlap with the channel region in a strict sense,
It may not have a function of connecting to another gate electrode. However, it is formed of the same material as the gate electrode or gate wiring, and is the same island as the gate electrode or gate wiring.
Is formed and connected (region, conductive film, wiring, etc.). Such a portion (region, conductive film, wiring, or the like) may also be called a gate electrode or a gate wiring.

For example, in a multi-gate transistor, one gate electrode is often connected to another gate electrode by a conductive film formed using the same material as the gate electrode. Such a portion (region, conductive film, wiring, or the like) is a portion (region, conductive film, wiring, or the like) for connecting the gate electrode and the gate electrode, and thus may be called a gate wiring. Since the above transistor can be regarded as one transistor, it may be called a gate electrode.
That is, a portion (region, conductive film, wiring, or the like) formed of the same material as the gate electrode or the gate wiring and connected by forming the same island as the gate electrode or the gate wiring is connected to the gate electrode or the gate wiring. You can call me. Further, for example, a conductive film in a portion connecting the gate electrode and the gate wiring, which is formed of a material different from that of the gate electrode or the gate wiring, may be referred to as a gate electrode. You can call it.

The gate terminal refers to a part of a gate electrode portion (a region, a conductive film, a wiring, or the like) or a portion electrically connected to the gate electrode (a region, a conductive film, a wiring, or the like).

When called a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of a transistor may not be connected to the wiring. In this case, the gate wiring, the gate line, the gate signal line, the scanning line, and the scanning signal line are wirings formed in the same layer as the gate of the transistor,
It may mean a wiring formed of the same material as the gate of the transistor or a wiring formed at the same time as the gate of the transistor. Examples include a storage capacitor wiring, a power supply line, and a reference potential supply wiring.

The source means the whole including a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, or the like), or part of them. The source region refers to a semiconductor region in which a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic) are contained. Therefore, a region containing a small amount of P-type impurities or N-type impurities, that is, a so-called LDD (Lightly Doped Drain) region is not included in the source region. The source electrode refers to a conductive layer in a portion formed of a material different from that of the source region and electrically connected to the source region. However, the source electrode is
The source region may also be referred to as a source electrode. The source wiring refers to a wiring for connecting between the source electrodes of each pixel or for connecting the source electrode and another wiring.

However, there is a portion (a region, a conductive film, a wiring, or the like) which also functions as a source electrode and a source wiring. Such a portion (a region, a conductive film, a wiring, or the like) may be referred to as a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, in the case where part of the source wiring which is extended and overlaps with the source region, that portion (region, conductive film, wiring, or the like) functions as a source wiring, but as a source electrode. Will also be working. Therefore, such a portion (region, conductive film, wiring, or the like) may be referred to as a source electrode or a source wiring.

A portion (region, conductive film, wiring, etc.) formed of the same material as the source electrode and connected by forming the same island as the source electrode, or a portion connecting the source electrode and the source electrode (region, conductivity). A film, wiring, etc.) may also be referred to as a source electrode. Further, a portion overlapping with the source region may also be called a source electrode. Similarly, a region which is formed of the same material as the source wiring and which is connected to form the same island as the source wiring may be referred to as a source wiring. In a strict sense, such a portion (region, conductive film, wiring, or the like) may not have a function of connecting to another source electrode. But,
There is a portion (region, conductive film, wiring, or the like) formed of the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring. Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a source electrode or a source wiring.

For example, a conductive film in a portion connecting the source electrode and the source wiring, which is formed of a material different from that of the source electrode or the source wiring, may be referred to as a source electrode,
It may be called source wiring.

The source terminal refers to a part of a source region, a source electrode, or a portion (a region, a conductive film, a wiring, or the like) electrically connected to the source electrode.

When referred to as a source wiring, a source line, a source signal line, a data line, a data signal line, or the like, the source (drain) of a transistor might not be connected to the wiring. In this case, the source wiring, the source line, the source signal line, the data line, and the data signal line are formed using the same layer as the source (drain) of the transistor and the same material as the source (drain) of the transistor. Alternatively, it may mean a wiring formed at the same time as the source (drain) of the transistor. Examples include a storage capacitor wiring, a power supply line, and a reference potential supply wiring.

The drain is similar to the source.

A semiconductor device refers to a device having a circuit including a semiconductor element (a transistor, a diode, a thyristor, or the like). Furthermore, all devices that can function by utilizing semiconductor characteristics may be called semiconductor devices.

The display element includes an optical modulation element, a liquid crystal element, a light emitting element, an EL element (organic EL element, inorganic EL
Element or EL element including organic substance and inorganic substance), electron emission element, electrophoretic element, discharge element,
It refers to a light reflecting element, a light diffracting element, a digital micromirror device (DMD), and the like. However, it is not limited to this.

A display device refers to a device having a display element. Note that the display device may be a display panel body in which a plurality of pixels each including a display element or a peripheral driver circuit for driving those pixels are formed over the same substrate. Note that the display device includes a peripheral drive circuit arranged on the substrate by wire bonding, bumps, or the like, an IC chip connected by a so-called chip on glass (COG), or an IC chip connected by a TAB or the like. You can stay. The display device may include a flexible wiring board (FPC) to which an IC chip, a resistance element, a capacitance element, an inductor, a transistor and the like are attached. The display device may include a printed wiring board (PWB) that is connected through a flexible wiring board (FPC) or the like and has an IC chip, a resistance element, a capacitance element, an inductor, a transistor, or the like attached thereto. The display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include a lighting device, a housing, a voice input / output device, an optical sensor, and the like. Here, the lighting device such as the backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water cooling type, air cooling type), and the like. good.

The illumination device refers to a device including a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, hot cathode tube, etc.), a cooling device, and the like.

Note that a light emitting device refers to a device having a light emitting element or the like.

The reflecting device refers to a device including a light reflecting element, a light diffracting element, a light reflecting electrode, and the like.

A liquid crystal display device refers to a display device having a liquid crystal element. The liquid crystal display device has a direct-view type,
There are projection type, transmission type, reflection type, semi-transmission type and the like.

A driving device refers to a device including a semiconductor element, an electric circuit, and an electronic circuit. For example, a transistor that controls input of a signal from a source signal line into a pixel (sometimes referred to as a selection transistor or a switching transistor), a transistor that supplies a voltage or current to a pixel electrode, a voltage or current to a light-emitting element A transistor or the like for supplying the is an example of a driving device. Further, a circuit that supplies a signal to a gate signal line (sometimes referred to as a gate driver or a gate line driver circuit) and a circuit that supplies a signal to a source signal line (a source driver,
A source line driver circuit or the like) is an example of a driver.

The display device, the semiconductor device, the lighting device, the cooling device, the light emitting device, the reflecting device, the driving device, and the like may overlap with each other. For example, the display device may include a semiconductor device and a light-emitting device, or the semiconductor device may include a display device and a driver.

In the present specification, when it is explicitly described that B is formed on A or B is formed on A, B is formed directly on A. It is not limited to this. The case where they are not in direct contact, that is, the case where another object is interposed between A and B is also included. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals,
Conductive film, layer, etc.).

Thus, for example, if it is explicitly stated that layer B is formed on layer A (or on layer A), layer B is formed directly on layer A. It includes a case and a case where another layer (for example, the layer C or the layer D) is formed directly on the layer A and the layer B is directly formed on the other layer. The other layers (for example, layer C and layer D) may be a single layer or multiple layers.

Further, the same applies to the case where it is explicitly described that B is formed above A, and the present invention is not limited to the case where B is directly contacted on A, The case where another object intervenes is also included. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed directly on the layer A and the case where another layer is formed directly on the layer A are mentioned. (For example, the layer C and the layer D are formed, and the case where the layer B is formed in direct contact therewith are also included. The other layers (for example, layer C and layer D) may be a single layer or multiple layers.

When it is explicitly described that B is formed directly on A, it includes the case where B is formed on A directly and includes another object between A and B. It does not include the case where

The same applies to the case where B is below A or B is below A.

It is possible to suppress the characteristic deterioration of all the transistors included in the shift register. Therefore, malfunction of a semiconductor device including the liquid crystal display device to which the shift register is applied can be suppressed.

7A and 7B are diagrams illustrating a structure of a flip-flop described in Embodiment 1; 3 is a timing chart explaining the operation of the flip-flop shown in FIG. 1. FIG. 3 is a diagram illustrating an operation of the flip-flop shown in FIG. 1. 7A and 7B are diagrams illustrating a structure of a flip-flop described in Embodiment 1; 7A and 7B are diagrams illustrating a structure of a flip-flop described in Embodiment 1; 3 is a timing chart illustrating the operation of the flip-flop described in Embodiment 1. 7A and 7B are diagrams illustrating a structure of a flip-flop described in Embodiment 1; 6A and 6B are diagrams illustrating a structure of the display device described in Embodiment 1; 9 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 8. 6A to 6C each illustrate a structure of a shift register described in Embodiment 1; 11 is a timing chart illustrating the operation of the shift register illustrated in FIG. 10. 11 is a timing chart illustrating the operation of the shift register illustrated in FIG. 10. 6A to 6C each illustrate a structure of a shift register described in Embodiment 1; 6A to 6C each illustrate a structure of a shift register described in Embodiment 1; 6A to 6C each illustrate a structure of a shift register described in Embodiment 1; 6A and 6B are diagrams illustrating a structure of a display device described in Embodiment 2; 6A to 6C each illustrate a structure of a shift register described in Embodiment 1; 6A and 6B are diagrams illustrating a structure of the display device described in Embodiment 1; 19 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 18. 6A and 6B are diagrams illustrating a structure of the display device described in Embodiment 1; 7A and 7B are diagrams illustrating a structure of a flip-flop described in Embodiment 1; 6A and 6B are diagrams illustrating a structure of a flip-flop described in Embodiment 2; 14A and 14B are diagrams illustrating a structure of a flip-flop described in Embodiment 4; 24 is a timing chart explaining the operation of the flip-flop shown in FIG. 23. The top view of the flip-flop shown in FIG. The figure explaining the structure of the buffer shown in FIG. 9A and 9B are diagrams illustrating a structure of a flip-flop described in Embodiment 3; FIG. 28 is a timing chart explaining the operation of the flip-flop shown in FIG. 27. 7A to 7C each illustrate a structure of a shift register described in Embodiment 3; 30 is a timing chart illustrating the operation of the shift register illustrated in FIG. 7 is a timing chart illustrating operation of the flip-flop described in Embodiment 2; 7 is a timing chart illustrating operation of the flip-flop described in Embodiment 2; 7A to 7C each illustrate a structure of a shift register described in Embodiment 2; 7A to 7C each illustrate a structure of a shift register described in Embodiment 2; 34 is a timing chart illustrating the operation of the shift register illustrated in FIG. 34 is a timing chart illustrating the operation of the shift register illustrated in FIG. FIG. 16 illustrates a structure of a signal line driver circuit shown in Embodiment 5; 38 is a timing chart illustrating the operation of the signal line driver circuit illustrated in FIG. FIG. 16 illustrates a structure of a signal line driver circuit shown in Embodiment 5; 40 is a timing chart illustrating an operation of the signal line driver circuit illustrated in FIG. 39. FIG. 16 illustrates a structure of a signal line driver circuit shown in Embodiment 5; 7A and 7B are diagrams illustrating a structure of a protection diode described in Embodiment 6; 7A and 7B are diagrams illustrating a structure of a protection diode described in Embodiment 6; 7A and 7B are diagrams illustrating a structure of a protection diode described in Embodiment 6; 14A and 14B are diagrams illustrating a structure of a display device described in Embodiment 7. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. Sectional drawing of the display element of a semiconductor device. Sectional drawing of the display element of a semiconductor device. Sectional drawing of the display element of a semiconductor device. FIG. 3 is a top view of a display element of a semiconductor device. FIG. 3 is a top view of a display element of a semiconductor device. FIG. 3 is a top view of a display element of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. FIG. 9 illustrates a panel circuit configuration of a semiconductor device. FIG. 9 illustrates a panel circuit configuration of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device. 6A and 6B are diagrams illustrating peripheral components of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. 6A and 6B are diagrams illustrating peripheral components of a semiconductor device. 6A and 6B are diagrams illustrating peripheral components of a semiconductor device. 6A and 6B are diagrams illustrating peripheral components of a semiconductor device. 7A to 7C each illustrate a semiconductor device. 6A and 6B are diagrams illustrating a method for driving a semiconductor device. 6A and 6B are diagrams illustrating a method for driving a semiconductor device. 6A and 6B are diagrams illustrating a method for driving a semiconductor device. 6A and 6B are diagrams illustrating a method for driving a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. 6A and 6B are a pixel layout example and a cross-sectional view of a semiconductor device. Sectional drawing of the display element of a semiconductor device. 6A and 6B are diagrams illustrating a device for forming a display element of a semiconductor device. 6A and 6B are diagrams illustrating a device for forming a display element of a semiconductor device. 6A and 6B are diagrams illustrating a method for driving a semiconductor device. 6A and 6B are diagrams illustrating a method for driving a semiconductor device. FIG. 6 illustrates an example of a pixel circuit of a semiconductor device. FIG. 6 illustrates an example of a pixel circuit of a semiconductor device. 6A to 6C are diagrams illustrating a process of manufacturing a semiconductor device. 7A to 7C each illustrate a display element of a semiconductor device. 7A to 7C each illustrate a display element of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 7A to 7C each illustrate a structure of a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. 6A to 6C each illustrate an electronic device including a semiconductor device. The figure explaining the structure of the buffer shown in FIG. The figure explaining the structure and timing chart of a conventional flip-flop.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be implemented in many different modes, and various changes can be made in the form and details without departing from the spirit and scope of the present invention. To be done. Therefore, the present invention is not construed as being limited to the description of this embodiment.

(Embodiment 1)
In this embodiment, structures and driving methods of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit are described.

The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. The flip-flop shown in FIG. 1 includes a first transistor 101, a second transistor 102, and a third transistor 102.
A transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, and a seventh transistor 107. In this embodiment, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor
Transistor 104, fifth transistor 105, sixth transistor 106 and seventh transistor
The transistor 107 is an N-channel transistor, and the gate-source voltage (V
When gs) exceeds the threshold voltage (Vth), it becomes conductive.

The connection relationship of the flip-flops in FIG. 1 will be described. First of the first transistor 101
Is connected to the fifth wiring 125, and the second electrode (the other one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125.
3 is connected. The first electrode of the second transistor 102 is connected to the fourth wiring 124, and the second electrode of the second transistor 102 is connected to the third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102, and the third transistor 1
The gate electrode 03 is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the ninth wiring 129, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate of the fourth transistor 104 is connected. The electrode is connected to the gate electrode of the first transistor 101. The first electrode of the fifth transistor 105 is connected to the eighth wiring 128, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate of the fifth transistor 105 is connected. The electrode is connected to the first wiring 121. The first electrode of the sixth transistor 106 is the tenth wiring 1
30, the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101, and the gate electrode of the sixth transistor 106 is connected to the second transistor 1.
02 gate electrode. A first electrode of the seventh transistor 107 is connected to the eleventh wiring 131, and a second electrode of the seventh transistor 107 is connected to the first transistor 101.
And the gate electrode of the seventh transistor 107 is connected to the second wiring 122.

Note that the gate electrode of the first transistor 101, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the second electrode of the seventh transistor 107. The connection point of the electrode of is a node 141. Furthermore, the second
A connection point of the gate electrode of the transistor 102, the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, and the gate electrode of the sixth transistor 106 is referred to as a node 142.

Note that the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 13
1 may be connected to each other or may be the same wiring. Further, the seventh wiring 127 and the eighth wiring 128 may be connected to each other or may be the same wiring.

Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 are connected to the first signal line, the second signal, and the third signal line, respectively. , Fourth signal line, and fifth signal line. Further, the fourth wiring 124, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are respectively connected to the first power supply line and the second power supply. It may be called a line, a third power line, a fourth power line, a fifth power line, and a sixth power line.

Note that the potential of V1 is supplied to the seventh wiring 127 and the eighth wiring 128, respectively.
The potential of V2 is supplied to each of the wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131. Furthermore, V1> V2.

Note that signals are input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126, respectively. The signal input to the first wiring 121 is a start signal, the signal input to the second wiring 122 is a reset signal, and the signal input to the fifth wiring 125 is a first clock signal. The signal input to the sixth wiring 126 is the second clock signal. Further, regarding signals input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126, the potential of the H signal is V1 (hereinafter also referred to as H level) and the L signal. Is a digital signal whose potential is V2 (hereinafter, also referred to as L level).

Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the second wiring 122 to the eleventh wiring 131, respectively.

Note that a signal is output from the third wiring 123. The signal output from the third wiring 123 is an output signal of the flip-flop of each stage and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop of the next stage. Further, regarding the signal output from the third wiring 123, the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2.
(Hereinafter, also referred to as L level) digital signal.

Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart of FIG. 2 and FIG. Further, the timing chart of FIG. 2 will be described by dividing it into a selection period and a non-selection period. Further, the non-selection period will be described by being divided into a first non-selection period, a second non-selection period, a set period, and a reset period. Furthermore, in the non-selection period, the set period,
During the operation period excluding the selection period and the reset period, the first non-selection period and the second non-selection period are sequentially repeated.

Note that in FIG. 2, the signal 221, the signal 225, the signal 226, the potential 241, the potential 242,
A signal 222 and a signal 223 are input to the first wiring 121, a signal input to the fifth wiring 125, a signal input to the sixth wiring 126, a potential of the node 141, and a potential of the node 142, respectively. , A signal input to the second wiring 122 and a signal output from the third wiring 123.

First, in the set period shown in FIGS. 2A and 3A, since the signal 221 is at H level, the fifth transistor 105 is turned on, and since the signal 222 is at L level, the seventh transistor 107 is turned off. The potential of the node 141 at this time is the second potential of the fifth transistor 105.
Becomes a source electrode and has a value obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the eighth wiring 128. Therefore, V1−Vth (105) (Vth (105): fifth transistor 105 threshold voltage). Therefore, the first transistor 101 and the fourth transistor 104 are turned on, and the fifth transistor 105 is turned off. At this time, the potential of the node 142 (potential 242) is equal to that of the third transistor 103 and the fourth transistor 1.
It is determined by the resistance ratio (L / W and applied voltage) with respect to 04, and becomes V2 + β (β: any positive number). Furthermore, β <Vth (102) (Vth (102): second transistor 10
2) and β <Vth (106) (threshold voltage of sixth transistor 106). That is, the potential (V2) of the ninth wiring 129 and the potential (V1 of the sixth wiring 126
Potential difference (V1-V2) from the third transistor 103 and the fourth transistor 104.
Is divided by. Therefore, the second transistor 102 and the sixth transistor 106
Turns off. Thus, in the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input, so that the potential of the third wiring 123 becomes V2. Therefore,
The L signal is output from the third wiring 123. Further, the node 141 changes the potential to V1-Vt.
A floating state is obtained while maintaining h (105).

In the selection period illustrated in FIGS. 2B and 3B, the signal 221 is at the L level, the fifth transistor 105 is off, and the signal 222 is at the L level, so that the seventh transistor 10
7 remains off. At this time, the node 141 maintains the potential at V1-Vth (105). Therefore, the first transistor 101 and the fourth transistor 104 remain on. At this time, the potential of the node 142 is V because the sixth wiring 126 is at an L level.
It becomes 2. Therefore, the second transistor 102 and the sixth transistor 106 remain off. Here, since the H signal is input to the fifth wiring 125, the potential of the third wiring 123 starts to rise. At this time, the potential of the node 141 is V by the bootstrap operation.
The voltage rises from 1-Vth (105) and becomes V1 + Vth (101) + α (Vth (101): threshold voltage of the first transistor 101, α: any positive number). Therefore, the third
The potential of the wiring 123 is equal to that of the fifth wiring 125, and thus becomes V1. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode of the first transistor 101 and the second electrode. Thus, in the selection period, the third wiring 123
Becomes conductive with the fifth wiring 125 to which the H signal is input, so that the potential of the third wiring 123 becomes V1. Therefore, the H signal is output from the third wiring 123.

In the reset period illustrated in FIGS. 2C and 3C, the signal 221 remains at L level, so that the fifth transistor 105 remains off and the signal 222 becomes H level and the seventh transistor 107 remains. Turns on. The potential of the node 141 at this time is the potential of the eleventh wiring (
Since V2) is supplied via the seventh transistor 107, it becomes V2. Therefore, the first transistor 101 and the fourth transistor 104 are turned off. Node 142 at this time
The second electrode of the third transistor 103 serves as a source electrode of the potential of the sixth wiring 1
Since it has a value obtained by subtracting the threshold voltage of the third transistor 103 from the potential (V1) of 26, it becomes V1-Vth (103) (Vth (103): threshold voltage of the third transistor 103). Therefore, the second transistor 102 and the sixth transistor 106 are turned on. As described above, in the reset period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

In the first non-selection period illustrated in FIGS. 2D and 3D, the signal 221 remains at L level, so that the fifth transistor 105 remains off and the signal 222 becomes L level. 7
Transistor 107 is turned off. At this time, the potential of the node 142 is 6th wiring 126.
Since the L signal is input to V2, it becomes V2. Therefore, the second transistor 102 and the sixth transistor 106 are turned off. At this time, the node 141 is in a floating state, so the potential is V
Keep at 2. Therefore, the first transistor 101 and the fourth transistor 104 remain off. As described above, in the first non-selection period, the third wiring 123 is in a floating state, so that the potential of the third wiring 123 maintains V2.

In the second non-selection period illustrated in FIGS. 2E and 3E, the signal 221 remains at the L level, so that the fifth transistor 105 remains off and the signal 222 remains at the L level. No. 7 transistor 107 remains off. The potential of the node 142 at this time is the sixth
Since the H signal is input to the wiring 126 of the transistor 104 and the transistor 104 is off, V1−Vth
It becomes (103). Therefore, the second transistor 102 and the sixth transistor 106 are turned on. At this time, the potential of the node 141 is the sixth potential of the tenth wiring 130 (V2).
V2 is still maintained because it is supplied via the transistor 106 of FIG. Therefore, the first transistor 101 and the fourth transistor 104 remain off. As described above, in the second non-selection period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 remains V2. Therefore, the L signal is the third wiring 12
It is output from 3.

From the above, the flip-flop in FIG. 1 sets the potential of the third wiring 123 to V1 by making the potential of the node 141 higher than V1 + Vth (101) by using the bootstrap operation in the selection period. be able to. Further, in the flip-flop of FIG. 1, the bootstrap operation is performed by using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 101, thereby reducing the layout area and the device. It is possible to obtain advantages such as a reduction in the number.

Further, in the flip-flop of FIG. 1, since the second transistor 102 and the sixth transistor 106 are turned on only in the second non-selection period, the threshold voltage of the second transistor 102 and the sixth transistor 106 is reduced. The shift can be suppressed.

Note that the flip-flop in FIG. 1 supplies V1 to the gate electrode of the third transistor 103 and inputs the second clock signal to the first electrode, so that the threshold voltage of the third transistor 103 is changed. The shift can also be suppressed.

Further, the flip-flop of FIG. 1 includes a first transistor 101, a fourth transistor 1
04, the fifth transistor 105, and the seventh transistor 107 do not turn on in the first non-selection period and the second non-selection period; therefore, the first transistor 101, the fourth transistor 104, the fifth transistor 105, and The threshold voltage shift of the seventh transistor 107 can be suppressed.

Further, in the flip-flop of FIG. 1, even when the potential of the node 141 and the potential of the third wiring 123 fluctuates in the first non-selection period, the node 141 and the third wiring 123 in the next second non-selection period. By supplying V2 to 123, the potential of the node 141 and the potential of the third wiring 123 can be reset to V2. Therefore, the flip-flop in FIG. 1 can suppress a malfunction caused by the node 141 and the wiring 123 being in a floating state and the potentials of the node 141 and the third wiring 123 being changed.

Furthermore, the flip-flop of FIG. 1 can suppress the threshold shift of the transistor,
Malfunction due to the threshold voltage shift of the transistor can be suppressed.

Further, in the flip-flop in FIG. 1, the first transistor 101 to the seventh transistor 107 are all N-channel transistors. Therefore, since the flip-flop in FIG. 1 can use amorphous silicon as a semiconductor layer of a transistor, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved. Further, it becomes possible to manufacture a large-sized display device. However, even if polysilicon or polycrystalline silicon is used for the semiconductor layer of the transistor, the manufacturing process can be simplified.

Note that the flip-flop in FIG. 1 has a long life because the characteristic deterioration of the transistor can be suppressed even when amorphous silicon in which characteristic deterioration (shift of threshold voltage) is prominently used as a semiconductor layer of the transistor. Display device can be manufactured.

Here, functions of the first transistor 101 to the eighth transistor 108 are described. The first transistor 101 has a function of selecting the timing of supplying the potential of the fifth wiring 125 to the third wiring 123 and increasing the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor. To do. Second transistor 10
2 has a function of selecting the timing of supplying the potential of the fourth wiring 124 to the third wiring 123 and functions as a switching transistor. The third transistor 103 has a sixth
It has a function of dividing the potential of the wiring and the potential of the ninth wiring 129 and functions as a resistance element or a transistor having a resistance component. The fourth transistor 104 has a ninth wiring 129
Has a function of selecting the timing of supplying the potential of the node 142 to the node 142, and functions as a switching transistor. The fifth transistor has a function of selecting the timing of supplying the potential of the eighth wiring to the node 141, and functions as an input transistor. The sixth transistor 106 has a function of selecting the timing of supplying the potential of the tenth wiring 130 to the node 141 and functions as a switching transistor. Seventh transistor 10
Reference numeral 7 has a function of selecting the timing of supplying the potential of the eleventh wiring 131 to the node 141, and functions as a switching transistor. However, the first transistor 101 to the seventh transistor 107 are not limited to the transistors as long as they have the functions described above. For example, the second transistor 102 which functions as a switching transistor
, The fourth transistor 104, the sixth transistor 106, and the seventh transistor 107.
May be a diode, a CMOS analog switch, various logic circuits, or the like as long as the element has a switching function. Further, the fifth transistor 105 that functions as an input transistor may have a function of increasing the potential of the node 141 and selecting the timing of turning off, and a PN junction diode, a diode-connected transistor, or the like is used. Good.

Note that the third transistor 103 and the fourth transistor 104 form an AC pulse generation circuit. The AC pulse generation circuit outputs a signal input from the first electrode of the third transistor 103 to the node 142. However, when the gate electrode of the fourth transistor 104 is at the H level, the AC pulse generation circuit outputs the L signal to the node 142 regardless of the signal input from the first electrode of the third transistor 103.

Note that in the flip-flop of this embodiment, the W / L value of the first transistor 101 is maximized among the W / L values of the first transistor 101 to the seventh transistor 107. With this, the fall time and rise time of the signal 223 can be shortened. Thus, the flip-flop of this embodiment can output a signal with less bluntness and delay even when a large load is connected to the wiring 123.

Further, in the flip-flop of this embodiment, the W / L of the first transistor 101 is
The value of is preferably 2 to 5 times, more preferably 3 to 4 times the W / L value of the fifth transistor 105. Thus, the flip-flop of Embodiment 1 can output a signal with less bluntness and delay even when a large load is connected to the wiring 123.

Furthermore, in the flip-flop of this embodiment, the W / L of the fourth transistor 104 is
When the value of is larger than the value of W / L of the third transistor 103, the potential of the node 142 in the set period can be reduced. Accordingly, in the flip-flop of this embodiment, the sixth transistor 106 can be surely turned off during the set period, so that malfunction can be suppressed.

Furthermore, in the flip-flop of this embodiment, the L value of the third transistor 103 is preferably larger than the L value of the fourth transistor 104, more preferably 2
Double to triple. Thus, in the flip-flop of this embodiment, the W / L value of the third transistor 103 is reduced, so that the W value of the fourth transistor 104 can be reduced and the layout area can be reduced. be able to.

Note that the arrangement, the number, and the like of each transistor are not limited to those in FIG. 1 as long as the same operation as in FIG. 1 is performed. As can be seen from FIG. 3 which describes the operation of the flip-flop in FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are respectively shown in FIG. It suffices that electrical continuity is established as indicated by the solid lines in (A) to (E). Therefore, if it is possible to arrange transistors to satisfy this and operate them, newly arrange transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, and various logic circuits. Good.

For example, in the flip-flop illustrated in FIG. 4A, by disposing the capacitor 401 between the gate electrode and the second electrode of the first transistor 101, the bootstrap operation in the selection period is further stabilized. Can be done by Further, the flip-flop in FIG.
Since the parasitic capacitance between the gate electrode and the second electrode of the transistor 101 can be reduced,
Each transistor can switch at high speed. Alternatively, as illustrated in FIG. 4B, a transistor 402 may be used as the capacitor 401. The gate electrode of the transistor 402 is connected to the node 141, and the first electrode and the second electrode of the transistor 402 are connected to the third wiring 123, whereby the transistor 402 can function as a capacitor having a large capacitance component. However, the transistor 402 can function as a capacitor even when one of the first electrode and the second electrode is in a floating state. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Note that in the capacitor 401, a gate insulating film may be used as an insulating layer and a gate electrode layer and a wiring layer may be used as a conductive layer, or a gate insulating film may be used as an insulating layer and a gate electrode layer and impurities may be used as a conductive layer. An added semiconductor layer may be used, or an interlayer film (insulating film) may be used as an insulating layer.
Alternatively, a wiring layer and a transparent electrode layer may be used as the conductive layer. However, in the capacitor 401, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101 and the wiring layer is connected to the second electrode of the first transistor 101. Good to connect. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101 and the wiring layer is directly connected to the second electrode of the first transistor 101. Good to do. This is because the layout area of the flip-flop due to the arrangement of the capacitive element 401 does not increase.

As another example, the flip-flop illustrated in FIG.
By connecting the electrode of the first wiring 121 to the first wiring 121 (by diode-connecting the first transistor 101), the eighth wiring 128 becomes unnecessary and the wiring and the power supply (V1) can be reduced by one. it can. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 4D, the wiring and the power supply can be reduced by one by using the resistance element 403 instead of the third transistor 103. further,
The flip-flop in FIG. 4D changes the potential of the node 142 to the sixth level during the second non-selection period.
Since the potential can be made equal to the potential (V1) of the wiring 126, the driving capability can be improved.
The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 7A, the gate electrode of the second transistor 102 is connected to a wiring 711 to which an arbitrary signal is input, so that the second transistor 10 can be connected.
A reverse bias can be applied to the second gate electrode. Further, Vgs of the second transistor 102
Can be made smaller. Therefore, the threshold shift of the second transistor 102 can be further suppressed. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 7B, the gate electrode of the second transistor 102 is connected to the sixth wiring 126, so that the second transistor 102 can be turned on even in the set period. Therefore, the driving ability can be improved. Furthermore, the third wiring 1
23 noise can be reduced. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 7C, a wiring and a power supply can be reduced by one by using a diode-connected transistor 701 and a diode-connected transistor 702 instead of the third transistor 103. . The first electrode of the transistor 701, the second electrode of the transistor 702, and the gate electrode of the transistor 701 are the sixth wiring 1
26, the second electrode of the transistor 701, the second electrode of the transistor 702, and the gate electrode of the transistor 702 are connected to the node 141. That is, the sixth wiring 1
Two opposite diodes are connected in parallel between 26 and node 141. Note that FIG.
The same parts as those in FIG.

As another example, as illustrated in FIG. 21A, the sixth transistor 106 is not always necessary. This is because the sixth transistor 106 is not necessarily required if the potential of the node 141 can be kept at the L level in the non-selection period. Therefore, the flip-flop in FIG. 21A can reduce the number of transistors, which leads to advantages such as reduction in layout area. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As another example, as shown in FIG. 21B, instead of the fourth transistor 104, an eighth transistor
Alternatively, the transistor 2108 may be used. The first electrode of the eighth transistor 2108 is connected to the twelfth wiring 2132, and the second electrode of the eighth transistor 2108 is connected to the node 14
2 and the gate electrode of the eighth transistor 2108 is connected to the first wiring 121. Furthermore, V2 is supplied to the twelfth wiring 2132. By doing so, FIG.
The ON / OFF of the eighth transistor 2108 is controlled by the start signal in the flip-flop (4), so that the fall time of the potential of the node 142 in the set period can be shortened and the second transistor 102 and The time when the sixth transistor 106 is turned off can be shortened. Further, in the flip-flop in FIG. 21B, the time when the sixth transistor 106 is turned off is short, so that the rise time of the potential of the node 141 can be shortened in the set period. Thus, the flip-flop in FIG. 21B can have improved driving capability. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Note that the eighth wiring 128 is the fourth wiring 124, the ninth wiring 129, and the tenth wiring 130.
Alternatively, it may be connected to the eleventh wiring 131.

As another example, an eighth transistor 2108 may be added as shown in FIG. The eighth transistor 2108 can have a small transistor size because the potential of the node 142 can be set to the L level when the start signal is at the H level. Furthermore, FIG.
In the flip-flop in (C), on / off of the eighth transistor 2108 is controlled by the start signal, so that the driving capability of the flip-flop can be improved similarly to the flip-flop in FIG. .. Note that the same parts as those in FIGS. 1 and 21B are denoted by the same reference numerals and the description thereof will be omitted.

Note that the connection relationship of each wiring is not limited to that in FIG. 1 as long as the same operation as in FIG. 1 is performed.
As can be seen from FIG. 3 which describes the operation of the flip-flop in FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are respectively shown in FIG. It suffices that electrical continuity is established as indicated by the solid lines in (A) to (E). Therefore, the wirings may be arranged or connected so as to satisfy this.

For example, as illustrated in FIG. 5A, the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, the first electrode of the sixth transistor 106, and the seventh transistor 107. The first electrode of may be connected to the sixth wiring 506. Further, the first electrode of the third transistor 103 and the first electrode of the fifth transistor 105 may be connected to the seventh wiring 507. Thus, the number of wirings in the flip-flop in FIG. 5A can be reduced from 11 to 7 as compared with the flip-flop in FIG. Further, in the flip-flop in FIG. 5A, the number of wirings is reduced, so that the yield of the shift register can be improved. Further, in the flip-flop in FIG. 5A, a wiring routing area can be reduced and a layout area of a shift register can be reduced. Further, since the width of each wiring can be increased in the flip-flop of FIG. 5A, the voltage drop can be reduced and the driving capability of the shift register can be improved. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Note that the sixth wiring 506 illustrated in FIG. 5A corresponds to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 illustrated in FIG. Furthermore, FIG.
7 corresponds to the seventh wiring 127 and the eighth wiring 128 shown in FIG. Further, the first wiring 501, the second wiring 502, and the third wiring 50 illustrated in FIG.
The third, fourth wiring 504 and fifth wiring 505 are the first wiring 121 shown in FIG. 1, respectively.
Correspond to the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126.

Note that the sixth wiring 506 and the seventh wiring 507 may be referred to as a first power supply line and a second power supply line, respectively. Furthermore, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 are respectively connected to the first signal line, the second signal line, and the third signal line. It may be called a line, a fourth signal line, and a fifth signal line.

As another example, as illustrated in FIG. 5B, the first electrode of the fourth transistor 104 is the eighth electrode.
May be connected to the wiring 508. The flip-flop in FIG. 5B can suppress an erroneous operation due to a voltage drop of the sixth wiring 506 by causing an instantaneous current generated in the fourth transistor 104 in the set period to flow in the eighth wiring 508. 1 and 5 (A)
The same parts as those in FIG.

As another example, as illustrated in FIG. 5C, the first electrode of the second transistor 102 is the ninth electrode.
May be connected to the wiring 509. In the flip-flop in FIG. 5B, the instantaneous current generated in the second transistor 102 in the reset period is caused to flow in the ninth wiring 509, whereby the sixth
A malfunction due to a voltage drop of the wiring 506 can be suppressed. 1 and 5 (A
The same parts as those in () are denoted by the same reference numerals and the description thereof will be omitted.

As another example, as illustrated in FIG. 5D, the gate electrode of the third transistor 103 is the first electrode.
It may be connected to the 0 wiring 510. The flip-flop in FIG. 5D is the tenth wiring 5
When a potential lower than V1 is supplied to 10, the potential of the gate electrode of the second transistor 102 and the potential of the gate electrode of the sixth transistor 106 are reduced in the second non-selection period, so that the second transistor 102 and The characteristic deterioration of the sixth transistor 106 can be suppressed. Note that the portions common to the configurations of FIGS. 1 and 5A are denoted by the common reference numerals, and the description thereof will be omitted.

Note that the power supply potential, the signal amplitude, and the signal timing are not limited to the timing chart in FIG. 2 as long as the same operation as that in FIG. 1 is performed. As can be seen from FIG. 3 which describes the operation of the flip-flop in FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are respectively shown in FIG. It suffices that electrical continuity is established as indicated by the solid lines in (A) to (E). Therefore, the power supply potential, the signal amplitude, and the signal timing may be changed so as to satisfy this.

For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the fifth wiring 125
The period for inputting the H signal to the sixth wiring 126 may be shortened. 6, the timing at which the signal switches from the L level to the H level is in the period Ta, as compared with the timing chart of FIG.
It is delayed by 1 and the timing at which the signal switches from the H level to the L level is advanced by the period Ta2. That is, in FIG. 6, as compared with FIG. 2, a period in which the signal is at the H level (period Tb
) Is shortened by the period Ta1 + the period Ta2. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current of each wiring is small, so that power saving, suppression of malfunction, improvement of driving capability, and the like can be achieved. Further, the flip-flop to which the timing chart in FIG. 6 is applied can shorten the fall time of the signal output from the third wiring 123 in the reset period. . This is because the timing at which the potential of the node 141 is at the L level is delayed by the period Ta1 + the period Ta2, so that the L signal input to the fifth wiring 125 has high current capability (large channel width). This is because it is supplied to the third wiring 123 via. Note that parts that are the same as those in the timing chart of FIG.

Note that the relationship among the period Ta1, the period Ta2, and the period Tb is ((Ta1 + Tb) / (Ta1 +
It is desirable that Ta2 + Tb)) × 100 <10 [%]. More preferably, ((T
It is desirable that a1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <5 [%].
Further, it is desirable that the period Ta1≈the period Ta2.

As another example, when Va (V2 <Va <V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va−Vth (103) in the reset period and the second non-selection period, The threshold voltage shifts of the transistor 102 and the sixth transistor 106 can be suppressed.

As another example, when Vb (V1 + Vth (103) <Vb) is supplied to the seventh wiring 127, the potential of the node 142 becomes V1 in the reset period and the second non-selection period, so that the second transistor 102 and The sixth transistor 106 can be easily turned on.

As another example, by setting the potential of the L signal input to the sixth wiring 126 to Vc (Vc <V2) and the potential of the H signal to Vd (V1>Vd> V2), the second transistor 102 and Sixth
The threshold voltage shift of the transistor 106 can be suppressed. This is because the potential of the node 142 becomes Vc in the set period and the first non-selection period, and a reverse bias is applied to the second transistor 102 and the sixth transistor 106. Further, the potential of the node 142 becomes Vd during the reset period and the second non-selection period,
This is because Vgs of the transistor 102 and the sixth transistor 106 becomes smaller.

FIG. 25 illustrates an example of a top view of the flip-flop illustrated in FIG. The conductive layer 2501 includes a portion functioning as a gate electrode of the second transistor 102 and a gate electrode of the sixth transistor 106, and is connected to the conductive layer 2502 through the wiring 2547. Conductive layer 25
02 includes a portion functioning as a second electrode of the third transistor 103 and a second electrode of the fourth transistor 104. The conductive layer 2503 includes a portion functioning as a first electrode of the second transistor 102, a first electrode of the sixth transistor 106, and a first electrode of the fourth transistor 104, and a sixth wiring 506 and Connected. The conductive layer 2504 includes a portion functioning as a second electrode of the second transistor 102 and is connected to the third wiring 503 through the wiring 2548. The conductive layer 2505 is the second electrode of the fifth transistor 105,
It includes a portion functioning as a second electrode of the seventh transistor 107 and is connected to the conductive layer 2510 through the wiring 2549. The conductive layer 2506 includes a portion functioning as the first electrode of the seventh transistor 107 and is connected to the sixth wiring 506. The conductive layer 2507 includes a portion functioning as a first electrode of the first transistor 101 and is connected to the fourth wiring 504 through the wiring 2541. The conductive layer 2508 includes a portion functioning as the second electrode of the first transistor 101 and is connected to the third wiring 503 through the wiring 2548.
The conductive layer 2510 is included in the gate electrode of the first transistor 101 and the fourth transistor 104.
Of the gate electrode. The conductive layer 2511 is used for the seventh transistor 107.
Of the gate electrode, and is connected to the second wiring 502 through the wiring 2546. The conductive layer 2512 includes a portion functioning as a gate electrode of the third transistor 103 and is connected to the seventh wiring 507 through the wiring 2544. The conductive layer 2513 is the third
The portion including a portion functioning as the first electrode of the transistor 103 is connected to the fifth wiring 505 through the wiring 2543. The conductive layer 2514 includes a portion functioning as a gate electrode of the fifth transistor 105 and is connected to the first wiring 501 through the wiring 2545. The conductive layer 2515 includes a portion functioning as the second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 through the wiring 2547.

Note that a portion functioning as a gate electrode, a first electrode, and a second electrode of the first transistor 101 is a portion where a conductive layer including each of them and the semiconductor layer 2581 are overlapped with each other. A portion functioning as a gate electrode, a first electrode, and a second electrode of the second transistor 102 is a portion where a conductive layer including each of them and a semiconductor layer 2582 are overlapped with each other. A portion functioning as a gate electrode, a first electrode, and a second electrode of the third transistor 103 is a portion where a conductive layer including each of them and the semiconductor layer 2583 are overlapped with each other. A portion functioning as a gate electrode, a first electrode, and a second electrode of the fourth transistor 104 is a portion where a conductive layer including each of them and a semiconductor layer 2584 are overlapped with each other. A portion functioning as a gate electrode, a first electrode, and a second electrode of the fifth transistor 105 is a portion where a conductive layer including each of them and a semiconductor layer 2585 are overlapped with each other. A portion functioning as a gate electrode, a first electrode, and a second electrode of the sixth transistor 106 is a portion where a conductive layer including each of them and the semiconductor layer 2586 are overlapped with each other. A portion functioning as a gate electrode, a first electrode, and a second electrode of the seventh transistor 107 is a portion where a conductive layer including each of them and a semiconductor layer 2587 are overlapped with each other.

A structure and a driving method of the shift register including the flip-flop of this embodiment described above will be described.

The structure of the shift register in this embodiment will be described with reference to FIG. The shift register in FIG. 10 includes n flip-flops (flip-flops 1001_1 to 1001_n).

The connection relationship of the shift register in FIG. 10 will be described. In the shift register in FIG. 10, the i-th stage flip-flop 1001_i (one of the flip-flops 1001_1 to 1001_n) has a second wiring 1012, a third wiring 1013, a fourth wiring 1014, and a fifth wiring. 1015, sixth wiring 1016, eighth wiring 1018_i-1, and eighth wiring 10
18_i and the eighth wiring 1018_i + 1. However, the first-stage flip-flop 1001_1 includes a first wiring 1011, a second wiring 1012, a third wiring 1013,
The fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, and the eighth wiring 1018_
It is connected to the first and eighth wirings 1018_2. In addition, the flip-flop 100 of the nth stage
1_n is the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, the seventh wiring 1017, the eighth wiring 1018_n−1, and the eighth wiring 1018. It is connected to the wiring 1018_n.

The first wiring 1011 is connected to the first wiring 121 of the flip-flop 1001_1 shown in FIG. The second wiring 1012 is connected to the fifth wiring 125 shown in FIG. 1 in the odd-numbered flip-flops and connected to the sixth wiring 126 shown in FIG. 1 in the even-numbered flip-flops. The third wiring 1013 is connected to the sixth wiring 126 shown in FIG. 1 in the odd-numbered flip-flops and connected to the fifth wiring 125 shown in FIG. 1 in the even-numbered flip-flops. The fourth wiring 1014 is a flip-flop for all stages, and the seventh wiring 1 shown in FIG.
Connected to 27. The fifth wiring 1015 is a flip-flop in all stages and is connected to the eighth wiring 128 shown in FIG. The sixth wiring 1016 is a flip-flop in all stages and is connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. The eighth wiring 1018_i is the second wiring 122 of the flip-flop 1001_i-1 shown in FIG. 1, the third wiring 123 of the flip-flop 1001_i shown in FIG. 1, and the first wiring 121 of the flip-flop 1001_i + 1 shown in FIG. Connected to. However,
The eighth wiring 1018_1 is the third wiring 12 of the flip-flop 1001_1 shown in FIG.
3 and the flip-flop 1001_2 are connected to the first wiring 121 shown in FIG. Further, the eighth wiring 1018_n is connected to the second wiring 122 of the flip-flop 1001_n−1 illustrated in FIG. 1 and the third wiring 123 of the flip-flop 1001_n illustrated in FIG.

Note that the potential of V1 is supplied to the fourth wiring 1014 and the fifth wiring 1015,
The potential of V2 is supplied to the sixth wiring 1016.

Note that the first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1
A signal is input to each of 017. The signal input to the first wiring 1011 is a start signal, the signal input to the second wiring 1012 is a first clock signal, and the signal input to the third wiring 1013 is a second clock signal. A signal which is a signal and is input to the seventh wiring 1017 is a reset signal. Furthermore, the first wiring 1011 and the second wiring 1012,
The signals input to the third wiring 1013 and the seventh wiring 1017 are digital signals whose H signal potential is V1 and whose L signal potential is V2, respectively.

Note that various signals, power supply potentials, or currents may be input to the first wiring 1011 to the seventh wiring 1017.

Note that signals are output from the eighth wiring 1018_1 to the eighth wiring 1018_n. For example, the signal output from the eighth wiring 1018_i is the output signal of the flip-flop 1001_i. Further, the signal output from the eighth wiring 1018_i is also a start signal of the flip-flop 1001_i + 1 and a reset signal of the flip-flop 1001_i-1.

Note that in the case where signals input to or supplied from the first wiring 1011 to the seventh wiring 1017 are the same, the first wiring 1011 to the seventh wiring 1017 may be connected or the same. The wiring may be.

Next, the operation of the shift register shown in FIG. 10 will be described with reference to the timing chart of FIG. 11 and the timing chart of FIG. Here, the timing chart of FIG. 11 is divided into a scanning period and a blanking period. The scanning period is a period from when output of the selection signal from the eighth wiring 1018_1 is started to when output of the selection signal from the eighth wiring 1018_n is ended. The blanking period is a period until the output of the selection signal from the eighth wiring 1018_n is finished and the output of the selection signal from the eighth wiring 1018_1 is started.

Note that in FIG. 11, the signal 1111 input to the first wiring 1011 and the second wiring 10
The signal 1112 input to the second wiring 12, the signal 1113 input to the third wiring 1013, the signal 1117 input to the seventh wiring 1017, the signal 8th output to the eighth wiring 1018_1
The signal 1118_n output to the wiring 1018_2 and the eighth wiring 1018_n is shown. Further, in FIG. 12, the signal 1211 input to the first wiring 1011, the signal 1218_1 output to the eighth wiring 1018_1, the signal 1218_i output to the eighth wiring 1018_i, and the signal 1218_i output to the eighth wiring 1018_i + 1 are output. Signal 1218_i + 1 and the signal 1218_n output to the eighth wiring 1018_n.

As shown in FIG. 12, for example, when the flip-flop 1001_i enters the selection period (, the H signal is output from the eighth wiring 1018_i. At this time, the flip-flop 1001_i
i + 1 is a set period. After that, the flip-flop 1001_i is in a reset period, and the L signal is output from the eighth wiring 1018_i. At this time, flip-flop 1
001_i + 1 is a selection period. After that, in the first non-selection period of the flip-flop 1001_i, the eighth wiring 1018_i is in a floating state and the potential is maintained at the L level. At this time, the flip-flop 1001_i + 1 enters a reset period. After that, the flip-flop 1001_i is in the second non-selection period and the L signal is output from the eighth wiring 1018_i. At this time, the flip-flop 1001_i + 1 is in the first non-selection period. Thus, the flip-flop 1001_i repeats the first non-selection period and the second non-selection period until the next set period.

From the above, the shift register in FIG. 10 can output the selection signal sequentially from the eighth wiring 1018_1 to the eighth wiring 1018_n. That is, the shift register in FIG. 10 can scan the eighth wiring 1018_1 to the eighth wiring 1018_n. Therefore, the shift register in FIG. 10 can sufficiently obtain a function as a shift register.

Further, the reset signal input to the final-stage flip-flop 1001_n is input through the seventh wiring 1017. By doing so, the shift register in FIG. 10 does not need a dummy flip-flop, and thus the layout area can be reduced. However, a dummy flip-flop may be arranged.

Further, the shift register in FIG. 10 can freely determine the blanking period depending on the timing of the signal input to the first wiring 1011.

Further, by applying the flip-flop described in this embodiment to the shift register in FIG. 10, threshold shift of a transistor can be suppressed. Further, the shift register in FIG. 10 can have a long life. Further, the shift register in FIG. 10 can improve driving capability. Furthermore, malfunction can be suppressed. further,
The shift register in FIG. 10 can simplify processes and the like.

Note that the configuration is not limited to that of FIG. 10 as long as the same operation as that of FIG. 10 is performed.

For example, as shown in FIG. 13, the output signal of each flip-flop may be output via a buffer. In the shift register in FIG. 13, since the flip-flops 1001_1 to 1001_n are connected to the eighth wiring 1018_1 to the eighth wiring 1018_n via the buffers 1301_1 to 1301_n, respectively, a wide driving capability can be obtained. This is because when a large load is connected to each of the eighth wiring 1018_1 to the eighth wiring 1018_n, delay and rounding occur in the signals output from the eighth wiring 1018_1 to the eighth wiring 1018_n. That is, the eighth wiring 1018_1 to
This is because the delay and rounding of the signal output from each of the eighth wirings 1018_n do not affect the operation of the shift register. It should be noted that parts that are the same as the configuration of FIG.

Note that each of the buffers 1301_1 to 1301_n can be a logic circuit such as a NAND or NOR, an operational amplifier, or a circuit in which these are combined. That is, an inverter or an analog buffer can be used. In addition, buffer 1
When the flip-flops are configured by N-channel transistors, each of the 301_1 to the buffers 1301_n is preferably configured by N-channel transistors.
Furthermore, it is desirable that each of the buffers 1301_1 to 1301_n be configured to perform a bootstrap operation. Further, the driving voltage (potential difference between the negative power supply and the positive power supply) of each of the buffers 1301_1 to 1301_n is equal to the flip-flop 1
It is preferable that the driving voltage of each of 001_1 to flip-flop 1001_n is higher.

Here, the buffers 1301_1 to 1301 included in the shift register illustrated in FIG.
An example of _n will be described with reference to FIGS. 123A and 123B. 123 (
The buffer 8000 shown in A) includes an inverter 8001 between the wiring 8011 and the wiring 8012.
By connecting a, the inverter 8001b, and the inverter 8001c, an inverted signal of a signal input to the wiring 8011 is output from the wiring 8012. However, the number of inverters connected between the wiring 8011 and the wiring 8012 is not limited, and for example, the wiring 8011 and the wiring 8012 may be connected.
When an even number of inverters are connected between 12 and 12, a signal having the same polarity as the signal input to the wiring 8011 is output from the wiring 8012. Further, the buffer 810 in FIG.
0, an inverter 8002a, an inverter 8002b and an inverter 8002c connected in series, and an inverter 8003a and an inverter 8003b arranged in series.
And the inverter 8003c may be connected in parallel. The buffer 81 in FIG. 123 (B)
Since 00 can average variations in transistor characteristics, delay and rounding of the signal output from the wiring 8012 can be reduced. Further, the inverter 8002a and the inverter 8
The output of 002a and the outputs of the inverter 8002b and the inverter 8002b may be connected to each other.

Note that in FIG. 123A, it is preferable that W of a transistor included in the inverter 8001a <W of a transistor included in the inverter 8001b <W of a transistor included in the inverter 8001c. This is because the W of the inverter 8001a is small, so that the driving capability of the flip-flop (specifically, the W / L value of the transistor 101 in FIG. 1) can be reduced, and thus the shift register of this embodiment has a small layout area. Can be made smaller. Similarly, in FIG. 123B, it is preferable that W of a transistor included in the inverter 8002a <W of a transistor included in the inverter 8002b <W of a transistor included in the inverter 8002c. Similarly, in FIG. 123B, it is preferable that W of a transistor included in the inverter 8003a <W of a transistor included in the inverter 8003b <W of a transistor included in the inverter 8003c. Furthermore, the inverter 800
2a of the transistor included in 2a = W of the transistor included in the inverter 8003a, W of the transistor included in the inverter 8002b = W of the transistor included in the inverter 8003b, W of the transistor included in the inverter 8002c = W of the transistor included in the inverter 8003c. preferable.

Note that the inverters illustrated in FIGS. 123A and 123B are not particularly limited as long as they can invert an input signal and output the inverted signal. For example, as shown in FIG. 123C, an inverter may be formed using the first transistor 8201 and the second transistor 8202. Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. When the H signal is input to the first wiring 8211, the inverter in FIG. 123C has a potential (W / L of the first transistor 8201) obtained by dividing V1-V2 by the first transistor 8201 and the second transistor 8202. <W / L of second transistor 8202)
Output from the second wiring 8212. Further, when the L signal is input to the first wiring 8211, the inverter in FIG. 123C receives V1-Vth (8201) (Vth (8201): first
The threshold voltage of the transistor 8201) is output from the second wiring 8212. further,
The first transistor 8201 may be a PN junction diode as long as it has a resistance component, or may be simply a resistance element.

Further, as shown in FIG. 123D, an inverter may be formed using the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, a signal is output from the second wiring 8312, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and a fourth wiring 8314 and V6 is supplied to the sixth wiring 8316. FIG. 123
In the inverter (D), when an H signal is input to the first wiring 8311, V2 changes to the second wiring 8
It outputs from 312. At this time, the potential of the node 8341 is set at the L level, so that the first transistor 8301 is turned off. Further, the inverter in FIG. 123D has the first wiring 83
When the L signal is input to 11, V1 is output from the second wiring 8312. At this time, when the potential of the node 8341 becomes V1−Vth (8303) (Vth (8303): threshold voltage of the third transistor 8303), the node 8341 is in a floating state and the node 8341 is in a floating state.
Potential of V1 + Vth (8301) (Vth (8301)
: Threshold voltage of the first transistor 8301), the first transistor 8301 is turned on. Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode.

Further, as shown in FIG. 26A, an inverter may be formed using the first transistor 8401, the second transistor 8402, the third transistor 8403, and the fourth transistor 8404. The inverter in FIG. 26A is a two-input inverter and can perform bootstrap operation. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413.
V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. In the inverter in FIG. 26A, when an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, V2 is changed to the third wiring 841.
Output from 3. At this time, the potential of the node 8441 becomes V2, so that the first transistor 8401 is turned off. Further, the inverter in FIG.
When a signal and an L signal are input to the second wiring 8412, V1 is output from the third wiring 8413. At this time, the potential of the node 8441 is V1-Vth (8403) (Vth (8403)
: Threshold voltage of the third transistor 8403), the node 8441 becomes floating, and the potential of the node 8441 becomes V1 + Vth (8401) by the bootstrap operation.
Since it becomes higher than (Vth (8401): threshold voltage of the first transistor 8401), the first transistor 8401 is turned on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, one of the first wiring 8411 and the second wiring 8412 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG.

Further, as shown in FIG. 26B, an inverter may be formed using the first transistor 8501, the second transistor 8502, and the third transistor 8503. Figure 2
The 6 (B) inverter is a 2-input inverter and is capable of bootstrap operation. Further, a signal is input to the first wiring 8511, an inverted signal is input to the second wiring 8512, a signal is output from the third wiring 8513, and the fourth wiring 8514 and the sixth wiring 8514.
The wiring 8516 is supplied with V2, and the fifth wiring 8515 is supplied with V2. FIG. 26
When the L signal is input to the first wiring 8511 and the H signal is input to the second wiring 8512, the inverter in (B) outputs V2 from the third wiring 8513. At this time, the potential of the node 8541 becomes V2, so that the first transistor 8501 is turned off. Further, when the H signal is input to the first wiring 8511 and the L signal is input to the second wiring 8512, the inverter in FIG.
1 is output from the third wiring 8513. At this time, the potential of the node 8541 is V1-Vth
When (8503) (Vth (8503): threshold voltage of the third transistor 8503), the node 8541 becomes in a floating state, and the potential of the node 8541 is V1 + Vth (8501) (Vth (8501): One transistor 8501
Threshold voltage of 1), the first transistor 8501 is turned on. Further, since the first transistor 8501 functions as a bootstrap transistor,
A capacitor may be arranged between the second electrode and the gate electrode. Further, the first wiring 85
One of the eleventh and second wirings 8512 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG.

Further, as shown in FIG. 26C, an inverter may be formed using the first transistor 8601, the second transistor 8602, the third transistor 8603, and the fourth transistor 8604. The inverter in FIG. 26C is a two-input inverter and can perform bootstrap operation. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613.
V1 is supplied to the fourth wiring 8614, and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. In the inverter of FIG. 26A, the first wiring 8611 has an L signal and a second signal
When the H signal is input to the wiring 8612, V2 is output from the third wiring 8613. At this time, the potential of the node 8641 becomes V2, so that the first transistor 8601 is turned off.
Further, in the inverter in FIG. 26C, the H signal is input to the first wiring 8611 and the second wiring 861 is used.
When the L signal is input to 2, V1 is output from the third wiring 8613. At this time, node 8
The potential of 641 is V1-Vth (8603) (Vth (8603): third transistor 8
(Threshold voltage of 603), the node 8641 is in a floating state, and the potential of the node 8641 is V1 + Vth (8601) (Vth (8601):
Threshold voltage of the first transistor 8601), the first transistor 8601 is turned on. Further, since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, the third wiring 123 shown in FIG. 1 may be connected to one of the first wiring 8611 and the second wiring 8612, and the node 142 shown in FIG. 1 may be connected to the other.

As another example, the reset signal input to the flip-flop 1001_n can be another input signal or output signal of the shift register. That is, the flip-flop 100
By generating the reset signal input to 1_n inside the shift register, one wiring and one signal can be reduced. For example, in the case where the flip-flop 1001_n is in an even-numbered stage, it may be connected to the eighth wiring 1018_1 as illustrated in FIG. . As another example, when the flip-flop 1001_n is in an even-numbered stage, as shown in FIG.
May be connected to the wiring 1011. As another example, as shown in FIG. 17, a dummy flip-flop 1001_d may be used to generate a reset signal to be input to the flip-flop 1001_n. As the dummy flip-flop 1001_d, the same one as the flip-flop 1001_n-1 can be used. However, the second wiring 122 in FIG. 1 of the dummy flip-flop 1001_d is connected to the sixth wiring 1016 in FIG. It should be noted that parts that are the same as the configuration of FIG.

Next, a structure and a driving method of the display device having the shift register of this embodiment described above will be described. However, the display device of this embodiment may include at least the flip-flop of this embodiment.

The structure of the display device of this embodiment will be described with reference to FIG. The display device in FIG. 18 includes a signal line driver circuit 1801, a scan line driver circuit 1802, and a pixel portion 1804. In the pixel portion 1804, a plurality of signals which are arranged so as to extend in the column direction from the signal line driver circuit 1801. Line S
1 to Sm, a plurality of scanning lines G1 to G1 extending in the row direction from the scanning line driving circuit 1802
The pixel 1803 includes a plurality of pixels 1803 which are arranged in matrix in correspondence with the Gn, the signal lines S1 to Sm, and the scan lines G1 to Gn. Each pixel 1803 has a signal line Sj (signal lines S1 to S).
m) and the scanning line Gi (any one of the scanning lines G1 to Gn). Further, the scan line driver circuit 1802 may be referred to as a driver circuit.

Note that the shift register of this embodiment can be applied to the scan line driver circuit 1802. Needless to say, the shift register of this embodiment may be used for the signal line driver circuit 1801.

Note that the scan lines G1 to Gn are connected to the eighth wiring 1808_1 to the eighth wiring 1808_n illustrated in FIGS. 10, 12, 13, 14, 15, and 17, respectively.

Note that the signal line and the scan line may be simply referred to as a wiring. Further, a signal line driver circuit 1801
Each of the scan line driver circuit 1802 and the scan line driver circuit 1802 may be referred to as a driver circuit.

Note that the pixel 1803 includes at least one switching element, one capacitor, and a pixel electrode. However, the pixel 1803 may include a plurality of switching elements or a plurality of capacitors. Furthermore, the capacitive element is not always necessary. Further, the pixel 1803
May further include a transistor that operates in a saturation region. Further, the pixel 1803
May have a display element such as a liquid crystal element or an EL element. Here, a transistor and a PN junction diode can be used as the switching element. However, when using a transistor as a switching element, it is desirable that the transistor operates in a linear region. Further, in the case where the scan line driver circuit 1802 includes only N-channel transistors, it is desirable to use N-channel transistors as switching elements. Further, in the case where the scan line driver circuit 1802 includes only P-channel transistors, it is desirable to use P-channel transistors as switching elements.

Note that the scan line driver circuit 1802 and the pixel portion 1804 are formed over the insulating substrate 1805, and the signal line driver circuit 1801 is not formed over the insulating substrate 1805. The signal line driver circuit 1801 is formed over a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1805. Then, the signal line driver circuit 1801 is connected to the signal lines S1 to Sm via a printed circuit board such as an FPC. However, the signal line driver circuit 1801 may be formed over the insulating substrate 1805, or a circuit which forms part of the function of the signal line driver circuit 1801 may be formed over the insulating substrate 1805.

Wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (T).
a), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd)
, Chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (C
u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn)
, Niobium (Nb), Silicon (Si), Phosphorus (P), Boron (B), Arsenic (As), Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O) Selected from the group consisting of one or more elements selected from the above, or compounds containing one or more elements selected from the above groups, alloy materials (for example, indium tin oxide (ITO), indium zinc oxide (IZO)). ), Indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
Aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium (
Mo-Nb) or the like) is preferable. Alternatively, the wiring, the electrode, the conductive layer, the conductive film, the terminal, and the like are preferably formed using a substance in which these compounds are combined. Alternatively, a compound of one or more elements selected from the above group and silicon (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), one or more elements selected from the above group and nitrogen It is desirable to be formed by using a compound (for example, titanium nitride, tantalum nitride, molybdenum nitride, etc.).

Silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron).
May be included. Since silicon contains impurities, the conductivity can be improved. Alternatively, it becomes possible to behave like a normal conductor. Therefore, it can be easily used as a wiring or an electrode.

As the silicon, silicon having various crystallinity such as single crystal, polycrystal (polysilicon), and microcrystal (microcrystal silicon) can be used. Alternatively, amorphous (
Amorphous silicon) or the like can also be used. By using single crystal silicon or polycrystalline silicon, resistance of wirings, electrodes, conductive layers, conductive films, terminals, and the like can be reduced. By using amorphous silicon or microcrystalline silicon, wiring or the like can be formed in a simple process.

Note that since aluminum or silver has high conductivity, signal delay can be reduced.
Further, since etching is easy, patterning is easy and fine processing can be performed.

Since copper has a high conductivity, it is possible to reduce signal delay. When using copper,
In order to improve the adhesion, it is desirable to have a laminated structure.

Note that molybdenum or titanium is preferable because it has advantages of not causing a defect even when contacted with an oxide semiconductor (ITO, IZO, or the like) or silicon, easily etched, and high in heat resistance.

Note that tungsten is preferable because it has advantages such as high heat resistance.

Note that neodymium is desirable because it has advantages such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, heat resistance is improved and aluminum is less likely to cause hillocks.

Note that silicon is preferable because it has the advantages that it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.

In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
Since nO) has a light-transmitting property, it can be used for a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

Note that the wiring, the electrode, the conductive layer, the conductive film, the terminal, and the like may have a single-layer structure or a multi-layer structure. With a single-layer structure, manufacturing steps for wiring, electrodes, conductive layers, conductive films, terminals, and the like can be simplified, the number of process days can be reduced, and cost can be reduced. Alternatively, by adopting a multi-layer structure, it is possible to reduce the demerits while making the most of the merits of the respective materials, and to form high-performance wiring, electrodes and the like. For example, by including a low resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. Further, by forming a laminated structure in which a low heat resistant material is sandwiched between high heat resistant materials, it is possible to increase the heat resistance of wirings, electrodes, etc. while taking advantage of the advantage of the low heat resistant material. For example, a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like is preferable.

Further, when the wiring and the electrodes directly contact each other, they may adversely affect each other. For example, one wiring, electrode, or the like may enter the material of the other wiring, electrode, or the like, changing its properties and failing to serve its original purpose. Alternatively, a high resistance portion may be formed. Alternatively, a problem may occur during manufacturing, which prevents normal manufacturing. In such a case, it is advisable to sandwich or cover a material that easily reacts due to the laminated structure with a material that does not easily react. For example, when connecting ITO and aluminum, ITO
It is desirable to sandwich a titanium, molybdenum or neodymium alloy between the aluminum and the aluminum.
Also, when connecting silicon and aluminum, between the ITO and aluminum,
It is desirable to sandwich a titanium-molybdenum-neodymium alloy.

Note that the wiring means a wiring in which a conductor is arranged. It may extend linearly or may be arranged short without extending. Therefore, the electrodes are included in the wiring.

Note that the wirings and electrodes described above can be applied to other display devices, shift registers, and pixels.

Note that the signal line driver circuit 1801 inputs voltage or current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Furthermore, the positive and negative polarities of the video signal may be inverted for each frame (frame inversion drive), the positive and negative polarities may be inverted for each row (gate line inversion drive), and each column may be reversed. To the positive electrode
The negative electrode may be inverted (source line inversion drive), and the positive electrode / negative electrode may be inverted for each row and column (dot line inversion drive). Furthermore, the video signal may be input to the signal lines S1 to Sm by dot-sequential driving or line-sequential driving. Further, the signal line driver circuit 1801 supplies not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm.
You may enter in. It is desirable to input a constant voltage such as a precharge voltage for each gate selection period and for each frame.

Note that the scan line driver circuit 1802 inputs a signal to the scan lines G1 to Gn and scans the scan lines G1 to Gn.
Are sequentially selected from the first row (hereinafter, also referred to as scanning). Then, the scanning line drive circuit 180
2 selects a plurality of pixels 1803 connected to the selected scan line. Here, a period in which one scanning line is selected is called a one-gate selection period, and a period in which the scanning line is not selected is called a non-selection period. Further, a signal output to the scan line by the scan line driver circuit 1802 is called a scan signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

Note that when the pixel 1803 is selected, a video signal is input from the signal line driver circuit 1801 to the pixel 1803 through the signal line. Further, when the pixel 1803 is not selected, the pixel 1803 has a video signal input in the selection period (a potential corresponding to the video signal).
Holding

Although not shown, the signal line driver circuit 1801 and the scan line driver circuit 1802 are supplied with a plurality of potentials and a plurality of signals.

Next, the operation of the display device shown in FIG. 18 will be described with reference to the timing chart in FIG. Further, FIG. 19 shows one frame period corresponding to a period for displaying an image for one screen. However, although one frame period is not particularly limited, it is preferably at least 1/60 seconds or less so that a viewer of the image does not feel flicker.

Note that in the timing chart of FIG. 19, the scanning line G1 in the first row and the scanning line Gi, i in the i-th row
The timings at which the + 1th scanning line Gi + 1 and the nth scanning line Gn are selected are shown.

In FIG. 19, for example, the scanning line Gi of the i-th row is selected, and the plurality of pixels 1803 connected to the scanning line Gi are selected. Then, the plurality of pixels 1803 connected to the scan line Gi each input a video signal and hold a potential corresponding to the video signal. After that, the scanning line Gi of the i-th row is deselected, the scanning line Gi + 1 of the i + 1-th row is selected, and the plurality of pixels 1803 connected to the scanning line Gi + 1 are selected. Then, the plurality of pixels 1803 connected to the scan line Gi + 1 each input a video signal and hold a potential corresponding to the video signal. Thus, in one frame period, the scan lines G1 to Gn are sequentially selected, and the pixels 1803 connected to each scan line are also sequentially selected. Then, the plurality of pixels 1803 connected to each scan line each input a video signal and hold a potential corresponding to the video signal.

From the above, the display device in FIG. 18 can input video signals to all pixels independently, so that the function as an active matrix display device can be sufficiently obtained.

Further, in the display device in FIG. 18, the shift register of this embodiment is used as the scan line driver circuit 1802, so that the threshold shift of the transistor can be suppressed. The display device in FIG. 18 can have a long life. The display device of FIG. 18 can improve the driving capability. The display device of FIG. 18 can suppress malfunction. The display device in FIG. 18 can simplify the process.

Further, in the display device in FIG. 18, the signal line driver circuit 1801 which needs to operate at high speed, the scan line driver circuit 1802, and the pixel 1803 are formed over different substrates.
Amorphous silicon can be used for the semiconductor layer of the transistor included in 2 and the semiconductor layer of the transistor included in the pixel 1803. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, the display device of FIG. 18 can improve the yield. Furthermore, the display device of this embodiment can be upsized. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon for the semiconductor layer of the transistor.

Note that in the case where the signal line driver circuit 1801, the scan line driver circuit 1802, and the pixel 1803 are formed over the same substrate, a polysilicon layer is used as a semiconductor layer of a transistor included in the scan line driver circuit 1802 and a semiconductor layer of a transistor included in the pixel 1803. It is preferable to use silicon or polycrystalline silicon.

Note that, as shown in FIG. 18, as long as a pixel can be selected and a video signal can be written independently to the pixel, the number, arrangement, or the like of the driver circuits is not limited to that in FIG.

For example, as shown in FIG. 20, the scanning lines G1 to Gn are the first scanning line driving circuit 2002.
a and the second scan line driver circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are the scanning line driving circuit 1 shown in FIG.
The configuration is similar to that of 802, and the scanning lines G1 to Gn are scanned at the same timing. Further, the first scan line driver circuit 2002a and the second scan line driver circuit 2002b may be referred to as a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 20 includes a first scan line driver circuit 2002a and a second scan line driver circuit 200.
Even if a defect occurs in one of the scanning lines 2b, the other of the scanning line driving circuit 2002a and the second scanning line driving circuit 2002b can scan the scanning lines G1 to Gn, so that redundancy can be provided. Further, in the display device of FIG. 20, the load of the first scanning line driving circuit 2002a (wiring resistance of scanning lines and parasitic capacitance of scanning lines) and the load of the second scanning line driving circuit 2002b are shown in FIG.
Therefore, the delay and rounding of signals input to the scanning lines G1 to Gn (output signals of the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b) can be reduced. Further, in the display device in FIG. 20, since the load of the first scan line driver circuit 2002a and the load of the second scan line driver circuit 2002b are reduced, the scan lines G1 to Gn can be scanned at high speed. it can. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the definition of the panel. Further, the merits of the display device in FIG. 20 are more effective when amorphous silicon is used for the semiconductor layers of the transistors included in the first scan line driver circuit 2002a and the second scan line driver circuit 2002b. Note that the portions common to the configuration of FIG. 18 are denoted by the same reference numerals and the description thereof is omitted.

As another example, FIG. 8 shows a display device in which a video signal can be written to a pixel at high speed. In the display device in FIG. 8, video signals are input to the pixels 1803 in the odd rows from signal lines in the odd columns, and video signals are input to the pixels 1803 in the even rows from signal lines in the even columns. Further, in the display device of FIG. 8, odd-numbered scanning lines of the scanning lines G1 to Gn are scanned by the first scanning line driving circuit 802a, and even-numbered scanning lines of the scanning lines G1 to Gn are scanned. The scan line is scanned by the second scan line driver circuit 802b. Further, the first scan line driver circuit 802
The start signal input to b is delayed by 1/4 cycle of the clock signal than the start signal input to the first scan line driver circuit 802a.

Note that the display device in FIG. 8 can perform dot inversion driving simply by inputting a positive video signal and a negative video signal to each signal line for each column in one frame period. further,
The display device in FIG. 8 can perform frame inversion driving by inverting the polarity of the video signal input to each signal line every one frame period.

The operation of the display device in FIG. 8 will be described with reference to the timing chart in FIG. In the timing chart of FIG. 9, the first scanning line G1, the i−1th scanning line Gi-1, the ith scanning line Gi, the i + 1th scanning line Gi + 1, and the nth scanning line Gn. Indicates the timing of selection. Further, in the timing chart of FIG. 9, one selection period is divided into a selection period a and a selection period b. Further, in the timing chart of FIG.
A case will be described in which the display device performs the dot inversion drive and the frame inversion drive.

In FIG. 9, for example, in the selection period a of the scanning line Gi on the i-th row, the scanning line Gi-1 on the i-1th row
Selection period b of the scanning line Gi of the i-th row overlaps the selection period a of the scanning line Gi + 1 of the i + 1-th row. Therefore, in the selection period a, i-1 row
Similar to the video signal input to the pixel 1803 in the (j + 1) th column, the pixel 1 in the i-th row and the j-th column
803 is input. Further, in the selection period b, a video signal similar to that input to the pixel 1803 in the i-th row and the j-th column is input to the pixel 1803 in the i + 1-th row and the j + 1-th column. Note that the video signal input to the pixel 1803 in the selection period b is an original video signal, and the video signal input to the pixel 1803 in the selection period a is a video signal for precharging the pixel 1803. Therefore, each of the pixels 1803 is i in the selection period a.
After being precharged by the video signal input to the pixel 1803 in the −1 row and j + 1 column, the original (i row and j column) video signal is input in the selection period b.

From the above, the display device in FIG. 8 can write a video signal into the pixel 1803 at high speed, and thus can easily achieve large size or high definition. Further, in the display device in FIG. 8, since video signals of the same polarity are input to the signal lines in one frame period,
The amount of charge and discharge of each signal line is small, and low power consumption can be realized. Further, in the display device of FIG. 8, the load of the IC for supplying the video signal is significantly reduced, so that heat generation of the IC, power consumption of the IC, and the like can be reduced. Further, in the display device in FIG. 8, the driving frequency of the first scanning line driving circuit 802a and the second scanning line driving circuit 802b can be reduced to about half.

Note that the display device in this embodiment can perform various driving methods depending on the structure and the driving method of the pixel 1803. For example, in one frame period, the scan line driver circuit may scan the scan line a plurality of times.

Note that in the display device in FIGS. 8, 18, and 20, another wiring or the like may be added depending on the structure of the pixel 1803. For example, a power supply line kept at a constant potential, a capacitance line, a new scanning line, or the like may be added. However, when a scan line is newly added, a scan line driver circuit to which the shift register of this embodiment is applied may be newly added. As another example, a dummy scanning line, a signal line, a power supply line, or a capacitance line may be arranged in the pixel portion.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined. Furthermore, in each of the figures described so far,
More figures can be constructed by combining different parts.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example in which the contents described in the other embodiments are embodied, an example in which the contents are slightly modified, an example in which a part is changed, an example in the case of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 2)
In this embodiment, a structure and a driving method of a flip-flop different from that in Embodiment 1, a driver circuit including the flip-flop, and a display device including the driver circuit are described. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

As the structure of the flip-flop of this embodiment, the structure of the flip-flop similar to that of Embodiment 1 can be used. However, the timing for driving the flip-flop is the same as in the first embodiment.
Is different from. Therefore, description of the structure of the flip-flop is omitted in this embodiment.

Note that the case where the drive timing of this embodiment is applied to the flip-flop of FIG. 1 is described. The drive timing of this embodiment is shown in FIG. 4A, FIG. 4B, FIG. 4 (D), 5 (A), 5 (B), 5 (C), 5 (D), 7 (A), 7 (B)
It can be implemented by being freely combined with the flip-flop of FIG. 7C, FIG. 21A, FIG. 21B, or FIG. Further, the drive timing of this embodiment can be freely combined with the drive timing described in Embodiment 1.

Next, the operation of the flip-flop of this embodiment will be described with reference to the flip-flop of FIG. 1 and the timing chart of FIG. Further, the timing chart of FIG. 31 will be described by dividing it into a selection period and a non-selection period. Further, the non-selection period is the first non-selection period,
The second non-selection period, the set period a, the set period b, and the reset period will be described separately.
Further, the selection period will be described by being divided into a selection period a and a selection period b. Further, in the non-selection period, the operation period excluding the set period a, the set period b, the selection period a, the selection period b, and the reset period repeats the first non-selection period and the second non-selection period.

Note that in FIG. 31, a signal 3121, a signal 3125, a signal 3126, a potential 3141, a potential 3142, a signal 3122, and a signal 3123 are signals input to the first wiring 121 and a signal input to the fifth wiring 125, respectively. , The signal input to the sixth wiring 126, the potential of the node 141, the potential of the node 142, the signal input to the second wiring 122, the third wiring 1
23 shows a signal output from 23.

Note that the signal 3121, the signal 3125, the signal 3126, the potential 3141, the potential 3142, the signal 3122, and the signal 3123 are converted into the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 in FIG. It is compatible and has similar features.

Note that the flip-flop of this embodiment basically performs the same operation as the flip-flop described in Embodiment 1. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that the timing at which the H signal is input to the first wiring 121 is delayed by 1/4 cycle of the clock signal.

Note that the flip-flop of this embodiment has the first non-selection period and the second non-selection period of the flip-flop described in Embodiment 1 in the first non-selection period and the second non-selection period. Perform the same operation. Furthermore, the flip-flop of this embodiment performs the same operation as that of the second non-selection period in the set period a. Further, the flip-flop of this embodiment performs the same operation in the reset period as in the reset period of the flip-flop described in Embodiment 1. Further, the flip-flop of this embodiment performs the same operation in the selection period a and the selection period b as in the selection period of the flip-flop described in Embodiment 1. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that the H signal is input to the first wiring 121 in the selection period a. However, even when the H signal is input to the first wiring 121 in the selection period a, the fifth transistor 105 is off, so that the operation of this embodiment is hardly affected. Therefore, the set period a, the set period b, the selection period a, the selection period b, the reset period, the first non-selection period and the second period
The detailed description of the flip-flop of this embodiment in the non-selected period is omitted.

Note that the flip-flop of this embodiment can reduce the layout area similarly to the flip-flop described in Embodiment 1. Further, the flip-flop of this embodiment can suppress the threshold shift of the transistor. Furthermore, the flip-flop of this embodiment can simplify the process.

By applying the timing chart shown in FIG. 32 to the flip-flop of this embodiment, the flip-flop of this embodiment can significantly shorten the fall time of the output signal. This is because the L signal can be input to the third wiring 123 through the first transistor 101 by shifting the timing when the signal 3122 (reset signal) goes to the H level.

Next, a structure and a driving method of the shift register including the above-described flip-flop of this embodiment will be described.

The structure of the shift register in this embodiment will be described with reference to FIG. The shift register in FIG. 33 includes n flip-flops (flip-flops 3301_1 to 3301_n).

The connection relationship of the shift register in FIG. 33 will be described. The shift register in FIG. 33 includes the 4N-3 (N is a natural number of 1 or more) stage flip-flop 330 among the i-th stage flip-flops 3301_i (one of the flip-flops 3301_1 to 3301_n).
The flip-flops 3301_4N-1 in the 1_4N−3 and 4N−1th stages include the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, and the eleventh wiring. Wiring 3321_i-1, eleventh wiring 3321_i, eleventh wiring 3
321_i + 2. Furthermore, the 4N−2nd stage flip-flop 3301_4N
The second and the 4N-th stage flip-flops 3301_4N include a third wiring 3313, a fifth wiring 3315, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318, and an eleventh wiring.
Connected to the wiring 3321_i−1, the eleventh wiring 3321_i, and the eleventh wiring 3321_i + 2. However, the first-stage flip-flop 3301_1 includes the first wiring 3111,
A second wiring 3312, a fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317,
The eighth wiring 3318, the eleventh wiring 3321_1, and the eleventh wiring 3321_3 are connected. Further, the flip-flop 3101_n−1 at the n−1th stage includes the second wiring 3312,
A fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318,
Tenth wiring 3320, eleventh wiring 3321_n-2, eleventh wiring 3321_n-1
Connected to. Further, the n-th stage flip-flop 3301_n is connected to the third wiring 3313.
A fifth wiring 3315, a sixth wiring 3316, a seventh wiring 3317, and an eighth wiring 3318.
, The ninth wiring 3319, the eleventh wiring 3321_n−1, and the eleventh wiring 3321_n.

The first wiring 3311 is connected to the first wiring 121 of the flip-flop 3301_1 illustrated in FIG. The second wiring 3312 is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N-3 and is connected to the sixth wiring 126 shown in FIG. 1 in the flip-flop 3301_4N-1. The third wiring 3313 is connected to the flip-flop 3301_4N
2 is connected to the fifth wiring 125 shown in FIG. 1, and the flip-flop 3301_4N is connected to the sixth wiring 126 shown in FIG. The fourth wiring 3314 is connected to the flip-flop 3
301_4N-3 is connected to the sixth wiring 126 in FIG.
1_4N-1 is connected to the fifth wiring 125 shown in FIG. The fifth wiring 3315 is connected to the sixth wiring 126 shown in FIG. 1 in the flip-flop 3301_4N-2 and is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N. 6th wiring 3
Reference numeral 306 is a flip-flop of all stages, which is connected to the seventh wiring 127 shown in FIG. The seventh wiring 3317 is a flip-flop in all stages and is connected to the eighth wiring 128 shown in FIG.
The eighth wiring 3318 and all stages of flip-flops are connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 illustrated in FIG. Ninth wiring 331
9 is connected to the second wiring 122 of the flip-flop 3301_n illustrated in FIG. 1. First
The wiring 3120 of 0 is the second wiring 122 of the flip-flop 3301_n−1 shown in FIG.
Connected to. The eleventh wiring 3321_i corresponds to the flip-flop 3301_i-2 in FIG.
2 and the third wiring 123 of the flip-flop 3301_i shown in FIG.
, And the first wiring 121 of the flip-flop 3301_i + 1 shown in FIG.
However, the eleventh wiring 3321_1 is the third wiring of the flip-flop 3301_1 shown in FIG.
Wiring 123 and the first wiring 121 of the flip-flop 3301_2 shown in FIG. Further, the eleventh wiring 3321_2 is the third wiring 123 of the flip-flop 3301_2 shown in FIG. 1 and the first wiring 12 of the flip-flop 3301_3 shown in FIG.
Connected to 1. Further, the eleventh wiring 3321_n is connected to the flip-flop 3301_n.
Is connected to the third wiring 123 shown in FIG.

Note that the potential of V1 is supplied to the sixth wiring 3316 and the seventh wiring 3317,
The potential of V2 is supplied to the eighth wiring 3318.

Note that the first wiring 3311, the second wiring 3312, the third wiring 3314, and the fifth wiring 33.
A signal is input to each of the fifteenth, ninth wiring 3319, and tenth wiring 3320. The signal input to the first wiring 3311 is a start signal, the signal input to the second wiring 3312 is a first clock signal, and the signal input to the third wiring 3313 is a second clock. A signal, which is a signal input to the fourth wiring 3314 is a third clock signal,
The signal input to the fifth wiring 3315 is the fourth clock signal, and the ninth wiring 3319
The signal input to the first reset signal is the first reset signal, and the signal input to the tenth wiring 3320 is the second reset signal. Further, the first wiring 3311, the second wiring 3312, and the third wiring
The signals input to the wiring 3314, the fifth wiring 3315, the ninth wiring 3319, and the tenth wiring 3320 are digital signals in which the potential of the H signal is V1 and the potential of the L signal is V2.

Note that various signals, currents, or voltages may be input to each of the first wiring 1031 to the tenth wiring 3320.

Note that signals are output from the eleventh wiring 3321_1 to the eleventh wiring 3321_n.
For example, the signal output from the eleventh wiring 3321_i is the flip-flop 3301_i.
It becomes the output signal of i. Further, the signal output from the eleventh wiring 3321_i is also the input signal of the flip-flop 3301_i + 1 and the reset signal of the flip-flop 3301_i-2.

Next, operation of the shift register illustrated in FIG. 33 is described with reference to a timing chart in FIG. 35 and a timing chart in FIG. Here, the timing chart of FIG. 35 is divided into a scanning period and a blanking period. The scan period is a period from when the output of the selection signal from the eleventh wiring 3311_1 is started to when the output of the selection signal from the eleventh wiring 3311_n is ended. The blanking period is a period until the output of the selection signal from the eleventh wiring 3311 — n ends and the output of the selection signal from the eleventh wiring 3311 — 1 starts.

Note that in FIG. 35, a signal 3511 input to the first wiring 3311 and a second wiring 33
12, a signal 3512 input to the third wiring 3313, a signal 3514 input to the fourth wiring 3314, and a signal 3515 input to the fifth wiring 3315.
, A signal 3519 input to the ninth wiring 3319, a signal 3520 input to the tenth wiring 3320, a signal 3521_1 output to the eleventh wiring 3321_1, and a signal 3521_n output to the eleventh wiring 3321_n. ing. Further, in FIG. 36, a signal 3611 input to the first wiring 3311, a signal 3621_1 output to the eleventh wiring 3321_1, a signal 3621_i−1 output to the eleventh wiring 3321_i−1, and an eleventh wiring Signal 3621_i output to 3321_i, eleventh wiring 3321_i + 1
Signal 3621_i + 1 output to the third line and the signal 36 output to the eleventh wiring 3321_n
21_n is shown.

As illustrated in FIG. 36, for example, when the flip-flop 3301_i-1 enters the selection period a, the H signal is output from the eleventh wiring 3321_i-1. At this time, flip-flop 3
301_i is the set period a. After that, the flip-flop 3301_i-1 is in the selection period b and the H signal is still output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i enters the selection period a. Then flip-flop 33
01_i-1 is in the reset period, and the H signal is output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i enters the selection period b. That is, in the shift register of this embodiment, the H signal is sequentially output from the flip-flop 3301_i-1, but the selection period b of the flip-flop 3301_i-1 and the flip-flop 3301_i-1.
i has a period in which the selection period a overlaps.

When the timing chart of FIG. 32 is applied to the flip-flop of this specification, the structure of the shift register may be as shown in FIG. In the shift register in FIG. 34, for example, the wiring 122 in the i-th stage flip-flop 3301_i shown in FIG. 1 is the eleventh wiring 33.
21_i + 3. Further, the second wiring 122 of the flip-flop 3301_n-2 illustrated in FIG. 1 is connected to the twelfth wiring 3322 to which the third reset signal is input.
Note that the same parts as those in FIG. 33 are denoted by the same reference numerals and the description thereof will be omitted.

Note that since the shift register of this embodiment mode uses the flip-flop of this embodiment mode, it suppresses threshold shift of a transistor, has a long life, improves driving capability, suppresses malfunction, and has a It can be simplified.

Note that the shift register in this embodiment can be implemented by being freely combined with the shift register described in Embodiment 1. For example, the shift register of this embodiment has the structure shown in FIGS.
This can be implemented by freely combining with the shift register of FIGS. Specifically, in the shift register of this embodiment, a buffer may be connected to the eleventh wiring 3321_1 to the eleventh wiring 3321_n, a reset signal may be generated internally, or a dummy flip-flop may be used. May be placed. As described above, the same parts as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

Next, a structure and a driving method of the display device having the shift register of this embodiment described above will be described. However, the display device of this embodiment may include at least the flip-flop of this embodiment.

The structure of the display device of this embodiment will be described with reference to FIG. In the display device in FIG. 16, the scan lines G1 to Gn are scanned by the scan line driver circuit 1602. Furthermore, FIG.
In the display device of No. 6, video signals are input to the odd-numbered pixels 1803 from the odd-numbered signal lines, and video signals are input to the even-numbered pixels 1803 from the even-numbered signal lines. Note that FIG.
The same parts as those of the configuration 8 are designated by the common reference numerals and the description thereof will be omitted.

Note that the display device in FIG. 16 can perform the same operation as the display device in FIG. 8 with one scan line driver circuit by applying the shift register of this embodiment to the scan line driver circuit 1602. Therefore, the display device in FIG. 16 can write a video signal into a pixel at high speed. Furthermore, the display device in FIG. 16 can be made larger or have higher definition. Further, the display device of FIG. 16 can further reduce power consumption. Furthermore, the display device of FIG. 16 can suppress heat generation of the IC. Furthermore, the display device in FIG. 16 can achieve power saving of the IC.

Note that, as shown in FIG. 22, the scan lines G1 to Gn are the first scan line driver circuit 2202a.
And may be scanned by the second scan line driver circuit 2202b. The first scan line driver circuit 2002a and the second scan line driver circuit 2002b are the scan line driver circuit 16 shown in FIG.
The scan line G1 to the scan line Gn are scanned at the same timing as the scan line G02. Further, the first scan line driver circuit 2202a and the second scan line driver circuit 2202b may be referred to as a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 22 includes a first scan line driver circuit 2202a and a second scan line driver circuit 220.
Even if a defect occurs in one of the scanning lines 2b, the other of the scanning line driving circuit 2202a and the second scanning line driving circuit 2202b can scan the scanning lines G1 to Gn and thus can have redundancy. Further, in the display device in FIG. 22, since the first scan line driver circuit 2202a and the second scan line driver circuit 2202b scan the scan lines G1 to Gn, the load of the first scan line driver circuit 2202a ( The wiring resistance of the scan line and the parasitic capacitance of the scan line) and the load of the second scan line driver circuit 2202b can be halved compared to those in FIG. Therefore, in the display device in FIG. 22, since the load of the first scan line driver circuit 2202a and the load of the second scan line driver circuit 2202b are reduced, signals input to the scan lines G1 to Gn (first It is possible to reduce delay and rounding of the output signals of the first scan line driver circuit 2202a and the second scan line driver circuit 2202b. Further, in the display device in FIG. 22, since the load of the first scan line driver circuit 2202a and the load of the second scan line driver circuit 2202b are reduced, the scan line G1 to the scan line Gn.
Can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the definition of the panel. Further, the advantage of the display device in FIG. 22 is that when amorphous silicon is used for a semiconductor layer of a transistor included in the first scan line driver circuit 2202a and the second scan line driver circuit 2202b,
It is even more effective. Note that the portions common to the configuration of FIG. 16 are denoted by the common reference numerals and the description thereof will be omitted.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined. Furthermore, in each of the figures described so far,
More figures can be constructed by combining different parts.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example of a case where the content described in another embodiment is embodied, an example of a slightly modified case, an example of a partial change, an example of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 3)
In this embodiment mode, a structure and a driving method of a flip-flop different from those in Embodiment Modes 1 and 2, a driver circuit including the flip-flop, and a display device including the driver circuit are described. The flip-flop of this embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. Note that components similar to those in Embodiment 1 and Embodiment 2 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. Figure 2
7 includes a first transistor 101, a second transistor 102,
The third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, the seventh transistor 107, the eighth transistor 108, and the ninth transistor 109 are included. In this embodiment, the eighth transistor 108 and the ninth transistor 109 are N-channel transistors and are in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). And

The flip-flop shown in FIG. 27 is the same as the flip-flop shown in FIG.
This is the same as the addition of the 8th and 9th transistors 109. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are similar to those in FIG. Any thing can be used.

The connection relationship of the flip-flops in FIG. 27 will be described. The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode of the first transistor 101 (the other of the source electrode and the drain electrode) is the first electrode. Wiring 1 of 3
23 is connected. The first electrode of the second transistor 102 is connected to the fourth wiring 124, and the second electrode of the second transistor 102 is connected to the third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126, and the third transistor 103
Of the second transistor 102 is connected to the gate electrode of the second transistor 102, and the gate electrode of the third transistor 103 is connected to the seventh wiring 127. The first of the fourth transistor 104
Is connected to the ninth wiring 129, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 101. It is connected to the gate electrode. First of fifth transistor 105
Of the fifth transistor 105 is connected to the eighth wiring 128, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate electrode of the fifth transistor 105 is connected to the first wiring 121. Connected. The first electrode of the sixth transistor 106 is connected to the tenth wiring 130, and the second electrode of the sixth transistor 106 is the first transistor 101.
The gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 102. A first electrode of the seventh transistor 107 is connected to the eleventh wiring 131, and a second electrode of the seventh transistor 107 is connected to the first transistor 10.
The gate electrode of the seventh transistor 107 is connected to the gate electrode of
Connected to. The first electrode of the eighth transistor 108 is connected to the thirteenth wiring 133, the second electrode of the eighth transistor 108 is connected to the twelfth wiring, and the gate electrode of the eighth transistor 108 is the first electrode. Connected to the gate electrode of the transistor 101. The first electrode of the ninth transistor 109 is connected to the fourteenth wiring 134, and the ninth transistor 1
The second electrode of No. 09 is connected to the twelfth wiring 132, and the gate electrode of the ninth transistor 109 is connected to the gate electrode of the second transistor 102.

Note that the twelfth wiring 132 and the third wiring 133 may be referred to as a sixth signal line and a seventh signal line, respectively. Further, the fourteenth wiring may be called a seventh power supply line.

Note that V2 is supplied to the fourteenth wiring 134.

Note that a signal is input to the 13th wiring 133. The signal input to the third wiring is the fifth
A signal similar to the signal input to the wiring 125 can be used.

A signal is output from the twelfth wiring 132. Furthermore, as described in Embodiment 1, a signal is also output from the third wiring 123.

Note that the first wiring 121, the second wiring 122, the fourth wiring 124, the fifth wiring 125, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, A signal input to or a potential supplied to each of the tenth wiring 130 and the eleventh wiring 131 is shown in FIG.
Is the same as.

The flip-flop shown in FIG. 27 is the same as the flip-flop shown in FIG.
Although the case where the 8th and 9th transistors 109 are added is shown in FIG. 4A and FIG.
B), FIG. 4 (C), FIG. 4 (D), FIG. 5 (A), FIG. 5 (B), FIG. 5 (C), FIG. 5 (D), FIG. 7 (A), FIG. 7 (B) The eighth transistor 108 and the ninth transistor 109 may be added to the flip-flops illustrated in FIGS. 7C, 21A, 21B, and 21C.

Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart in FIG. Further, the same parts as those in the timing chart of FIG.

Note that the signal 232 indicates a signal output from the twelfth wiring 132. Further, a signal 221, a signal 225, a signal 226, a potential 241, a potential 242, a signal 222 and a signal 22.
3 is the same as in FIG. However, the signal 221, the signal 225, the signal 226, the potential 241,
As the potential 242, the signal 222, and the signal 223, the same ones as those in FIG. 6, FIG. 31, or FIG. 32 can be used.

As described above, the present embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. That is, the flip-flop in FIG. 27 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and the eighth transistor 108.
And a signal is output from the twelfth wiring 132 by the ninth transistor. Furthermore, the eighth
28 and the ninth transistor are connected in the same manner as the first transistor 101 and the second transistor 102, the twelfth wiring 132 as shown in FIG.
The signal (signal 232) output from is the signal (signal 223) output from the third wiring 123.
) Is almost the same waveform. Here, the signal 232 is the output signal of the flip-flop and the signal 223 is the transfer signal of the flip-flop. However, the signal 223 may be the output signal of the flip-flop and the signal 232 may be the transfer signal of the flip-flop.

Note that the eighth transistor 108 and the ninth transistor 109 have functions similar to those of the first transistor 101 and the second transistor 102, respectively. Further, the eighth transistor 108 and the ninth transistor 109 may be referred to as a buffer portion.

From the above, the flip-flop in FIG. 27 can prevent malfunction even if a large load is connected to the third wiring 132 and the signal 232 is delayed or blunted. The flip-flop of FIG. 27 outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors, so that delay, rounding, etc. of the output signal can affect the operation of the flip-flop. It has no effect.

Further, the flip-flop in FIG. 27 is similar to the flip-flops described in Embodiments 1 and 2 in that the layout area is reduced, the transistor threshold shift is suppressed, the process is simplified, a large-sized display device, and the like. It is possible to obtain merits such as the production of the semiconductor device, the production of a semiconductor device such as a display panel having a long life, and the like.

Note that the operation timing described in Embodiment 2 can be applied to the flip-flop of this embodiment.

A structure and a driving method of the shift register including the flip-flop of this embodiment described above will be described.

The structure of the shift register of this embodiment will be described with reference to FIG. The shift register in FIG. 29 includes n flip-flops (flip-flops 2901_1 to 2901_n).

The connection relationship of the flip-flops in FIG. 29 will be described. The flip-flop shown in FIG. 29 is
i-th stage flip-flop 2901_i (flip-flops 2901_1 to 2901_n
Any one of them is the second wiring 2912, the third wiring 2913, and the fourth wiring 2914.
, The fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_i-1, the eighth wiring 2918_i, the eighth wiring 2918_i + 1, and the ninth wiring 2919_i.
However, the first-stage flip-flop 2901_1 includes the first wiring 2911 and the second wiring 2
912, third wiring 2913, fourth wiring 2914, fifth wiring 2915, and sixth wiring 2
916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. Further, the n-th stage flip-flop 2901_n includes the second wiring 2912,
A third wiring 2913, a fourth wiring 2914, a fifth wiring 2915, a sixth wiring 2916,
The seventh wiring 2917, the eighth wiring 2918_n-1, the eighth wiring 2918_n, and the ninth wiring 2919_n are connected to each other.

The first wiring 2911 is the first wiring 121 of the flip-flop 2901_1 illustrated in FIG.
Connected to. The second wiring 2912 is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the odd-numbered flip-flops and is connected to the even-numbered flip-flops in FIG.
It is connected to the sixth wiring 126 shown in FIG. The third wiring 2913 is connected to the sixth wiring 126 shown in FIG. 27 in the odd-numbered flip-flops and connected to the fifth wiring 125 third wiring 133 shown in FIG. 27 in the even-numbered flip-flops. To be done. The fourth wiring 2914 is
The flip-flops of all stages are connected to the seventh wiring 127 shown in FIG. Fifth wiring 29
Reference numeral 15 is a flip-flop in all stages, which is connected to the eighth wiring 128 shown in FIG. The sixth wiring 2916 is a flip-flop in all stages and is connected to the fourth wiring 124, the ninth wiring 129, the 29th wiring 130, and the eleventh wiring 131 illustrated in FIG. 8th wiring 2918
_I is the second wiring 122 of the flip-flop 2901_i-1 shown in FIG. 27, the third wiring 123 of the flip-flop 2901_i shown in FIG. 27, and the flip-flop 2901i.
+1 is connected to the first wiring 121 shown in FIG. However, the eighth wiring 2918_1 is connected to the third wiring 123 of the flip-flop 2901_1 shown in FIG. 27 and the first wiring 121 of the flip-flop 2901_2 shown in FIG. Furthermore, the eighth wiring 291
8_n is connected to the second wiring 122 of the flip-flop 2901_n−1 illustrated in FIG. 27 and the third wiring 123 of the flip-flop 2901_n illustrated in FIG. 9th wiring 2
The 919_1 to ninth wirings 2919_n are connected to the twelfth wirings 132 of the flip-flops 2901_1 to 2901_n illustrated in FIG. 27, respectively.

Note that the flip-flops 2901_1 to 2901_n, the first wiring 29
11, second wiring 2912, third wiring 2913, fourth wiring 2914, fifth wiring 29
15, a fifth wiring 2916, and a seventh wiring 2907 are the flip-flops 1001_1 to 1001_n, the first wiring 1011, the second wiring 1012, the third wiring 1013, and the fourth wiring 1013 shown in FIG. 10, respectively. They correspond to the wiring 1014, the fifth wiring 1015, the fifth wiring 1016, and the seventh wiring 1007 and are supplied with the same signal or potential.

Next, operation of the shift register shown in FIG. 29 is described with reference to a timing chart in FIG.

30, a signal 3011 input to the first wiring 2911 and an eighth wiring 2918_
Signal 3018_1 output to 1 and the signal 3018_ output to the eighth wiring 2918_i
i, the signal 3018_i + 1 output to the eighth wiring 2918_i + 1, and the eighth wiring 291
The signal 3018_n output to 8_n and the signal 301 output to the ninth wiring 2919_1
9_1, a signal 3019_i output to the ninth wiring 2918_i, and a ninth wiring 2918_i
The signal 3019_i + 1 output to i + 1 and the signal 3018_n output to the ninth wiring 2919_n are illustrated.

As shown in FIG. 30, for example, when the flip-flop 2901_i enters the selection period, the eighth
The H signal is output from the wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i + 1 is in a set period. Then flip-flop 290
1_i is in the reset period, and the L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i + 1 is in the selection period. After that, the flip-flop 2901_i is in the first non-selection period and the eighth wiring 29
The 18_i and the ninth wiring 2919_i are in a floating state and maintain the potential at the L level. At this time, the flip-flop 2901_i + 1 is in a reset period. After that, the flip-flop 2901_i is in the second non-selection period and the L signal is output from the eighth wiring 9918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i + 1
Is the first non-selection period. In this way, the flip-flop 2901_i repeats the first non-selection period and the second non-selection period until the next set period.

From the above, the shift register in FIG. 29 can sequentially output a transfer signal from the eighth wiring 2918_1 to the eighth wiring 2918_n. Further, the shift register in FIG. 29 can output the selection signal sequentially from the ninth wiring 2919_1 to the ninth wiring 2919_n. That is, the shift register in FIG. 29 can scan the ninth wiring 2919_1 to the ninth wiring 2919_n. Therefore, the shift register in FIG. 29 can sufficiently obtain a function as a shift register.

Further, in the shift register in FIG. 29, the ninth wiring 2919_1 to the ninth wiring 2919_n
Even if a large load (such as a resistance and a capacitance) is connected to, it can operate without being affected by the load. Further, in the shift register in FIG. 29, the ninth wiring 2919_1 to the ninth wiring 29
Even if any of 19_n is short-circuited with the power supply line or the signal line, the normal operation can be continued. Therefore, the shift register in FIG. 29 can have improved driving capability. This is because the shift register in FIG. 29 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

Further, by applying the flip-flop described in this embodiment to the shift register in FIG. 29, a layout area is reduced, a threshold shift of a transistor is suppressed, a process is simplified,
Advantages such as manufacturing of semiconductor devices such as large-sized display devices and manufacturing of semiconductor devices such as long-life display panels can be obtained.

Note that the configuration is not limited to that of FIG. 29 as long as the same operation as that of FIG. 29 is performed. For example,
By freely combining with the shift registers of FIGS. 13, 14, 15, and 17, the same advantages as those of FIGS. 13, 14, 15, and 17 can be obtained.

The structure and driving method of the above-described display device including the shift register of this embodiment will be described. However, the display device of this embodiment may include at least the flip-flop of this embodiment.

As the display device of this embodiment, the display device of FIGS. 8, 18, 16, 20, and 22 can be used. Therefore, in the display device of this embodiment, the layout area can be reduced by applying the shift register of this embodiment as the scan line driver circuit. Further, the display device of this embodiment can suppress the threshold shift of the transistor. Further, the display device of this embodiment can have a simplified process. Further, the display device of this embodiment can have a larger size or higher definition. Furthermore, the display device of this embodiment can have a long life. In particular, when the shift register of this embodiment is applied to the display device in FIGS. 8, 16, and 22 as a scan line driver circuit, a larger size or higher definition can be achieved. Further, the display device in FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can save power. Further, the display device in FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can suppress heat generation of the IC. Further, the display device in FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied is I
Power saving of C can be achieved.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined and combined. Further, in each of the drawings described so far, more drawings can be formed by combining each part with another part.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example in which the contents described in the other embodiments are embodied, an example in which the contents are slightly modified, an example in which a part is changed, an example in the case of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 4)
In this embodiment, a case where a P-channel transistor is used as a transistor included in the flip-flop of this specification will be described. Further, a structure and a driving method of a driver circuit including the flip-flop and a display device including the driver circuit will be described.

The flip-flop of this embodiment will be described in the case where the polarity of the transistor included in the flip-flop in FIG. 1 is a P-channel type. However, FIG. 4 (A), FIG. 4 (B), and FIG.
(C), FIG. 4 (D), FIG. 5 (A), FIG. 5 (B), FIG. 5 (C), FIG. 5 (D), FIG. 7 (A),
The polarity of the transistor included in the flip-flop illustrated in FIG. 7B, FIG. 7C, FIG. 21A, FIG. 21B, FIG. 21C, or FIG. 27 may be a P-channel type. it can. Further, the flip-flop of this embodiment can be implemented by being freely combined with the description of Embodiments 1 to 3.

The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. Figure 2
The flip-flop shown in FIG. 3 includes a first transistor 2301 and a second transistor 230.
2, third transistor 2303, fourth transistor 2304, fifth transistor 2
305, a sixth transistor 2306, and a seventh transistor 2307. In this embodiment, the first transistor 2301, the second transistor 2302, the third transistor 2303, the fourth transistor 2304, the fifth transistor 2305, and the sixth transistor
The second transistor 2306 and the seventh transistor 2307 are P-channel transistors, and the absolute value of the voltage between the gate and the source (| Vgs |) is the absolute value of the threshold voltage (| Vt).
When h |) is exceeded (when Vgs is lower than Vth), the conductive state is assumed.

The connection relationship of the flip-flops in FIG. 23 will be described. A first electrode of the first transistor 2301 (one of a source electrode and a drain electrode) is connected to the fifth wiring 2325, and a second electrode of the first transistor 2301 (the other of the source electrode and the drain electrode) is a second electrode. 3 wiring 2323. The first electrode of the second transistor 2302 is the fourth wiring 23.
24, and the second electrode of the second transistor 2302 is connected to the third wiring 2323. The first electrode of the third transistor 2303 is connected to the sixth wiring 2326, the second electrode of the third transistor 2303 is connected to the gate electrode of the second transistor 2302, and the gate of the third transistor 2303 is connected. The electrode is connected to the seventh wiring 2327.
The first electrode of the fourth transistor 2304 is connected to the ninth wiring 2329, the second electrode of the fourth transistor 2304 is connected to the gate electrode of the second transistor 2302,
The gate electrode of the fourth transistor 2304 is connected to the gate electrode of the first transistor 2301. The first electrode of the fifth transistor 2305 is connected to the eighth wiring 2328, the second electrode of the fifth transistor 2305 is connected to the gate electrode of the first transistor 2301, and the gate of the fifth transistor 2305 is connected. The electrode is connected to the first wiring 2321. The first electrode of the sixth transistor 2306 is connected to the tenth wiring 2330,
The second electrode of the transistor 2306 is connected to the gate electrode of the first transistor 2301, and the gate electrode of the sixth transistor 2306 is connected to the gate electrode of the second transistor 2302. The first electrode of the seventh transistor 2307 is connected to the eleventh wiring 2331, the second electrode of the seventh transistor 2307 is connected to the gate electrode of the first transistor 2301, and the gate of the seventh transistor 2307 is connected. The electrode is connected to the second wiring 2322.

Note that the gate electrode of the first transistor 2301, the gate electrode of the fourth transistor 2304, the second electrode of the fifth transistor 2305, the second electrode of the sixth transistor 2306, and the second electrode of the seventh transistor 2307. A node 2341 is defined as a connection point of the electrode of.
Further, the gate electrode of the second transistor 2302 and the second electrode of the third transistor 2303
A node 2342 is a connection portion of the electrode of the second transistor, the second electrode of the fourth transistor 2304, and the gate electrode of the sixth transistor 2306.

Fourth wiring 2324, ninth wiring 2329, tenth wiring 2330, and eleventh wiring 23
31 may be connected to each other or may be the same wiring. Furthermore, the seventh wiring 23
The 27 and the eighth wiring 2328 may be connected to each other or may be the same wiring.

Note that the first transistor 2301 to the seventh transistor 2307 respectively correspond to the first transistor 101 to the seventh transistor 107 in FIG. 1 and have similar functions.

Note that the first wiring 2321 to the eleventh wiring 2331 are respectively the first wiring 121 in FIG.
~ Corresponding to the eleventh wiring 131. However, the first wiring 2321 to the eleventh wiring 23
The signal input to 31, the supplied potential, or the output signal is the first wiring 121 in FIG.
The H level and the L level are inverted as compared with the signal input to the eleventh wiring 131, the supplied potential, or the output signal.

Note that the potential of V2 is supplied to the seventh wiring 2327 and the eighth wiring 2328,
Fourth wiring 2324, ninth wiring 2329, tenth wiring 2330, and eleventh wiring 23
The potential of V1 is supplied to each 31.

Note that the first wiring 2321, the second wiring 2322, the fifth wiring 2325, and the sixth wiring 2
A signal is input to each of 326. The signal input to the first wiring 2321 is a start signal, the signal input to the second wiring 2322 is a reset signal, and the signal input to the fifth wiring 2325 is a first clock signal. The signal input to the sixth wiring 2326 is the second clock signal. Further, a first wiring 2321 and a second wiring 2322
The signals input to the fifth wiring 6325 and the sixth wiring 2326 are H signal potential V1 (hereinafter also referred to as H level) and L signal potential V2 (hereinafter also referred to as L level).
Is a digital signal.

Note that the first wiring 2321, the second wiring 2322, the second wiring 2322 to the eleventh wiring 2
Various signals, currents, or voltages may be input to 331.

Note that a signal is output from the third wiring 2323. The signal output from the third wiring 2323 is an output signal of the flip-flop of each stage and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop of the next stage. Further, the third wiring 2323
The signal output from is a digital signal in which the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level).

Next, the operation of the flip-flop shown in FIG. 23 will be described with reference to the timing chart of FIG. Further, the timing chart of FIG. 24 will be described by dividing it into a selection period and a non-selection period. Further, the non-selection period will be described by being divided into a first non-selection period, a second non-selection period, a set period, and a reset period. Here, as shown in the timing chart of FIG. 24, each period includes a set period, a selection period, a reset period, a first non-selection period, a second non-selection period, a first non-selection period, and a second non-selection period. They are arranged in the order of non-selected period. That is, the set period,
During the operation period excluding the selection period and the reset period, the first non-selection period and the second non-selection period are sequentially repeated. Further, the period before the set period is the second non-selection period.

The timing chart of FIG. 24 is the same as the timing chart of FIG. 2 with the H level and L level inverted.

Note that the flip-flop of this embodiment is not limited to the one in which the H level and the L level in FIG. 2 are inverted, but the one in which the H level and the L level in the timing charts in FIGS. You may use what was done.

Note that in FIG. 24, a signal 2421, a signal 2425, a signal 2426, a potential 2441, a potential 2442, a signal 2422, and a signal 2423 are signals input to the first wiring 2321 and a fifth wiring 2325, respectively. , A signal input to the sixth wiring 2326,
A potential of the node 2341, a potential of the node 2342, a signal input to the second wiring 2322,
A signal output from the third wiring 2323 is shown.

Note that the signal 2421, the signal 2425, the signal 2426, the potential 2441, the potential 2442, the signal 2422, and the signal 223 correspond to the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 in FIG. 2, respectively. is doing. However, as described above, the H level and the L level are inverted.

First, in the set period illustrated in FIG. 24A, the fifth transistor 2305 is turned on because the signal 2421 is at L level, and the seventh transistor 230 is because the signal 2422 is at H level.
7 turns off. The potential of the node 2341 at this time is the second potential of the fifth transistor 2305.
Becomes the source electrode, and the potential of the eighth wiring 2328 and the fifth transistor 2305
Is the sum of the absolute value of the threshold voltage of V2 + | Vth (2305) | (Vth (23
05): the threshold voltage of the fifth transistor 2305). Therefore, the first transistor 2301 and the fourth transistor 2304 are turned on, and the fifth transistor 2305 is turned off. At this time, the potential of the node 2342 (potential 2442) is the third transistor 2
It is determined by the resistance ratio (L / W and applied voltage) between 303 and the fourth transistor 2304, and becomes V1-θ (θ: any positive number). Further, θ <| Vth (2302) | (Vt
h (2302): threshold voltage of the second transistor 2302) and θ <| Vth (23
06) | (threshold voltage of sixth transistor 2306). That is, the ninth wiring 2
The potential difference (V1−V2) between the potential (V1) of 329 and the potential (V2) of the sixth wiring 2326 is divided by the third transistor 2303 and the fourth transistor 2304. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned off. As described above, in the set period, the third wiring 2323 is the fifth wiring 2325 to which the H signal is input.
Therefore, the potential of the third wiring 2323 becomes V1. Therefore, the H signal is output from the third wiring 2323. Further, the node 2341 has the potential V2 + | Vth (23
05) Floating state while maintaining at |.

In the selection period shown in FIG. 24B), the signal 2421 is at the H level and the fifth transistor 2
The seventh transistor 2307 remains off because 305 is off and the signal 2422 remains at H level. At this time, the node 2341 maintains the potential at V2 + | Vth (2305) |. Therefore, the first transistor 2301 and the fourth transistor 2304 remain on. At this time, the potential of the node 2342 becomes V1 because the sixth wiring 2326 is at the H level. Therefore, the second transistor 2302 and the sixth transistor 23
06 remains off. Here, since the L signal is input to the fifth wiring 2325,
The potential of the wiring 2323 starts to decrease. Then, the potential of the node 2341 drops from V2 + | Vth (2305) | by the bootstrap operation, and V2- | Vth (230
1) | −γ (Vth (2301): threshold voltage of the first transistor 2301, γ: any positive number). Therefore, the potential of the third wiring 2323 becomes equal to that of the fifth wiring 2325, and thus becomes V2. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode of the first transistor 2301 and the second electrode.
Thus, in the selection period, the third wiring 2323 is the fifth wiring 2 to which the L signal is input.
Since it is electrically connected to 325, the potential of the third wiring 2323 becomes V2. Therefore, the L signal is output from the third wiring 2323.

In the reset period illustrated in FIG. 24C, the signal 2421 remains at H level, the fifth transistor 2305 remains off, the signal 2422 becomes L level, and the seventh transistor 2307 is turned on. The potential of the node 2341 at this time is the potential of the eleventh wiring (V
Since 1) is supplied via the seventh transistor 2307, it becomes V1. Therefore, the first transistor 2301 and the fourth transistor 2304 are turned off. Node 2 at this time
The potential of 342 is the sixth electrode when the second electrode of the third transistor 2303 serves as a source electrode.
V2 + | Vth (2303) | (Vth (2303): threshold voltage of the third transistor 2303), because it is a value obtained by subtracting the threshold voltage of the third transistor 2303 from the potential (V2) of the wiring 2326 of Becomes Therefore, the second transistor 2302 and the sixth transistor 2306 are turned on. Thus, in the reset period, the third wiring 2323 is V
1 is electrically connected to the fourth wiring 2324 which is supplied, the potential of the third wiring 2323 is V
It becomes 1. Therefore, the H signal is output from the third wiring 2323.

In the first non-selection period illustrated in FIG. 24D, the signal 2421 remains at H level, so that the fifth transistor 2305 remains off, the signal 2422 becomes H level, and the seventh transistor 2307 is off. To do. At this time, the potential of the node 2342 is 6th wiring 2326.
Since the H signal is input to V, it becomes V1. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned off. At this time, the node 2341 is in a floating state and thus maintains the potential at V1. Therefore, the first transistor 2301 and the fourth transistor 23
04 remains off. As described above, in the first non-selection period, the third wiring 2323 is in a floating state, so that the potential of the third wiring 2323 is kept at V1.

In the second non-selection period illustrated in FIG. 24E, the signal 2421 remains at H level, the fifth transistor 2305 remains off, and the signal 2422 remains at H level, so that the seventh transistor 2307 is off. It remains. At this time, the potential of the node 2342 is V2 + | V because the L signal is input to the sixth wiring 2326 and the transistor 2304 is off.
th (2303) | Therefore, the second transistor 2302 and the sixth transistor 2306 are turned on. At this time, the potential of the node 2341 remains V1 because the potential (V1) of the tenth wiring 2330 is supplied through the sixth transistor 2306. Therefore, the first transistor 2301 and the fourth transistor 2304 remain off. As described above, in the second non-selection period, the third wiring 2323 is supplied with V1 at the fourth level.
Since the second wiring 2324 is electrically connected to the second wiring 2324, the potential of the third wiring 2323 remains V1. Therefore, the H signal is output from the third wiring 2323.

From the above, the flip-flop in FIG. 23 uses the bootstrap operation in the selection period to set the potential of the node 2341 lower than V2- | Vth (2301) |, so that the potential of the third wiring 2323 is reduced. Can be V2. Further, in the flip-flop of FIG. 23, the bootstrap operation is performed by using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 2301 to reduce the layout area and the device. It is possible to obtain advantages such as a reduction in the number.

Further, in the flip-flop in FIG. 23, the second transistor 2302 and the sixth transistor 2306 are turned on only in the second non-selection period, so that the second transistor 230
The threshold voltage shifts of the second and sixth transistors 2306 can be suppressed.

Note that the flip-flop in FIG. 23 supplies V2 to the gate electrode of the third transistor 2303 and inputs the second clock signal to the first electrode, so that the third transistor 2303
The shift of the threshold voltage of 3 can also be suppressed.

Further, in the flip-flop in FIG. 23, the first transistor 2301, the fourth transistor 2304, the fifth transistor 2305, and the seventh transistor 2307 do not turn on in the first non-selection period and the second non-selection period. A first transistor 2301, a fourth transistor 2304, a fifth transistor 2305, and a seventh transistor 230.
7 can be suppressed.

Further, in the flip-flop of FIG. 23, even when the potential of the node 2341 and the potential of the third wiring 2323 vary in the first non-selection period, the node 23 in the second non-selection period is next.
By supplying V1 to the signal line 41 and the third wiring 2323, the potential of the node 2341 and the potential of the third wiring 2323 can be reset to V1. Therefore, the flip-flop in FIG. 23 can suppress a malfunction caused by a change in the potentials of the node 2341 and the third wiring 2323 due to the node 2341 and the wiring 2323 being in a floating state.

Further, since the flip-flop in FIG. 23 can suppress the threshold voltage shift of the transistor, malfunction due to the threshold voltage shift of the transistor can be suppressed.

Further, the flip-flop in FIG. 23 is characterized in that the first transistor 2301 to the seventh transistor 2307 are all P-channel transistors. Therefore, the flip-flop in FIG. 23 can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

Note that the arrangement and the number of each transistor are the same as those in FIG.
It is not limited to 4. Therefore, a transistor, another element (a resistance element, a capacitance element, or the like), a diode, a switch, various logic circuits, or the like may be newly arranged in the flip-flop in FIG.

Note that the shift register of this embodiment can be implemented by freely combining the flip-flop of this embodiment with the shift register described in any of Embodiments 1 to 3. For example, the shift register of this embodiment includes the flip-flop of this embodiment in FIG.
, FIG. 13, FIG. 14, FIG. 15, FIG. 17, FIG. 29, FIG. 33, and FIG. 34 can be freely combined and implemented. However, in the shift register of this embodiment mode, the H level and the L level are inverted as compared with the shift registers described in Embodiment Modes 1 to 3.

Note that the display device of this embodiment can be implemented by freely combining the shift register of this embodiment with the display device described in any of Embodiments 1 to 3. For example, the display device of this embodiment can be implemented by being freely combined with the display devices of FIGS. 8, 18, 16, 20, and 22. However, in the display device of this embodiment, the H level and the L level are inverted as compared with the display devices described in Embodiments 1 to 3.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined. Furthermore, in each of the figures described so far,
More figures can be constructed by combining different parts.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example in which the contents described in the other embodiments are embodied, an example in which the contents are slightly modified, an example in which a part is changed, an example in the case of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 5)
In this embodiment, a signal line driver circuit included in the display device described in any of Embodiments 1 to 4 is described.

The signal line driver circuit in FIG. 37 will be described. The signal line drive circuit shown in FIG.
C5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b, and a third switch 5603c.

The driver IC 5601 includes a first wiring 5611, a second wiring 5612, and a third wiring 5613.
And wirings 5621_1 to 5621_M. Then, the switch group 5602_1 to
Each of 5602_M includes a first wiring 5611, a second wiring 5612, and a third wiring 561.
3 and switch groups 5602_1 to 5602_M respectively corresponding to the wirings 5621_1 to 5621_1
621_M. Then, each of the wirings 5621_1 to 5621_M includes the first switch 5603a, the second switch 5603b, and the third switch 563.
It is connected to three signal lines via 03c. For example, the wiring 5621_J in the J-th column (any one of the wiring 5621_1 to the wiring 5621_M) has a first switch 5603a, a second switch 5603b, and a third switch 5603c included in the switch group 5602_J.
Via the signal line Sj-1, the signal line Sj, and the signal line Sj + 1.

Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

Note that the driver IC 5601 is preferably formed over a single crystal substrate or a glass substrate using a polycrystalline semiconductor. Further, the switch group 5602 is preferably formed over the same substrate as the pixel portion described in any of Embodiments 1 to 4. Therefore,
The driver IC 5601 and the switch group 5602 may be connected to each other via an FPC or the like.

Next, the operation of the signal line driver circuit illustrated in FIG. 37 will be described with reference to the timing chart in FIG. Note that the timing chart of FIG. 38 shows a timing chart when the i-th scanning line Gi is selected. Further, the selection period of the i-th scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driver circuit in FIG. 37 operates similarly to FIG. 38 even when a scan line in another row is selected.

Note that in the timing chart of FIG. 38, the wiring 5621_J in the J-th column is the first switch 56.
03a, the second switch 5603b and the third switch 5603c, the signal line Sj
-1, the signal line Sj, and the signal line Sj + 1 are connected.

Note that in the timing chart of FIG. 38, the timing at which the i-th scanning line Gi is selected, the timing 5703a at which the first switch 5603a is turned on and off, and the timing at which the second switch 5603 is turned on and off.
b shows an on / off timing 5703b, a third switch 5603c on / off timing 5703c, and a signal 5721_J input to the wiring 5621_J in the Jth column.

Note that different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj−1, and a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj. The wiring 5621 is formed in the third sub-selection period T3.
The video signal input to _J is input to the signal line Sj + 1. Further, in the selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_J are Dataj-1, Dataj, and Dataj + 1, respectively.

As shown in FIG. 38, the first switch 5603a is turned on and the second switch 5603b and the third switch 5603c are turned off in the first sub-selection period T1. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on and the first switch 5603a and the third switch 5603c are turned off. At this time,
Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on,
The first switch 5603a and the second switch 5603b are turned off. At this time, the wiring 5
Dataj + 1 input to 621_J is sent to the signal line S via the third switch 5603c.
It is input to j + 1.

From the above, the signal line driver circuit in FIG. 37 can input a video signal from one wiring 5621 to three signal lines during one gate selection period by dividing one gate selection period into three. it can. Therefore, the signal line driver circuit in FIG. 37 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1/3 of the number of signal lines. By reducing the number of connections to about 1/3, the signal line driver circuit in FIG. 37 can improve reliability, yield, and the like.

Note that by applying the signal line driver circuit of this embodiment to the display device described in any of Embodiments 1 to 4, the number of connections between the substrate in which the pixel portion is formed and the external substrate can be further reduced. .. Therefore, the display device of this embodiment can have improved reliability. Further, the display device of this embodiment can have high yield.

Next, the first switch 5603a, the second switch 5603b, and the third switch 560
A case where an N-channel type transistor is applied to 3c will be described with reference to FIG.
Note that parts similar to those in FIG. 37 are denoted by common reference numerals, and detailed description of the same parts or parts having similar functions is omitted.

The first transistor 5903a corresponds to the first switch 5603a, the second transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the third switch 5603c.

For example, in the case of the switch group 5602_J, in the first transistor 5903a, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj−1, and the gate electrode is connected to the first wiring 5611. To be done. In the second transistor 5903b, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the second wiring 5612. In the third transistor 5903c, the first electrode is the wiring 5621_.
J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is the third wiring 561.
3 is connected.

Note that the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as a switching transistor. Further, a first transistor 5903a, a second transistor 5903b, and a third transistor 5903.
c is turned on when the signal input to the gate electrode is at the H level, and is turned off when the signal input to the gate electrode is at the L level.

Note that the first switch 5603a, the second switch 5603b, and the third switch 560 are included.
By using an N-channel transistor as 3c, amorphous silicon can be used as a semiconductor layer of the transistor, so that the manufacturing process can be simplified, manufacturing cost can be reduced, and yield can be improved. Because you can. Furthermore, it is also possible to manufacture a semiconductor device such as a large-sized display panel. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon for the semiconductor layer of the transistor.

In the signal line driver circuit in FIG. 39, the first transistor 5903a and the second transistor 59
03b and the case where an N-channel type transistor is used as the third transistor 5903c, the first transistor 5903a, the second transistor 5903b,
A P-channel transistor may be used as the third transistor 5903c. At this time, the transistor is turned on when the signal input to the gate electrode is at the L level and is turned off when the signal input to the gate electrode is at the H level.

Note that, as shown in FIG. 37, if one gate selection period is divided into a plurality of sub-selection periods and a video signal can be input to one of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods, the switch There is no limitation on the arrangement, number and driving method.

For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, when one gate selection period is divided into four or more sub selection periods, one sub selection period becomes shorter. Therefore, it is desirable that one gate selection period is divided into two or three sub-selection periods.

As another example, as shown in the timing chart of FIG. 40, one selection period is divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. May be. Further, in the timing chart of FIG. 40, the timing at which the i-th row scanning line Gi is selected, the timing 5803a at which the first switch 5603a is turned on and off, and the second timing
ON / OFF timing 5803b of the switch 5603b, ON / OFF timing 5803c of the third switch 5603c, and the signal 58 input to the wiring 5621_J in the Jth column.
21_J is shown. As shown in FIG. 40, the first switch 5603a, the second switch 5603b, and the third switch 5603c are turned on in the precharge period Tp.
At this time, the precharge voltage Vp input to the wiring 5621_J is the first switch 560.
3a, the second switch 5603b, and the third switch 5603c, to be input to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1, respectively. In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 563 are turned on.
03c turns off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5
603c turns off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third
Switch 5603c is turned on, and the first switch 5603a and the second switch 5603 are turned on.
b turns off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third switch 5603c.

From the above, the signal line driver circuit in FIG. 37 to which the timing chart in FIG. 40 is applied can precharge the signal line by providing the precharge selection period before the sub selection period; Can be written at high speed. Note that parts similar to those in FIG. 38 are denoted by common reference numerals, and detailed description of the same parts or parts having similar functions is omitted.

Also in FIG. 41, as shown in FIG. 37, one gate selection period is divided into a plurality of sub-selection periods,
A video signal can be input to one of a plurality of signal lines from one wiring in each of a plurality of sub-selection periods. Note that FIG. 41 illustrates only the switch group 6022_J in the Jth column in the signal line driver circuit. The switch group 6022_J includes the first transistor 60
01, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 6006. A first transistor 6001, a second transistor 6002, and a third transistor 6003
, A fourth transistor 6004, a fifth transistor 6005, a sixth transistor 60
Reference numeral 06 is an N-channel type transistor. The switch group 6022_J includes the first wiring 60.
11, second wiring 6012, third wiring 6013, fourth wiring 6014, fifth wiring 60
15, sixth wiring 6016, wiring 5621_J, signal line Sj-1, signal line Sj, signal line S
connected to j + 1.

A first electrode of the first transistor 6001 is connected to the wiring 5621_J, a second electrode of the first transistor 6001 is connected to the signal line Sj−1, and a gate electrode of the first transistor 6001 is connected to the first wiring 6011. A first electrode of the second transistor 6002 is connected to the wiring 5621_J, and a second electrode of the second transistor 6002 is connected to the signal line Sj.
−1, and the gate electrode is connected to the second wiring 6012. Third transistor 6
The first electrode of 003 is connected to the wiring 5621_J, the second electrode of 003 is connected to the signal line Sj, and the gate electrode thereof is connected to the third wiring 6013. A first electrode of the fourth transistor 6004 is connected to the wiring 5621_J, a second electrode of the fourth transistor 6004 is connected to the signal line Sj, and a gate electrode of the fourth transistor 6004 is connected to the fourth wiring 6014. The first electrode of the fifth transistor 6005 is the wiring 56
21_J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is connected to the fifth wiring 6015. A first electrode of the sixth transistor 6006 is connected to the wiring 5621_J, a second electrode of the sixth transistor 6006 is connected to the signal line Sj + 1, and a gate electrode of the sixth transistor 6006 is connected to the sixth wiring 6016.

Note that the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as a switching transistor. Further, the first transistor 6001, the second transistor 6002, the third transistor 6003, and the fourth transistor 6003.
The transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 are turned on when the signal input to the gate electrode is at H level, and turned off when the signal input to the gate electrode is at L level. ..

Note that the first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. The third wiring 6013 and the fourth wiring 6014 correspond to the second wiring 5912 in FIG. The fifth wiring 6015 and the sixth wiring 6016 are the third wiring 5913 in FIG.
Equivalent to. Note that the first transistor 6001 and the second transistor 6002 correspond to the first transistor 5903a in FIG. Third transistor 6003 and fourth
Transistor 6004 corresponds to the second transistor 5903b in FIG. The fifth transistor 6005 and the sixth transistor 6006 correspond to the third transistor 5903c in FIG.

41, the first transistor 600 in the first sub-selection period T1 shown in FIG.
Either the first transistor 6002 or the second transistor 6002 is turned on. In the second sub-selection period T2, either the third transistor 6003 or the fourth transistor 6004 is turned on. In the third sub-selection period T3, either the fifth transistor 6005 or the sixth transistor 6006 is turned on. Furthermore, the first transistor 6001, the third transistor 6003, and the fifth transistor 60 in the precharge period Tp illustrated in FIG.
05, or any one of the second transistor 6002, the fourth transistor 6004, and the sixth transistor 6006 is turned on.

Therefore, in FIG. 41, since the on-time of each transistor can be shortened, deterioration of characteristics of each transistor can be suppressed. This is because, for example, in the first sub-selection period T1 illustrated in FIG. 38, the first transistor 6001 or the second transistor 60
This is because the video signal can be input to the signal line Sj-1 if either of the two is turned on. Note that a video signal can be input to the signal line Sj-1 at high speed by turning on the first transistor 6001 and the second transistor 6002 at the same time in the first sub-selection period T1 illustrated in FIG. 38, for example. it can.

Note that in FIG. 41, the case where two transistors are connected in parallel between the wiring 5621 and the signal line is described. However, the present invention is not limited to this.
You may connect in parallel between 21 and a signal wire. By doing so, the characteristic deterioration of each transistor can be further suppressed.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined. Furthermore, in each of the figures described so far,
More figures can be constructed by combining different parts.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example in which the contents described in the other embodiments are embodied, an example in which the contents are slightly modified, an example in which a part is changed, an example in the case of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 6)
In this embodiment mode, a structure for preventing a defect due to electrostatic breakdown of the display device described in any of Embodiment Modes 1 to 4 will be described.

Note that electrostatic breakdown means that when positive or negative electric charge accumulated in a human body or an object touches a semiconductor device, it is instantly discharged through an input / output terminal of the device, resulting in a large current inside the device. Destruction caused by flowing.

FIG. 42A shows a structure for preventing electrostatic discharge damage on a scan line by a protection diode. FIG. 42A shows a structure in which a protective diode is provided between the wiring 6111 and the scan line. Although not shown, a plurality of pixels are connected to the i-th scanning line Gi. Note that the transistor 6101 is used as the protective diode. Note that the transistor 61
Reference numeral 01 is an N-channel type transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6101 may be similar to that of the transistor included in the scan line driver circuit or the pixel.

Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series.

In the transistor 6101, the first electrode is connected to the i-th scanning line Gi, the second electrode is connected to the wiring 6111, and the gate electrode is connected to the i-th scanning line Gi.

The operation of FIG. 42A will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the i-th scan line Gi. When the positive or negative charge is not discharged to the i-th scan line Gi, the potential of the i-th scan line Gi is at the H level or the L level, so that the transistor 6101 is off. On the other hand, when the negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi is instantaneously lowered. At this time, the potential of the scan line Gi in the i-th row is changed from the potential of the wiring 6111 to the transistor 61.
When it becomes lower than the value obtained by subtracting the threshold voltage of 01, the transistor 6101 is turned on, and current flows through the transistor 6101 to the wiring 6111. Therefore, with the structure shown in FIG. 42A, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that FIG. 42B shows a structure for preventing electrostatic discharge damage when positive charge is discharged to the i-th row scan line Gi. A transistor 6102 which functions as a protective diode is provided between the scan line and the wiring 6112. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series. Note that the transistor 6102 is an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6102 may be similar to that of the transistor included in the scan line driver circuit or the pixel. A first electrode of the transistor 6102 is connected to the scan line Gi in the i-th row,
Is connected to the wiring 6112, and the gate electrode is connected to the wiring 6112. Note that a potential higher than the H level of the signal input to the i-th scan line Gi is input to the wiring 6112. Therefore, the transistor 6102 is off when electric charge is not discharged to the i-th scan line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi instantaneously rises. At this time, the scanning line Gi of the i-th row
Potential of the wiring 6112 becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on and current flows through the transistor 6102.
It flows to 12. Therefore, with the structure shown in FIG. 42B, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that, as shown in FIG. 42C, a structure in which FIGS. 42A and 42B are combined is used, so that even when positive charge is discharged to the i-th scan line Gi. Even when negative charges are discharged to the i-th row scanning line Gi, electrostatic breakdown of the pixel can be prevented. Note that FIG.
2 (A) and 2 (B) are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions will be omitted.

FIG. 43A illustrates a structure in which the transistor 6201 which functions as a protective diode is connected between a scan line and a storage capacitor line. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series. Note that the transistor 6201 is an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6201 may be similar to that of the transistor included in the scan line driver circuit or the pixel. Note that the wiring 6211 functions as a storage capacitor line. Transistor 6201
The first electrode of is connected to the i-th scanning line Gi and the second electrode is connected to the wiring 6211,
The gate electrode is connected to the i-th row scanning line Gi. Note that a potential lower than the L level of the signal input to the i-th scan line Gi is input to the wiring 6211. Therefore, the transistor 6201 is off when electric charge is not discharged to the i-th scan line Gi. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the i-th scanning line Gi
The electric potential of drops momentarily. At this time, when the potential of the i-th row scan line Gi becomes lower than the value of the potential of the wiring 6211 minus the threshold voltage of the transistor 6201, the transistor 62
01 is turned on, and current flows to the wiring 6211 through the transistor 6201. Therefore, with the structure shown in FIG. 43A, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented. Further, in the structure shown in FIG. 43A, since the storage capacitor line is used as a wiring for releasing charges, it is not necessary to add a new wiring.

Note that FIG. 43B shows a structure for preventing electrostatic discharge damage when positive charges are discharged to the i-th row scan line Gi. Here, a potential higher than the H level of the signal input to the i-th scan line Gi is input to the wiring 6211. Therefore, the transistor 6201
Is off when the charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi instantaneously rises. At this time, the potential of the scan line Gi in the i-th row is equal to the potential of the wiring 6211 and the transistor 62.
When it becomes higher than the sum of the threshold voltage of 01 and the threshold voltage of 01, the transistor 6201 is turned on and current flows through the transistor 6201 to the wiring 6211. Therefore, with the structure shown in FIG. 43B, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented. Furthermore, in the structure shown in FIG. 43B, since the storage capacitor line is used as a wiring for releasing charges, it is not necessary to add a new wiring. 43 (
Components similar to those in B) are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions will be omitted.

Next, FIG. 44 shows a configuration for preventing electrostatic breakdown that occurs in the signal line by the protection diode.
It shows in (A). FIG. 44A shows a structure in which a protective diode is provided between the wiring 6411 and the signal line. Although not shown, a plurality of pixels are connected to the signal line Sj in the jth column. Note that a transistor 6401 is used as the protective diode. Note that the transistor 6401 is an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6401 may be similar to that of the transistor included in the signal line driver circuit or the pixel.

Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series.

In the transistor 6401, the first electrode is connected to the j-th signal line Sj, the second electrode is connected to the wiring 6411, and the gate electrode is connected to the j-th signal line Sj.

The operation of FIG. 44A will be described. A certain potential is input to the wiring 6411, and the potential is also a potential at which the minimum value of the video signal input to the signal line Sj in the j-th row is low. When the positive or negative charge is not discharged to the j-th signal line Sj, the potential of the j-th signal line Sj is the same as that of the video signal, so that the transistor 6401 is off. On the other hand, when negative charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj instantaneously drops.
At this time, when the potential of the signal line Sj in the j-th row becomes lower than the value of the potential of the wiring 6411 minus the threshold voltage of the transistor 6401, the transistor 6401 is turned on and current flows through the transistor 6401 through the wiring 6411. Flow to. Therefore, with the structure shown in FIG. 44A, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that FIG. 44B shows a structure for preventing electrostatic breakdown when positive charges are discharged to the signal line Sj in the j-th row. A transistor 6402 which functions as a protective diode is provided between the scan line and the wiring 6412. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, may be arranged in parallel, or may be arranged in series. Note that the transistor 6402 is an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6402 may be similar to that of the transistor included in the scan line driver circuit or the pixel. A first electrode of the transistor 6402 is connected to the signal line Sj in the j-th row,
Is connected to the wiring 6412, and the gate electrode is connected to the wiring 6412. Note that a potential higher than the maximum value of the video signal input to the j-th signal line Sj is input to the wiring 6412. Therefore, the transistor 6402 is off when electric charge is not discharged to the j-th signal line Sj. On the other hand, when positive charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj instantaneously rises. At this time, when the potential of the signal line Sj in the j-th row becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on and current flows to the wiring 6412 through the transistor 6402. Flowing. Therefore, with the structure shown in FIG. 44B, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that, as shown in FIG. 44C, by combining FIG. 44A and FIG. 44B, even when positive charge is discharged to the j-th signal line Sj. Even when negative charges are discharged to the signal line Sj on the j-th row, electrostatic breakdown of the pixel can be prevented. Note that FIG.
4A and 4B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

In this embodiment, the structure for preventing electrostatic discharge damage of the pixels connected to the scan line and the signal line has been described. However, the configuration of this embodiment is not limited to the prevention of electrostatic breakdown of pixels connected to the scanning lines and the signal lines. For example, in the case of applying this embodiment to the scan line driver circuit described in any of Embodiments 1 to 4 and the wiring to which a signal or a potential is connected, which is connected to the signal line driver circuit, the scan line driver circuit is used. Also, electrostatic breakdown of the signal line drive circuit can be prevented.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined. Furthermore, in each of the figures described so far,
More figures can be constructed by combining different parts.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example in which the contents described in the other embodiments are embodied, an example in which the contents are slightly modified, an example in which a part is changed, an example in the case of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 7)
In this embodiment mode, a new structure of a display device which can be applied to the display device described in any of Embodiment Modes 1 to 4 will be described.

FIG. 45A illustrates a structure in which a diode-connected transistor is provided between one scan line and another scan line. In FIG. 45A, a diode-connected transistor 6301a is provided between the i−1th scanning line Gi−1 and the ith scanning line Gi, and the ith scanning line Gi and the i + 1th scanning line Gi are arranged. Transistor 63 diode-connected to the eye scanning line Gi + 1
The configuration when 01b is arranged is shown. Note that the transistors 6301a and 6301b are N-channel transistors. However, P-channel transistors may be used, and the polarities of the transistors 6301a and 6301b may be similar to those of the transistors included in the scan line driver circuit or the pixel.

Note that in FIG. 45A, the scan line Gi−1 of the i−1th row, the scan line Gi of the ith row, and the scan line Gi + 1 of the i + 1th row are shown as representatives, but other scan lines are also included. Similarly, diode-connected transistors are arranged.

A first electrode of the transistor 6301a is connected to the i-th scanning line Gi and a second electrode of the transistor 6301a is i
The gate electrode is connected to the scanning line Gi-1 of the −1th row and the gate electrode is connected to the scanning line Gi-1 of the Gi−1th row. A first electrode of the transistor 6301b is connected to the i + 1-th scanning line Gi + 1, a second electrode thereof is connected to the i-th scanning line Gi, and a gate electrode thereof is connected to the i-th scanning line Gi.

The operation of FIG. 45A will be described. In the scan line driver circuit described in any of Embodiments 1 to 4, in the non-selection period, the scan line Gi−1 of the i−1th row, the scan line Gi of the ith row, and the scan line Gi + 1 of the i + 1th row. Keeps the L level. Therefore, the transistor 6
301a and the transistor 6301b are off. However, when the potential of the scanning line Gi on the i-th row rises due to, for example, noise, the scanning line Gi on the i-th row selects a pixel, and an incorrect video signal is written to the pixel. Therefore, by disposing a diode-connected transistor between the scan lines as in FIG. 45A, an illegal video signal can be prevented from being written to a pixel. This is because when the potential of the i-th scanning line Gi rises above the sum of the potential of the i−1-th scanning line Gi-1 and the threshold voltage of the transistor 6301a, the transistor 6301a turns on and the i-th row The potential of the eye scanning line Gi is lowered. Therefore, the pixel is not selected by the i-th scanning line Gi.

Note that the structure in FIG. 45A is particularly advantageous when the scan line driver circuit and the pixel portion are formed over one substrate. This is because, in a scan line driver circuit including only N-channel transistors or P-channel transistors, scan lines may be in a floating state and noise is likely to be generated in the scan lines.

Note that FIG. 45B illustrates a structure in which the diode-connected transistors arranged between the scan lines are reversed in direction. Note that the transistor 6302a and the transistor 6302b
Is an N-channel type transistor. However, P-channel transistors may be used, and the polarities of the transistors 6302a and 6302b may be similar to those of the transistors included in the scan line driver circuit or the pixel. In FIG. 45B, the first electrode of the transistor 6302a is connected to the scanning line Gi in the i-th row, the second electrode is connected to the scanning line Gi-1 in the i−1-th row, and the gate electrode is i. It is connected to the scanning line Gi of the row. A first electrode of the transistor 6302b is connected to the i + 1th scanning line Gi + 1, a second electrode thereof is connected to the ith scanning line Gi, and a gate electrode thereof is connected to the i + 1th scanning line Gi + 1. In FIG. 45B, similarly to FIG. 44A, the potential of the scan line Gi in the i-th row is greater than or equal to the sum of the potential of the scan line Gi + 1 in the i−1-th row and the threshold voltage of the transistor 6302b. When rising,
The transistor 6302b is turned on and the potential of the i-th row scan line Gi is lowered. Therefore,
No pixel is selected by the scanning line Gi in the i-th row, and it is possible to prevent an illegal video signal from being written in the pixel.

Note that as illustrated in FIG. 45C, with the structure in which FIG. 45A and FIG. 45B are combined, even if the potential of the scan line Gi in the i-th row rises, the transistor 6301a Since the transistor 6302b is turned on, the potential of the scan line Gi in the i-th row is lowered. Note that FIG.
In (C), since the current flows through the two transistors, larger noise can be removed. Note that components similar to those in FIGS. 45A and 45B are denoted by common reference numerals, and detailed description of the same portion or a portion having a similar function is omitted.

Note that as shown in FIGS. 43A and 43B, even if a diode-connected transistor is provided between the scan line and the storage capacitor line, the same as in FIGS. 45A, 45B, and 45C. The effect of can be obtained.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each drawing can be applied to the contents or part of the contents described in another drawing. Alternatively, they can be combined. Furthermore, in each of the figures described so far,
More figures can be constructed by combining different parts.

Similarly, the content or part of the content described in each drawing in this embodiment can be applied to the content or part of the content described in the drawing in another embodiment. Alternatively, they can be combined.
Further, in the drawings of this embodiment, more drawings can be formed by combining each part with parts of another embodiment.

Note that this embodiment is an example in which the contents described in the other embodiments are embodied, an example in which the contents are slightly modified, an example in which a part is changed, an example in the case of improvement, and details. An example of the case described, an example of the application, an example of related parts, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 8)
In this embodiment, the pixel structure of the display device will be described. In particular, the pixel structure of the liquid crystal display device will be described.

FIG. 46 is a cross-sectional view and a top view of a pixel in the case where a thin film transistor (TFT) is combined with what is called a TN method among pixel structures of a liquid crystal display device. 46A is a cross-sectional view of the pixel, and FIG. 46B is a top view of the pixel. The cross-sectional view of the pixel illustrated in FIG. 46A corresponds to the line segment aa ′ in the top view of the pixel illustrated in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 46, the liquid crystal display device can be manufactured at low cost.

A pixel structure of a TN liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part called an liquid crystal panel for displaying an image. LCD panel,
It is manufactured by bonding two processed substrates together with a gap of several micrometers, and injecting a liquid crystal material between the two substrates. In FIG. 46A, the two substrates are the first substrate 10101 and the second substrate 10116. TFT on the first substrate
Then, a pixel electrode is formed, and a light-blocking film 10114 and a color filter 1011 are formed on the second substrate.
5, the fourth conductive layer 10113, the spacer 10117, and the second alignment film 10112 may be formed.

Note that this can be performed without forming a TFT on the first substrate 10101. When this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Further, since the structure is simple, the yield can be improved. on the other hand,
When a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

The TFT shown in FIG. 46 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel-etched type and a channel-protected type in a bottom gate type TFT. Alternatively, a top gate type may be used. Further, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment can be implemented without forming the light-blocking film 10114 on the second substrate 10116. When this embodiment is performed without forming the light-blocking film 10114, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10114 is manufactured and this embodiment is performed, a display device with less light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10115 on the second substrate 10116. When this embodiment is performed without manufacturing the color filter 10115, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment is performed without manufacturing the color filter 10115, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10115 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10117 on the second substrate 10116. When the present embodiment is carried out by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, the spacer 101
In the case of manufacturing 17 and implementing this embodiment, the position of the spacer does not vary,
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, processing performed on the first substrate 10101 will be described. The first substrate 10101 is preferably a substrate having a light-transmitting property, and may be, for example, a quartz substrate, a glass substrate, or a plastic substrate. Note that the first substrate 10101 may be a light-blocking substrate, a semiconductor substrate, or an SOI (S
It may be an ilicon on Insulator) substrate.

First, the first insulating film 10102 may be formed over the first substrate 10101. The first insulating film 10102 is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxN).
It may be an insulating film such as y). Alternatively, as the first insulating film 10102, an insulating film having a stacked structure in which two or more films of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiOxNy), or the like are combined may be used. When the present embodiment is performed by forming the first insulating film 10102, it is possible to prevent impurities from the substrate from affecting the semiconductor layer and changing the properties of the TFT. Moreover, since the change in the properties of the TFT can be suppressed,
A highly reliable display device can be obtained. Note that in the case where this embodiment is performed without forming the first insulating film 10102, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved.

Next, the first conductive layer 1010 is formed over the first substrate 10101 or the first insulating film 10102.
3 is formed. Note that the first conductive layer 10103 may be formed by processing the shape. The process of processing the shape is preferably as follows. First, the first conductive layer 101
03 is formed on the entire surface. At this time, the first conductive layer 10103 is formed by a sputtering apparatus or C
The film may be formed using a film forming device such as a VD device. Next, a photosensitive resist material is formed on the entire surface of the first conductive layer formed on the entire surface. Next, the resist material is exposed to light according to the shape to be formed by photolithography or laser direct writing. Next, either the exposed resist material or the unexposed resist material is removed by etching, whereby a mask for shaping the first conductive layer 10103 can be obtained. Then, according to the formed mask pattern, the first conductive layer 10103
By removing by etching, the first conductive layer 10103 can be processed into a desired pattern. Note that there are a chemical method (wet etching) and a physical method (dry etching) as a method for etching the first conductive layer 10103. The material is appropriately selected in consideration of the properties of the material below the conductive layer 10103. Note that the materials used for the first conductive layer 10103 are Mo, Ti, and Al.
, Nd, Cr and the like are preferable. Alternatively, it may have a laminated structure in which two or more of Mo, Ti, Al, Nd, Cr and the like are combined.

Next, the second insulating film 10104 is formed. At this time, the second insulating film 10104 may be formed using a film formation apparatus such as a sputtering apparatus or a CVD apparatus. Note that a material used for the second insulating film 10104 is preferably a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Alternatively, a laminated structure in which two or more of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like are combined may be used.
Note that it is particularly preferable that the portion of the second insulating film 10104 which is in contact with the first semiconductor layer 10105 be a silicon oxide film. This is because when the silicon oxide film is used, the semiconductor layer 10
This is because the trap level at the interface with 105 decreases. The first conductive layer 10
When 103 is formed of Mo, the second insulating film 1 in a portion in contact with the first conductive layer 10103 is formed.
0104 is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo.

Next, the first semiconductor layer 10105 is formed. After that, it is preferable to continuously form the second semiconductor layer 10106. Note that the first semiconductor layer 10105 and the second semiconductor layer 1
0106 may be formed by processing the shape. The step of processing the shape is preferably a method such as the photolithography method described above. Note that the material used for the first semiconductor layer 10105 is preferably silicon, silicon germanium (SiGe), or the like. The material used for the second semiconductor layer 10106 is preferably silicon containing phosphorus or the like.

Next, the second conductive layer 10107 is formed. At this time, a sputtering method or a printing method is preferably used as a method for forming the second conductive layer 10107. The second conductive layer 10
The material used for 107 may be transparent or reflective. In the case of having transparency, for example, indium tin oxide (IT
O) film, indium tin oxide (ITSO) film in which silicon oxide is mixed with indium tin oxide (ITO), indium zinc oxide (IZO) film in which zinc oxide is mixed with indium oxide, zinc oxide film or tin oxide Membranes can be used. In addition, IZO is 2 to ITO.
It is a transparent conductive material formed by sputtering using a target in which 20 wt% zinc oxide (ZnO) is mixed. On the other hand, if it has reflectivity, Ti, Mo, Ta, Cr
, W, Al or the like can be used. Further, it may have a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, or a three-layer structure in which Al is sandwiched by metals such as Ti, Mo, Ta, Cr and W. Note that the second conductive layer 10107 may be formed by processing the shape. The method for processing the shape is preferably a method such as the photolithography method described above. The etching method is preferably dry etching. Dry etching is performed by ECR (Electron Cyclotron Resonance) or ICP (In
It may be performed by a dry etching apparatus using a high-density plasma source, such as a Duplicate Coupled Plasma.

Next, the channel region of the TFT is formed. At this time, the second conductive layer 10107 may be used as a mask for etching the second semiconductor layer 10106, or a mask (resist) for etching the second conductive layer 10107 may be used. Good. By doing so, the number of masks can be reduced, so that the manufacturing cost can be reduced. By etching the second semiconductor layer 10106 having conductivity, the removed portion is removed by the TFT.
Channel region. Note that without forming the first semiconductor layer 10105 and the second semiconductor layer 10106 continuously, after forming the first semiconductor layer 10105, a film which serves as a stopper is formed in a portion which becomes a channel region of the TFT. Patterning, then the second semiconductor layer 10
106 may be formed. Note that the first semiconductor layer 10105 and the second semiconductor layer 10106
Are etched using the same mask when processing the shape of the second conductive layer 10107 by a method such as the photolithography method described above. By doing so, the second conductive layer 1010
Since the channel region of the TFT can be formed without using 7 as a mask, there is an advantage that the degree of freedom of the layout pattern is increased. In addition, since the first semiconductor layer 10105 is not etched when the second semiconductor layer 10106 is etched, there is an advantage that the channel region of the TFT can be reliably formed without causing etching failure.

Next, a third insulating film 10108 is formed. The third insulating film is preferably transparent. Note that the material used for the third insulating film 10108 is an inorganic material (silicon oxide,
Silicon nitride, silicon oxynitride, or the like) or a low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material) or the like is preferable. Alternatively, a material containing siloxane may be used. Siloxane is a material whose skeletal structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used. Alternatively, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. Note that contact holes are selectively formed in the third insulating film 10108 by etching. In addition, the contact hole is formed at least over the second conductive layer 10107. In addition,
By etching the second insulating film 10104 at the same time as etching the third insulating film 10108, a contact hole with the first conductive layer 10103 as well as the second conductive layer 10107 can be formed. Note that the surface of the third insulating film 10108 is preferably as flat as possible. This is because the alignment of the liquid crystal molecules is affected by the unevenness of the surface in contact with the liquid crystal.

Next, the third conductive layer 10109 is formed. At this time, it is preferable to use a sputtering method or a printing method as a method for forming the third conductive layer 10109. The third conductive layer 10
The material used for 109 may be either transparent or reflective, like the second conductive layer 10107. Note that the material that can be used for the third conductive layer 10109 is the second
The conductive layer 10107 may be similar to the conductive layer 10107. Further, the third conductive layer 10109 may be formed by processing the shape. The method of processing the shape may be the same as that of the second conductive layer 10107.

Next, the first alignment film 10110 is formed. A polymer film such as polyimide can be used for the alignment film 10110. Note that after forming the first alignment film 10110, rubbing may be performed in order to control the alignment of liquid crystal molecules. Rubbing is a step of rubbing the alignment film with a cloth to form stripes on the alignment film. By rubbing, the alignment film can be made to have orientation.

The first substrate 10101 manufactured as described above, the light-shielding film 10114, and the color filter 10
115, the fourth conductive layer 10113, the spacer 10117, and the second substrate 10116 on which the second alignment film 10112 is formed are attached to each other with a gap of several μm by a sealant. Then, by injecting a liquid crystal material between the two substrates, a liquid crystal panel can be manufactured. In a TN type liquid crystal panel as shown in FIG. 46, the fourth conductive layer 101
13 may be formed on the entire surface of the second substrate 10116.

Next, the features of the pixel structure of the TN type liquid crystal panel shown in FIG. 46 will be described. Figure 46
The liquid crystal molecule 10118 shown in (A) is an elongated molecule having a long axis and a short axis. In order to show the orientation of the liquid crystal molecule 10118, the length is expressed in FIG. That is, it is assumed that the long axis of the liquid crystal molecule 10118 is parallel to the paper surface, and the shorter the liquid crystal molecule 10118 is, the closer the long axis direction is to the normal direction of the paper surface. . That is, in the liquid crystal molecule 10118 illustrated in FIG. 46A, the major axis direction of the liquid crystal molecule 10118 close to the first substrate 10101 and the liquid crystal molecule 10118 illustrated in FIG.
The major axis of the liquid crystal molecules 10118, which are different by 0 degree and are located in the middle, are oriented so as to smoothly connect them. That is, the liquid crystal molecule 101 shown in FIG.
18 is in an orientation state in which it is twisted by 90 degrees between the first substrate 10101 and the second substrate 10116.

Next, an example of a pixel layout in the case where this embodiment is applied to a TN type liquid crystal display device will be described with reference to FIG. Pixels of a TN liquid crystal display device to which this embodiment is applied include a scan line 10121, a video signal line 10122, and a capacitor line 10123.
And a TFT 10124, a pixel electrode 10125, and a pixel capacitor 10126.

The scan line 10121 is electrically connected to the gate electrode of the TFT 10124, and thus is preferably formed using the first conductive layer 10103.

Since the video signal line 10122 is electrically connected to the source electrode or the drain electrode of the TFT 10124, the video signal line 10122 is preferably formed using the second conductive layer 10107. Further, since the scan lines 10121 and the video signal lines 10122 are arranged in matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10123 is arranged in parallel with the pixel electrode 10125, so that the pixel capacitor 1012
It is a wiring for forming 6, and is preferably composed of the first conductive layer 10103. Note that as illustrated in FIG. 46B, the capacitor line 10123 may extend along the video signal line 10122 so as to surround the video signal line 10122. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, that is, so-called crosstalk, with the potential change of the video signal line 10122. Note that in order to reduce the cross capacitance with the video signal line 10122, the first semiconductor layer 10105 can be formed as shown in FIG.
May be provided in the intersection region of the capacitor line 10123 and the video signal line 10122.

The TFT 10124 operates as a switch that electrically connects the video signal line 10122 and the pixel electrode 10125. Note that as shown in FIG. 46B, either the source region or the drain region of the TFT 10124 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 46B, the TFT
The gate electrode of 10124 may be arranged so as to surround the first semiconductor layer 10105.

The pixel electrode 10125 is electrically connected to one of a source electrode and a drain electrode of the TFT 10124. The pixel electrode 10125 is an electrode for applying the signal voltage transmitted by the video signal line 10122 to the liquid crystal element. In addition, by arranging the capacitance line 10123,
The pixel capacitor 10126 may be formed. By doing so, the pixel electrode 10125 can easily hold the signal voltage transmitted by the video signal line 10122. The pixel electrode 101
25 may be rectangular as shown in FIG. 46 (B). By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0125 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In addition, when the pixel electrode 10125 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that when the pixel electrode 10125 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that when the pixel electrode 10125 is formed using a reflective material, the surface of the pixel electrode 10125 may have unevenness. Alternatively, the pixel electrode 10125 can be made uneven by giving unevenness to the surface of the third insulating film 10108. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Next, with reference to FIG. 47, a case where the present embodiment is applied to a liquid crystal display device of VA (Vertical Alignment) mode will be described. FIG. 47 shows a so-called MVA (Multi-domain) in which a liquid crystal molecule is controlled to have various orientations and a viewing angle is increased by using an alignment control protrusion in a pixel structure of a VA mode liquid crystal display device. Ver
FIG. 6 is a cross-sectional view and a top view of a pixel when the present embodiment is applied to a digital alignment (Tal Alignment) method. 47A is a cross-sectional view of the pixel, and FIG. 47B is a top view of the pixel. The cross-sectional view of the pixel illustrated in FIG. 47A corresponds to the line segment aa ′ in the top view of the pixel illustrated in FIG. 47B. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 47, a liquid crystal display device having a wide viewing angle, a high response speed, and a large contrast can be obtained.

The pixel structure of the MVA liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part called an liquid crystal panel for displaying an image. The liquid crystal panel is made by bonding two processed substrates together with a gap of several micrometers.
It is manufactured by injecting a liquid crystal material between the substrates. In FIG. 47A, the two substrates are the first substrate 10201 and the second substrate 10216. The first substrate is TF
T and the pixel electrode are formed, and the light shielding film 10214 and the color filter 102 are formed on the second substrate.
15, the fourth conductive layer 10213, the spacer 10217, the second alignment film 10212, and the alignment control protrusion 10219 may be formed.

Note that this embodiment mode can be implemented without forming a TFT on the first substrate 10201. When this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Further, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

The TFT shown in FIG. 47 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel-etched type and a channel-protected type in a bottom gate type TFT. Alternatively, a top gate type may be used. Further, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment mode can be implemented without forming the light-blocking film 10214 on the second substrate 10216. When this embodiment is performed without forming the light-blocking film 10214, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-blocking film 10214 is manufactured and this embodiment is performed, a display device with less light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10215 on the second substrate 10216. When this embodiment is performed without manufacturing the color filter 10215, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment is performed without manufacturing the color filter 10215, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10215 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10217 on the second substrate 10216. When the present embodiment is carried out by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, the spacer 102
In the case of manufacturing 17 and implementing this embodiment, the position of the spacer does not vary,
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, for the processing performed on the first substrate 10201, the method described with reference to FIG. Here, the first substrate 10201, the first insulating film 10202, the first conductive layer 10203, the second insulating film 10204, the first semiconductor layer 10205, the second semiconductor layer 10206, and the second conductive layer 10207. , Third insulating film 10208, third conductive layer 1020
9, the first alignment film 10210 corresponds to the first substrate 10101 and the first alignment film 10210 in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Although not shown, an alignment control protrusion may be provided on the first substrate side as well. By doing so, the alignment of the liquid crystal molecules can be controlled more reliably. In addition, the first alignment film 10210 and the second alignment film
The alignment film 10212 may be a vertical alignment film. By doing so, the liquid crystal molecules 10218 can be aligned vertically.

The first substrate 10201 manufactured as described above, the light shielding film 10214, and the color filter 10
215, the fourth conductive layer 10213, the spacer 10217, and the second alignment film 10212.
A liquid crystal panel can be manufactured by bonding the manufactured second substrate 10216 with a sealing material with a gap of several micrometers and injecting a liquid crystal material between the two substrates. Note that in the MVA type liquid crystal panel as shown in FIG. 47, the fourth conductive layer 102
13 may be formed on the entire surface of the second substrate 10216. In addition, the fourth conductive layer 10
The alignment control protrusion 10219 may be formed in contact with the 213. The alignment control protrusion 1
The shape of 0219 is not limited, but a shape having a smooth curved surface is preferable. By doing so, the alignment of the liquid crystal molecules 10218 adjacent to each other becomes extremely close to each other, so that alignment defects are reduced. In addition, defects in the alignment film, which are caused when the second alignment film 10212 is disconnected due to the alignment control protrusion 10219, can be reduced.

Next, the features of the pixel structure of the MVA type liquid crystal panel shown in FIG. 47 will be described. Figure 4
The liquid crystal molecule 10218 shown in FIG. 7A is an elongated molecule having a long axis and a short axis. In order to show the orientation of the liquid crystal molecule 10218, it is represented by its length in FIG. That is, the long axis of the liquid crystal molecule 10218 is parallel to the paper surface, and the shorter the liquid crystal molecule 10218 is, the closer the long axis direction is to the normal direction of the paper surface. .. That is, the liquid crystal molecules 10218 shown in FIG. 47A are aligned so that their major axes are oriented in the direction normal to the alignment film. Therefore, the alignment control protrusion 1021
The liquid crystal molecules 10218 in the part where 9 is present are radially aligned with the alignment control protrusion 10219 as the center. In this state, a liquid crystal display device having a wide viewing angle can be obtained.

Next, an example of a pixel layout in the case where this embodiment is applied to an MVA liquid crystal display device will be described with reference to FIG. The pixels of the MVA liquid crystal display device to which this embodiment is applied are the scan line 10221, the video signal line 10222, and the capacitor line 102.
23, the TFT 10224, the pixel electrode 10225, the pixel capacitor 10226, and the alignment control protrusion 10219 may be provided.

The scan line 10221 is electrically connected to the gate electrode of the TFT 10224, and thus is preferably formed of the first conductive layer 10203.

Since the video signal line 10222 is electrically connected to the source electrode or the drain electrode of the TFT 10224, the video signal line 10222 is preferably formed using the second conductive layer 10207. Further, since the scan lines 10221 and the video signal lines 10222 are arranged in matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10223 is arranged in parallel with the pixel electrode 10225, so that the pixel capacitor 1022
It is a wiring for forming 6 and is preferably composed of the first conductive layer 10203. Note that as illustrated in FIG. 47B, the capacitor line 10223 may extend along the video signal line 10222 so as to surround the video signal line 10222. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, that is, so-called crosstalk, in accordance with the potential change of the video signal line 10222. Note that in order to reduce the cross capacitance with the video signal line 10222, the first semiconductor layer 10205 is formed as illustrated in FIG.
May be provided in the intersection region of the capacitor line 10223 and the video signal line 10222.

The TFT 10224 operates as a switch that electrically connects the video signal line 10222 and the pixel electrode 10225. Note that as shown in FIG. 47B, either the source region or the drain region of the TFT 10224 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 47B, the TFT
The gate electrode of 10224 may be arranged so as to surround the first semiconductor layer 10205.

The pixel electrode 10225 is electrically connected to one of a source electrode and a drain electrode of the TFT 10224. The pixel electrode 10225 is an electrode for applying the signal voltage transmitted by the video signal line 10222 to the liquid crystal element. In addition, by arranging the capacitor line 10223,
The pixel capacitor 10226 may be formed. By doing so, the pixel electrode 10225 can easily hold the signal voltage transmitted by the video signal line 10222. The pixel electrode 102
25 may be rectangular as shown in FIG. 47 (B). By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0225 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, when the pixel electrode 10225 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that when the pixel electrode 10225 is formed using both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having both advantages can be obtained. When the pixel electrode 10225 is made of a reflective material, the surface of the pixel electrode 10225 may have unevenness. Alternatively, the pixel electrode 10225 can be made uneven by giving unevenness to the surface of the third insulating film 10208. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Next, with reference to FIG. 48, another example in the case where the present embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described. In FIG. 48, in a pixel structure of a VA mode liquid crystal display device, by patterning the fourth conductive layer 10313, liquid crystal molecules are controlled to have various orientations and a so-called viewing angle is increased. PVA (P
FIG. 3 is a cross-sectional view and a top view of a pixel when the present embodiment is applied to an at least vertical alignment) method. 48A is a cross-sectional view of the pixel, and FIG. 48B is a top view of the pixel. The cross-sectional view of the pixel illustrated in FIG. 48A corresponds to the line segment aa ′ in the top view of the pixel illustrated in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 48, a liquid crystal display device having a wide viewing angle, a high response speed, and a large contrast can be obtained.

A pixel structure of a PVA liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part called an liquid crystal panel for displaying an image. The liquid crystal panel is made by bonding two processed substrates together with a gap of several micrometers.
It is manufactured by injecting a liquid crystal material between the substrates. In FIG. 48A, the two substrates are the first substrate 10301 and the second substrate 10316. The first substrate has T
The FT and the pixel electrode are formed, and the light shielding film 10314, the color filter 10315, the fourth conductive layer 10313, the spacer 10317, and the second alignment film 10 are formed on the second substrate.
312 may be made.

Note that this embodiment mode can be implemented without forming a TFT on the first substrate 10301. When this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Further, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

The TFT shown in FIG. 48 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel-etched type and a channel-protected type in a bottom gate type TFT. Alternatively, a top gate type may be used. Further, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment can be implemented without forming the light-blocking film 10314 on the second substrate 10316. When this embodiment is performed without forming the light-blocking film 10314, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10314 is formed and this embodiment is performed, a display device with less light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10315 on the second substrate 10316. When this embodiment is performed without manufacturing the color filter 10315, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even in the case where this embodiment mode is performed without manufacturing the color filter 10315, a display device capable of color display by field sequential driving can be obtained. On the other hand, in the case where the color filter 10315 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10317 on the second substrate 10316. When the present embodiment is carried out by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, the spacer 103
In the case of manufacturing 17 and implementing this embodiment, the position of the spacer does not vary,
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, for the processing performed on the first substrate 10301, the method described in FIG. Here, the first substrate 10301, the first insulating film 10302, the first conductive layer 10303, the second insulating film 10304, the first semiconductor layer 10305, the second semiconductor layer 10306, and the second conductive layer 10307. A third insulating film 10308 and a third conductive layer 1030
9, the first alignment film 10310 corresponds to the first substrate 10101 and the first alignment film 10310 in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Note that an electrode cutout portion may be provided in the third conductive layer 10309 on the first substrate 10301 side. By doing so, the alignment of the liquid crystal molecules can be controlled more reliably. In addition, the first alignment film 10
The 310 and the second alignment film 10312 may be vertical alignment films. By doing so, the liquid crystal molecules 10318 can be vertically aligned.

The first substrate 10301 manufactured as described above, the light shielding film 10314, and the color filter 10
315, the fourth conductive layer 10313, the spacer 10317, and the second alignment film 10312.
A liquid crystal panel can be manufactured by bonding the manufactured second substrate 10316 with a sealant with a gap of several μm and injecting a liquid crystal material between the two substrates. Note that in a PVA liquid crystal panel as shown in FIG. 48, the fourth conductive layer 10313 may be patterned to form the electrode cutout portion 10319. Note that the shape of the electrode cutout portion 10319 is not limited, but a shape in which a plurality of rectangles having different directions are combined is preferable. By doing so, a plurality of regions having different orientations can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. The shape of the fourth conductive layer 10313 at the boundary between the electrode cutout portion 10319 and the fourth conductive layer 10313 is preferably a smooth curve. By doing so, the alignment of the liquid crystal molecules 10318 adjacent to each other becomes extremely close to each other, so that alignment defects are reduced. In addition, the second alignment film 10312 has the electrode cutout 10
Alignment film defects due to step breakage caused by 319 can also be reduced.

Next, the characteristics of the pixel structure of the PVA type liquid crystal panel shown in FIG. 48 will be described. Figure 4
The liquid crystal molecule 10318 shown in FIG. 8A is an elongated molecule having a long axis and a short axis. In order to show the orientation of the liquid crystal molecule 10318, it is represented by its length in FIG. That is, it is assumed that the long axis of the liquid crystal molecule 10318 is parallel to the paper surface, and the shorter the liquid crystal molecule 10318 is, the closer the long axis direction is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10318 illustrated in FIG. 48A is aligned so that the major axis of the liquid crystal molecule 10318 is aligned with the normal direction of the alignment film. Therefore, the electrode cutout portion 1031
The liquid crystal molecules 10318 in the part where 9 is present are the same as those in the electrode cutout portion 10319 and the fourth conductive layer 103.
It is oriented radially around the boundary of 13. In this state, a liquid crystal display device having a wide viewing angle can be obtained.

Next, an example of a pixel layout when this embodiment is applied to a PVA liquid crystal display device will be described with reference to FIG. The pixels of the PVA liquid crystal display device to which this embodiment is applied include a scan line 10321, a video signal line 10322, and a capacitor line 103.
23, the TFT 10324, the pixel electrode 10325, the pixel capacitor 10326, and the electrode cutout portion 10319 may be provided.

Since the scan line 10321 is electrically connected to the gate electrode of the TFT 10324, the scan line 10321 is preferably formed using the first conductive layer 10303.

Since the video signal line 10322 is electrically connected to the source electrode or the drain electrode of the TFT 10324, the video signal line 10322 is preferably formed using the second conductive layer 10307. Further, since the scan lines 10321 and the video signal lines 10322 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10323 is arranged in parallel with the pixel electrode 10325, so that the pixel capacitor 1032
It is a wiring for forming 6 and is preferably composed of the first conductive layer 10303. Note that as illustrated in FIG. 48B, the capacitor line 10323 may extend along the video signal line 10322 so as to surround the video signal line 10322. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, that is, so-called crosstalk, in accordance with the potential change of the video signal line 10322. Note that in order to reduce the cross capacitance with the video signal line 10322, as illustrated in FIG. 48B, the first semiconductor layer 10305 is used.
May be provided in the intersection region of the capacitor line 10323 and the video signal line 10322.

The TFT 10324 operates as a switch that electrically connects the video signal line 10322 and the pixel electrode 10325. Note that as shown in FIG. 48B, either the source region or the drain region of the TFT 10324 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 48B, the TFT
The gate electrode of 10324 may be arranged so as to surround the first semiconductor layer 10305.

The pixel electrode 10325 is electrically connected to one of a source electrode and a drain electrode of the TFT 10324. The pixel electrode 10325 is an electrode for applying the signal voltage transmitted by the video signal line 10322 to the liquid crystal element. In addition, by arranging the capacitance line 10323,
The pixel capacitor 10326 may be formed. By doing so, the pixel electrode 10325 can easily hold the signal voltage transmitted by the video signal line 10322. The pixel electrode 103
As shown in FIG. 48B, 25 is a pixel electrode 103 corresponding to the shape of the electrode cutout portion 10319 provided in the fourth conductive layer 10313 in a portion where the electrode cutout portion 10319 is not formed.
It is preferable to form a notched portion of 25. By doing so, liquid crystal molecules 10318
Since a plurality of regions having different orientations can be formed, a liquid crystal display device with a wide viewing angle can be obtained. When the pixel electrode 10325 is made of a transparent material,
A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, when the pixel electrode 10325 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that when the pixel electrode 10325 is formed using both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10325 is formed using a reflective material, the surface of the pixel electrode 10325 may have unevenness. Alternatively, the pixel electrode 10325 can be made uneven by giving unevenness to the surface of the third insulating film 10308. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Next, with reference to FIG. 49, a case where the present embodiment is applied to a horizontal electric field type liquid crystal display device will be described. FIG. 49 shows a pixel electrode 10425 and a common electrode 10423 in a pixel structure of a liquid crystal display device in which an electric field is applied in a lateral direction in order to perform switching so that the orientation of liquid crystal molecules is always horizontal to a substrate. FIG. 3 is a cross-sectional view and a top view of a pixel when this embodiment is applied to a method of applying an electric field in a lateral direction by performing comb-shaped pattern processing, that is, an IPS (In-Plane-Switching) method. .. 49A is a cross-sectional view of the pixel, and FIG. 49B is a top view of the pixel. The cross-sectional view of the pixel illustrated in FIG. 49A corresponds to the line segment aa ′ in the top view of the pixel illustrated in FIG. 49B. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 49, it is possible in principle to obtain a liquid crystal display device having a large viewing angle and a small response speed gradation dependency.

A pixel structure of an IPS liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part called an liquid crystal panel for displaying an image. A liquid crystal panel is manufactured by laminating two processed substrates with a gap of several μm, and injecting a liquid crystal material between the two substrates. In FIG. 49A, the two substrates are a first substrate 10401 and a second substrate 10416. TFTs and pixel electrodes are formed on the first substrate, and the light-shielding film 10414 and the color filter 10415 are formed on the second substrate.
The spacer 10417 and the second alignment film 10412 may be formed.

Note that this embodiment mode can be implemented without forming a TFT on the first substrate 10401. When this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Further, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

The TFT shown in FIG. 49 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel-etched type and a channel-protected type in a bottom gate type TFT. Alternatively, a top gate type may be used. Further, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment can be implemented without forming the light-blocking film 10414 on the second substrate 10416. When this embodiment is performed without forming the light-blocking film 10414, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-blocking film 10414 is formed and this embodiment is performed, a display device with less light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10415 on the second substrate 10416. When this embodiment is performed without manufacturing the color filter 10415, the number of steps is reduced, so that manufacturing cost can be reduced. However, even when this embodiment is performed without manufacturing the color filter 10415, a display device capable of color display can be obtained by field sequential driving. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the color filter 10415 is manufactured to implement this embodiment, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10417 on the second substrate 10416. When the present embodiment is carried out by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, the spacer 104
In the case of manufacturing 17 and implementing this embodiment, the position of the spacer does not vary,
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, for the processing performed on the first substrate 10401, the method described in FIG. Here, the first substrate 10401, the first insulating film 10402, the first conductive layer 10403, the second insulating film 10404, the first semiconductor layer 10405, the second semiconductor layer 10406, and the second conductive layer 10407. , Third insulating film 10408, third conductive layer 1040
9, the first alignment film 10410 corresponds to the first substrate 10101 and the first alignment film 10410 in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Note that patterning was performed on the third conductive layer 10409 on the first substrate 10401 side and
You may form in one comb-tooth shape. Further, one comb-teeth electrode may be electrically connected to one of the source electrode and the drain electrode of the TFT 10424, and the other comb-teeth electrode may be electrically connected to the common electrode 10423. By doing so, liquid crystal molecules 10418
A horizontal electric field can be effectively applied to the.

The first substrate 10401, the light shielding film 10414, and the color filter 10 manufactured as described above.
415, the spacer 10417, and the second substrate 10 on which the second alignment film 10412 is formed.
A liquid crystal panel can be manufactured by bonding 416 with a sealant so that a gap of several micrometers is provided, and injecting a liquid crystal material between two substrates. Although not shown,
A conductive layer may be formed on the second substrate 10416 side. By forming the conductive layer on the second substrate 10416 side, it is possible to reduce the influence of electromagnetic noise from the outside.

Next, the features of the pixel structure of the IPS liquid crystal panel shown in FIG. 49 will be described. Figure 4
The liquid crystal molecule 10418 shown in FIG. 9A is an elongated molecule having a long axis and a short axis. In order to show the orientation of the liquid crystal molecules 10418, the length is expressed in FIG. That is, the long axis of the liquid crystal molecule 10418 is parallel to the paper surface, and the shorter the liquid crystal molecule 10418 is, the closer the long axis direction is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10418 shown in FIG. 49A is aligned so that the major axis of the liquid crystal molecule 10418 is always aligned with the substrate. In FIG. 49A,
Although the orientation is shown in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10418, the liquid crystal molecules 10418 rotate in a horizontal plane while keeping the direction of the major axis always horizontal to the substrate. In this state, a liquid crystal display device having a wide viewing angle can be obtained.

Next, with reference to FIG. 49B, an example of a pixel layout in the case where this embodiment is applied to an IPS liquid crystal display device will be described. Pixels of an IPS liquid crystal display device to which this embodiment is applied include a scan line 10421, a video signal line 10422, and a common electrode 10.
423, the TFT 10424, and the pixel electrode 10425 may be provided.

The scan line 10421 is electrically connected to the gate electrode of the TFT 10424, and thus is preferably formed using the first conductive layer 10403.

The video signal line 10422 is electrically connected to the source electrode or the drain electrode of the TFT 10424, and thus is preferably formed of the second conductive layer 10407. Further, since the scan lines 10421 and the video signal lines 10422 are arranged in matrix, at least
It is preferable that the conductive layers are formed of different layers. Note that as illustrated in FIG. 49B, the video signal line 10422 may be bent and formed in a pixel so as to match the shapes of the pixel electrode 10425 and the common electrode 10423. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device can be improved.

The common electrode 10423 is an electrode for generating a horizontal electric field by being arranged in parallel with the pixel electrode 10425, and is composed of the first conductive layer 10403 and the third conductive layer 10409. It is suitable. Note that as shown in FIG. 49B, the common electrode 1042
3 may be extended along the video signal line 10422 so as to surround the video signal line 10422. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, that is, so-called crosstalk, in accordance with the potential change of the video signal line 10422.
Note that in order to reduce the cross capacitance with the video signal line 10422, the first semiconductor layer 10405 may be provided in the cross region of the common electrode 10423 and the video signal line 10422 as illustrated in FIG. 49B.

The TFT 10424 operates as a switch that electrically connects the video signal line 10422 and the pixel electrode 10425. Note that as shown in FIG. 49B, either the source region or the drain region of the TFT 10424 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 49B, the TFT
The gate electrode of 10424 may be arranged so as to surround the first semiconductor layer 10405.

The pixel electrode 10425 is electrically connected to one of a source electrode and a drain electrode of the TFT 10424. The pixel electrode 10425 is an electrode for applying the signal voltage transmitted by the video signal line 10422 to the liquid crystal element. Alternatively, a pixel capacitor may be formed by disposing the common electrode 10423. By doing so, the pixel electrode 10325 is connected to the video signal line 10
It becomes easier to hold the signal voltage transmitted by 422. Note that the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are preferably formed in a bent comb-teeth shape as shown in FIG. 49B. By doing so, a plurality of regions in which the liquid crystal molecules 10418 have different orientations can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. When the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are made of a transparent material, a transmissive liquid crystal display device can be obtained. Transmissive liquid crystal display device,
It is possible to display images with high color reproducibility and high image quality. Further, in the transmissive liquid crystal display device, the pixel has a high aperture ratio, and the light efficiency can be improved. However, a transmissive liquid crystal display device can be obtained even when the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are made of a material which is neither transparent nor reflective. In the transmissive liquid crystal display device, light transmits only liquid crystal molecules 10418 in a portion where a horizontal electric field exists, so that color reproducibility is high and an image with high image quality can be displayed. When the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are made of a reflective material,
A transflective liquid crystal display device can be obtained. A semi-transmissive liquid crystal display device has high visibility in a bright environment such as outdoors and can consume very little power. further,
The transflective liquid crystal display device has high color reproducibility and can display an image with high image quality. However, even when the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are formed using both a transparent material and a reflective material, a semi-transmissive liquid crystal display device can be obtained. When the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are made of a reflective material, the pixel electrode 10425 and the comb-teeth-shaped common electrode 10 are formed.
The surface of 423 may be uneven. Alternatively, the pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 can be made uneven by giving unevenness to the surface of the third insulating film 10408. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Although the comb-teeth-shaped pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 are both formed of the third conductive layer 10409, the pixel structure to which this embodiment is applicable is not limited to this. Instead, it can be appropriately selected. For example, the comb-teeth-shaped pixel electrode 10425 and the comb-teeth-shaped common electrode 10423 may both be formed of the second conductive layer 10407, or both of them may be formed of the first conductive layer 10403. Either one may be formed of the third conductive layer 10409 and the other may be formed of the second conductive layer 10407, or either one may be formed of the third conductive layer 10409 and the other may be formed of the first conductive layer. The layer 10407 may be formed, or one of the layers may be formed of the second conductive layer 10409 and the other may be formed of the first conductive layer 10407.

Next, with reference to FIG. 50, a case where the present embodiment is applied to another lateral electric field type liquid crystal display device will be described. FIG. 50 is a diagram showing another pixel structure of a liquid crystal display device in which an electric field is applied in the lateral direction in order to perform switching so that the orientation of liquid crystal molecules is always horizontal with respect to the substrate. More specifically, one of the pixel electrode 10525 and the common electrode 10523 is subjected to comb-tooth pattern processing, and the other is uniformly formed in a region overlapping with the comb-tooth shape, whereby A method of applying an electric field in the direction, so-called FFS (Fringe Field S
3A and 3B are a cross-sectional view and a top view of a pixel in the case where this embodiment is applied to a Witching method. 50A is a cross-sectional view of the pixel, and FIG. 50B is a top view of the pixel.
The cross-sectional view of the pixel illustrated in FIG. 50A corresponds to the line segment aa ′ in the top view of the pixel illustrated in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 50, it is possible in principle to obtain a liquid crystal display device having a large viewing angle and a small response speed gradation dependency.

A pixel structure of an FFS liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part called an liquid crystal panel for displaying an image. A liquid crystal panel is manufactured by bonding two processed substrates with a gap of several macrometers, and injecting a liquid crystal material between the two substrates. In FIG. 50A, the two substrates are the first substrate 10501 and the second substrate 10516. TFT on the first substrate
Then, a pixel electrode is formed, and a light-blocking film 10514 and a color filter 1051 are formed over the second substrate
5, the spacer 10517, and the second alignment film 10512 may be formed.

Note that this embodiment can be implemented without forming a TFT on the first substrate 10501. When this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

Note that the TFT shown in FIG. 50 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel-etched type and a channel-protected type in a bottom gate type TFT. Alternatively, a top gate type may be used. Further, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment can be implemented without forming the light-blocking film 10514 on the second substrate 10516. When this embodiment is performed without forming the light-blocking film 10514, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10514 is manufactured and this embodiment is performed, a display device with less light leakage during black display can be obtained.

Note that this embodiment can be implemented without forming the color filter 10515 on the second substrate 10516. When this embodiment is performed without manufacturing the color filter 10515, the number of steps is reduced, so that manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even when this embodiment is performed without manufacturing the color filter 10515, a display device capable of color display can be obtained by field sequential driving. On the other hand, when the color filter 10515 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10517 on the second substrate 10516. When the present embodiment is carried out by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, the spacer 105
In the case of manufacturing 17 and implementing this embodiment, the position of the spacer does not vary,
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, for the processing applied to the first substrate 10501, the method described in FIG. Here, the first substrate 10501, the first insulating film 10502, the first conductive layer 10503, the second insulating film 10504, the first semiconductor layer 10505, the second semiconductor layer 10506, and the second conductive layer 10507. , Third insulating film 10508, third conductive layer 1050
9, the first alignment film 10510 corresponds to the first substrate 10101 and the first alignment film 10510 in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110.

However, the difference from FIG. 46 is that the fourth insulating film 10519 and the fourth conductive layer 10513 may be formed on the first substrate 10501 side. More specifically, after patterning the third conductive layer 10509, a fourth insulating film 10519 is formed, patterning is performed to form a contact hole, and then the fourth conductive layer 10513 is formed. The first alignment film 10510 may be formed after the film is formed and similarly patterned. Note that as a material and a processing method which can be used for the fourth insulating film 10519 and the fourth conductive layer 10513, the same materials as those used for the third insulating film 10508 and the third conductive layer 10509 can be used. Alternatively, one of the comb-teeth-shaped electrodes may be electrically connected to one of the source electrode and the drain electrode of the TFT 10524, and the other uniform electrode may be electrically connected to the common electrode 10523. By doing so, a horizontal electric field can be effectively applied to the liquid crystal molecules 10518.

The first substrate 10501 manufactured as described above, the light shielding film 10514, and the color filter 10
515, the spacer 10517, and the second substrate 10 on which the second alignment film 10512 is formed.
A liquid crystal panel can be manufactured by bonding 516 with a sealing material so that a gap of several macrometers is provided and injecting a liquid crystal material between two substrates. Although not shown, a conductive layer may be formed on the second substrate 10516 side. By forming the conductive layer on the second substrate 10516 side, the influence of electromagnetic wave noise from the outside can be suppressed.

Next, the characteristics of the pixel structure of the FFS type liquid crystal panel shown in FIG. 50 will be described. Figure 5
The liquid crystal molecule 10518 shown in (A) of 0 is an elongated molecule having a long axis and a short axis. In order to show the orientation of the liquid crystal molecules 10518, the length is expressed in FIG. That is, the long axis of the liquid crystal molecule 10518 is parallel to the paper surface, and the shorter the liquid crystal molecule 10518 is, the closer the long axis direction is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10518 shown in FIG. 50A is aligned so that the major axis of the liquid crystal molecule 10518 is always horizontal to the substrate. In FIG. 50A,
Although the orientation is shown in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10518, the liquid crystal molecules 10518 rotate in a horizontal plane while keeping the direction of the major axis always horizontal to the substrate. In this state, a liquid crystal display device having a wide viewing angle can be obtained.

Next, with reference to FIG. 50B, an example of a pixel layout in the case where this embodiment is applied to an FFS liquid crystal display device will be described. The pixels of the FFS type liquid crystal display device to which the present embodiment is applied include the scanning line 10521, the video signal line 10522, and the common electrode 10.
523, the TFT 10524, and the pixel electrode 10525 may be provided.

The scan line 10521 is electrically connected to the gate electrode of the TFT 10524, and thus is preferably formed of the first conductive layer 10503.

The video signal line 10522 is electrically connected to the source electrode or the drain electrode of the TFT 10524, and thus is preferably formed of the second conductive layer 10507. Further, since the scan lines 10521 and the video signal lines 10522 are arranged in matrix, at least
It is preferable that the conductive layers are formed of different layers. Note that, as shown in FIG. 50B, the video signal line 10522 may be bent in the pixel so as to match the shape of the pixel electrode 10525. By doing so, the aperture ratio of the pixel can be increased,
The efficiency of the liquid crystal display device can be improved.

The common electrode 10523 is preferably composed of the first conductive layer 10503 and the third conductive layer 10509. Note that in order to reduce the cross capacitance with the video signal line 10522,
As shown in FIG. 50B, the first semiconductor layer 10505 may be provided in the intersection region between the common electrode 10523 and the video signal line 10522.

The TFT 10524 operates as a switch that electrically connects the video signal line 10522 and the pixel electrode 10525. Note that as shown in FIG. 50B, either the source region or the drain region of the TFT 10524 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. Note that, as shown in FIG.
The gate electrode of 10524 may be arranged so as to surround the first semiconductor layer 10505.

The pixel electrode 10525 is electrically connected to one of a source electrode and a drain electrode of the TFT 10524. The pixel electrode 10525 is an electrode for applying the signal voltage transmitted by the video signal line 10522 to the liquid crystal element. Alternatively, the pixel capacitance may be formed by disposing the common electrode 10523. By doing so, the pixel electrode 10525 is connected to the video signal line 10
It becomes easier to hold the signal voltage transmitted by 522. The pixel electrode 10525 is
As shown in FIG. 50 (B), it is preferable to form it in a bent comb-tooth shape. By doing so, a plurality of regions in which the liquid crystal molecules 10518 have different orientations can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. Further, the comb-teeth-shaped pixel electrode 1052
When 5 and the common electrode 10523 are made of a transparent material, a transmissive liquid crystal display device can be obtained. However, even when the comb-teeth-shaped pixel electrode 10525 is made of a material having no reflectivity and the common electrode 10523 is made of a material having transparency, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In addition, when the comb-teeth-shaped pixel electrode 10525 and the common electrode 10523 are made of a reflective material, a reflective liquid crystal display device can be obtained. However, if at least the common electrode 10523 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that when the comb-teeth-shaped pixel electrode 10525 and the common electrode 10523 are formed using both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having both advantages is obtained. Obtainable. However, the comb-teeth-shaped pixel electrode 1
Even when 0525 is formed using a reflective material and the pixel electrode 10525 is formed using a transmissive material, a semi-transmissive liquid crystal display device can be obtained. Note that in the case where the pixel electrode 10525 and the comb-teeth-shaped common electrode 10523 are made of a reflective material, the comb-teeth-shaped pixel electrode 10525 and the common electrode 10523 may have unevenness. Alternatively, the comb-teeth-shaped pixel electrode 10525 and the common electrode 10523 can be made uneven by giving unevenness to the surface of the third insulating film 10508. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness at any angle.

Although the comb-teeth-shaped pixel electrode 10525 is formed of the fourth conductive layer 10513 and the uniform common electrode 10523 is formed of the third conductive layer 10509, this embodiment can be applied. The pixel configuration is not limited to this, and can be appropriately selected as long as a certain condition is satisfied. More specifically, it is sufficient that the comb-teeth-shaped electrode is located closer to the liquid crystal than the uniform electrode when viewed from the first substrate 10501. This is because the electric field in the lateral direction is always generated in the direction opposite to the uniform electrode when viewed from the comb-teeth-shaped electrode. That is, in order to apply a lateral electric field to the liquid crystal, the comb-teeth-shaped electrode must be positioned closer to the liquid crystal than the uniform electrode.

To satisfy this condition, for example, a comb-teeth-shaped electrode may be formed of the fourth conductive layer 10513 and a uniform electrode may be formed of the third conductive-layer 10509, or a comb-teeth-shaped electrode may be formed. Fourth conductive layer 1
0513 and the uniform electrode may be formed of the second conductive layer 10507, or the comb-teeth-shaped electrode may be formed of the fourth conductive layer 10513 and the uniform electrode may be formed of the first conductive layer. 10503, the comb-teeth-shaped electrode may be formed of the third conductive layer 10509, and the uniform electrode may be formed of the second conductive layer 10507, or the comb-teeth-shaped electrode may be formed. The third conductive layer 10509 may be formed and a uniform electrode may be formed of the first conductive layer 10503, or the comb-teeth-shaped electrode may be formed of the second conductive layer 1.
0507, and a uniform electrode may be formed using the first conductive layer 10503. Note that the comb-teeth-shaped electrode is electrically connected to one of the source region and the drain region of the TFT 10524, and the uniform electrode is electrically connected to the common electrode 10523, but this connection is reversed. But it's okay. In that case, uniform electrodes may be formed independently for each pixel.

Next, various liquid crystal modes applicable to the liquid crystal display device of this embodiment will be described.

First, FIGS. 51A1 and 51A2 are schematic views of a TN mode liquid crystal display device.

Similar to the above embodiment mode, the liquid crystal layer 10600 is sandwiched between the first substrate 10601 and the second substrate 10602 which are arranged so as to face each other. Then, the first substrate 106
A layer 10603 including a first polarizer is stacked on the 01 side and a layer 10604 including a second polarizer is arranged on the second substrate 10602 side. The layer 10 including the first polarizer
603 and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

Although not shown, the backlight and the like are arranged outside the layer including the second polarizer. A first electrode 10605 is provided over each of the first substrate 10601 and the second substrate 10602.
, And a second electrode 10606 is provided. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least a light-transmitting property.

In the liquid crystal display device having the structure shown in FIGS. 51A1 and 51A2, in the normally white mode, voltage is applied to the first electrode 10605 and the second electrode 10606 (referred to as a vertical electric field method). Then, black display is performed as shown in FIG. At this time, the liquid crystal molecules are aligned vertically. Then, the light from the backlight cannot pass through the substrate, resulting in black display.

Then, as shown in FIG. 51A2, the first electrode 10605 and the second electrode 10606
When no voltage is applied between the two, white display is performed. At this time, the liquid crystal molecules are arranged side by side,
It is rotating in the plane. As a result, light from the backlight passes through a layer including a pair of polarizers (a layer including a first polarizer 10603, and a layer including a second polarizer 10604) which are arranged so as to be crossed Nicols. It is possible to display a predetermined image.

A liquid crystal display device having a structure as shown in FIGS. 51A1 and 51A2 can perform full-color display by providing a color filter. The color filter is the first substrate 10.
It can be provided on either the 601 side or the second substrate 10602 side. However, FIG.
A liquid crystal display device having a configuration such as 1 (A1) or (A2) can perform full-color display by field sequential driving if the light from the backlight changes with time without providing a color filter.

A known liquid crystal material may be used for the TN mode.

FIG. 51B1 is a schematic view of a VA mode liquid crystal display device. The VA mode is a mode in which liquid crystal molecules are aligned so as to be perpendicular to the substrate when there is no electric field.

Similarly to FIGS. 51A1 and 51A2, the first electrode 10605 and the second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least a light-transmitting property. Then, a layer 10603 containing a first polarizer is stacked on the first substrate 10601 side, and a layer 1 containing a second polarizer 1 is provided on the second substrate 10602 side.
0604 is arranged. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In the liquid crystal display device having the structure shown in FIGS. 51A1 and 51A1, the first electrode 106
05 and a voltage is applied to the second electrode 10606 (vertical electric field method), FIG.
As shown in, the display is in a white state and is in an on state. At this time, the liquid crystal molecules are aligned horizontally. Then, the light from the backlight includes a layer including a pair of polarizers arranged in a crossed Nicols state (a layer including a first polarizer 10603, and a layer including a second polarizer 10604).
) Can be passed and a predetermined image display is performed. At this time, full-color display can be performed by providing a color filter. The color filter is the first substrate 10.
It can be provided on either the 601 side or the second substrate 10602 side.

Then, as shown in FIG. 51B2, the first electrode 10605 and the second electrode 10606
When no voltage is applied between the two, the display is black, that is, the off state. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in black display.

In the off state, the liquid crystal molecules rise vertically to the substrate to display black, and in the on state, the liquid crystal molecules fall horizontally to the substrate to display white. In the off state, the liquid crystal molecules stand up, so the light from the polarized backlight passes through the cell without being affected by the birefringence of the liquid crystal molecules, and is blocked by the layer including the polarizer on the counter substrate side. be able to.

Here, an example in which the layer including the stacked polarizer of this embodiment is applied to the MVA mode in which the alignment of the liquid crystal is divided is shown in FIGS. The MVA mode is a method of mutually compensating for the viewing angle dependence of each part. As shown in FIG. 51C1, in the MVA mode, protrusions 10607 and 10608 having triangular cross sections are provided over the first electrode 10605 and the second electrode 10606 for controlling alignment. The first electrode 10605 and the second
When a voltage is applied to the electrode 10606 (vertical electric field method), a white display is performed as shown in FIG. At this time, the liquid crystal molecules are the projections 10607 and 1060.
It will be in a state of falling side by side with respect to 8. Then, the light from the backlight passes through the layer including the pair of polarizers (the layer including the first polarizer 10603, and the layer including the second polarizer 10604) arranged in a crossed Nicols state. It is possible to display a predetermined image. Note that a liquid crystal display device having a structure as shown in FIGS. 51C1 and 51C2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in FIGS. 51C1 and 51C2 can perform full-color display by field sequential driving without providing a color filter.

Then, as illustrated in FIG. 51C2, the first electrode 10605 and the second electrode 1060
When the voltage is not applied during 6, the black display, that is, the off state. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in black display.

FIG. 54 shows a top view and a cross-sectional view of another example of the MVA mode. As shown in FIG. 54A, the second electrodes 10606a, 10606b, and 10606c may be formed in a bent pattern like a dogleg shape. Insulating layers 10901 and 10902 are formed near the liquid crystal layer 10600. Note that the insulating layers 10901 and 10902 may be alignment films. As shown in FIG. 54 (B), the protrusion 1 is provided in the vicinity of the first electrode 10605.
0607 may be formed corresponding to the second electrodes 10606a, 10606b, and 10606c. The protrusion 10607 is connected to the second electrode 10606a, 10606b, 10606c.
And the second electrodes 10606a, 10606b, 10606
The opening of c functions like a protrusion, and the liquid crystal molecules can be effectively aligned. Note that the order in which the first electrode 10605 and the protrusion 10607 are formed may be opposite to that in FIG.

52A1 and 52A2 are schematic views of OCB mode liquid crystal display devices. In the OCB mode, the alignment of liquid crystal molecules in the liquid crystal layer forms an optically compensated state, which is called bend alignment.

Similar to FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. Although not shown, a backlight or the like is provided outside the layer 10604 including the second polarizer. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least a light-transmitting property. Then, on the side of the first substrate 10601, the layer 1 including the first polarizer 1
0603 is stacked, and the layer 10604 including the second polarizer is provided on the second substrate 10602 side. Note that the layer 10603 containing the first polarizer and the layer 10 containing the second polarizer 10
604 is arranged so as to form a crossed Nicols.

In the liquid crystal display device having the structure shown in FIGS. 52A1 and 52A2, the first electrode 106
05, and a constant ON voltage is applied to the second electrode 10606 (longitudinal electric field method), FIG.
As shown in 2 (A1), black display is performed. At this time, the liquid crystal molecules are aligned vertically. Then, the light from the backlight cannot pass through the substrate, resulting in black display.

Then, as illustrated in FIG. 52A2, the first electrode 10605 and the second electrode 1060
When a constant off voltage is applied during 6, white display is performed. At this time, the liquid crystal molecules are in a bend alignment state. As a result, light from the backlight passes through a layer including a pair of polarizers (a layer including a first polarizer 10603, and a layer including a second polarizer 10604) which are arranged so as to be crossed Nicols. It is possible to display a predetermined image. Note that FIG.
The liquid crystal display device having the configurations of A1) and (A2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, FIG.
1) The liquid crystal display device having the configuration as in (A2) can perform full-color display by field sequential driving without providing a color filter.

In the OCB mode as shown in FIGS. 52 (A1) and (A2), the alignment of liquid crystal molecules in the liquid crystal layer can be optically compensated so that the viewing angle dependence is small, and the contrast is increased by a layer including a pair of stacked polarizers. The ratio can be increased.

52 (B1) and (B2) show schematic views of liquid crystal in FLC mode and AFLC mode.

Similar to FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least a light-transmitting property. Then, on the first substrate 10601 side, the layer 10603 including the first polarizer is provided.
And a layer 10604 including a second polarizer is provided on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In the liquid crystal display device having the structure shown in FIGS. 52B1 and 52B1, the first electrode 106
No. 05 and the second electrode 10606 are applied with a voltage (referred to as a vertical electric field method).
As shown in 1), the display is white. At this time, the liquid crystal molecules are aligned horizontally in a direction deviated from the rubbing direction. Therefore, the light from the backlight passes through the layer including the pair of polarizers (the layer including the first polarizer 10603, and the layer including the second polarizer 10604) which are arranged so as to be crossed Nicols. It is possible to display a predetermined image.

Then, as shown in FIG. 52B2, the first electrode 10605 and the second electrode 1060
When no voltage is applied during 6, black display is performed. At this time, the liquid crystal molecules are aligned horizontally along the rubbing direction. Then, the light from the backlight cannot pass through the substrate, resulting in black display.

Note that a liquid crystal display device having a structure as shown in FIGS. 52B1 and 52B can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in FIGS. 52B1 and 52B can perform full-color display by field sequential driving without providing a color filter.

Known liquid crystal materials may be used for the FLC mode and the AFLC mode.

53A1 and 53A2 are schematic views of an IPS mode liquid crystal display device. The IPS mode is a mode in which liquid crystal molecules are always rotated in a plane with respect to a substrate, and an in-plane switching system in which electrodes are provided only on one substrate side is adopted.

The IPS mode is characterized in that the liquid crystal is controlled by a pair of electrodes provided on one substrate. Therefore, paired electrodes 10801 and 10802 are provided over the second substrate 10602. The pair of electrodes 10801 and 10802 may have a light-shielding property. Then, the layer 10603 including the first polarizer is stacked on the first substrate 10601 side, and the layer 10604 including the second polarizer is arranged on the second substrate 10602 side. Note that the layer 10603 containing the first polarizer and the layer 10604 containing the second polarizer may be arranged so as to be crossed Nicols.

In the liquid crystal display device having a structure as shown in FIGS. 53A1 and 53A2, the pair of electrodes 10 is formed.
When a voltage is applied to 801 and 10802, liquid crystal molecules are aligned along the lines of electric force deviated from the rubbing direction as shown in FIG. Then, the light from the backlight passes through the layer including the pair of polarizers (the layer including the first polarizer 10603, and the layer including the second polarizer 10604) arranged in a crossed Nicols state. It is possible to display a predetermined image.

Note that a liquid crystal display device having a structure as shown in FIGS. 53A1 and 53A can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in FIGS. 53A1 and 53A can perform full-color display by field sequential driving without providing a color filter.

Then, as shown in FIG. 53A2, when a voltage is not applied between the pair of electrodes 10801 and 10802, black display, that is, an off state is performed. At this time, the liquid crystal molecules are aligned horizontally along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, resulting in black display.

FIG. 55 shows an example of the pair of electrodes 10801 and 10802 which can be used in the IPS mode. In FIGS. 55A to 55D, the electrode 10801 is the electrode 10801a, and the electrode 1010.
801b, an electrode 10801c, and an electrode 10801d. In addition, the electrode 10802
Correspond to the electrode 10802a, the electrode 10802b, the electrode 10802c, and the electrode 10802d. In FIG. 55A, the electrode 10801a and the electrode 10802a have a wavy shape with undulations, and in FIG. 55B, the electrode 10801b and the electrode 10802b each have a concentric opening portion, and FIG. Then, the electrode 10801c and the electrode 10802c
55D has a comb-like shape and partially overlaps with each other. In FIG. 55D, the electrodes 10801d and 10802d have a comb-like shape and the electrodes are meshed with each other.

Besides the IPS mode, the FFS mode can also be used. In the IPS mode, paired electrodes are formed on the same insulating film, while in the FFS mode, the electrodes shown in FIGS.
As shown in 2), the pair of electrodes 10803 and 10804 may be formed on different insulating films.

When a voltage is applied to the pair of electrodes 10803 and 10804 in the liquid crystal display device having a structure illustrated in FIGS. 53B1 and 53B2, white display is performed as illustrated in FIG. It turns on. Then, the light from the backlight passes through the layer including the pair of polarizers (the layer including the first polarizer 10603, and the layer including the second polarizer 10604) arranged in a crossed Nicols state. It is possible to display a predetermined image.

Note that a liquid crystal display device having a structure as shown in FIGS. 53B1 and 53B2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in FIGS. 53B1 and 53B can perform full-color display by field sequential driving without providing a color filter.

Then, as shown in FIG. 53 (B2), when no voltage is applied between the pair of electrodes 10803 and 10804, black display, that is, an off state is performed. At this time, the liquid crystal molecules are arranged side by side and rotated in a plane. As a result, the light from the backlight cannot pass through the substrate, resulting in black display.

FIG. 56 shows an example of the pair of electrodes 10803 and 10804 which can be used in the FFS mode. In FIGS. 56A to 56D, the electrode 10803 is the electrode 10803a, and the electrode 10
803b, an electrode 10803c, and an electrode 10803d. Also, the electrode 10804
Correspond to the electrode 10804a, the electrode 10804b, the electrode 10804c, and the electrode 10804d. In FIG. 56A, the electrode 10803a has a bent dogleg shape.
4a may not be patterned in the pixel area. In FIG. 56B, the electrode 108
03b has a concentric shape, and the electrode 10804b does not have to be patterned in the pixel region. In FIG. 56C, the electrode 10803c has a comb-like shape and the electrodes are intermeshed with each other, and the electrode 10804c may not be patterned in the pixel region.
In FIG. 56D, the electrode 10803d has a comb-like shape, and the electrode 10804d does not need to be patterned in the pixel region.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d) are
It may have translucency. With the light-transmitting property, a transmissive display device having a large aperture ratio can be obtained.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d) are
It may have a light-shielding property or a reflective property. By having a light-blocking property or a reflective property, a reflective display device which does not require a backlight and consumes less power can be obtained.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d) are
It may have both a region having a light-transmitting property and a region having a light-shielding property or a reflective property. By having both areas, a transparent display with high display quality is displayed in a dark environment such as indoors, and a reflective display with low power consumption that does not require a backlight is displayed in a bright environment such as outdoors. A transflective display device can be obtained.

Known liquid crystal materials may be used for the IPS mode and the FFS mode.

As a liquid crystal mode that can be applied to the liquid crystal display device of the present embodiment, in addition to the above-mentioned liquid crystal mode, an ASM (Axially Symmetric aligned Micro-
cell mode, PDLC (Polymer Dispersed Liquid C)
There is a physical mode.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 9)
In this embodiment, a display panel structure and a peripheral structure of a display device which can carry out this embodiment will be described. In particular, a display panel (also referred to as a liquid crystal panel) configuration of a liquid crystal display device and peripheral configurations thereof will be described.

First, a simple structure of the liquid crystal panel will be described with reference to FIG. Also, FIG.
FIG. 7A is a top view of the liquid crystal panel.

In the liquid crystal panel illustrated in FIG. 57A, a pixel portion 20101, a scan line input terminal 20103, and a signal line input terminal 20104 are formed over a substrate 20100. Scan line input terminal 201
03, scanning lines extend in the row direction and are formed on the substrate 20100.
A signal line from 04 extends in the column direction and is formed on the substrate 20100. In addition, the pixel unit 2
In 0101, pixels 20102 are arranged in a matrix at the intersection of the scan line and the signal line. In addition, a switching element and a pixel electrode layer are arranged in the pixel 20102.

As shown in the liquid crystal panel of FIG. 57A, the scan line input terminal 20103 is provided on the substrate 20100.
Are formed on both sides in the row direction. The signal line input terminal 20104 is formed on one side of the substrate 20100 in the column direction. Further, the scan lines extending from one scan line input terminal 20103 and the scan lines extending from the other scan line input terminal 20103 are formed alternately.

In each of the pixels 20102 of the pixel portion 20101, the first terminal of the switching element is connected to the signal line and the second terminal is connected to the pixel electrode layer, so that each pixel 201
02 can be controlled independently by a signal input from the outside. The on / off of the switching element is controlled by the signal supplied to the scanning line.

Note that the pixels 20102 can be arranged at high density by arranging the scan line input terminals 20103 in both of the row directions of the substrate 20100. In addition, the signal line input terminal 20103
Is arranged in one of the column directions of the substrate 20100 to reduce the frame of the liquid crystal panel,
The area of the pixel portion 20101 can be increased.

Note that as the substrate 20100, as described above, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate having a stainless steel foil, or the like is used. Can be used.

As described above, a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, etc.), a thyristor, or a logic circuit combining them can be used as the switching element. ..

Note that when a TFT is used as a switching element, the gate of the TFT is connected to the scan line, the first terminal is connected to the signal line, and the second terminal is connected to the pixel electrode layer, so that each pixel 20102 is connected. Can be controlled independently by a signal input from the outside.

Note that the scan line input terminal 20103 may be arranged in one of the row directions of the substrate 20100. By arranging the scan line input terminal 20103 in one of the row directions of the substrate 20100, the frame of the liquid crystal panel can be small and the area of the pixel portion 20101 can be large.

The scanning line extending from one scanning line input terminal 20103 and the other scanning line input terminal 2
The scan line extending from 0103 may be common.

Note that the scan line input terminals 20103 may be arranged in both of the column directions of the substrate 20100. By arranging the scan line input terminals 20103 in both of the column directions of the substrate 20100, the pixels 20102 can be arranged at high density.

Note that a capacitor may be further formed in the pixel 20102. When a capacitor is provided in the pixel 20102, a capacitor line may be formed over the substrate 20100. When the capacitor line is formed over the substrate 20100, the first electrode of the capacitor is connected to the capacitor line and the second terminal is connected to the pixel electrode layer. In the case where a capacitor line is not formed over the substrate 20100, the first electrode of the capacitor element is connected to a scan line which is different from the pixel 20102 in which this capacitor element is arranged, and the second terminal is connected to the pixel electrode layer. Like

Here, although the liquid crystal panel shown in FIG. 57A has a structure in which signals supplied to the scan lines and the signal lines are controlled by an external driver circuit, as shown in FIG. COG (
The driver IC 20201 may be mounted on the substrate 20100 by a Chip on Glass method. As another configuration, as shown in FIG. 58B, TAB (Tape
The driver IC 20201 is connected to the FPC2 by the Automated Bonding method.
0200 (Flexible Printed Circuit) may be mounted.
Further, in FIG. 58, the driver IC 20201 is connected to the FPC 20200.

Note that the driver IC 20201 may be formed over a single crystal semiconductor substrate or may be formed over a glass substrate to form a circuit with a TFT.

Note that in the liquid crystal panel illustrated in FIG. 57A, the scan line driver circuit 20105 may be formed over the substrate 20100 as illustrated in FIG. Further, as illustrated in FIG. 57C, the scan line driver circuit 20105 and the signal line driver circuit 20106 may be formed over the substrate 20100.

Note that the scan line driver circuit 20105 and the scan line driver circuit 20105 are composed of a large number of N-channel transistors and a large number of P-channel transistors. However, it may be composed of only a large number of N-channel transistors or may be composed of only a large number of P-channel transistors.

Next, details of the pixel 20102 will be described with reference to circuit diagrams of FIGS.

A pixel 20102 in FIG. 59A includes a transistor 20301, a liquid crystal element 20302, and a capacitor 20303. A gate of the transistor 20301 is connected to the wiring 20305 and a first terminal is connected to the wiring 20304. A first electrode of the liquid crystal element 20302 is connected to the counter electrode 20307, and a second electrode thereof is connected to the second terminal of the transistor 20301. A first electrode of the capacitor 20303 is connected to the capacitor line 20306, and a second electrode thereof is connected to a second terminal of the transistor 20301.

Note that the wiring 20304 is a signal line, the wiring 20305 is a scanning line, and the capacitor line 2030.
Reference numeral 6 is a capacitance line. The transistor 20301 is a switching transistor and may be a P-channel transistor or an N-channel transistor. In addition, the liquid crystal element 2
0302 is a TN (Twisted Nematic) mode as an operation mode, and IPS.
(In-Plane-Switching) mode, FFS (Fringe Field)
Switching mode, MVA (Multi-domain Vertical)
Alignment mode, PVA (Patterned Vertical Al)
igment), ASM (Axially Symmetric aligned M)
micro-cell) mode, OCB (Optical Compensated Bi)
refrence mode, FLC (Ferroelectric Liquid)
Crystal mode, AFLC (Anti Ferroelectric Liquid)
id Crystal) or the like can be used.

A video signal and a scan signal are input to the wiring 20304 and the wiring 20305, respectively. The video signal is an analog voltage signal, and the scanning signal is an H level or L level digital voltage signal. However, the video signal may be a current signal or a digital signal. Further, the H level and the L level of the scan signal may be any potential with which the transistor 20301 can be turned on and off.

A constant power supply voltage is supplied to the capacitor line 20306. However, a pulsed signal may be supplied.

The operation of the pixel 20102 in FIG. 59A will be described. First, when the wiring 20305 is at the H level, the transistor 20301 is turned on, and the video signal is turned on from the wiring 20304. The second electrode of the liquid crystal element 20302 and the capacitor 2030 are transmitted through the transistor 20301.
3 to the second electrode. Then, the capacitor 20303 holds the potential difference between the potential of the wiring 203076 and the potential of the video signal.

Next, when the wiring 20305 becomes L level, the transistor 20301 is turned off and the wiring 20305
304 is electrically disconnected from the second electrode of the liquid crystal element 20302 and the second electrode of the capacitor 20303. However, since the capacitor 20303 holds the potential difference between the potential of the wiring 203076 and the potential of the video signal, the potential of the second electrode of the capacitor 20303 can maintain the same potential as that of the video signal.

Thus, in the pixel 20102 in FIG. 59A, the potential of the second electrode of the liquid crystal element 20302 can be kept at the same potential as the video signal, and the liquid crystal element 20302 can be kept at a transmittance corresponding to the video signal.

Although not shown, the capacitor element 20303 is not always necessary as long as the liquid crystal element 20302 has a capacity component capable of holding a video signal.

Note that as in FIG. 59B, the first electrode of the liquid crystal element 20302 may be connected to the capacitor line 20306. For example, when the liquid crystal mode of the liquid crystal element 20302 is the FFS mode, the liquid crystal element 20302 has the structure of FIG.

Note that, as in FIG. 60, the first electrode of the capacitor 20303 may be connected to the wiring 20305a in the preceding row. Note that when the wiring 20305a is the scan line in the n-th row (n is a positive integer), the wiring 20305b is the scan line in the (n + 1) -th row. Similarly, the transistor 20301a
, The pixel 20102a and the capacitive element 20303a are elements in the n-th row, the transistor 2
Reference numeral 0301b, the pixel 20102b, and the capacitor 20303b are elements in the (n + 1) th row. Thus, the first electrode of the capacitor 20303b is connected to the wiring 20305a in the front row, so that the number of wirings can be reduced. Therefore, the pixels 20102a and 20102 of FIG.
b can increase the aperture ratio.

Next, a more detailed configuration of the liquid crystal panel than the configuration of the liquid crystal panel described with reference to FIGS. 57 and 58 will be described with reference to FIG. 61. Specifically, a TFT substrate, a counter substrate,
The structure of a liquid crystal panel having a liquid crystal layer sandwiched between a counter substrate and a TFT substrate will be described. Further, FIG. 61A is a top view of the liquid crystal panel. FIG. 61 (B) corresponds to FIG.
It is sectional drawing in line CD of A). Note that FIG. 61B is a cross-sectional view of the case where a top-gate transistor in which a crystalline semiconductor film (polysilicon film) is used as a semiconductor film is formed over the substrate 20100.

In the liquid crystal panel illustrated in FIG. 61A, a pixel portion 20101, a scan line driver circuit 20105a, a scan line driver circuit 20105b, and a signal line driver circuit 20106 are formed over a substrate 20100. Pixel portion 20101, scan line driver circuit 20105a, scan line driver circuit 20105
b and the signal line driver circuit 20106 are sealed between the substrate 20100 and the counter substrate 20515 by a sealant 20516. In addition, by the TAB method, FPC2051
8 and the IC chip 20530 are arranged on the substrate 20100.

A cross-sectional structure taken along line CD in FIG. 61A will be described with reference to FIG.
A pixel portion 20101 and its peripheral driver circuit portion (scanning line circuit 20105) are formed over a substrate 20100.
a, a scan line driver circuit 20105b, and a signal line driver circuit 20106) are formed, here, the driver circuit region 20525 (scan line driver circuit 20105a and scan line driver circuit 20105b) and the pixel region 20526 (pixel portion 20101) are formed. ) And are shown.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. As the insulating film 20501, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Si
A single layer of an insulating film such as OxNy) or a laminated structure having at least two films of these films may be used.

Note that it is preferable to use a silicon oxide film in a portion in contact with the semiconductor. As a result, electron traps in the base film and hysteresis of transistor characteristics can be suppressed. Also,
At least one film containing a large amount of nitrogen is preferably arranged as the base film. Thereby, impurities from the glass can be reduced.

Next, a semiconductor layer 20502 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like.

Next, the insulating layer 2 is formed as a gate insulating film over the insulating film 20501 and the semiconductor layer 20502.
0503 is formed.

Note that as the insulating layer 20503, a single layer or a stacked structure of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used. Semiconductor layer 20502
The insulating layer 20503 which is in contact with is preferably a silicon oxide film. This is because the silicon oxide film reduces the trap level at the interface with the semiconductor layer 20502. When the gate electrode is made of Mo, the gate insulating film in contact with the gate electrode is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo. Here, the insulating layer 20503
As a silicon oxynitride film with a thickness of 115 nm (composition ratio Si = 3
2%, O = 59%, N = 7%, H = 2%).

Next, a conductive layer 20504 is formed over the insulating layer 20503 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like.

Note that the conductive layer 20504 is formed of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, A.
Examples include g, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements. Alternatively, they may be formed by stacking these elements or alloys of these elements. Here, the gate electrode is formed of Mo. Mo is preferable because it is easily etched and resistant to heat.

Note that in the semiconductor layer 20502, the semiconductor layer 20502 is doped with an impurity element using the conductive layer 20504 or a resist as a mask, so that a channel formation region and impurity regions to be a source region and a drain region are formed.

The impurity region may have a high concentration region and a low concentration region formed by controlling the impurity concentration.

Note that the conductive layer 20504 of the transistor 20521 has a dual gate structure.
The transistor 20521 has a dual-gate structure so that the transistor 20521 has a dual-gate structure.
The off-state current can be reduced. The dual gate structure is a structure having two gate electrodes. However, a plurality of gate electrodes may be provided over the channel region of the transistor.

Next, an insulating layer 20505 is formed as an interlayer film over the insulating layer 20503 and the conductive layer 20504.
Are formed.

Note that as the insulating layer 20505, an organic material, an inorganic material, or a stacked structure thereof can be used. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide or aluminum oxide having a nitrogen content higher than oxygen content, diamond like carbon (DLC), polysilazane, nitrogen content It can be formed of a material selected from carbon (CN), PSG (phosphorus glass), BPSG (phosphorus glass), alumina, and other substances including an inorganic insulating material. Further, an organic insulating material may be used, and the organic material may be photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimide amide, resist or benzocyclobutene, siloxane resin or the like can be used. .. The siloxane resin means Si-
It corresponds to a resin containing an O-Si bond. Siloxane has a skeleton structure formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used. A fluoro group may be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Note that contact holes are selectively formed in the insulating layer 20503 and the insulating layer 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor.

Next, a conductive film 20506 is formed over the insulating layer 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like.

Note that the material of the conductive film 20506 is Ti, Mo, Ta, Cr, W, Al, N.
There are d, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge and the like, and alloys of these elements. Alternatively, a stacked structure of these elements or an alloy of these elements can be used.

Note that in the portion where the contact hole is formed in the insulating layer 20503 and the conductive layer 20504, the conductive film 20506 is connected to the impurity region of the semiconductor layer 20502 of the transistor.

Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505.

Note that the insulating layer 20507 is preferably formed using an organic material because it preferably has high flatness and coverage. Note that the insulating layer 20507 may have a multi-layer structure, and an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride).

Note that contact holes are selectively formed in the insulating layer 20507. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521.

Next, a conductive layer 20508 is formed over the insulating layer 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like.

Note that as the conductive layer 20508, a transparent electrode which transmits light and a reflective electrode which reflects light can be used.

In the case of a transparent electrode, for example, indium tin oxide (indium oxide mixed with tin oxide)
ITO) film, indium tin oxide (ITSO) film in which indium tin oxide (ITO) is mixed with silicon oxide, indium zinc oxide (IZO) in which zinc oxide is mixed with indium oxide
) Film, a zinc oxide film, a tin oxide film, or the like can be used. IZO is I
The transparent conductive material is formed by sputtering using a target in which TO is mixed with 2 to 20 wt% of zinc oxide (ZnO), but is not limited thereto.

In the case of a reflective electrode, for example, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, A
It is possible to use u, Pt, Nb, Si, Zn, Fe, Ba, Ge or the like, or an alloy thereof. In addition, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, Al is Ti,
A three-layer laminated structure sandwiched by metals such as Mo, Ta, Cr and W may be used.

Next, over the insulating layer 20507 and the conductive layer 20508 formed over the insulating layer 20507,
An insulating layer 20509 is formed as an alignment film.

Next, a sealant 20516 is formed on the peripheral portion of the pixel portion 20101, or the peripheral portion of the pixel portion 20101 and its peripheral driving circuit portion by an inkjet method or the like.

Next, the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are attached to the substrate 20100 with a spacer 20531, and the liquid crystal layer 20510 is provided in the gap. It is arranged.

Note that the substrate 20115 may function as a counter substrate. The insulating film 20514 is
It may function as a black matrix (light-shielding film). Further, the insulating film 20513 may function as a color filter. Further, the spacer 20531 may be provided by a method in which particles of several μm are scattered and provided, or may be formed by forming a resin film over the entire surface of the substrate and then etching the resin film. The conductive film 20512 may function as a counter electrode. As the conductive film 20512, the same material as the conductive layer 20508 can be used.
Further, the insulating film 20511 may function as an alignment film.

Note that an insulating film 20532 may be formed as a planarizing film between the insulating film 20513, the insulating film 20514, and the conductive film 20512. However, the insulating film 20532 is not shown in FIG.

Note that a known liquid crystal can be freely used for the liquid crystal layer 20510. For example, a ferroelectric liquid crystal or antiferroelectric liquid crystal may be used as the liquid crystal layer 20510. Further, the liquid crystal driving method is TN (Twisted Nematic) mode, IPS (
In-Plane-Switching mode, FFS (Fringe Field)
Switching mode, MVA (Multi-domain Vertical)
Alignment mode, PVA (Patterned Vertical Ali)
GMment), ASM (Axially Symmetric aligned Mi)
cro-cell mode, OCB (Optical Compensated Bir)
fringe mode, FLC (Ferroelectric Liquid)
Crystal mode, AFLC (Anti Ferroelectric Liquid)
d Crystal) or the like can be used freely.

Next, the conductive film 205 electrically connected to the pixel portion 20101 and its peripheral driver circuit portion.
The FPC 20200 is arranged on the surface of the FPC 33 via the anisotropic conductive layer 20517. Further, an IC chip is arranged over the FPC 20200 with an anisotropic conductor layer 20517 interposed therebetween. That is, the FPC 20200, the conductive film 20533, and the IC chip 20530 are electrically connected.

Note that the conductive film 20533 has a function of transmitting a signal and a potential input from the FPC 20200 to pixels and peripheral circuits. The conductive film 20533 may be similar to the conductive film 20506, may be similar to the conductive layer 20504, or may be similar to the impurity region of the semiconductor layer 20502. Alternatively, a combination of at least two layers may be used.

Note that the IC chip 20530 can effectively utilize the substrate area by forming a functional circuit (a memory or a buffer).

61A and 61B, the scanning line driving circuit 20105a and the scanning line driving circuit 2 are provided.
The structure in which the 0105b and the signal line driver circuit 20106 are formed over the substrate 20100 has been described. As shown in the liquid crystal panel of FIG. 62A, a driver circuit corresponding to the signal line driver circuit 20106 is formed in the driver IC 20601. Then, it may be configured to be mounted on the liquid crystal panel by a COG method or the like. By forming the signal line driver circuit 20106 in the driver IC 20601, power saving can be achieved. When the driver IC 20601 is a semiconductor chip such as a silicon wafer, the liquid crystal panel in FIG. 62A can have higher speed and lower power consumption.

Similarly, as shown in the liquid crystal panel in FIG. 62B, driver circuits corresponding to the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 20106 are provided in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively. It may be formed and mounted on a liquid crystal panel by a COG method or the like. Further, cost reduction can be achieved by forming driver circuits corresponding to the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 20106 in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively.

Although the transistor 20521 has a dual gate structure, the pixel region 205 in FIG.
As shown in FIG. 26, the transistor 20521 may have a single gate structure. However, FIG. 63 shows only the pixel region 20526.

Next, a cross-sectional view of the case where a bottom-gate transistor is formed over the substrate 20100 is described with reference to FIGS. However, FIG. 64 shows only the pixel region 20526.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive layer 20504 is formed over the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that the transistor 2052
The first conductive layer 20504 has a dual gate structure. This is because, as already described, the transistor 20521 has a dual gate structure,
The off current of 1 can be reduced. Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504. Next, on the insulating layer 20503,
The semiconductor layer 20502 is formed by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502 is formed over the semiconductor layer 20502 using a resist as a mask.
502 is doped with an impurity element, and a channel formation region and impurity regions to be a source region and a drain region are formed. The impurity region may have a high concentration region and a low concentration region formed by controlling the impurity concentration. Next, an insulating layer 20505 is formed as an interlayer film over the insulating layer 20503 and the semiconductor layer 20502. Note that contact holes are selectively formed in the insulating layer 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, the insulating layer 2050
5, a conductive film 20506 is formed as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like. Note that the insulating layer 205
In the portion where the contact hole 05 is formed, the conductive film 20506 is connected to the impurity region of the semiconductor layer 20502 of the transistor. Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20505 and the conductive film 20506. Note that contact holes are selectively formed in the insulating layer 20507. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed over the insulating layer 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, the insulating film 20
A liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that in FIG. 64, the transistor 20521 has a dual gate structure. However,
As shown in the pixel region 20526 of FIG. 65, the transistor 20521 may have a single gate structure.

Next, a cross-sectional view of the case where a double-gate transistor is formed over the substrate 20100 is described with reference to FIGS. However, FIG. 66 shows only the pixel region 20526.

Note that a double-gate transistor refers to a structure in which gate electrodes are provided above and below a semiconductor film, respectively. In addition, the double-gate transistor has twice as much current as the top-gate transistor and the bottom-gate transistor with the same size and the same applied voltage. That is, the double-gate transistor can flow more current with a smaller transistor size.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive layer 20504a is formed over the insulating film 20501 as a first gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 205
For 04a, the same material and structure as the conductive layer 20504 can be used. next,
As the first gate insulating film, the insulating layer 2 is formed over the insulating film 20501 and the conductive layer 20504a.
0503a is formed. Note that the insulating layer 20503a can be formed using a material and a structure similar to those of the insulating layer 20503. Next, a semiconductor layer 20502 is formed over the insulating layer 20503a by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20503b is formed as a second gate insulating film over the insulating layer 20503a and the semiconductor layer 20502. Note that the insulating layer 20503b is the insulating layer 20.
The same material and structure as 503 can be used. Next, a conductive layer 20504b is formed over the insulating layer 20503b as a second gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 20504b is the conductive layer 2
Materials and structures similar to 0504 can be used. Note that the semiconductor layer 20502
In the semiconductor layer 20502, an impurity element is doped with the conductive layer 20504b or a resist as a mask to form a channel formation region and impurity regions to be a source region and a drain region. The impurity region may have a high concentration region and a low concentration region formed by controlling the impurity concentration. Note that the insulating layer 20503 is formed over the semiconductor layer 20502.
b and the conductive layer 20504b are formed, the semiconductor layer 2050 is formed using the resist as a mask.
2 may be doped with an impurity element to form a channel formation region and impurity regions to be a source region and a drain region. Next, the insulating layer 20503b and the conductive layer 20 are formed.
An insulating layer 20505 is formed as an interlayer film over 504b. Note that the insulating layer 205
Contact holes are selectively formed in the insulating layer 03505 and the insulating layer 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed over the insulating layer 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like. In addition,
In the portion where the contact holes of the insulating layer 20503 and the insulating layer 20505 are formed,
The conductive film 20506 is connected to the impurity region of the semiconductor layer 20502 of the transistor. Next, the insulating layer 205 is formed as a planarization film over the insulating layer 20505 and the conductive film 20506.
07 are formed. Note that contact holes are selectively formed in the insulating layer 20507. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, the liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that in FIGS. 61 and 63 to 66, cross-sectional views in the case where the insulating layer 20507 is formed as a flat film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505 are described. .. However, the insulating layer 20507 is not always necessary as shown in FIG.

Note that the cross-sectional view illustrated in FIG. 67 illustrates the case of a top-gate transistor, but the same applies to the case of a bottom-gate transistor and a double-gate transistor.

Next, an amorphous semiconductor film (amorphous silicon film) is formed as a semiconductor film on the substrate 20100.
A cross-sectional view in the case where a transistor including is formed is described with reference to FIGS. The cross-sectional view illustrated in FIG. 68 is a cross-sectional view of a transistor having an inverted staggered channel etch structure.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive layer 20504 is formed over the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504. Next, a semiconductor layer 20502 is formed over the insulating layer 20503 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502 has a first semiconductor film and a second semiconductor film, and the second semiconductor film is formed over the first semiconductor film. Further, the first semiconductor film and the second semiconductor film may be continuously formed and simultaneously patterned by the photolithography method. Further, the second semiconductor film contains an impurity element. Next, a conductive film 20506 is formed over the insulating layer 20503 and the semiconductor layer 20502 by a photolithography method, an inkjet method, a printing method, or the like. In addition,
The semiconductor layer 20502 is etched using the conductive film 20506 as a mask to have a channel formation region and impurity regions to be a source region and a drain region. That is, the second semiconductor film containing the impurity element is removed in the channel region. However, the semiconductor layer 20502 may be etched using a resist for etching the conductive film 20506 as a mask. Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20503, the semiconductor layer 20502, and the conductive film 20506. Note that contact holes are selectively formed in the insulating layer 20507. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed over the insulating layer 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, the insulating film 2
A liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 0514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that although the transistor with a channel-etch structure is described, an insulating film 21301 may be provided over the semiconductor layer 20502 as shown in FIG. The insulating film 21301 is formed between the first semiconductor film and the second semiconductor film. The semiconductor layer 20502 is the conductive film 20.
When forming 506, it is etched at the same time.

Note that the transistor 20521 in FIG. 68 is called a channel-etch structure and the transistor 20521 in FIG. 69 is called a channel-protection structure.

Next, a cross-sectional view of the case where a top-gate transistor including an amorphous semiconductor film as a semiconductor film is formed over the substrate 20100 is described with reference to FIGS.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive film 20506 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Next, a semiconductor layer 20502a is formed over the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502a can be formed using a material and a structure similar to those of the semiconductor layer 20502. In addition, the semiconductor layer 20502a contains an impurity element. Next, a semiconductor layer 20502b is formed over the insulating film 20501 and the semiconductor layer 20502a by a photolithography method, an inkjet method, a printing method, or the like. The semiconductor layer 2
For 0502b, a material and a structure similar to those of the semiconductor layer 20502 can be used.
Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501, the semiconductor layer 20502b, and the conductive film 20506. Next, a conductive layer 20504 is formed over the insulating layer 20503 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, the insulating layer 20507 is formed as a planarizing film over the insulating layer 20503 and the conductive layer 20504 formed over the insulating layer 20503. Note that contact holes are selectively formed in the insulating layer 20507. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed over the insulating layer 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, the liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that in FIGS. 69 and 70, the cross-sectional views in the case where the insulating layer 20507 is formed as a flat film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505 are described. However, the insulating layer 20507 is not always necessary as shown in FIG.

Note that the cross-sectional view illustrated in FIG. 71 illustrates the case of a transistor with an inverted staggered channel etch structure, but the same applies to the case of a transistor with an inverted staggered channel protection structure. 71 shows a case of an inverted staggered transistor,
A top gate type transistor may be used. 72 and 73 are cross-sectional views of a top-gate transistor.

In the case of the cross-sectional view in FIG. 72, the conductive layer 2 is formed over the insulating film 20501 and the conductive film 20506 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like.
0508 is formed. The conductive layer 20508 is formed after the conductive film 20506 is formed and before the insulating layer 20503 is formed.

Note that in the case of the cross-sectional view in FIG. 73, a conductive layer 20508 is formed over the insulating film 20501 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. The conductive layer 20508 is formed after the insulating film 20501 is formed.

Next, a cross-sectional view of the semi-transmissive liquid crystal panel will be described with reference to FIG.

Note that the cross-sectional view of FIG. 74 is a cross-sectional view of a liquid crystal panel when a transistor uses a polycrystalline semiconductor as a semiconductor film. However, the transistor may be a bottom gate type or a double gate type. The gate electrode of the transistor may have a single gate structure,
It may have a dual gate structure.

Note that FIG. 74 is similar to FIG. 63 until the conductive film 20506 is formed. Therefore, a process and a structure after the conductive film 20506 is formed will be described.

First, a photolithography method, an inkjet method, a printing method, or the like is used as a film for thinning the thickness (so-called cell gap) of the liquid crystal layer 20510 over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505. Thus, the insulating film 21801 is formed. Note that the insulating film 21801 is preferably formed using an organic material because it preferably has high flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to have a multilayer structure. Note that contact holes are selectively formed in the insulating film 21801. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508a is formed over the insulating layer 20505 and the insulating layer 20507 as a first pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that as the conductive layer 20508a, a transparent electrode which transmits light similar to that of the conductive layer 20508 can be used. Next, a conductive layer 20508b is formed over the conductive layer 20508a as a second pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that as the conductive layer 20508b, a reflective electrode which reflects light similar to that of the conductive layer 20508 can be used. Note that a region where the conductive layer 20508b is formed is referred to as a reflective region. Further, among the regions where the conductive layer 20508a is formed, a region where the conductive layer 20508b is not formed over the conductive layer 20508a is referred to as a transmissive region. Next, an insulating layer 20509 is formed as an alignment film over the insulating film 21801, the conductive layers 20508a, and 20508b. Next, the liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Although the conductive layer 20508b is formed after the conductive layer 20508a is formed in FIG. 74, the conductive layer 20508b is formed after the conductive layer 20508b is formed as shown in FIG.
a may be formed.

74 and 75, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed below the conductive layer 20508a and the conductive layer 20508b. But,
An insulating film 22001 may be formed on the counter substrate 20515 side as shown in FIG. The insulating film 22001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap) similarly to the insulating film 21801.

Note that although the case where the insulating layer 20507 is formed as the planarization film is described in FIG. 76, the insulating layer 20507 may not be formed as illustrated in FIG. 77. In the case of FIG. 77, the conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that the insulating film 22001 may be formed between the conductive film 20512 and the insulating film 20511, or may be formed between the insulating film 20511 and the liquid crystal layer 20510.

Next, FIG. 78 shows a sectional view of a semi-transmissive liquid crystal panel in which a polycrystalline semiconductor is used as a semiconductor film of a transistor.

The cross-sectional view of FIG. 78 is a cross-sectional view of a liquid crystal panel having a transistor using an inverted stagger type channel etch structure. However, the transistor may be a top gate type or an inverted staggered type channel protection structure.

Note that FIG. 78 is similar to FIG. 78 until the conductive film 20506 is formed. Therefore, a process and a structure after the conductive film 20506 is formed will be described.

First, the liquid crystal layer 20 is formed over the semiconductor layer 20502, the insulating layer 20503, and the conductive film 20506.
As a layer for reducing the thickness of 510 (so-called cell gap), an insulating film 22201 is formed by a photolithography method, an inkjet method, a printing method, or the like. Note that the insulating film 22201 is preferably formed using an organic material because it preferably has high flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to have a multilayer structure. The insulating film 22
A contact hole is selectively formed in 201. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521. Next, the insulating layer 205
03 and the insulating film 22201, a conductive layer 20508a is formed as a first pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, a conductive layer 20508b is formed over the conductive layer 20508a as a second pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 20508
The area where b is formed is called a reflection area. Further, among the regions where the conductive layer 20508a is formed, a region where the conductive layer 20508b is not formed over the conductive layer 20508a is referred to as a transmissive region. Next, over the insulating film 22201, the conductive layers 20508a and 20508b,
An insulating layer 20509 is formed as an alignment film. Next, the insulating film 20514 and the insulating film 2
0513, a conductive film 20512, an insulating film 20511 and the like are formed on the counter substrate 20515.
And a liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the substrate 20100.

78, the conductive layer 20508b is formed after the conductive layer 20508a is formed, but as shown in FIG. 79, the conductive layer 20508b is formed after the conductive layer 20508b is formed.
a may be formed.

78 and 79, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed below the conductive layer 20508a and the conductive layer 20508b. But,
An insulating film 22001 may be formed on the counter substrate 20515 side as shown in FIG. The insulating film 22001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap) similarly to the insulating film 22201.

Note that although the case where the insulating layer 20507 is formed as the planarization film is described in FIGS. 79 and 80, the insulating layer 20507 may not be formed as illustrated in FIG. 81. In the case of FIG. 81, the conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that in FIGS. 61 and 63 to 81, a pair of electrodes for applying a voltage to the liquid crystal layer 20510 (
An example in which the conductive layer 20508 and the conductive film 20512) are formed over different substrates is shown. However, the conductive film 20512 may be provided over the substrate 20100. In this way, the IPS (In-Plane-Switching) mode can be used as a liquid crystal driving method. Further, depending on the liquid crystal layer 20510, one or both of the two alignment films (the insulating layer 20509 and the insulating film 20511) can be omitted.

Although the conductive layer 20508 (conductive layer 20508b) is formed as the reflective pixel electrode in FIGS. 61 and 63 to 81, the conductive layer 20508 preferably has an uneven shape. This is because the reflective pixel electrode reflects external light to perform display. This is because the external light that has entered the reflective electrode can be efficiently utilized and diffused reflected by the reflective electrode in order to increase the display brightness. Note that the film below the conductive layer 20508 (the insulating layer 20
505, the insulating layer 20507, the insulating film 21801, the insulating film 22201, or the like) has an uneven shape, so that the conductive layer 20508 has an uneven shape.

Subsequently, a liquid crystal display device having the liquid crystal panel described in FIGS. 61 to 81 will be described with reference to FIG.

First, the liquid crystal display device illustrated in FIG. 82 is provided with a backlight unit 22601, a liquid crystal panel 22607, a layer 22608 containing a first polarizer, and a layer 22609 containing a second polarizer.

Note that the liquid crystal panel 22607 can be similar to that described in this embodiment. Further, although the liquid crystal panel of the present embodiment has been described as an active type structure in which a switching element is provided in each pixel, the liquid crystal panel of FIG. 82 may have a passive type structure.

The structure of the backlight unit 22601 will be described. Backlight unit 226
01 is a diffusion plate 22602, a light guide plate 22603, a reflection plate 22604, a lamp reflector 2
2605 and a light source 22606. A cold cathode tube, a hot cathode tube, a light emitting diode, an inorganic EL or an organic EL is used as the light source 22606.
Reference numeral 6 has a function of emitting light as necessary. The lamp reflector 22605 is a light source 2260.
It has a function of efficiently guiding the fluorescent light from 6 to the light guide plate 22603. The light guide plate 22603 has a function of totally reflecting fluorescence and guiding light to the entire surface. The diffusion plate 22602 has a function of reducing unevenness in brightness. The reflection plate 22604 extends downward from the light guide plate 22603 (the liquid crystal panel 2).
It has a function of reflecting and reusing light leaking in the direction opposite to 2607).

Note that by disposing a prism sheet between the diffusion plate 22602 and the layer 22609 including the second polarizer, the liquid crystal display device of this embodiment can improve the brightness of the screen of the liquid crystal panel.

A control circuit for adjusting the luminance of the light source 22606 is connected to the backlight unit 22601. The brightness of the light source 22606 can be adjusted by supplying a signal from the control circuit.

A layer 22609 including a second polarizer is provided between the liquid crystal panel 22607 and the backlight unit 22601, and the liquid crystal panel 2 in a direction opposite to the backlight unit 22601 is provided.
2607 is also provided with the layer 22608 including the first polarizer.

Note that the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be crossed Nicols when the liquid crystal element of the liquid crystal panel 22607 is driven in the TN mode. Further, the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be crossed Nicols when the liquid crystal element of the liquid crystal panel 22607 is driven in the VA mode. In addition, a layer 22608 including a first polarizer and a layer 226 including a second polarizer
09, when the liquid crystal element of the liquid crystal panel 22607 is driven in the IPS mode and the FFS mode, the liquid crystal panel 22607 may be arranged in a crossed Nicols or may be arranged in a parallel Nicols.

A phase difference plate may be provided between the liquid crystal panel 22607 and either or both of the layer 22608 including the first polarizer and the layer 22609 including the second polarizer.

As shown in FIG. 85, the layer 22609 including the second polarizer and the backlight unit 2 are provided.
By arranging a slit (grating) 22610 between the liquid crystal display device and the liquid crystal display device 2601, the liquid crystal display device of this embodiment can perform three-dimensional display.

The slit 22610 having an opening arranged on the backlight unit side transmits light incident from the light source in a stripe shape and transmits the light to the display device. This slit 2261
With 0, parallax can be created in both eyes of the viewer on the viewing side, and the viewer simultaneously sees only the pixels for the right eye with the right eye and only the pixels for the left eye with the left eye. Therefore, the viewer can see the three-dimensional display. That is, the light given a specific viewing angle by the slit 22610 passes through the pixels corresponding to each of the right-eye image and the left-eye image,
The right-eye image and the left-eye image are separated into different viewing angles, and three-dimensional display is performed.

When an electronic device such as a television set or a mobile phone is manufactured using the liquid crystal display device in FIG. 85, a highly functional and high-quality electronic device capable of three-dimensional display can be provided.

Subsequently, a detailed configuration of the backlight will be described with reference to FIG. The backlight is provided in the liquid crystal display device as a backlight unit having a light source, and the light source is surrounded by a reflection plate in order to scatter light efficiently.

As shown in FIG. 84 (A), the backlight unit 22852 includes a cold cathode tube 2 as a light source.
2801 can be used. Further, a lamp reflector 22832 can be provided in order to efficiently reflect the light from the cold cathode fluorescent lamp 22801. The cold cathode fluorescent lamp 22801 is often used for a large-sized display device. This is due to the intensity of the brightness from the cold cathode tube. Therefore, the backlight unit having a cold cathode tube can be used for a display of a personal computer.

As shown in FIG. 84B, the backlight unit 22852 can use a light emitting diode 22802 (LED) as a light source. For example, white light emitting diodes 22802 (W) are arranged at predetermined intervals. In addition, the light emitting diode 22802 (W) 22
A lamp reflector 22832 can be provided to efficiently reflect the light from 802.

In addition, as shown in FIG. 84C, the backlight unit 22852 is used as a light source for each color R.
GB light emitting diodes 22803, 22804, 22805 can be used. By using the light emitting diodes 22803, 22804, and 22805 of RGB for each color, color reproducibility can be improved as compared with only the light emitting diode 22802 (W) that emits white. In addition, in order to efficiently reflect the light from the light emitting diode, the lamp reflector 22
832 can be provided.

Further, as shown in FIG. 84 (D), light emitting diodes 2280 for each color RGB are used as a light source.
In the case of using 3, 22804, 22805, it is not necessary to make them the same in number and arrangement.
For example, a plurality of colors with low emission intensity (for example, green) may be arranged.

Further, a light emitting diode 22802 that emits white light and a light emitting diode 2280 for each color RGB are provided.
3, 22804, 22805 may be used in combination.

When the field sequential mode is applied in the case of having the RGB light emitting diodes, color display can be performed by sequentially lighting the RGB light emitting diodes according to time.

The use of the light emitting diode has high brightness and thus is suitable for a large-sized display device. In addition, since the color purity of each of the RGB colors is good, the color reproducibility is superior to that of a cold cathode tube, and the arrangement area can be reduced. Therefore, when the display device is adapted to a small display device, a narrow frame can be achieved.

Further, it is not always necessary to arrange the light source as the backlight unit shown in FIG. For example, when a large-sized display device is equipped with a backlight having a light emitting diode, the light emitting diode can be arranged on the back surface of the substrate. At this time, the light emitting diodes can maintain a predetermined interval, and the light emitting diodes of each color can be sequentially arranged. The color reproducibility can be improved by arranging the light emitting diodes.

Next, an example of a layer including a polarizer (also referred to as a polarizing plate or a polarizing film) is described with reference to FIG.

The polarizing film 23000 of FIG. 86 includes a protective film 23001 and a substrate film 23002.
, PVA polarizing film 23003, substrate film 23004, adhesive layer 23005, and release film 23006.

The PVA polarizing film 23003 has a function of producing light only in a certain vibration direction (linearly polarized light). Specifically, the PVA polarizing film 23003 includes molecules (polarizers) having electron densities that are significantly different in the vertical and horizontal directions. The PVA polarizing film 23003 can produce linearly polarized light by aligning the directions of molecules in which the electron densities differ greatly in the vertical and horizontal directions.

As an example, the PVA polarizing film 23003 is made of polyvinyl alcohol (Poly V).
A polymer film of (inyl Alcohol) is doped with an iodine compound and the PVA film is pulled in a certain direction to obtain a film in which iodine molecules are aligned in a certain direction. Then, the light parallel to the long axis of the iodine molecule is absorbed by the iodine molecule. Further, for high durability and high heat resistance, a dichroic dye may be used instead of iodine. It is desirable that the dye is used in a liquid crystal display device that is required to have durability and heat resistance, such as a vehicle-mounted LCD and a projector LCD.

The PVA polarizing film 23003 is a film (substrate film 23002) whose both sides are base materials.
The reliability can be increased by sandwiching it with the substrate film 3604). Further, the PVA polarizing film 23003 may be sandwiched by highly transparent and highly durable triacetylose (TAC) films. Note that the substrate film and the TAC film function as a protective layer of the polarizer included in the PVA polarizing film 23003.

On one of the substrate films (substrate film 23004), a pressure-sensitive adhesive layer 23005 to be attached to the glass substrate of the liquid crystal panel is attached. The pressure-sensitive adhesive layer 23005 is formed by applying a pressure-sensitive adhesive to the substrate film (substrate film 23004) on one side. Further, the pressure-sensitive adhesive layer 23005 is provided with a release film 23006 (separate film).

The other substrate film (substrate film 23002) is provided with a protective film.

A hard coat scattering layer (anti-glare layer) may be provided on the surface of the polarizing film 23000. Since the hard coat scattering layer has fine irregularities formed on the surface by AG treatment and has an antiglare function for scattering external light, reflection of external light on the liquid crystal panel and surface reflection can be prevented.

Further, a plurality of optical thin film layers having different refractive indexes may be formed on the surface of the polarizing film 23000 (also referred to as anti-reflection treatment or AR treatment). The multilayered optical thin film layers having different refractive indexes can reduce the reflectance of the surface due to the interference effect of light.

Next, the operation of each circuit included in the liquid crystal display device will be described with reference to FIG.

FIG. 83 shows a system block diagram of the pixel portion 22705 and the driver circuit portion 22708 of the display device.

The pixel portion 22705 has a plurality of pixels, and the signal line 22712 and the scan line 22 which are each pixel.
A switching element is provided in the intersection region with 710. The switching element can control the application of voltage for controlling the tilt of the liquid crystal molecules. A structure in which a switching element is provided in each intersection region is called an active type. The pixel portion of this embodiment is not limited to such an active type and may have a passive type structure. Since the passive type does not have a switching element in each pixel, the process is simple.

The driver circuit portion 22708 includes a control circuit 22702, a signal line driver circuit 22703, and a scan line driver circuit 22704. The control circuit 22702 to which the video signal 22701 is input has a function of performing gradation control in accordance with display content of the pixel portion 22705. Therefore, the control circuit 2
Reference numeral 2702 denotes a signal generated by the signal line driver circuit 22703 and the scan line driver circuit 22704.
To enter. Then, when the switching element is selected through the scan line 22710 based on the scan line driver circuit 22704, a voltage is applied to the pixel electrode in the selected intersection region. The value of this voltage is determined based on the signal input from the signal line driver circuit 22703 through the signal line.

Further, the control circuit 22702 generates a signal for controlling the power supplied to the lighting means 22706, and the signal is input to the power supply 22707 of the lighting means 22706. The backlight unit described in any of the above embodiments can be used for the lighting means. The illumination means may be a front light in addition to the backlight. The front light is a plate-shaped light unit that is mounted on the front surface side of the pixel portion and that is configured by a light-emitting body and a light guide body that illuminates the whole. With such an illumination means, the pixel portion can be illuminated uniformly with low power consumption.

As illustrated in FIG. 83B, the scan line driver circuit 22704 includes circuits functioning as a shift register 22741, a level shifter 22742, and a buffer 22743. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 22741. Note that the scan line driver circuit in this embodiment is not limited to the structure shown in FIG.

In addition, as illustrated in FIG. 83C, the signal line driver circuit 22703 includes a shift register 22731.
, A circuit that functions as the first latch 22732, the second latch 22733, the level shifter 22734, and the buffer 22735. The circuit functioning as the buffer 22735 is a circuit having a function of amplifying a weak signal and includes an operational amplifier or the like. A signal such as a start pulse (SSP) is input to the level shifter 22734, and data (DATA) such as a video signal is input to the first latch 22732. The second latch 22733 has a latch (L
(AT) signals can be temporarily held and are simultaneously input to the pixel portion 22705. This is called line-sequential driving. Therefore, if the pixel performs dot-sequential driving instead of line-sequential driving, the second
Latches can be eliminated. As described above, the signal line driver circuit of this embodiment has the structure shown in FIG.
However, the configuration is not limited to that shown in FIG.

The signal line driver circuit 22703, the scan line driver circuit 22704, and the pixel portion 22705 can be formed using semiconductor elements provided over the same substrate. The semiconductor element can be formed using a thin film transistor provided over a glass substrate. In this case, a crystalline semiconductor film may be applied to the semiconductor element. Since the crystalline semiconductor film has high electric characteristics, especially mobility, a circuit included in the driver circuit portion can be formed. In addition, the signal line drive circuit 2
2703 and the scan line driver circuit 22704 are ICs (Integrated Circuits).
) Chips can also be used for mounting on a substrate. In this case, an amorphous semiconductor film can be applied to the semiconductor element in the pixel portion.

Here, the liquid crystal display module of the present embodiment will be described with reference to FIGS. 87 (A) and 87 (B).

FIG. 87A shows an example of a liquid crystal display module, which includes a TFT substrate 23100 and a counter substrate 23.
101 is fixed by a sealing material 23102, and a pixel portion 23103 including a TFT or the like in between.
And a liquid crystal layer 23104 are provided to form a display region. The colored layer 23105 is necessary when performing color display, and in the case of the RGB method, colored layers corresponding to red, green, and blue colors are provided corresponding to each pixel. A layer 23106 containing a first polarizer, a layer 23107 containing a second polarizer, and a diffusion plate 23113 are provided outside the TFT substrate 23100 and the counter substrate 23101.
Are arranged. The light source is composed of a cold cathode tube 23110 and a reflection plate 23111, the circuit board 23112 is connected to the TFT board 23100 by a flexible wiring board 23109, and external circuits such as a control circuit and a power supply circuit are incorporated.

A layer 2310 including a second polarizer is provided between the TFT substrate 23100 and a backlight which is a light source.
7 is stacked, and the counter substrate 23101 is also provided with a layer 23106 including the first polarizer. On the other hand, the absorption axis of the layer 23107 including the second polarizer and the absorption axis of the layer 23106 including the first polarizer which is provided on the viewing side are arranged so as to be crossed Nicols.

Layer 23107 including stacked second polarizer and layer 2310 including stacked first polarizer
6 is adhered to the TFT substrate 23100 and the counter substrate 23101. Alternatively, the layer including the stacked polarizer and the substrate may be stacked with a retardation plate. Further, if necessary, the layer 23106 including the first polarizer, which is the viewing side, may be subjected to antireflection treatment.

The liquid crystal display module has a TN (Twisted Nematic) mode, an IPS (I
n-Plane-Switching mode, FFS (Fringe Field S)
Witching) mode, MVA (Multi-domain Vertical A)
light mode), PVA (Patterned Vertical Alig)
Nent), ASM (Axially Symmetric aligned Mic)
ro-cell) mode, OCB (Optical Compensated Bire)
fringence) mode, FLC (Ferroelectric Liquid C)
Rystal mode, AFLC (Anti Ferroelectric Liquid)
Crystal), PDLC (Polymer Dispersed Liquid)
Crystal mode or the like can be used.

87B is an example in which an OCB mode is applied to the liquid crystal display module of FIG. 87A, which is an FS-LCD (Field sequential-LCD). FS-L
The CD emits red light emission, green light emission, and blue light emission in one frame period, respectively, and it is possible to perform color display by combining images using time division. Further, since each light emission is performed by a light emitting diode, a cold cathode tube or the like, a color filter is unnecessary. Therefore, it is not necessary to arrange the color filters of the three primary colors to limit the display area of each color, and it is possible to display all three colors in any area. On the other hand, since three colors of light are emitted in one frame period, high-speed response of the liquid crystal is required. By applying the FLC mode and the OCB mode using the FS method to the display device of this embodiment, a high-performance display device with high image quality and a liquid crystal television device can be completed.

The OCB mode liquid crystal layer has a so-called π cell structure. The π cell structure is a structure in which the pretilt angle of liquid crystal molecules is oriented in plane symmetry with respect to the center plane between the active matrix substrate and the counter substrate. The orientation state of the π cell structure is a splay orientation when a voltage is not applied between the substrates, and shifts to a bend orientation when a voltage is applied. This bend orientation is displayed in white. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned vertically to both substrates, and light is not transmitted. The OCB mode can realize high-speed response that is about 10 times faster than the conventional TN mode.

Further, as a mode corresponding to the FS method, a ferroelectric liquid crystal (FLC: Fe) capable of high-speed operation is used.
HV (Half V) using rroelectric Liquid Crystal
) -FLC, SS (Surface Stabilized) -FLC, etc. can also be used.

Also, by narrowing the cell gap of the liquid crystal display module, the optical response speed of the liquid crystal display module can be increased. Also, the speed can be increased by reducing the viscosity of the liquid crystal material. The higher speed is more effective when the pixel pitch of the pixel region of the TN mode liquid crystal display module is 30 μm or less. Further, the speed may be increased by using overdrive in which the applied voltage applied to the liquid crystal layer is momentarily higher (or lower) than the original voltage.

The liquid crystal display module in FIG. 87B is a transmissive liquid crystal display module, and is provided with a red light source 23190a, a green light source 23190b, and a blue light source 23190c as light sources. As a light source, a control unit 23199 is installed to control on / off of each of the red light source 23190a, the green light source 23190b, and the blue light source 23190c. Control unit 2319
The emission of each color is controlled by 9 and the light is incident on the liquid crystal, and the images are combined using time division to perform color display.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 10)
In this embodiment mode, a driving method of a display device which can implement this embodiment mode will be described. In particular, a method of driving the liquid crystal display device will be described.

First, overdrive driving will be described with reference to FIG. 88. FIG. 88 (A) shows
It is a graph showing the change over time of the output luminance of the display element with respect to the input voltage. The change over time in the output luminance of the display element with respect to the input voltage 30121 represented by the broken line is as in the output luminance 30123 also represented by the broken line. That is, the voltage for obtaining the target output luminance Lo is Vi, but when Vi is directly input as the input voltage, it takes a time corresponding to the response speed of the element until the target output luminance Lo is reached. Will end up.

Overdrive driving is a technique for increasing this response speed. Specifically, first,
By applying Vo, which is a voltage higher than Vi, to the element for a certain period of time, the response speed of output brightness is increased to approach the target output brightness Lo, and then the input voltage is returned to Vi.
At this time, the input voltage is represented by the input voltage 30122, and the output luminance is represented by the output luminance 30124. The graph of the output brightness 30124 has a shorter time until reaching the target brightness Lo than the graph of the output brightness 30123.

Note that although the case where the output luminance changes positively with respect to the input voltage is described in FIG. 88A, the present embodiment also includes the case where the output luminance changes negatively with respect to the input voltage. I'm out.

A circuit for realizing such driving will be described with reference to FIGS. 88B and 88C. First, a case where the input video signal 30131 is a signal that takes an analog value (may be a discrete value) and the output video signal 30132 is also a signal that takes an analog value will be described with reference to FIG. 88 (B). The overdrive circuit shown in FIG. 88B includes an encoding circuit 30101, a frame memory 30102, a correction circuit 30103, and a DA conversion circuit 30.
104 is provided.

The input video signal 30131 is first input to the encoding circuit 30101 and encoded. That is, the analog signal is converted into a digital signal having an appropriate number of bits. After that, the converted digital signal is input to the frame memory 30102 and the correction circuit 30103, respectively. The video signal of the previous frame held in the frame memory 30102 is also input to the correction circuit 30103 at the same time. Then, the correction circuit 30103 outputs a corrected video signal from the video signal of the frame and the video signal of the previous frame according to a numerical table prepared in advance. At this time, the output switching signal 30133 may be input to the correction circuit 30103 so that the corrected video signal and the video signal of the frame can be switched and output. Next, the corrected video signal or the video signal of the frame is input to the DA conversion circuit 30104. Then, the output video signal 30132, which is an analog signal having a value according to the corrected video signal or the video signal of the frame, is output. In this way, overdrive drive can be realized.

Next, a case where the input video signal 30131 is a signal having a digital value and the output video signal 30132 is also a signal having a digital value will be described with reference to FIG. Figure 8
The overdrive circuit shown in FIG. 8C includes a frame memory 30112 and a correction circuit 301.
13 are provided.

The input video signal 30131 is a digital signal, and first, the frame memory 30112,
The correction circuits 30113 and 30 are respectively input. The video signal of the previous frame held in the frame memory 30112 is also input to the correction circuit 30113 at the same time. Then, the correction circuit 30113 outputs a corrected video signal from the video signal of the frame and the video signal of the previous frame according to a numerical table prepared in advance. At this time, the output switching signal 30133 may be input to the correction circuit 30113 so that the corrected video signal and the video signal of the frame can be switched and output. In this way, overdrive drive can be realized.

Note that the overdrive circuit in this embodiment includes a case where the input video signal 30131 is an analog signal and the output video signal 30132 is a digital signal. At this time,
The DA conversion circuit 30104 may be omitted from the circuit illustrated in FIG. 88B. The overdrive circuit in this embodiment also includes a case where the input video signal 30131 is a digital signal and the output video signal 30132 is an analog signal. At this time, the encoding circuit 30101 may be omitted from the circuit illustrated in FIG. 88B.

Next, driving for operating the potential of the common line will be described with reference to FIG. 89. 89 (
A) shows a plurality of pixel circuits when one common line is arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. It is a figure. The pixel circuit illustrated in FIG. 89A includes a transistor 30201, an auxiliary capacitor 30202, a display element 30203, a video signal line 30204, a scan line 30205, and a common line 30206.

A gate electrode of the transistor 30201 is electrically connected to a scan line 30205, one of a source electrode and a drain electrode of the transistor 30201 is electrically connected to a video signal line 30204, and the other of the source electrode and the drain electrode of the transistor 30201 is electrically connected. Are electrically connected to one electrode of the storage capacitor 30202 and one electrode of the display element 30203. The other electrode of the auxiliary capacitor 30202 is electrically connected to the common line 30206.

First, in the pixel selected by the scan line 30205, since the transistor 30201 is turned on, a voltage corresponding to a video signal is applied to the display element 30203 and the auxiliary capacitor 30202 through the video signal line 30204, respectively. At this time, the video signal is
If the lowest gradation is displayed for all the pixels connected to 0206, or if the highest gradation is displayed for all the pixels connected to common line 30206, It is not necessary to write a video signal to each of the video signal lines 30204.
The voltage applied to the display element 30203 can be changed by moving the potential of the common line 30206 instead of writing the video signal through the video signal line 30204.

Next, FIG. 89B shows a case where two common lines are arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. It is a figure showing a plurality of pixel circuits. The pixel circuit illustrated in FIG. 89B includes a transistor 30211, an auxiliary capacitor 30212, a display element 30213, a video signal line 30214, a scan line 30215, a first common line 30216, and a second common line 30217. ..

A gate electrode of the transistor 30211 is electrically connected to the scan line 30215, one of a source electrode and a drain electrode of the transistor 30211 is electrically connected to a video signal line 30214, and the other of the source electrode and the drain electrode of the transistor 30211 is electrically connected. Are electrically connected to one electrode of the auxiliary capacitor 30212 and one electrode of the display element 30213. The other electrode of the auxiliary capacitor 30212 is electrically connected to the first common line 30216. In the pixel adjacent to the pixel, the auxiliary capacitor 30212
The other electrode of is electrically connected to the second common line 30217.

In the pixel circuit shown in FIG. 89B, since there are few pixels electrically connected to one common line, instead of writing a video signal through the video signal line 30214, the first common line 30216 is used. Alternatively, by moving the potential of the second common line 30217, the display element 30213
The frequency at which the voltage applied to the power supply can be changed remarkably increases. Also, source inversion drive or dot inversion drive becomes possible. By source inversion drive or dot inversion drive, flicker can be suppressed while improving the reliability of the element.

Next, the scanning backlight will be described with reference to FIG. FIG. 90 (A) is a diagram showing a scanning backlight in which cold cathode tubes are juxtaposed. The scanning backlight shown in FIG. 90A includes a diffusion plate 30301 and N cold cathode tubes 30302-1 to 30302-N. By arranging N cold cathode fluorescent lamps 30302-1 to 30302-N side by side behind the diffusion plate 30301, the N cold cathode fluorescent lamps 30302-1 to 30302-N can be scanned while changing their brightness. You can

The change in the brightness of each cold cathode tube during scanning will be described with reference to FIG. First, the brightness of the cold cathode fluorescent lamp 30302-1 is changed for a certain period of time. Then, after that, the cold cathode fluorescent lamp 30
The brightness of the cold cathode fluorescent lamp 30302-2 arranged next to 302-1 is changed for the same time. In this way, the luminance is sequentially changed from the cold cathode tubes 30302-1 to 30302-N. Note that in FIG. 90C, the luminance changed for a certain period of time is smaller than the original luminance, but it may be larger than the original luminance. In addition, cold cathode tubes 30302-1 to 3030
Although it is assumed that the scanning is performed up to 2-N, the cold cathode tubes 30302-N to 30302-1 may be scanned in the opposite direction.

By driving as shown in FIG. 90, the average luminance of the backlight can be reduced. Therefore, the power consumption of the backlight, which accounts for most of the power consumption of the liquid crystal display device, can be reduced.

An LED may be used as the light source of the scanning backlight. The scanning backlight in that case is as shown in FIG. 90 (B). The scanning backlight shown in FIG. 90B includes a diffusion plate 30311 and light sources 30312-1 to 30312-N in which LEDs are arranged side by side. When LEDs are used as the light source of the scanning backlight, the backlight is thin,
It has the advantage of being light. Further, there is an advantage that the color reproduction range can be widened. Further, LEs are arranged in parallel with each of the light sources 30312-1 to 30312-N in which LEDs are arranged in parallel.
Since D can be similarly scanned, it can be used as a point scanning type backlight.
The point scanning type can further improve the quality of moving images.

Even when an LED is used as the light source of the backlight, it is possible to drive by changing the brightness as shown in FIG. 90 (C).

Next, high frequency driving will be described with reference to FIG. FIG. 91A is a diagram when one image and one intermediate image are displayed in one frame period 30400. 3040
1 is the image of the frame, 30402 is the intermediate image of the frame, 30403 is the image of the next frame, and 30404 is the intermediate image of the next frame.

The intermediate image 30402 of the frame may be an image created based on the video signals of the frame and the next frame. Further, the intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. Further, the intermediate image 30402 of the frame may be a black image. By doing so, the image quality of the moving image of the hold type display device can be improved. Further, in the case of displaying one image and one intermediate image in one frame period 30400, there is an advantage that matching with the frame rate of the video signal is easily achieved and the image processing circuit is not complicated.

FIG. 91B is a diagram when one image and two intermediate images are displayed in a period (two frame periods) in which two one frame periods 30400 are continuous. 30411 is an image of the frame, 30412 is an intermediate image of the frame, 30413 is an intermediate image of the next frame, 3
0414 is an image of one frame after another.

The intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the frame, the next frame, and the next frame. Further, the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame are
It may be a black image. When displaying one image and two intermediate images in two frame periods, there is an advantage that the image quality of a moving image can be effectively improved without increasing the operating frequency of the peripheral drive circuit so much.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 11)
In this embodiment mode, a pixel structure of a display device capable of implementing this embodiment mode will be described. In particular, the pixel structure of a display device using an organic EL element will be described.

FIG. 92A shows a layout example of a pixel element having two TFTs in one pixel.
In addition, FIG. 92B shows a cross-sectional view of a portion indicated by XX ′ in FIG.

As shown in FIG. 92A, the pixel in this embodiment has a first TFT 60105,
The first wiring 60106, the second wiring 60107, the second TFT 60108, and the third wiring 6
0111, counter electrode 60112, capacitor 60113, pixel electrode 60115, partition wall 60
116, the organic conductor film 60117, the organic thin film 60118, and the substrate 60119 may be included. Note that the first TFT 60105 serves as a switching TFT and is connected to the first wiring 601.
06 is a gate signal line and the second wiring 60107 is a source signal line.
It is preferable that 60108 is used as a driving TFT and the third wiring 60111 is used as a current supply line.

As shown in FIG. 92A, the gate electrode of the first TFT 60105 is the first wiring 60.
106 is electrically connected to one of the source electrode and the drain electrode of the first TFT 60105 is electrically connected to the second wiring 60107, and the other of the source electrode and the drain electrode of the first TFT 60105 is the second electrode. Is preferably electrically connected to the gate electrode of the TFT 60108 and one electrode of the capacitor 60113. The first TFT
The gate electrode of 60105 may be formed of a plurality of gate electrodes as shown in FIG. By doing so, the leak current in the off state of the first TFT 60105 can be reduced.

In addition, one of the source electrode and the drain electrode of the second TFT 60108 is connected to the third wiring 6
It is preferable that the second TFT 60108 is electrically connected to the pixel electrode 60115, and the other of the source electrode and the drain electrode of the second TFT 60108 is electrically connected to the pixel electrode 60115. By doing so, the current flowing through the pixel electrode 60115 can be controlled by the second TFT 60108.

An organic conductor film 60117 is provided on the pixel electrode 60115, and the organic thin film 601 is further provided.
18 (organic compound layer) may be provided. A counter electrode 60112 may be provided on the organic thin film 60118 (organic compound layer). Note that the counter electrode 60112 may be formed in a solid shape so as to be commonly connected to all pixels, or may be patterned using a shadow mask or the like.

Light emitted from the organic thin film 60118 (organic compound layer) passes through either the pixel electrode 60115 or the counter electrode 60112 and is emitted. At this time, in FIG. 92B, the case where light is emitted to the pixel electrode side, that is, the side where a TFT or the like is formed is called bottom emission, and the case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60115 is preferably formed by a transparent conductive film.
On the contrary, in the case of top emission, the counter electrode 60112 is preferably formed by a transparent conductive film.

In a color display light-emitting device, EL elements having R, G, and B emission colors may be separately painted, or a single-color EL element may be painted in a solid form and R-colored by a color filter.
-G / B light emission may be obtained.

Note that the structure shown in FIG. 92 is merely an example, and various structures other than the structure shown in FIG. 92 can be employed with respect to a pixel layout, a cross-sectional structure, a stacking order of electrodes of an EL element, and the like. In addition to the element formed of the organic thin film shown, various elements such as a crystalline element such as an LED and an element formed of an inorganic thin film can be used for the light emitting layer.

Next, with reference to FIG. 93A, a layout example of a pixel element having three TFTs in one pixel will be described. A cross-sectional view of a portion indicated by XX 'in FIG. 93A is shown in FIG.

As shown in FIG. 93A, the pixel in this embodiment includes a substrate 60200, a first wiring 60201, a second wiring 60202, a third wiring 60203, a fourth wiring 60204, a first TFT 60205, Second TFT 60206, third TFT 60207, pixel electrode 6
0208, partition 6021, organic conductor film 60212, organic thin film 60213, counter electrode 6
0214, may be included. Note that the first wiring 60201 serves as a source signal line, the second wiring 60202 serves as a writing gate signal line, the third wiring 60203 serves as an erasing gate signal line, and the fourth wiring 60204 serves as a current supply line. , The first TFT 60205 serves as a switching TFT, the second TFT 60206 serves as an erasing TFT, and the third TF
T60207 is preferably used as a driving TFT.

As shown in FIG. 93A, the gate electrode of the first TFT 60205 is the second wiring 602.
02, the first TFT 60205 has one of a source electrode and a drain electrode electrically connected to the first wiring 60201, and the other of the source electrode and the drain electrode of the first TFT 60205 has a third electrode Is preferably electrically connected to the gate electrode of the TFT 60207. Note that the gate electrode of the first TFT 60205 may be formed using a plurality of gate electrodes as illustrated in FIG. By doing so, leakage current in the off state of the first TFT 60205 can be reduced.

The gate electrode of the second TFT 60206 is electrically connected to the third wiring 60203, and one of the source electrode and the drain electrode of the second TFT 60206 is the fourth wiring 60.
It is preferable that the second TFT 60206 is electrically connected to the second TFT 60206, and the other of the source electrode and the drain electrode of the second TFT 60206 is electrically connected to the gate electrode of the third TFT 60207. Note that the gate electrode of the second TFT 60206 may be formed using a plurality of gate electrodes as illustrated in FIG. By doing so, leakage current in the off state of the second TFT 60206 can be reduced.

In addition, one of the source electrode and the drain electrode of the third TFT 60207 is connected to the fourth wiring 6
It is preferable that the third TFT 60207 is electrically connected to the pixel electrode 60208 and the other of the source electrode and the drain electrode of the third TFT 60207 is electrically connected to the pixel electrode 60208. By doing so, the current flowing through the pixel electrode 60208 can be controlled by the third TFT 60207.

An organic conductor film 60212 is provided on the pixel electrode 60208, and an organic thin film 602 is further provided.
13 (organic compound layer) may be provided. A counter electrode 60214 may be provided on the organic thin film 60213 (organic compound layer). Note that the counter electrode 60214 may be formed in a solid shape so as to be commonly connected to all pixels, or may be patterned using a shadow mask or the like.

Light emitted from the organic thin film 60213 (organic compound layer) passes through either the pixel electrode 60208 or the counter electrode 60214 and is emitted. At this time, in FIG. 93B, the case where light is emitted to the pixel electrode side, that is, the side where a TFT or the like is formed is called bottom emission, and the case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60208 is preferably formed by a transparent conductive film.
On the contrary, in the case of top emission, the counter electrode 60214 is preferably formed by a transparent conductive film.

In a color display light-emitting device, EL elements having R, G, and B emission colors may be separately painted, or a single-color EL element may be painted in a solid form and R-colored by a color filter.
, G, B may be obtained.

The structure shown in FIG. 93 is merely an example, and various structures other than the structure shown in FIG. 93 can be employed with respect to the pixel layout, the cross-sectional structure, the stacking order of the electrodes of the EL element, and the like. In addition to the element formed of the organic thin film shown, various elements such as a crystalline element such as an LED and an element formed of an inorganic thin film can be used for the light emitting layer.

Next, with reference to FIG. 94A, a layout example of a pixel element having four TFTs in one pixel will be described. Further, FIG. 94B is a cross-sectional view of a portion indicated by XX ′ in FIG.

As shown in FIG. 94A, the pixel in this embodiment includes a substrate 60300, a first wiring 60301, a second wiring 60302, a third wiring 60303, a fourth wiring 60304, a first TFT 60305, 2nd TFT 60306, 3rd TFT 60307, 4th TF
T 60308, the pixel electrode 60309, the fifth wiring 60311, the sixth wiring 60312, the partition 60321, the organic conductor film 60322, the organic thin film 60323, and the counter electrode 60324 may be provided. Note that the first wiring 60301 serves as a source signal line and the second wiring 60
302 is a writing gate signal line, 3rd wiring 60303 is an erasing gate signal line, 4th wiring 60304 is a reverse bias signal line, 1st TFT 60305 is a switching TFT, and 2nd. The TFT 60306 is a third TF as an erasing TFT.
T60307 is a driving TFT, and the fourth TFT 60308 is a reverse bias TFT.
It is preferable that the fifth wiring 60311 be used as a current supply line and the sixth wiring 60312 be used as a reverse bias power supply line.

As shown in FIG. 94A, the gate electrode of the first TFT 60305 is the second wiring 603.
02, the first TFT 60305 has one of a source electrode and a drain electrode electrically connected to the first wiring 60301, and the other of the source electrode and the drain electrode of the first TFT 60305 has a third electrode It is suitable to be electrically connected to the gate electrode of the TFT 60307. Note that the gate electrode of the first TFT 60305 may be composed of a plurality of gate electrodes as shown in FIG. By doing so, the leak current in the off state of the first TFT 60305 can be reduced.

A gate electrode of the second TFT 60306 is electrically connected to the third wiring 60303, and one of a source electrode and a drain electrode of the second TFT 60306 has a fifth wiring 60311.
It is preferable that the other of the source electrode and the drain electrode of the second TFT 60306 is electrically connected to the gate electrode of the third TFT 60307. Note that the gate electrode of the second TFT 60306 may be formed using a plurality of gate electrodes as illustrated in FIG. By doing so, leakage current in the off state of the second TFT 60306 can be reduced.

One of a source electrode and a drain electrode of the third TFT 60307 is connected to the fifth wiring 6031.
It is preferable that the pixel electrode 60309 is electrically connected to 1 and the other of the source electrode and the drain electrode of the third TFT 60307 is electrically connected to the pixel electrode 60309. By doing so, the current flowing through the pixel electrode 60309 can be controlled by the third TFT 60307.

A gate electrode of the fourth TFT 60308 is electrically connected to the fourth wiring 60304, and one of a source electrode and a drain electrode of the fourth TFT 60308 has a sixth wiring 60312.
It is preferable that the fourth TFT 60308 is electrically connected to the pixel electrode 60309 and the other of the source electrode and the drain electrode of the fourth TFT 60308 is electrically connected to the pixel electrode 60309. By doing so, the potential of the pixel electrode 60309 can be controlled by the fourth TFT 60308.
A reverse bias can be applied to the organic conductor film 60322 and the organic thin film 60323. By applying a reverse bias to the light emitting element including the organic conductor film 60322 and the organic thin film 60323, the reliability of the light emitting element can be greatly improved.

For example, a light emitting element having a luminance half time of about 400 hours when driven by a DC voltage (3.65V) is converted into an AC voltage (forward bias: 3.7V, reverse bias: 1.7V, duty 50%, It is known that when driven at an AC frequency of 60 Hz, the luminance half-life becomes 700 hours or longer.

An organic conductor film 60322 is provided on the pixel electrode 60309, and an organic thin film 603 is further provided.
23 (organic compound layer) may be provided. A counter electrode 60324 may be provided on the organic thin film 60323 (organic compound layer). Note that the counter electrode 60324 may be formed in a solid shape so as to be commonly connected to all pixels, or may be patterned using a shadow mask or the like.

The light emitted from the organic thin film 60323 (organic compound layer) is emitted through either the pixel electrode 60309 or the counter electrode 60324. At this time, in FIG. 94B, the case where light is emitted to the pixel electrode side, that is, the side where a TFT or the like is formed is called bottom emission, and the case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60309 is preferably formed by a transparent conductive film.
On the contrary, in the case of top emission, the counter electrode 60324 is preferably formed by a transparent conductive film.

In a color display light-emitting device, EL elements having emission colors of R, G, and B may be separately coated, or a single-color EL element may be coated in a solid form and R, G, and
B light emission may be obtained.

Note that the structure shown in FIG. 94 is merely an example, and various structures other than the structure shown in FIG. 94 can be employed with respect to a pixel layout, a cross-sectional structure, a stacking order of electrodes of an EL element, and the like. In addition to the element formed of the organic thin film shown, various elements such as a crystalline element such as an LED and an element formed of an inorganic thin film can be used for the light emitting layer.

Next, a structure of an EL element applicable to this embodiment will be described.

An EL element which can be applied to this embodiment is a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, an electron The electron injection layer and the like made of the injection material do not have a layered structure that can be clearly distinguished, and a plurality of materials such as a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material can be used. A configuration having a layer in which materials are mixed (mixed layer) (hereinafter referred to as a mixed junction type EL element) may be used.

A schematic diagram showing the structure of the mixed junction type EL element is shown in FIG. In FIG. 95, 6040
Reference numeral 1 is an anode of the EL element. 60402 is a cathode of the EL element. The layer sandwiched between the anode 60401 and the cathode 60402 corresponds to the EL layer.

In FIG. 95A, the EL layer includes a hole-transporting region 60403 including a hole-transporting material and an electron-transporting region 60404 including an electron-transporting material, and the hole-transporting region 60403 is more anode than the electron-transporting region 60404. A mixed region 60 located on the side and between the hole transport region 60403 and the electron transport region 60404 and including both the hole transport material and the electron transport material.
A structure in which 405 is provided can be used.

Note that the concentration of the hole transport material in the mixed region 60405 may decrease and the concentration of the electron transport material in the mixed region 60405 may increase in the direction from the anode 60401 to the cathode 60402.

Note that in the above structure, the hole-transporting region 60403 including only the hole-transporting material does not exist, and the concentration ratio of each functional material changes in the mixed region 60405 including both the hole-transporting material and the electron-transporting material. It may have a configuration (having a concentration gradient). In addition, a hole-transporting region 60403 including only a hole-transporting material and an electron-transporting region 60404 including only an electron-transporting material.
Does not exist, and the ratio of the concentration of each functional material changes (has a concentration gradient) inside the mixed region 60405 containing both the hole transport material and the electron transport material. Further, the ratio of the concentration may be changed depending on the distance from the anode or the cathode. Further, the change in the concentration ratio may be continuous. The method of setting the concentration gradient can be set freely.

The mixed region 60405 has a region 60406 to which a light emitting material is added. The emission color of the EL element can be controlled by the light emitting material. Further, carriers can be trapped by the light emitting material. As the light emitting material, various fluorescent dyes can be used in addition to a metal complex containing a quinoline skeleton, a metal complex containing a benzoxazole skeleton, a metal complex containing a benzothiazole skeleton, and the like. By adding these light emitting materials, the emission color of the EL element can be controlled.

As the anode 60401, an electrode material having a large work function is preferably used in order to efficiently inject holes. For example, a transparent electrode made of tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), ZnO, SnO ₂ , In ₂ O ₃ or the like can be used. Further, the anode 60401 may be an opaque metal material as long as it does not need to have a light-transmitting property.

As the hole transport material, an aromatic amine compound or the like can be used.

As the electron transport material, a quinoline derivative, a metal complex having 8-quinolinol or its derivative as a ligand (particularly, tris (8-quinolinolite) aluminum (Alq ₃ )) and the like can be used.

As the cathode 60402, it is preferable to use an electrode material having a small work function in order to efficiently inject electrons. A metal such as aluminum, indium, magnesium, silver, calcium, barium, or lithium can be used alone. Further, it may be an alloy of these metals or an alloy of these metals and another metal.

A schematic view of an EL element having a structure different from that in FIG. 95A is shown in FIG. Note that FIG.
The same parts as those in A) are denoted by the same reference numerals and the description thereof will be omitted.

In FIG. 95B, there is no region to which the light emitting material is added. However, the electron transport region 604
As a material added to 04, a material having both an electron-transporting property and a light-emitting property (electron-transporting light-emitting material), for example, tris (8-quinolinolite) aluminum (Alq ₃ ) is used, and light can be emitted.

Alternatively, as a material added to the hole-transporting region 60403, a material having both a hole-transporting property and a light-emitting property (a hole-transporting light-emitting material) may be used.

A schematic diagram of an EL element having a structure different from those in FIGS. 95A and 95B is shown in FIG. 95C. Note that the same portions as those in FIGS. 95A and 95B are denoted by the same reference numerals and the description thereof is omitted.

In FIG. 95C, a hole blocking material having a large energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital as compared with the hole transport material has a region 60407 added in the mixed region 60405. .. The region 60407 to which the hole blocking material is added is located closer to the cathode 60402 than the region 60406 to which the light emitting material is added in the mixed region 60405, whereby the recombination rate of carriers can be increased and the light emission efficiency can be increased. it can. The above-described structure in which the region 60407 to which the hole blocking material is added is particularly effective in an EL element utilizing light emission (phosphorescence) by triple photoexcitons.

FIG. 9 is a schematic view of an EL element having a structure different from those in FIGS. 95A, 95B, and 95C.
5 (D). Note that the same portions as those in FIGS. 95A, 95B, and 95C are denoted by the same reference numerals and the description thereof is omitted.

In FIG. 95D, an electron blocking material having a large energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital as compared with the electron transporting material has a region 60408 added in the mixed region 60405. The region 60408 to which the electron blocking material is added is arranged closer to the anode 60401 than the region 60406 to which the light emitting material is added in the mixed region 60405, whereby the recombination rate of carriers can be increased and light emission efficiency can be increased. .. The above-described structure in which the region 60408 added with the electron blocking material is provided is particularly effective in an EL element utilizing light emission (phosphorescence) by triple photoexcitons.

FIG. 95E is a schematic diagram showing a structure of a mixed-junction EL element which is different from those in FIGS. 95A, 95B, 95C, and 95D. FIG. 95E shows an example of a structure in which a region 60409 to which a metal material is added is provided in a portion of an EL layer which is in contact with an electrode of an EL element. In FIG. 95 (E), the same parts as those in FIGS. 95 (A) to 95 (D) are denoted by the same reference numerals, and description thereof will be omitted. The structure shown in FIG. 95E has, for example, MgA as the cathode 60402.
It is also possible to use g (Mg—Ag alloy) and have a region 60409 in which an Al (aluminum) alloy is added to a region in contact with the cathode 60402 of the electron transport region 60404 in which the electron transport material is added. With the above structure, oxidation of the cathode can be prevented and the efficiency of injecting electrons from the cathode can be improved. In this way, the life of the mixed junction type EL element can be extended. Further, the driving voltage can be lowered.

A co-evaporation method or the like can be used as a method for manufacturing the above-mentioned mixed junction type EL element.

In the mixed junction type EL element as shown in FIGS. 95A to 95E, there is no clear interface between layers, and charge accumulation can be reduced. In this way, its life can be extended. Further, the driving voltage can be lowered.

The configurations shown in FIGS. 95A to 95E can be freely combined and implemented.

The structure of the mixed junction type EL element is not limited to this. A known structure can be freely used.

The organic material forming the EL layer of the EL element may be a low molecular weight material or a high molecular weight material. Also, both of these materials may be used. When a low molecular weight material is used as the organic compound material, the film can be formed by a vapor deposition method. On the other hand, when a polymer material is used for the EL layer, the polymer material can be dissolved in a solvent and formed into a film by a spin coating method or an inkjet method.

The EL layer may be made of a medium molecular material. In the present specification, the medium molecular weight organic light emitting material refers to an organic light emitting material having no sublimation property and a degree of polymerization of about 20 or less. When a medium-molecular material is used for the EL layer, it can be formed by an inkjet method or the like.

A low molecular weight material, a high molecular weight material, and a medium molecular weight material may be used in combination.

Further, the EL element may be one that utilizes light emission (fluorescence) from singlet excitons or one that utilizes light emission (phosphorescence) from triplet excitons.

Next, a vapor deposition device for manufacturing a display device to which this embodiment can be applied will be described with reference to the drawings.

The display device to which this embodiment is applicable may be manufactured by forming an EL layer. The EL layer is
It is formed by including at least a part of a material exhibiting electroluminescence. The EL layer may be composed of a plurality of layers having different functions. In that case, the EL layer may be formed by combining layers having different functions, which are also called a hole injecting and transporting layer, a light emitting layer, an electron injecting and transporting layer, and the like.

FIG. 96 shows a structure of a vapor deposition device for forming an EL layer on an element substrate on which a transistor is formed.
Shown in. In this vapor deposition device, a plurality of processing chambers are connected to the transfer chambers 60560 and 60561. The processing chamber includes a load chamber 60562 for supplying a substrate and an unload chamber 605 for recovering the substrate.
63, others, a heat treatment chamber 60568, a plasma treatment chamber 60572, a film formation treatment chamber 60569 to 60575 for depositing an EL material, a film formation for forming aluminum or a conductive film containing aluminum as a main component as one electrode of an EL element. It includes a processing chamber 60576. Further, gate valves 60577a to 60577m are provided between the transfer chamber and the processing chambers, and the pressures of the processing chambers can be independently controlled, thereby preventing mutual contamination between the processing chambers.

The substrate introduced into the transfer chamber 60560 from the load chamber 60562 is carried into a predetermined processing chamber by the rotatably provided arm type transfer unit 60566. Further, the substrate is transferred from one processing chamber to another processing chamber by the transfer unit 60566. The transfer chamber 60560 and the transfer chamber 60561 are connected to each other in a film formation processing chamber 60570, and the substrate is transferred between the transfer unit 60566 and the transfer unit 60567.

The processing chambers connected to the transfer chamber 60560 and the transfer chamber 60561 are kept under reduced pressure. Therefore, in this vapor deposition apparatus, the EL layer is continuously formed without exposing the substrate to the atmosphere. Since the display panel on which the EL layer deposition process has been completed may be deteriorated by water vapor etc., this vapor deposition apparatus uses a sealing process for performing a sealing process before exposing it to the atmosphere to maintain quality. The chamber 60565 is connected to the transfer chamber 60561. Sealing processing chamber 605
Since 65 is under atmospheric pressure or reduced pressure close to it, an intermediate processing chamber 60564 is also provided between the transfer chamber 60561 and the sealing processing chamber 60565. Intermediate processing chamber 60564
Is provided to transfer the substrate and buffer the pressure between the chambers.

The load chamber, the unload chamber, the transfer chamber, and the film formation processing chamber are provided with exhaust means for keeping the inside of the chamber at a reduced pressure. As the exhaust means, various vacuum pumps such as a dry pump, a turbo molecular pump, a diffusion pump can be used.

In the vapor deposition apparatus in FIG. 96, the number of processing chambers connected to the transfer chamber 60560 and the transfer chamber 60561 and the structure thereof can be combined as appropriate depending on the stacked structure of the EL element. Below, an example of the combination is shown.

In the heat treatment chamber 60568, a substrate provided with a lower electrode, an insulating partition, and the like is first heated to perform degassing treatment. In the plasma treatment chamber 60572, the surface of the base electrode is subjected to rare gas or oxygen plasma treatment. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state (eg, work function) of the surface.

The film formation processing chamber 60569 is a processing chamber in which an electrode buffer layer which is in contact with one electrode of the EL element is formed. The electrode buffer layer has carrier injection properties (hole injection or electron injection), and
It is a layer that suppresses the occurrence of short circuits and dark spot defects in the L element. Typically, the electrode buffer layer is an organic-inorganic mixed material, has a resistivity of 5 × 10 ⁴ to 1 × 10 ⁶ Ωcm, and has a resistivity of 30 to 300.
It is formed to a thickness of nm. A film formation chamber 60571 is a treatment chamber in which a hole transport layer is formed.

The structure of the light emitting layer in the EL element differs depending on whether it emits monochromatic light or white light. In the vapor deposition apparatus, it is preferable to arrange the film forming processing chamber accordingly. For example,
When forming three types of EL elements having different emission colors on the display panel, it is necessary to form a light emitting layer corresponding to each emission color. In this case, the film formation treatment chamber 60570 is used for forming the first light emitting layer, the film formation treatment chamber 60573 is used for forming the second light emitting layer, and the film formation treatment chamber 60574 is formed for forming the third light emitting layer. It can be used for membranes. By dividing the film formation processing chamber for each light emitting layer, mutual contamination due to different light emitting materials can be prevented, and the throughput of film formation processing can be improved.

In the film formation processing chamber 60570, the film formation processing chamber 60573, and the film formation processing chamber 60574, three kinds of EL materials having different emission colors may be sequentially deposited. In this case, a shadow mask is used, and the mask is shifted according to the area to be evaporated to perform the evaporation.

In the case of forming an EL element which emits white light, light emitting layers of different emission colors are vertically stacked. Even in that case, the element substrate can be sequentially moved in the film formation processing chamber to form a film for each light emitting layer. Further, different light emitting layers can be continuously formed in the same film formation processing chamber.

In the film formation processing chamber 60576, an electrode is formed over the EL layer. The electrodes may be formed by an electron beam evaporation method or a sputtering method, but a resistance heating evaporation method is preferably used.

The element substrate for which the formation of electrodes has been completed passes through the intermediate processing chamber 60564 and then the sealing processing chamber 60565.
Be delivered to. The sealing treatment chamber 60565 is filled with an inert gas such as helium, argon, neon, or nitrogen, and a sealing plate is attached to the side where the EL layer of the element substrate is formed in the atmosphere and sealed. Stop. In the sealed state, between the element substrate and the sealing plate,
It may be filled with an inert gas or may be filled with a resin material. Sealing chamber 6
The 0565 is provided with a dispenser for drawing a sealing material, a mechanical element such as a fixed stage and an arm for fixing the sealing plate facing the element substrate, a dispenser for filling a resin material, a spin coater, and the like.

FIG. 97 shows the internal structure of the film formation processing chamber. The film formation processing chamber is kept under reduced pressure. In FIG. 97, the inside sandwiched between the top plate 60691 and the bottom plate 60692 is the interior, and the interior kept under reduced pressure is shown.

One or more evaporation sources are provided in the processing chamber. This is because it is preferable to provide a plurality of evaporation sources when forming a plurality of layers having different compositions or co-evaporating different materials. In FIG. 97, the evaporation sources 60681a, 60681b, and 60681c are attached to the evaporation source holder 60680. The evaporation source holder 60680 is held by an articulated arm 60683. The articulated arm 60683 allows the evaporation source holder 60 to be expanded and contracted by expanding and contracting the joints.
The position of 680 can be freely moved within the movable range. Also, the evaporation source holder 606
80 is provided with a distance sensor 60682, and evaporation sources 60681a to 60681c and a substrate 606 are provided.
The optimum interval during vapor deposition may be controlled by monitoring the interval with 89. In that case, the multi-joint arm may be a multi-joint arm that is also displaced in the vertical direction (Z direction).

The substrate stage 60686 and the substrate chuck 60687 form a pair to fix the substrate 60689. The substrate stage 60686 may have a built-in heater so that the substrate 60689 can be heated. The substrate 60689 is fixed to the substrate stage 60686 and is carried in and out by the restraint of the substrate chuck 60687. At the time of vapor deposition, a shadow mask 60690 having an opening corresponding to the vapor deposition pattern can be used if necessary. In that case, the shadow mask 60690 includes a substrate 60689 and evaporation sources 60681a to 60681c.
To be placed between. The shadow mask 60690 is in close contact with the substrate 60689 or fixed with a constant space by a mask chuck 60688. Shadow mask 6
When the alignment of 0690 is required, the camera is arranged in the processing chamber, and the mask chuck 60688 is provided with a positioning means for finely moving in the X, Y, and θ directions to perform the alignment.

The evaporation source 60681 is additionally provided with an evaporation material supply means for continuously supplying the evaporation material to the evaporation source. The vapor deposition material supply means includes material supply sources 60685a, 60685b, and 60685c arranged at a position apart from the evaporation source 60681, and a material supply pipe 6068 that connects the two.
Have four. Typically, the material supply sources 60685a, 60685b, and 60685c are provided corresponding to the evaporation source 60681. In the case of FIG. 97, the material supply source 60685a
And 606 evaporation sources 81a correspond. A material source 60685b and an evaporation source 60681b,
The same applies to the material supply source 60685c and the evaporation source 60681c.

As a method for supplying the vapor deposition material, an air flow transportation method, an aerosol method, or the like can be applied. In the air flow transfer method, a fine powder of a vapor deposition material is carried on an air flow and is transferred to an evaporation source 60681 using an inert gas or the like. The aerosol method is vapor deposition in which a raw material liquid in which a vapor deposition material is dissolved or dispersed in a solvent is conveyed, an aerosol is formed by a sprayer, and the solvent in the aerosol is vaporized. In any case, the evaporation source 60681 is provided with a heating means, and the transported evaporation material is evaporated to form a film on the substrate 60689. In the case of FIG. 97, the material supply pipe 60684
Is made of a thin tube that can be flexibly bent and has a rigidity that does not deform even under reduced pressure.

In the case of applying the air flow transport method or the aerosol method, the film formation may be performed under atmospheric pressure or lower in the film formation processing chamber, preferably under reduced pressure of 133 Pa to 13300 Pa. An inert gas such as helium, argon, neon, krypton, xenon, or nitrogen can be filled in the film formation treatment chamber, or the pressure can be adjusted while the gas is supplied (while being exhausted at the same time). In addition, a gas such as oxygen or nitrous oxide may be introduced into the film formation treatment chamber where an oxide film is formed to be an oxidizing atmosphere. Further, a gas such as hydrogen may be introduced into the film formation processing chamber in which the organic material is vapor-deposited to establish a reducing atmosphere.

As another method of supplying the vapor deposition material, a screw may be provided in the material supply pipe 60684 to continuously push the vapor deposition material toward the evaporation source.

According to this vapor deposition device, even a large-screen display panel can be formed with good uniformity and continuously. In addition, it is not necessary to replenish the evaporation source with the evaporation material each time the evaporation material runs out, so that the throughput can be improved.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 12)
In this embodiment mode, a pixel circuit and a driving method of a display device capable of implementing this embodiment mode will be described.

First, the digital time grayscale drive applicable to this embodiment will be described. First, a driving method in the case where a signal writing period (address period) to a pixel and a light emitting period (sustain period) are separated is described with reference to FIG. Here, as an example, a case of 4-bit digital time gradation will be described.

A period for completely displaying an image for one display area is called one frame period. One frame period has a plurality of subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required to write signals to pixels of all rows, and the periods Tb1 to Tb4 indicate the time required to write signals to pixels of one row (or one pixel). In addition, the sustain periods Ts1 to Ts4 indicate the time during which the lighting or non-lighting state is maintained according to the video signal written to the pixel, and the length ratio thereof is Ts1: Ts2: Ts3: Ts4 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8: 4: 2: 1. The gradation is expressed by which sustain period the light is emitted.

The operation will be described. First, in the address period Ta1, a pixel selection signal is sequentially input to the scan lines from the first row and a pixel is selected. Then, when the pixel is selected, a video signal is input from the signal line to the pixel. Then, when the video signal is written to the pixel, the pixel holds the signal until the signal is input again. Lighting and non-lighting of each pixel in the sustain period Ts1 are controlled by the written video signal. Similarly, a video signal is input to the pixel in the address periods Ta2, Ta3, and Ta4, and the video signal controls lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4. Then, in each sub-frame period, the pixel does not light during the address period, and after the address period ends, the sustain period starts, and the pixel in which the signal for lighting is written lights up.

Here, with reference to FIG. 98 (B), the description will focus on the i-th pixel row. First, in the address period Ta1, pixel selection signals are input to the scan lines sequentially from the first row,
The pixel in the i-th row is selected in the period Tb1 (i) of a1. Then, when the pixel in the i-th row is selected, a video signal is input from the signal line to the pixel in the i-th row. And
When the video signal is written to the pixels in the i-th row, the pixels in the i-th row hold the signal until the signal is input again. Lighting and non-lighting of the pixels in the i-th row in the sustain period Ts1 are controlled by the written video signal. Similarly, the address periods Ta2, Ta3, T
At a4, a video signal is input to the pixel in the i-th row, and the video signal controls lighting or non-lighting of the pixel in the i-th row in the sustain periods Ts2, Ts3, and Ts4. Then, in each sub-frame period, the pixel does not light during the address period, and after the address period ends, the sustain period starts, and the pixel in which the signal for lighting is written lights up.

Although the case of expressing 4-bit gradation is described here, the number of bits and the number of gradations are not limited to this. The order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of parts to emit light. Also, Ts1 and Ts2
, Ts3, Ts4 do not need to be a power of 2 and may have the same length of lighting, or may be slightly shifted from a power of 2.

Next, a driving method in the case where the signal writing period (address period) to the pixel and the light emitting period (sustain period) are not separated will be described. That is, the pixel in the row in which the video signal writing operation is completed holds the signal until the signal is written (or erased) in the pixel next time. The period from the writing operation to the writing of a signal to this pixel next is called a data holding time. Then, during this data holding time, the pixel is turned on or off according to the video signal written in the pixel. The same operation is performed until the last row, and the address period ends. Then, the signal writing operation in the next sub-frame period starts in order from the row in which the data holding time ends.

Thus, in the case of the driving method in which the pixel is immediately turned on or off according to the video signal written to the pixel when the signal writing operation is completed and the data holding time is reached, the data holding time is tried to be shorter than the address period. However, since signals cannot be input to two rows at the same time, it is necessary to prevent the address periods from overlapping, so that the data retention time cannot be shortened. Therefore, as a result, it becomes difficult to perform high gradation display.

Therefore, the data retention time shorter than the address period is set by providing the erase period. A driving method in the case of providing an erase period and setting a data holding time shorter than the address period will be described with reference to FIG.

First, in the address period Ta1, pixel scanning signals are sequentially input to the scanning lines from the first row,
The pixel is selected. Then, when the pixel is selected, a video signal is input from the signal line to the pixel. Then, when the video signal is written to the pixel, the pixel holds the signal until the signal is input again. The written video signal causes the sustain period Ts1.
Lighting and non-lighting of each pixel are controlled. In the row in which the writing operation of the video signal is completed, the pixel is turned on or off according to the written video signal immediately. The same operation is performed up to the last row, and the address period Ta1 ends. Then, the signal writing operation in the next sub-frame period starts in order from the row in which the data holding time ends. Similarly, a video signal is input to the pixel in the address periods Ta2, Ta3, and Ta4, and the video signal controls lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4. Then, the sustain period TS4 is set at the end thereof by starting the erase operation. This is because when the signal written in the pixel is erased during the erase time Te of each row, the signal is forced to be written in the address period regardless of the video signal written in the pixel until the signal is written in the next pixel. This is because it will not be illuminated. That is, the data holding time ends from the pixel in the row where the erasing time Te starts.

Here, with reference to FIG. 99 (B), the description will focus on the i-th pixel row. In the i-th pixel row, in the address period Ta1, pixel scanning signals are sequentially input to the scanning lines from the first row, and pixels are selected. Then, when the pixel in the i-th row is selected in the period Tb1 (i), the video signal is input to the pixel in the i-th row. Then, when the video signal is written to the pixel in the i-th row, the pixel in the i-th row holds the signal until the signal is input again. Lighting and non-lighting of the pixels in the i-th row in the sustain period Ts1 (i) are controlled by the written video signal. In other words, when the video signal write operation is completed on the i-th row,
Immediately according to the written video signal, the pixels in the i-th row are turned on or off. Similarly, a video signal is input to the pixels in the i-th row in the address periods Ta2, Ta3, and Ta4, and the video signal controls lighting and non-lighting of the pixels in the i-th row in the sustain periods Ts2, Ts3, and Ts4. The sustain period Ts4 (i) is set at the end of the sustain period Ts4 (i) by starting the erase operation. This is because, during the erase time Ts (i) of the i-th row, it is forcibly turned off regardless of the video signal written in the pixel of the i-th row. That is, when the erase time Te (i) starts, the data holding time of the pixels in the i-th row ends.

Therefore, it is possible to provide a display device having a high gray scale shorter than the address period and a high duty ratio (ratio of the lighting period in one frame period) without separating the address period and the sustain period. Further, since the instantaneous luminance can be lowered, the reliability of the display element can be improved.

Although the case of expressing 4-bit gradation is described here, the number of bits and the number of gradations are not limited to this. The order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of parts to emit light. Also, Ts1, Ts2,
The lighting time of Ts3 and Ts4 does not have to be a power of 2, and may be the same length of lighting time, or may be slightly shifted from a power of 2.

Here, FIG. 100A, FIG. 100B, FIG. 100C, FIG. 100D, and FIG. 100E are shown for the pixel structure capable of digital time grayscale driving described in FIG. 98A and FIG. 99A. It will be described with reference to FIG. Note that the display elements shown in FIGS. 100A, 100B, 100C, 100D, and 100E are EL
Element (organic EL element, inorganic EL element or EL element containing organic substance and inorganic substance), electron-emitting device, liquid crystal element, electronic ink, grating light valve (GLV), digital micromirror device (DMD), carbon nanotube, etc. A display medium whose contrast changes due to magnetic action can be applied. In addition, FIGS. 100 (A), (B), (
For the pixels shown in C), (D), and (E), self-luminous elements such as EL elements are suitable as display elements. Note that FIGS. 100A, 100B, 100C, 100D, and 100E show only one pixel, but the pixel portion of the display device is arranged in a matrix in a row direction and a column direction. A plurality of pixels are arranged.

The pixel illustrated in FIG. 100A includes a switching transistor 80301a, a driving transistor 80302a, and a capacitor 80304a. A gate terminal of the switching transistor 80301a is connected to the scan line 80312a, a first terminal (source terminal or drain terminal) is connected to the signal line 80311a, and a second terminal (source terminal or drain terminal) is connected to the driving transistor 80302a. It is connected to the gate terminal. The second terminal of the switching transistor 80301a is connected to the power line 8 through the capacitor 80304a.
It is connected to 0313a. Further, the driving transistor 80302a has a first terminal connected to the power supply line 80313a and a second terminal connected to the first electrode of the display element 80320a. A low power supply potential is set to the second electrode 80321a of the display element 80320a. Note that the low power supply potential is a potential satisfying the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80313a. For example, GND or 0V is set as the low power supply potential. Is also good. The potential difference between the high power source potential and the low power source potential is displayed by the display element 80320.
In order to cause the display element 80320a to emit light by applying a current to the display element 80320a, the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80320a. Set the electric potential. Note that the capacitor 80304a can be omitted by substituting the gate capacitance of the driving transistor 80302a. The gate capacitance of the driving transistor 80302a may be formed in a region where a source region, a drain region, an LDD region, and the like overlap with a gate electrode and overlap, or a channel region and a gate electrode. Capacitance may be formed between and.

When a pixel is selected by the scan line 80312a, that is, the switching transistor 8
When 0301a is turned on, a video signal is input to the pixel from the signal line 80311a. Then, electric charge for a voltage corresponding to the video signal is accumulated in the capacitor 80304a,
The capacitor 80304a holds the voltage. This voltage is the driving transistor 80302.
It is the voltage between the gate terminal and the first terminal of a and corresponds to the gate-source voltage Vgs of the driving transistor 80302a.

Generally, the operating region of a transistor can be divided into a linear region and a saturation region. The boundary is when (Vgs-Vth) = Vds, where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. (Vgs-Vth)> Vds
In the case of, the current value is determined by the magnitude of Vds and Vgs in the linear region. on the other hand,(
When Vgs-Vth) <Vds, it is in the saturation region, and ideally, even if Vds changes,
The current value hardly changes. That is, the current value is determined only by the magnitude of Vgs.

Here, in the case of the voltage input voltage driving method, a video signal which allows the driving transistor 80302a to be sufficiently turned on or turned off is input to the gate terminal of the driving transistor 80302a. .. That is, the driving transistor 80302a operates in the linear region.

Therefore, when the driving transistor 80302a is a video signal which is turned on, ideally, the power supply potential VDD set in the power supply line 80313a is kept as it is as the display element 80320.
Set to the first electrode of a.

That is, ideally, the voltage applied to the display element 80320a is kept constant and the display element 8032a
The brightness obtained from 0a is made constant. Then, a plurality of subframe periods are provided in one frame period, a video signal is written to a pixel in each subframe period, lighting or non-lighting of the pixel is controlled in each subframe period, and the pixel is turned on. The gradation is expressed by the total of the sub-frame periods.

Next, the pixel structure of FIG. 100B is described. The pixel shown in FIG. 100B includes a switching transistor 80301a, a driving transistor 80302a, and a rectifying element 80.
It has a display element 80320b and a display element 80320a. A gate terminal of the switching transistor 80301b is connected to the first scan line 80312b and
A terminal (source terminal or drain terminal) is connected to the signal line 80311b, and a second terminal (source terminal or drain terminal) is connected to the gate terminal of the driving transistor 80302b. Further, the gate terminal of the driving transistor 80302 is connected to the second scan line 80314b through the rectifying element 80306a. In addition, the switching transistor 80
The second terminal of 301b is connected to the power supply line 80313b through the capacitor 80304b. Further, the driving transistor 80302b has a first terminal connected to the power supply line 80313b and a second terminal connected to the first electrode of the display element 80320b. Display element 8032
A low power supply potential is set to the second electrode 80321b of 0b. Note that the low power supply potential is a potential satisfying the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80313b. For example, GND or 0V is set as the low power supply potential. Is also good.
By applying the potential difference between the high power source potential and the low power source potential to the display element 80320b,
Since a current is applied to 0320b to cause the display element 80320b to emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is greater than or equal to the forward threshold voltage of the display element 80320b. Note that the capacitor 80304b can be omitted by substituting the gate capacitance of the driving transistor 80302b. The gate capacitance of the driving transistor 80302b may be formed in a region where a source region, a drain region, an LDD region, or the like and a gate electrode overlap with each other or overlap each other, or a channel region and a gate electrode. Capacitance may be formed between and.

This pixel structure is similar to that of the pixel in FIG. 100A except that the rectifying element 80306a and the second scan line 8031 are provided.
4b is added. Therefore, the switching transistor 80301b, the driving transistor 80302b, the capacitor 80304b, the signal line 80311b, the first scan line 80312b, and the power supply line 80313b are respectively the switching transistor 80301b.
a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, a scanning line 80312a, and a power supply line 80313a, and a writing operation and a light emitting operation are the same, and thus description thereof is omitted here.

The erase operation will be described. During the erase operation, an H-level signal is input to the second scan line 80314b. Then, a current flows through the rectifying element 80306a and the gate potential of the driving transistor 80302b held by the capacitor 80304b can be set to a certain potential. That is, the potential of the gate terminal of the driving transistor 80302b is set to a certain potential and the driving transistor 80302b is set regardless of the video signal written to the pixel.
b can be forced off.

Note that the L-level signal input to the second scan line 80314b is set to a potential such that current does not flow to the rectifying element 80306a when a video signal which is not lit is written in the pixel. Further, the H-level signal input to the second scan line 80314b is a potential with which the gate terminal can be set to a potential at which the driving transistor 80302b is turned off regardless of the video signal written in the pixel. And

Note that a diode-connected transistor can be used for the rectifying element 80306a. Further, in addition to the diode-connected transistor, a PN junction or PIN junction diode, a Schottky diode, a diode formed of carbon nanotubes, or the like may be used. A case where a diode-connected N-channel transistor is applied is shown in FIG. The first terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal of the driving transistor 80302c. Also,
The second terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal and is connected to the second scan line 80314c. Then, when the second scan line 80314c is at the L level, current does not flow in the diode-connected transistor 80303c because the gate terminal and the source terminal are connected, but the second scan line 80314 is not connected.
When an H-level signal is input to c, the second terminal of the diode-connected transistor 80303c becomes a drain terminal, so that a current flows through the diode-connected transistor 80303c.
Therefore, the diode-connected transistor 80303c has a rectifying function.

Note that a switching transistor 80301c, a driving transistor 80302c, a capacitor 80304c, a signal line 80311c, a first scan line 80312c, a power supply line 8031.
3c is a switching transistor 80301a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, and a scan line 8031 in FIG.
2a, which corresponds to the power supply line 80313a. In addition, the second scan line 80314c is shown in FIG.
This corresponds to the second scan line 80312d in B).

A case where a diode-connected P-channel transistor is used is shown in FIG. The first terminal (source terminal or drain terminal) of the diode-connected transistor 80303d is connected to the second scan line 80313d. Also, a diode-connected transistor 803
The second terminal (source terminal or drain terminal) of 03d is connected to the gate terminal and the gate terminal of the driving transistor 80302d. Then, the second scan line 8031
When 3d is at the L level, current does not flow in the diode-connected transistor 80303d because the gate terminal and the source terminal are connected, but when the H-level signal is input to the second scan line 80313d, the diode-connected transistor 80303d becomes Since the two terminals serve as drain terminals, current flows through the diode-connected transistor 80303d. Therefore, the diode-connected transistor 80303d has a rectifying function.

Note that the switching transistor 80301d, the driving transistor 80302d, the capacitor 80304d, the signal line 80311d, the first scan line 80312d, and the power supply line 8031.
3d is a switching transistor 80301a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, and a scan line 8031 in FIG.
2a, which corresponds to the power supply line 80313a. In addition, the second scan line 80314d is shown in FIG.
This corresponds to the second scan line 80312d in B).

Further, an erasing transistor may be provided to erase the signal written in the pixel.
The pixel shown in FIG. 100E is the same as the pixel shown in FIG.
And a second scanning line 80312e is added. Therefore, the switching transistor 80301e, the driving transistor 80302e, the capacitor 80304e, and the signal line 80.
311e, the first scan line 80312e, and the power supply line 80313e are illustrated in FIG.
Corresponding to the switching transistor 80301a, the driving transistor 80302a, the capacitor 80304a, the signal line 80311a, the scan line 80312a, and the power supply line 80313a, and the writing operation and the light emitting operation are the same, and thus the description thereof is omitted here.

The erase operation will be described. During the erase operation, an H level signal is input to the second scan line 80312e. Then, the erasing transistor 80303e is turned on, and the gate terminal and the first terminal of the driving transistor 80302e can be set to the same potential. That is, the gate-source voltage of the driving transistor 80302e can be set to 0V. Note that the H-level potential of the second scan line 80312e is preferably higher than the potential of the power supply line 80313e by more than the threshold voltage Vth of the erasing transistor 80303e. In this way, the driving transistor 80302e can be forcibly turned off.

Next, an example of a threshold voltage correction type pixel circuit and a driving method which can be applied to this embodiment mode will be described with reference to FIG.

The pixel shown in FIG. 101A includes a driving transistor 80400 and a first switch 80401.
, A second switch 80402, a third switch 80403, a first capacitor 80404,
A second capacitor 80405 and a display element 80420 are included. Drive transistor 80
In 400, the gate terminal is connected to the signal line 80411 through the first capacitor 80404 and the first switch 80401 in order, the first terminal is connected to the power supply line 80412, and the second terminal is the third switch 80403. Is connected to the first electrode of the display element 80420 through. Further, the gate terminal of the driving transistor 80400 is connected to the power supply line 80412 through the second capacitor 80405. The gate terminal of the driving transistor 80400 is connected to the second terminal of the driving transistor 80400 via the second switch 80402. In addition, a low power supply potential is set to the second electrode 80421 of the display element 80420. Note that the low power supply potential is a potential that satisfies the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80412, and the low power supply potential is set to GND, 0 V, or the like. Is also good. The potential difference between the high power source potential and the low power source potential is displayed by the display element 80420.
In order to make the display element 80420 emit light by applying a current to the display element 80420,
The respective potentials are set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80420. Note that the second capacitor 80405 can be omitted by substituting the gate capacitance of the driving transistor 80400. Drive transistor 80
Regarding the gate capacitance of 400, the capacitance may be formed in a region in which the source region, the drain region, the LDD region, and the like overlap with the gate electrode and overlap, or between the channel region and the gate electrode. The capacitance may be formed by. The first switch 8
On / off of 0401, the second switch 80402, and the third switch 80403 is controlled by the first scan line 80413, the second scan line 80414, and the third scan line 80415, respectively.

The pixel driving method shown in FIG. 101A can be divided into an initialization period, a data writing period, a threshold acquisition period, and a light emission period.

In the initialization period, the second switch 80402 and the third switch 80403 are turned on,
The potential of the gate terminal of the driving transistor 80400 becomes lower than at least the potential of the power supply line 80412. Note that at this time, the first switch 80401 may be on or off. The initialization period is not always necessary.

In the threshold acquisition period, a pixel is selected by the first scan line 80413. That is, the first switch 80401 is turned on, and a certain voltage is input from the signal line 80411. At this time, the second switch 80402 is on and the drive transistor 80400 is diode-connected. Further, the third switch 80403 is off. Therefore, the potential of the gate terminal of the drive transistor 80400 has a value obtained by subtracting the threshold voltage of the drive transistor 80400 from the potential of the power supply line 80412. The threshold voltage of the driving transistor 80400 is held in the first capacitor 80404. In addition, the second capacitor 80405
Holds the potential difference between the potential of the gate terminal of the driving transistor 80400 and a constant voltage input from the signal line 80411.

In the data writing period, a video signal (voltage) is input from the signal line 80411. At this time, the first switch 80401 remains on, the second switch 80402 remains off, and the second switch 80402 remains off. In addition, a driving transistor 80400
The gate terminal of is in a floating state. Therefore, the potential of the gate terminal of the driving transistor 80400 changes depending on the potential difference between the constant voltage input to the signal line 80411 in the threshold acquisition period and the video signal input to the signal line 80411 in the data writing period. For example, if the capacitance value of the first capacitor 80404 << the capacitance value of the second capacitor 80405, the potential of the gate terminal of the driving transistor 80400 in the data writing period is input to the signal line 80411 in the threshold acquisition period. The potential difference between the constant voltage and the video signal input to the signal line 80411 in the data writing period is approximately equal to the value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80414. That is, the potential of the gate terminal of the drive transistor 80400 becomes a potential obtained by correcting the threshold voltage of the drive transistor 80400.

In the light emitting period, a current corresponding to the potential difference (Vgs) between the gate terminal of the driving transistor 80400 and the power supply line 80412 flows in the display element 80420. At this time, the first switch 80401 is turned off, the second switch 80402 remains off, and the third switch 80403 is turned on. Note that the current flowing in the display element 80420 is the same as that of the driving transistor 8
It is constant regardless of the threshold voltage of 0400.

Note that the pixel structure illustrated in FIG. 101A is not limited to that in FIG. For example, in FIG.
A switch, a resistance element, a capacitance element, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01 (A). In addition, for example, the second switch 80402 is formed using a P-channel transistor or an N-channel transistor, the third switch 80403 is formed using a transistor whose polarity is different from that of the second switch 80402, and the second switch 80402 is formed. Alternatively, the third switch 80403 may be controlled by the same scan line.

Subsequently, regarding an example of a current input type pixel circuit and a driving method which are applicable to this embodiment,
Description will be made with reference to FIG.

A pixel shown in FIG. 101B includes a driving transistor 80430 and a first switch 8043.
It has a first switch 80432, a second switch 80432, a third switch 80433, a capacitor 80434, and a display element 80450. The driving transistor 80430 has a gate terminal connected to the signal line 80441 through the second switch 80432 and the first switch 80431 in order, a first terminal connected to the power supply line 80442, and a second terminal connected to the third terminal. It is connected to the first electrode of the display element 80450 through the switch 80433. Further, the gate terminal of the driving transistor 80430 is connected to the power supply line 80442 through the capacitor 80434. The gate terminal of the driving transistor 80430 is connected to the second terminal of the driving transistor 80430 through the second switch 80432. In addition, the display element 804
A low power supply potential is set to the second electrode 80451 of 50. The low power supply potential is
It is a potential that satisfies the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80442, and the low power supply potential may be set to GND, 0V, or the like. The potential difference between the high power source potential and the low power source potential is applied to the display element 80450 to display the display element 8045.
Since the display element 80450 is caused to emit light by applying a current to 0, the respective potentials are set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80450. Note that the capacitor 80434 can be omitted by substituting the gate capacitance of the driving transistor 80430. Regarding the gate capacitance of the driving transistor 80430,
The capacitance may be formed in a region where the source region, the drain region, the LDD region, and the like overlap the gate electrode and overlap, or the capacitance may be formed between the channel region and the gate electrode. Good. Note that the first switch 80431 and the second switch 804
32 and the third switch 80433 are the first scanning line 80443 and the second scanning line 8 respectively.
ON / OFF is controlled by 0444 and the third scan line 80445.

The pixel driving method shown in FIG. 101B can be divided into a data writing period and a light emitting period.

In the data writing period, a pixel is selected by the first scan line 80443. That is,
The first switch 80431 is turned on, and current is input as a video signal from the signal line 80441. At this time, the second switch 80432 is turned on and the third switch 80433 is turned off. Therefore, the potential of the gate terminal of the driving transistor 80430 becomes a potential according to the video signal. That is, the capacitor 80434 includes a driving transistor 80430.
Holds the voltage between the gate and source of the driving transistor 80430 so that the same current as the video signal flows.

Next, in the light emitting period, the first switch 80431 and the second switch 80432 are turned off and the third switch 80433 is turned on. Therefore, a current having the same value as the video signal flows through the display element 80450.

Note that the pixel structure illustrated in FIG. 101B is not limited to that in FIG. For example, in FIG.
A switch, a resistance element, a capacitance element, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01 (B). Further, for example, the first switch 80431 is formed using a P-channel transistor or an N-channel transistor, the second switch 80432 is formed using a transistor whose polarity is the same as that of the first switch 80431, and the first switch 80431 and the The two switches 80432 may be controlled by the same scan line. In addition, the second switch 8043
2 may be arranged between the gate terminal of the driving transistor 80430 and the signal line 80441.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 13)
In this embodiment, a semiconductor device to which this embodiment is applicable is a thin film transistor (TF).
A method for manufacturing a semiconductor device having T) as an element will be described with reference to the drawings.

FIG. 102 is a diagram showing an example of a structure of a TFT and a manufacturing process which can be included in a semiconductor device to which this embodiment can be applied. FIG. 102A illustrates an example of a structure of a TFT that can be included in a semiconductor device to which this embodiment can be applied. In addition, FIG.
9A to 9G are diagrams illustrating an example of a manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment can be applied.

Note that the structure and manufacturing process of the TFT that can be included in the semiconductor device to which this embodiment can be applied are not limited to those illustrated in FIGS. 102A and 102B, and various structures and manufacturing processes can be used.

First, an example of a structure of a TFT which can be included in a semiconductor device to which this embodiment can be applied will be described with reference to FIG. FIG. 102A shows a T having a plurality of different structures.
It is sectional drawing of FT. Here, in FIG. 102A, T having a plurality of different structures is used.
The FTs are shown side by side, but this is an expression for explaining the structure of the TFT that can be included in the semiconductor device to which the invention can be applied, and the TFT that can be included in the semiconductor device to which the invention can be applied is Actually, it is not necessary that they are juxtaposed as shown in FIG. 102A, but they can be formed as needed.

Next, characteristics of each layer forming a TFT that can be included in a semiconductor device to which this embodiment can be applied will be described.

As the substrate 110111, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a quartz substrate, a ceramic substrate, a metal substrate containing stainless steel, or the like can be used. Besides, polyethylene terephthalate (PET), polyethylene naphthalate (P
It is also possible to use a substrate made of a flexible synthetic resin such as plastic typified by EN) or polyether sulfone (PES) or acrylic. By using a flexible substrate, a bendable semiconductor device can be manufactured. In addition, as long as it is a flexible substrate, the area and the shape of the substrate are not particularly limited. Therefore, for example, if the substrate 110111 has a rectangular shape with one side of 1 meter or more, , The productivity can be remarkably improved. Such an advantage is a great advantage as compared with the case of using a circular silicon substrate.

The insulating film 110112 functions as a base film. The substrate 110111 is provided in order to prevent an alkali metal such as Na or an alkaline earth metal from adversely affecting the characteristics of the semiconductor element. As the insulating film 110112, an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), and silicon nitride oxide (SiNxOy) (x> y). Can be provided with a single layer structure or a laminated structure thereof.
For example, when the insulating film 110112 has a two-layer structure, a silicon nitride oxide film may be provided as the first insulating film and a silicon oxynitride film may be provided as the second insulating film. In addition, the insulating film 110
When 112 is provided in a three-layer structure, a silicon oxynitride film is provided as the first insulating film, a silicon nitride oxide film is provided as the second insulating film, and a silicon oxynitride film is provided as the third insulating film. Good.

The semiconductor films 110113, 110114, and 110115 can be formed using an amorphous semiconductor or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor film may be used. SAS is a semiconductor that has an intermediate structure between amorphous and crystalline structures (including single crystals and polycrystals), has a third state that is stable in terms of free energy, and has a short-range order and a lattice. It contains a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum shifts to a lower wavenumber side than 520 cm ^−1. There is. In X-ray diffraction, diffraction peaks of (111) and (220) which are considered to be derived from a silicon crystal lattice are observed. Unbound hand (
Hydrogen or halogen is contained at least 1 atomic% or more as a compensator for the dangling bond). The SAS is formed by glow discharge decomposition (plasma CVD) of a material gas. As the material gas, SiH ₄ and other Si ₂ H ₆ , SiH ₂ Cl ₂ , S
It is possible to use iHCl ₃ , SiCl ₄ , SiF ₄ or the like. Alternatively, GeF ₄
May be mixed. This material gas may be diluted with H ₂ or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is approximately 0.1 Pa to 133 Pa, the power supply frequency is 1 MHz to 120 MHz,
Preferably 13 MHz-60 MHz. The substrate heating temperature may be 300 ° C. or lower. As the impurity element in the film, it is desirable that the atmospheric impurities such as oxygen, nitrogen, and carbon be 1 × 10 ²⁰ cm ⁻¹ or less, and particularly, the oxygen concentration is 5 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ^1
9 / cm ³ or less. Here, known means (sputtering method, LPCVD method, plasma C
A material containing silicon (Si) as a main component (for example, SixGe1-x) by using the VD method or the like)
A known method of forming an amorphous semiconductor film by using a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, etc. Crystallize by the crystallization method of.

The insulating film 110116 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (
A single-layer structure of an insulating film containing oxygen or nitrogen such as SiOxNy) (x> y) or silicon nitride oxide (SiNxOy) (x> y), or a stacked structure thereof can be provided.

The gate electrode 110117 can have a single-layer conductive film or a stacked-layer structure of two-layer and three-layer conductive films. A known conductive film can be used as a material for the gate electrode 110117. For example, a single film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), or silicon (Si), or a nitride film of the above element (typically, Tantalum nitride film, tungsten nitride film, titanium nitride film), alloy film in which the above elements are combined (typically Mo—W alloy, Mo—Ta alloy), or silicide film of the above elements (typically) A tungsten silicide film, a titanium silicide film) or the like can be used. Note that the single film, the nitride film, the alloy film, the silicide film, and the like described above may be used as a single layer or may be stacked.

The insulating film 110118 is formed by a known method (such as a sputtering method or a plasma CVD method) on silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y),
An insulating film containing oxygen or nitrogen such as silicon nitride oxide (SiNxOy) (x> y) or DLC (
A single layer structure of a film containing carbon such as (diamond-like carbon) or a laminated structure of these can be provided.

The insulating film 110119 is formed of siloxane resin, silicon oxide (SiOx), or silicon nitride (S).
iNx), silicon oxynitride (SiOxNy) (x> y), silicon oxynitride (SiNxOy) (
x> y) or the like insulating film having oxygen or nitrogen, a film containing carbon such as DLC (diamond-like carbon), or epoxy, polyimide, polyamide, polyvinylphenol,
It can be provided as a single layer or a laminated structure made of an organic material such as benzocyclobutene or acrylic. Note that the siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. Note that in the semiconductor device in this embodiment, the insulating film 110119 can be directly provided so as to cover the gate electrode 110117 without providing the insulating film 110118.

The conductive film 110123 is made of Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, M.
A single film of an element such as n, a nitride film of the above element, an alloy film in which the above elements are combined, a silicide film of the above element, or the like can be used. For example, as the alloy containing a plurality of the elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, and the like can be used. Further, in the case of providing a laminated structure, a structure in which Al is sandwiched by Mo, Ti, or the like can be used. By doing so, the resistance of Al to heat and chemical reactions can be improved.

Next, referring to a cross-sectional view of a TFT having a plurality of different structures shown in FIG.
The features of each structure will be described.

The reference numeral 110101 is a single drain TFT, which can be manufactured by a simple method, and thus has advantages of low manufacturing cost and high yield. Here, the semiconductor films 110113 and 1
10115 has different impurity concentrations, the semiconductor film 110113 is a channel region,
The semiconductor film 110115 is used as a source region and a drain region. By controlling the amount of impurities in this manner, the resistivity of the semiconductor film can be controlled. In addition, the semiconductor film and the conductive film 11
The electrical connection state with 0123 can be made closer to ohmic connection. As a method of separately forming semiconductor films having different amounts of impurities, a method of doping impurities into the semiconductor film with the gate electrode 110117 used as a mask can be used.

110102 is a TFT in which the gate electrode 110117 has a taper angle of a certain value or more, and since it can be manufactured by a simple method, it has advantages of low manufacturing cost and high yield. Here, the semiconductor films 110113, 110114, and 110115 have different impurity concentrations, the semiconductor film 110113 is a channel region, the semiconductor film 110114 is a lightly doped drain (LDD) region, and the semiconductor film 110115.
Is used as a source region and a drain region. By controlling the amount of impurities in this manner, the resistivity of the semiconductor film can be controlled. In addition, the electrical connection state between the semiconductor film and the conductive film 110123 can be close to ohmic contact. Also, because it has an LDD region,
It is difficult to apply a high electric field inside the TFT, and it is possible to suppress deterioration of the element due to hot carriers. Note that the gate electrode 11 is used as a method of separately forming semiconductor films having different amounts of impurities.
A method of doping impurities into the semiconductor film with 0117 as a mask can be used.
In 110102, since the gate electrode 110117 has a taper angle of a certain value or more, the concentration of the impurity which passes through the gate electrode 110117 and is doped into the semiconductor film can have a gradient, and the LDD region can be easily formed. Can be formed.

110103 is a TFT in which the gate electrode 110117 is composed of at least two layers, and the lower layer gate electrode is longer than the upper layer gate electrode. In this specification, the shapes of the upper-layer gate electrode and the lower-layer gate electrode are referred to as a hat shape. Gate electrode 110117
Since the shape is a hat shape, the LDD region can be formed without adding a photomask. In addition, as in 110103, the LDD region has a gate electrode 11011.
The structure overlapping with 7 is especially a GOLD structure (Gate Overlapped LDD).
). Note that the following method may be used as a method of forming the gate electrode 110117 into a hat shape.

First, when patterning the gate electrode 110117, the gate electrode in the lower layer and the gate electrode in the upper layer are etched by dry etching to have a shape with a side surface having an inclination (taper). Subsequently, anisotropic etching is performed so that the upper-layer gate electrode is inclined so as to be nearly vertical. As a result, a gate electrode having a hat-shaped cross section is formed. After that, twice
A semiconductor film 1101 used as a channel region by doping with an impurity element
13, a semiconductor film 110114 used as an LDD region, and a semiconductor film 110115 used as a source electrode and a drain electrode are formed.

The LDD region overlapping the gate electrode 110117 is the Lov region, and the gate electrode 11
The LDD region that does not overlap with 0117 will be referred to as the Loff region. Where Lof
The f region has a high effect of suppressing the off current value, but has a low effect of relaxing the electric field near the drain and preventing the deterioration of the on current value due to hot carriers. On the other hand, the Lov region relaxes the electric field near the drain and is effective in preventing the deterioration of the on-current value, but has a low effect of suppressing the off-current value. Therefore, it is preferable to manufacture a TFT having a structure according to the required characteristics for each of various circuits. For example, when the semiconductor device of this embodiment is used as a display device, the pixel TFT
In order to suppress the off current value, it is preferable to use a TFT having a Loff region. On the other hand, as the TFT in the peripheral circuit, it is preferable to use a TFT having a Lov region in order to relax the electric field near the drain and prevent deterioration of the on-current value.

110104 is in contact with the side surface of the gate electrode 110117 to form a sidewall 110121.
It is a TFT having. By including the sidewall 110121, a region overlapping with the sidewall 110121 can be an LDD region.

110105 is an LDD (Lof
f) A TFT in which a region is formed. By doing so, the LDD region can be reliably formed, and the off current value of the TFT can be reduced.

110106 is an LDD (Lov) by doping a semiconductor film using a mask.
) Is a TFT in which a region is formed. By doing so, the LDD region can be reliably formed, the electric field in the vicinity of the drain of the TFT can be relaxed, and the deterioration of the on-current value can be reduced.

Next, an example of a manufacturing process of a TFT which can be included in a semiconductor device to which this embodiment can be applied will be described with reference to FIGS.
Note that the structure and manufacturing process of the TFT that can be included in the semiconductor device to which this embodiment can be applied are not limited to those illustrated in FIGS. 102A and 102B, and various structures and manufacturing processes can be used.

In this embodiment mode, on the surface of the substrate 110111, on the surface of the insulating film 110112, on the surface of the semiconductor film 110113, on the surface of 110114, on the surface of 110115, the insulating film 1 is formed.
By oxidizing or nitriding the surface of 10116, the surface of the insulating film 110118, or the surface of the insulating film 110119 with plasma treatment, the semiconductor film or the insulating film can be oxidized or nitrided. As described above, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film by using plasma treatment, and C
Since a denser insulating film can be formed as compared with an insulating film formed by a VD method or a sputtering method, defects such as pinholes can be suppressed and characteristics of a semiconductor device can be improved.

First, the surface of the substrate 110111 is washed with hydrofluoric acid (HF), alkali, or pure water. As the substrate 110111, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a quartz substrate, a ceramic substrate, a metal substrate containing stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET), polyethylene naphthalate (
It is also possible to use a substrate made of plastic such as PEN) or polyether sulfone (PES) or a flexible synthetic resin such as acrylic. Note that here, a case where a glass substrate is used as the substrate 110111 is shown.

Here, an oxide film or a nitride film may be formed on the surface of the substrate 110111 by performing plasma treatment on the surface of the substrate 110111 to oxidize or nitride the surface of the substrate 110111 (FIG. 102B). .. An insulating film such as an oxide film or a nitride film formed by performing plasma treatment on the surface is also referred to as a plasma-treated insulating film below. In FIG. 102B, the insulating film 110131 is a plasma treatment insulating film. Generally, when a semiconductor element such as a thin film transistor is provided on a substrate such as glass or plastic, an impurity element such as alkali metal or alkaline earth metal such as Na contained in glass or plastic is mixed into the semiconductor element. Contamination may affect the characteristics of the semiconductor device. However, by nitriding the surface of the substrate made of glass, plastic, or the like, it is possible to prevent the impurity element such as Na or alkali metal or alkaline earth metal contained in the substrate from being mixed into the semiconductor element.

In addition, when the surface is oxidized by the plasma treatment, the oxygen atmosphere (for example, oxygen (O ₂
) And a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, or an atmosphere of oxygen and hydrogen (H ₂ ) and a rare gas, or an atmosphere of dinitrogen monoxide and a rare gas. ) And plasma treatment. On the other hand, when nitriding the semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, in a nitrogen (N ₂ ) and rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, or Plasma treatment is performed in an atmosphere of nitrogen and hydrogen and a rare gas, or in an atmosphere of NH ₃ and a rare gas. For example, Ar can be used as the rare gas. Alternatively, a gas in which Ar and Kr are mixed may be used. Therefore, the plasma treatment insulating film contains the rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. For example, when Ar is used, the plasma-treated insulating film contains Ar.

In the plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ in the atmosphere of the above gas.
Or more and 1 × 10 ¹³ cm ⁻³ or less, and the plasma electron temperature is 0.5 ev or more and 1.5 eV
It is preferable to do the following. Since the plasma has a high electron density and the electron temperature near the object to be processed is low, damage to the object to be processed due to the plasma can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is C
As compared with a film formed by the VD method, the sputtering method, or the like, it is possible to form a dense film having excellent uniformity in film thickness and the like. Alternatively, since the electron temperature of the plasma is as low as 1 eV or less, the oxidation or nitriding treatment can be performed at a lower temperature than the conventional plasma treatment or thermal oxidation method. For example, even if the plasma treatment is performed at a temperature lower than the strain point temperature of the glass substrate by 100 degrees or more, the oxidation or nitriding treatment can be sufficiently performed. Note that a high frequency wave such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Unless otherwise specified below, the plasma treatment is performed under the above conditions.

Note that FIG. 102B illustrates the case where the plasma-treated insulating film is formed by performing plasma treatment on the surface of the substrate 110111; however, in this embodiment, the substrate 1101 is used.
It also includes the case where the plasma-treated insulating film is not formed on the surface of 11.

Note that although a plasma-treated insulating film formed by performing plasma treatment on the surface of the object to be processed is not illustrated in FIGS. 102C to 102G, the substrate 1 is used in this embodiment mode.
10111, insulating film 110112, semiconductor films 110113, 110114, 110115
, A case where a plasma-treated insulating film formed by performing plasma treatment exists on the surface of the insulating film 110116, the insulating film 110118, or the insulating film 110119.

Next, an insulating film 110112 is formed over the substrate 110111 by a known method (a sputtering method, an LPCVD method, a plasma CVD method, or the like) (FIG. 102C). As the insulating film 110112, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) can be used.

Here, a plasma treatment insulating film may be formed on the surface of the insulating film 110112 by performing plasma treatment on the surface of the insulating film 110112 and oxidizing or nitriding the insulating film 110112. By oxidizing the surface of the insulating film 110112, the surface of the insulating film 110112 can be modified and a dense film with few defects such as pinholes can be obtained. In addition, the insulating film 110
By oxidizing the surface of 112, a plasma-treated insulating film having a low N atom content can be formed. Therefore, when a semiconductor film is provided as the plasma-treated insulating film, the interface characteristics of the plasma-treated insulating film and the semiconductor film are different from each other. improves. The plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. In addition,
The plasma treatment can be similarly performed under the above-mentioned conditions.

Next, island-shaped semiconductor films 110113 and 110114 are formed over the insulating film 110112 (
FIG. 102 (D)). The island-shaped semiconductor films 110113 and 110114 are the insulating films 110112.
The above-mentioned silicon (sputtering method, LPCVD method, plasma CVD method, etc.)
Provided by forming an amorphous semiconductor film using a material containing Si as a main component (for example, SixGe1-x), crystallizing the amorphous semiconductor film, and selectively etching the semiconductor film. be able to. Note that the amorphous semiconductor film is crystallized by a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. The known crystallization method can be used. Note that here, the end portions of the island-shaped semiconductor film are provided in a shape close to a right angle (θ = 85 to 100 °).
Alternatively, the semiconductor film 110114 to be the low-concentration drain region may be formed by doping impurities with a mask.

Here, plasma treatment is performed on the surfaces of the semiconductor films 110113 and 110114 to remove the semiconductor film 1.
By oxidizing or nitriding the surfaces of 10113 and 110114, the semiconductor film 1101
A plasma-treated insulating film may be formed on the surface of 13, 110114. For example, the semiconductor film 1
When Si is used for 10113 and 110114, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the plasma treatment insulating film. Alternatively, after the semiconductor films 110113 and 110114 are oxidized by plasma treatment, plasma treatment may be performed again to nitride the semiconductor films 110113 and 110114. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 110113 and 110114, and silicon nitride oxide (SiNxOy) (is formed on the surface of the silicon oxide.
x> y) is formed. Note that in the case of oxidizing the semiconductor film by plasma treatment, in an oxygen atmosphere (for example, an atmosphere of oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe)), or Plasma treatment is performed in an atmosphere of oxygen and hydrogen (H ₂ ) and a rare gas or in an atmosphere of dinitrogen monoxide and a rare gas. On the other hand, when nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (He, Ne, Ar, Kr).
, Xe) or in an atmosphere of nitrogen and hydrogen and a rare gas or in an atmosphere of NH ₃ and a rare gas). For example, Ar can be used as the rare gas. Moreover, you may use the gas which mixed Ar and Kr. Therefore, the plasma treatment insulating film contains the rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. For example, when Ar is used, A is used as the plasma treatment insulating film.
r is included.

Next, the insulating film 110116 is formed (FIG. 102E). The insulating film 110116 is formed of silicon oxide (SiO 2) by using known means (sputtering method, LPCVD method, plasma CVD method, etc.).
x), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like, a single-layer structure of an insulating film containing oxygen or nitrogen, or a stacked layer thereof. It can be provided in a structure. Note that when the plasma treatment insulating film is formed on the surfaces of the semiconductor films 110113 and 110114 by performing plasma treatment on the surfaces of the semiconductor films 110113 and 110114, the plasma treatment insulating film can be used as the insulating film 110116. ..

Here, a plasma treatment insulating film may be formed on the surface of the insulating film 110116 by performing plasma treatment on the surface of the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116. Note that the plasma-treated insulating film is a rare gas (He, Ne) used for plasma treatment.
, Ar, Kr, and Xe). Further, the plasma treatment can be similarly performed under the above-mentioned conditions.

Alternatively, the insulating film 110116 may be once oxidized by performing plasma treatment in an oxygen atmosphere and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this manner, by performing plasma treatment on the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116, the surface of the insulating film 110116 can be modified and a dense film can be formed. The insulating film obtained by performing the plasma treatment is denser and has fewer defects such as pinholes as compared with an insulating film formed by a CVD method or a sputtering method; therefore, the characteristics of the thin film transistor can be improved.

Next, the gate electrode 110117 is formed (FIG. 102F). Gate electrode 110117
Can be formed by using known means (sputtering method, LPCVD method, plasma CVD method, etc.).

In 110101, the semiconductor film 110115 used as a source region and a drain region can be formed by performing impurity doping after forming the gate electrode 110117.

In 110102, after the gate electrode 110117 is formed, impurity doping is performed, so that 110114 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

In 110103, by performing impurity doping after forming the gate electrode 110117, a 110114 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

In 110104, a sidewall 110121 is formed on the side surface of the gate electrode 110117.
And then used as an LDD region by performing impurity doping.
Then, a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

The sidewall 110121 is made of silicon oxide (SiOx) or silicon nitride (SiNx).
) Can be used. As a method of forming the side wall 110121 on the side surface of the gate electrode 110117, for example, after forming the gate electrode 110117, silicon oxide (SiOx) or silicon nitride (SiNx) is formed by a known method, and then anisotropic. A method of etching a silicon oxide (SiOx) or silicon nitride (SiNx) film by etching can be used. Thus, silicon oxide (only on the side surface of the gate electrode 110117 (
Since the SiOx) or silicon nitride (SiNx) film can be left, the gate electrode 1101
A sidewall 110121 can be formed on the side surface of 17.

In 110105, a mask 110122 is formed so as to cover the gate electrode 110117, and then impurity doping is performed to use it as an LDD (Loff) region 11
0114 and a semiconductor film 110115 used as a semiconductor film source region and a drain region.
Can be formed.

In 110106, by performing impurity doping after forming the gate electrode 110117, a 110114 used as an LDD (Lov) region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

Next, the insulating film 110118 is formed (FIG. 102G). The insulating film 110118 is formed of silicon oxide (SiOx) or silicon nitride (SiOx) by a known means (such as a sputtering method or a plasma CVD method).
SiNx), silicon oxynitride (SiOxNy) (x> y), silicon oxynitride (SiNxOy)
Insulating film containing oxygen or nitrogen such as (x> y) or DLC (diamond-like carbon)
It is possible to provide a single layer structure of a film containing carbon such as, or a laminated structure thereof.

Here, a plasma treatment insulating film may be formed on the surface of the insulating film 110118 by performing plasma treatment on the surface of the insulating film 110118 and oxidizing or nitriding the surface of the insulating film 110118. Note that the plasma-treated insulating film is a rare gas (He, Ne) used for plasma treatment.
, Ar, Kr, and Xe). Further, the plasma treatment can be similarly performed under the above-mentioned conditions.

Next, the insulating film 110119 is formed. The insulating film 110119 is formed by known means (such as a sputtering method or a plasma CVD method) on silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) ( In addition to an insulating film containing oxygen or nitrogen such as x> y) or a film containing carbon such as DLC (diamond-like carbon), epoxy, polyimide, polyamide, polyvinylphenol,
A single layer structure of an organic material such as benzocyclobutene or acrylic, or a siloxane resin, or a laminated structure of these can be provided. Note that the siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. The plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. For example, when Ar is used, the plasma-treated insulating film is used. Ar is contained in the film.

When an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane resin is used as the insulating film 110119, the insulating film 110119 is used.
The surface of the insulating film can be modified by oxidizing or nitriding its surface by plasma treatment. By modifying the surface, the strength of the insulating film 110119 is improved, and it is possible to reduce physical damage such as generation of cracks at the time of forming openings and film loss at the time of etching. Further, by modifying the surface of the insulating film 110119, the adhesion with the conductive film is improved when the conductive film 110123 is formed over the insulating film 110119.
For example, when nitriding is performed using plasma treatment with a siloxane resin for the insulating film 110119, the surface of the siloxane resin is nitrided, whereby a plasma-treated insulating film containing nitrogen or a rare gas is formed, and physical strength is increased. improves.

Next, in order to form the conductive film 110123 which is electrically connected to the semiconductor film 110115,
Contact holes are formed in the insulating film 110119, the insulating film 110118, and the insulating film 110116. The shape of the contact hole may be tapered. By doing this,
The coverage of the conductive film 110123 can be improved.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 14)
In this embodiment mode, a detailed structure of a light-emitting element which can be applied to a display device in which this embodiment mode is implemented will be described.

A light emitting element utilizing electroluminescence is distinguished depending on whether a light emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

The inorganic EL element is classified into a dispersion type inorganic EL element and a thin film type inorganic EL element depending on the element structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, and the latter has an electroluminescent layer composed of a thin film of a luminescent material, but is accelerated by a high electric field. It is common in that it requires an electron. Note that as a mechanism of light emission obtained, there are donor-acceptor recombination type light emission utilizing a donor level and an acceptor level, and localized type light emission utilizing a core electron transition of a metal ion. Generally, in the dispersed inorganic EL, the donor-
In many cases, the acceptor recombination type emission and the thin film type inorganic EL element are localized type emission.

A light-emitting material that can be used in this embodiment includes a base material and an impurity element which serves as a light emission center. Light emission of various colors can be obtained by changing the contained impurity element. Various methods such as a solid phase method and a liquid phase method (coprecipitation method) can be used as a method for manufacturing the light emitting material. Alternatively, a spray pyrolysis method, a metathesis method, a method by a pyrolysis reaction of a precursor, a reverse micelle method, a method combining these methods and high temperature firing, a liquid phase method such as a freeze-drying method, and the like can be used.

The solid phase method is to measure a base material and an impurity element or a compound containing an impurity element and mix them in a mortar.
This is a method in which the base material contains an impurity element by heating and firing in an electric furnace to cause a reaction. The firing temperature is preferably 700 to 1500 ° C. This is because if the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the host material will decompose. Although firing may be performed in a powder state, firing is preferably performed in a pellet state. Although it requires firing at a relatively high temperature, it is a simple method and has good productivity and is suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing a base material is reacted with an impurity element or a compound containing an impurity element in a solution, dried, and then baked. The particles of the light emitting material are uniformly distributed, the particle size is small, and the reaction can proceed even at a low baking temperature.

As the base material used for the light-emitting material, sulfide, oxide, or nitride can be used.
Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), and sulfide. Barium (BaS) or the like can be used. As the oxide, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ) or the like can be used. As the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Further, zinc selenide (ZnSe), or the like can also be used zinc telluride (ZnTe), calcium sulfide - gallium (CaGa ₂ S _4), strontium sulfide - gallium (SrGa ₂ S _4), barium sulfide - gallium (BaGa _It may be a ternary mixed crystal such as ₂ S ₄ ).

Manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium is used as the emission center of localized emission. (Pr) or the like can be used. A halogen element such as fluorine (F) or chlorine (Cl) may be added for charge compensation.

On the other hand, as a luminescent center of donor-acceptor recombination type luminescence, a first donor level is formed.
The light-emitting material containing the impurity element and the second impurity element forming the acceptor level can be used. As the first impurity element, for example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used. As the second impurity element, for example, copper (Cu),
Silver (Ag) or the like can be used.

When a light-emitting material for donor-acceptor recombination emission is synthesized by a solid-phase method, a host material, a first impurity element or a compound containing the first impurity element, a second impurity element, or a second impurity element
Each of the compounds containing the impurity element is weighed, mixed in a mortar, and then heated and baked in an electric furnace. As the base material, the base material described above can be used, and examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), and aluminum sulfide (Al ₂ S). ₃ ) and the like, and examples of the second impurity element or the compound containing the second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), and silver sulfide (Ag). ₂ S) or the like can be used. The firing temperature is preferably 700 to 1500 ° C.
This is because if the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the host material will decompose. Although firing may be performed in a powder state, firing is preferably performed in a pellet state.

Further, as the impurity element in the case of utilizing the solid-phase reaction, a compound composed of the first impurity element and the second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction is likely to proceed, a uniform light emitting material can be obtained. Furthermore, since an extra impurity element does not enter, a light emitting material with high purity can be obtained. As the compound composed of the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.

Note that the concentration of these impurity elements may be 0.01 to 10 atom% with respect to the base material, and is preferably in the range of 0.05 to 5 atom%.

In the case of a thin film type inorganic EL, the electroluminescent layer is a layer containing the above-mentioned light emitting material, and the resistance heating vapor deposition method,
Vacuum evaporation methods such as electron beam evaporation (EB evaporation), physical vapor deposition methods such as sputtering (
PVD), metalorganic CVD, hydride transport low pressure CVD, and other chemical vapor deposition (CV)
D), atomic epitaxy (ALE), or the like.

103A to 103C show an example of a thin film type inorganic EL element which can be used as a light emitting element. In FIGS. 103A to 103C, the light-emitting element is the first electrode layer 120100.
, An electroluminescent layer 120102, and a second electrode layer 120103.

The light-emitting element shown in FIGS. 103B and 103C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element of FIG. 103A. The light-emitting element shown in FIG. 103B has an insulating layer 120104 between a first electrode layer 120100 and an electroluminescent layer 120102, and the light-emitting element shown in FIG. 103C has a first electrode layer 120100. And electroluminescent layer 120
102, an insulating layer 120105, a second electrode layer 120103, and an electroluminescent layer 12010.
2 and the insulating layer 120106. As described above, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Also,
The insulating layer may be a single layer or a stacked layer including a plurality of layers.

Note that in FIG. 103B, the insulating layer 120104 is in contact with the first electrode layer 120100.
However, the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120103 is provided.
The insulating layer 120104 may be provided so as to be in contact with.

In the case of a dispersion type inorganic EL, a particulate electroluminescent material is dispersed in a binder to form a film electroluminescent layer. Process into particles. When particles having a desired size cannot be obtained depending on the method for manufacturing the light-emitting material, the particles may be processed into particles by pulverization in a mortar or the like. What is a binder?
It is a substance for fixing a granular light emitting material in a dispersed state and maintaining the shape as an electroluminescent layer. The light emitting material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of the dispersion type inorganic EL, the method for forming the electroluminescent layer includes a droplet discharge method capable of selectively forming the electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coating method, and dipping. Method, dispenser method, etc. can also be used. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. Further, in the electroluminescent layer including the light emitting material and the binder, the proportion of the light emitting material may be 50 wt% or more and 80 wt% or less.

104A to 104C each show an example of a dispersion-type inorganic EL element which can be used as a light-emitting element. The light-emitting element in FIG. 104A has a stacked-layer structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and a light-emitting material 120201 held by a binder in the electroluminescent layer 120202. Including.

An insulating material can be used for the binder that can be used in this embodiment mode. As the insulating material, an organic material and an inorganic material can be used. Alternatively, a mixed material of an organic material and an inorganic material may be used. As the organic insulating material, a polymer having a relatively high dielectric constant such as cyanoethyl cellulose resin, or a resin such as polyethylene, polypropylene, polystyrene resin, silicone resin, epoxy resin, or vinylidene fluoride can be used. Alternatively, aromatic polyamide, polybenzimidazole (polybenzi)
A heat resistant polymer such as midazole) or a siloxane resin may be used. Note that the siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used. A fluoro group may be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Alternatively, a resin material such as a polyvinyl resin such as polyvinyl alcohol or polyvinyl butyral, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, a urethane resin, or an oxazole resin (polybenzoxazole) may be used. Barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ) are added to these resins.
It is also possible to adjust the dielectric constant by appropriately mixing fine particles having a high dielectric constant such as).

The inorganic insulating material contained in the binder includes silicon oxide (SiOx) and silicon nitride (SiNx).
), Silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, aluminum oxide containing oxygen and nitrogen (Al ₂ O ₃ ), titanium oxide (TiO ₂ ).
, BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KN
bO _3), lead niobate (PbNbO _3), tantalum oxide _{(Ta 2 O} 5), barium tantalate (BaTa ₂ O _6), lithium tantalate (LiTaO _3), yttrium oxide (Y
₂ O ₃ ), zirconium oxide (ZrO ₂ ), ZnS, and other materials including an inorganic insulating material can be used. By including (by adding, etc.) an inorganic material having a high dielectric constant in the organic material, the dielectric constant of the electroluminescent layer composed of the light emitting material and the binder can be more controlled, and the dielectric constant can be further increased. ..

In the manufacturing process, the light emitting material is dispersed in a solution containing a binder. As a solvent of a solution containing a binder that can be used in this embodiment mode, a method in which a binder material is dissolved to form an electroluminescent layer (various wet processes) and a solution having a viscosity suitable for a desired film thickness can be manufactured Such a solvent may be appropriately selected. For example, an organic solvent or the like can be used as the solvent. When using a siloxane resin as a binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also called PGMEA)
, 3-methoxy-3-methyl-1-butanol (also referred to as MMB) or the like can be used as a solvent.

The light-emitting element shown in FIGS. 104B and 104C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element of FIG. 104A. The light-emitting element shown in FIG. 104B has an insulating layer 120204 between a first electrode layer 120200 and an electroluminescent layer 120202, and the light-emitting element shown in FIG. 104C has a first electrode layer 120200. And electroluminescent layer 120
The insulating layer 120205, the second electrode layer 120203 and the electroluminescent layer 12020
2 and an insulating layer 120206. As described above, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. The insulating layer may be a single layer or a stacked layer including a plurality of layers.

In addition, in FIG. 104B, the insulating layer 120204 is in contact with the first electrode layer 120200.
However, the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120203 is provided.
The insulating layer 120204 may be provided so as to be in contact with.

A material that can be used for an insulating layer such as the insulating layer 120104 in FIG. 103 and the insulating layer 120204 in FIG. 104 preferably has high insulation resistance and a dense film quality.
Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTi
O ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), and the like, or a mixed film thereof or a laminated film of two or more kinds thereof is used. be able to. These insulating films can be formed by sputtering, vapor deposition, CVD or the like. The insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder included in the electroluminescent layer. The film thickness is not particularly limited, but is preferably 10 to 10
The range is 00 nm.

The light-emitting element described in this embodiment can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, but can operate in either direct-current driving or alternating-current driving.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 15)
In the present embodiment, an example of a display device capable of implementing the present embodiment, particularly a case of performing optical handling will be described.

A rear projection display device 130100 shown in FIGS. 105A and 105B includes a projector unit 130111, a mirror 130112, and a screen panel 130101.
In addition, a speaker 130102 and operation switches 130104 may be provided. The projector unit 130111 is a housing 130 of the rear projection display device 130100.
The mirror 13011 is provided below the mirror 110 and projects projection light for projecting an image based on an image signal.
Project toward 2. The rear projection display device 130100 has a screen panel 130101.
It is configured to display the image projected from the back of the.

On the other hand, FIG. 106 shows a front projection display device 130200. The front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201. The projection optical system 130201 is configured to project an image on a screen or the like arranged on the front surface.

The configuration of a projector unit 130111 applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG. 106 will be described below.

FIG. 107 shows a configuration example of the projector unit 130111. The projector unit 130111 includes a light source unit 130301 and a modulation unit 13030.
4 is equipped. The light source unit 130301 includes a light source optical system 130303 including lenses and a light source lamp 130302. The light source lamp 130302 is housed in the housing so that stray light does not diffuse. As the light source lamp 130302, for example, a high pressure mercury lamp or a xenon lamp that can emit a large amount of light is used. The light source optical system 130303 is configured by appropriately providing an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film and the like. Then, the light source unit 130301
Are arranged so that the emitted light is incident on the modulation unit 130304. The modulation unit 130304 includes a plurality of display panels 130308, color filters, a dichroic mirror 130305, a total reflection mirror 130306, a prism 130309, and a projection optical system 13.
It is equipped with 0310. The light emitted from the light source unit 130301 is separated into a plurality of optical paths by the dichroic mirror 130305.

Each optical path is provided with a color filter that transmits light of a predetermined wavelength or a wavelength band, and a display panel 130308. The transmissive display panel 130308 modulates transmitted light based on a video signal. The light of each color transmitted through the display panel 130308 is reflected by the prism 13
It is incident on 0309, and an image is displayed on the screen through the projection optical system 130310. A Fresnel lens may be provided between the mirror and the screen. Then, the projection light projected by the projector unit 130111 and reflected by the mirror is converted into substantially parallel light by the Fresnel lens and projected on the screen.

The projector unit 130111 shown in FIG. 108 has a reflective display panel 130407.
, 130408, 130409 are shown.

The projector unit 130111 shown in FIG. 108 includes a light source unit 130301 and a modulation unit 130400. The light source unit 130301 may have the same configuration as in FIG. 107. Light from the light source unit 130301 is emitted from the dichroic mirror 13.
0401, 130402, the total reflection mirror 130403, it is divided into a plurality of optical paths,
It enters the polarization beam splitters 130404, 130405, and 130406. The polarization beam splitters 130404, 130405, 130406 are provided corresponding to the reflective display panels 130407, 130408, 130409 corresponding to the respective colors. The reflective display panels 130407, 130408, 130409 modulate the reflected light based on the video signal. The lights of the respective colors reflected by the reflective display panels 130407, 130408, 130409 are incident on the prism 130309 to be combined and projected through the projection optical system 130411.

The light emitted from the light source unit 130301 is transmitted through the dichroic mirror 130401 only in the red wavelength region and reflected in the green and blue wavelength regions. Further, the dichroic mirror 130402 reflects only light in the green wavelength range. The light in the red wavelength region that has passed through the dichroic mirror 130401 is reflected by the total reflection mirror 130403 and enters the polarization beam splitter 130404, and the light in the blue wavelength region enters the polarization beam splitter 130405 and the green wavelength region. The light in the area is polarized beam splitter 1304.
It is incident on 06. The polarization beam splitters 130404, 130405, 130406 are
It has a function of separating incident light into P-polarized light and S-polarized light, and has a function of transmitting only P-polarized light. The reflective display panels 130407, 130408, 130409 polarize the incident light based on the video signal.

Only S-polarized light corresponding to each color is incident on the reflective display panels 130407, 130408, and 130409 corresponding to each color. Note that the reflective display panels 130407 and 130408.
, 130409 may be a liquid crystal panel. At this time, the liquid crystal panel operates in the electric field control birefringence mode (ECB). Further, the liquid crystal molecules are vertically aligned at a certain angle with respect to the substrate. Therefore, in the reflective display panels 130407, 130408, and 130409, the display molecules are oriented so that the incident light is reflected without changing the polarization state when the pixel is in the off state. Further, when the pixel is in the ON state, the alignment state of the display molecules changes, and the polarization state of incident light changes.

The projector unit 130111 shown in FIG. 108 can be applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG. 106.

The projector unit shown in FIG. 109 has a single plate configuration. A projector unit 130111 shown in FIG. 109A includes a light source unit 130301, a display panel 1
30507, a projection optical system 130511, and a retardation plate 130504. The projection optical system 130511 is composed of one or a plurality of lenses. The display panel 130507 may be provided with a color filter.

FIG. 109B shows a projector unit 1 that operates in the field sequential system.
The structure of 30111 is shown. The field-sequential system is a system in which light of each color such as red, green, and blue is temporally shifted and sequentially made incident on a display panel to perform color display without a color filter. In particular, when combined with a display panel having a high response speed with respect to a change in an input signal, a high definition image can be displayed. In FIG. 109B, a rotatable color filter plate 130505 provided with a plurality of color filters of red, green, blue, and the like is provided between the light source unit 130301 and the display panel 130508.

A projector unit 130111 shown in FIG. 109C has a color separation method using a macro lens as a color display method. In this system, a microlens array 130506 is provided on the light incident side of the display panel 130509, and color display is realized by illuminating light of each color from each direction. The projector unit 130111 adopting this method has a feature that light from the light source unit 130301 can be effectively used because light loss due to the color filter is small. Figure 10
A projector unit 130111 illustrated in FIG. 9C includes a dichroic mirror 130501, a dichroic mirror 130502, and a red light dichroic mirror 130503 so as to illuminate the display panel 130509 with light of each color from each direction.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 16)
In this embodiment, examples of electronic devices according to this embodiment will be described.

FIG. 110 shows a display panel module in which a display panel 900101 and a circuit board 900111 are combined. The display panel 900101 includes a pixel portion 900102, a scan line driver circuit 900103, and a signal line driver circuit 900104. On the circuit board 900111, for example, a control circuit 900112, a signal division circuit 900113, and the like are formed. The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114. An FPC or the like can be used for the connection wiring.

In the display panel 900101, a pixel portion 900102 and a part of peripheral driving circuits (a driving circuit with a low operating frequency among a plurality of driving circuits) are formed over a substrate by using TFTs, and a part of the peripheral driving circuits (a plurality of A driver circuit having a high operating frequency among driver circuits may be formed over an IC chip and the IC chip may be mounted on the display panel 900101 by COG (Chip On Glass) or the like. Thus, the area of the circuit board 900111 can be reduced and a small display device can be obtained. Alternatively, the IC chip may be replaced with a TAB (Tape Auto B
onboard) or a printed board. By doing so, the area of the display panel 900101 can be reduced, so that a display device with a small frame size can be obtained.

For example, in order to reduce power consumption, a pixel portion is formed using a TFT on a glass substrate, all peripheral driver circuits are formed on an IC chip, and the IC chip is mounted on a display panel by COG or TAB. May be.

A television receiver can be completed with the display panel module illustrated in FIG. FIG. 111 is a block diagram showing a main configuration of a television receiver. Tuner 9002
01 receives a video signal and an audio signal. The video signal includes a video signal amplifier circuit 900202,
A video signal processing circuit 900203 that converts a signal output from the video signal amplifier circuit 900202 into color signals corresponding to red, green, and blue colors, and a control circuit 900212 that converts the video signal into input specifications of a driver circuit. Is processed by. Control circuit 9002
Reference numeral 12 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 900213 may be provided on the signal line side and an input digital signal may be divided into m (m is a positive integer) and supplied.

Of the signals received by the tuner 900201, the audio signal is the audio signal amplifier circuit 900205.
To the speaker 900207 via the audio signal processing circuit 900206. The control circuit 900208 inputs the control information of the receiving station (reception frequency) and volume to the input unit 9.
The signal is received from 00209, and a signal is transmitted to the tuner 900201 and the audio signal processing circuit 900206.

FIG. 112A shows a television receiver incorporating a display panel module which is different from that in FIG. 111. In FIG. 112A, a display screen 900302 contained in a housing 900301 is formed using a display panel module. The speaker 90030
3, the operation switch 900304 and the like may be appropriately provided.

In addition, FIG. 112B shows a television receiver in which only the display can be wirelessly carried. A battery and a signal receiver are incorporated in the housing 900312, and the display portion 900313 and the speaker portion 930017 are driven by the battery. The battery can be repeatedly charged by the charger 900310. In addition, the charger 900310 can transmit and receive a video signal, and the video signal can be transmitted to a signal receiver of a display. The housing 900312 is controlled by operation keys 900316. Alternatively, FIG.
The device shown in FIG. 12B operates the operation key 900316 to operate the housing 9003.
It may be a video / audio two-way communication device capable of sending a signal from 12 to the charger 900310. Alternatively, by operating the operation key 900316, the housing 9003
It may be a general-purpose remote control device capable of controlling the communication of another electronic device by sending a signal from 12 to the charger 900310 and by causing another electronic device to receive the signal that can be transmitted by the charger 900310. .. This embodiment can be applied to the display portion 900313.

FIG. 113A shows a module in which a display panel 900401 and a printed wiring board 900402 are combined. A display panel 900401 includes a pixel portion 900403 provided with a plurality of pixels, a first scan line driver circuit 900404, and a second scan line driver circuit 9004.
05, and a signal line driver circuit 900406 which supplies a video signal to the selected pixel.

A printed circuit board 900402 includes a controller 900407 and a central processing unit (CPU).
) 900408, memory 900409, power supply circuit 900410, audio processing circuit 90041
1 and a transmission / reception circuit 900412 and the like. The printed wiring board 900402 and the display panel 900401 are connected by a flexible wiring board (FPC) 900413. A printed wiring board (FPC) 900413 may be provided with a storage capacitor, a buffer circuit, or the like to prevent noise from being added to a power supply voltage or a signal or a slow rise of a signal. Further, the controller 900407, the audio processing circuit 900411, the memory 900409, the central processing unit (CPU) 900408, the power supply circuit 900410, and the like can be mounted on the display panel 900401 by a COG (Chip On Glass) method. The COG method can reduce the scale of the printed wiring board 900402.

Interface (I / F) unit 900414 provided on the printed wiring board 900402
Various control signals are input and output via the. Further, an antenna port 900415 for transmitting / receiving a signal to / from the antenna is provided in the printed wiring board 900402.

FIG. 113 (B) shows a block diagram of the module shown in FIG. 113 (A). This module includes a VRAM 900416, a DRAM 900417, a flash memory 900418, and the like as the memory 900409. The VRAM 900416 stores image data to be displayed on the panel, the DRAM 900417 stores image data or audio data, and the flash memory stores various programs.

The power supply circuit 900410 supplies power for operating the display panel 900401, the controller 900407, the central processing unit (CPU) 900408, the audio processing circuit 900411, the memory 900409, and the transmission / reception circuit 900421. Depending on the specifications of the panel, the power supply circuit 900410 may include a current source.

The central processing unit (CPU) 900408 includes a control signal generation circuit 900420 and a decoder 90.
0421, a register 900422, an arithmetic circuit 900423, a RAM 900424, an interface 900419 for a central processing unit (CPU) 900408, and the like. Various signals input to the central processing unit (CPU) 900408 through the interface 900419 are temporarily held in the register 900422, and then input to the arithmetic circuit 900423, the decoder 900421, and the like. The arithmetic circuit 900423 performs arithmetic operations based on the input signal and specifies a place to send various commands. On the other hand, the signal input to the decoder 900421 is decoded and input to the control signal generation circuit 900420. The control signal generation circuit 900420 generates a signal including various commands based on the input signal, and the arithmetic circuit 900
The location designated in 423, specifically, the memory 900409, the transmission / reception circuit 90041
2. Send to the voice processing circuit 900411, controller 900407, etc.

The memory 900409, the transmission / reception circuit 900412, the voice processing circuit 900411, and the controller 900407 operate according to the received instructions. The operation will be briefly described below.

The signal input from the input means 900425 is the interface (I / F) unit 90041.
Central processing unit (CPU) 9004 mounted on a printed wiring board 900402 via
Sent to 08. The control signal generation circuit 900420 converts the image data stored in the VRAM 900416 into a predetermined format in accordance with a signal sent from the input device 900425 such as a pointing device or a keyboard, and sends the image data to the controller 900407.

The controller 900407 is a central processing unit (CPU) 9004 according to the panel specifications.
The signal including the image data sent from 08 is subjected to data processing, and the display panel 90040
Supply to 1. Further, the controller 900407 receives Hs based on the power supply voltage input from the power supply circuit 900410 and various signals input from the central processing unit (CPU) 900408.
The sync signal, the Vsync signal, the clock signal CLK, the AC voltage (AC Cont), and the switching signal L / R are generated and supplied to the display panel 900401.

In the transmission / reception circuit 900412, a signal transmitted / received as a radio wave in the antenna 900428 is processed. Specifically, an isolator, a bandpass filter, a VCO (Volt)
age Controlled Oscillator), LPF (Low Pass)
It may include a high frequency circuit such as a filter), a coupler, or a balun. Transmitter / receiver circuit 90
Of the signals transmitted and received in 0412, the signal including voice information is the central processing unit (CPU).
) According to the command from 900408, it is sent to the voice processing circuit 900411.

The signal including the audio information sent in accordance with the instruction from the central processing unit (CPU) 900408 is demodulated into an audio signal in the audio processing circuit 900411 and sent to the speaker 900427. Further, the audio signal sent from the microphone 900426 is an audio processing circuit 90041.
1 and is sent to the transmission / reception circuit 900412 according to an instruction from the central processing unit (CPU) 900408.

Controller 900407, central processing unit (CPU) 900408, power supply circuit 90041
0, the voice processing circuit 900411, and the memory 900409 can be mounted as a package of this embodiment.

Of course, the present embodiment is not limited to the television receiver, and is used as a display medium for a large area such as a personal computer monitor, an information display panel at a railway station or an airport, an advertisement display panel at the street, and the like. Can be applied to.

Next, with reference to FIG. 114, a configuration example of the mobile phone according to the present embodiment will be described.

The display panel 900501 is detachably incorporated in the housing 900530. The shape and size of the housing 900530 can be changed as appropriate in accordance with the size of the display panel 900501. The housing 900530 to which the display panel 900501 is fixed is fitted into the printed board 900531 and assembled as a module.

The display panel 900501 is connected to a printed circuit board 900513 via an FPC 900513. The printed circuit board 900513 has a speaker 900532 and a microphone 90.
0533, a transmission / reception circuit 900534, a signal processing circuit 9 including a CPU, a controller, and the like
00535 is formed. Such a module, an input means 900536, and a battery 900537 are combined and housed in a housing 900539. Display panel 900501
The pixel portion is placed so that it can be seen through an opening window formed in the housing 900359.

In the display panel 900501, a pixel portion and part of a peripheral driver circuit (a driver circuit with a low operating frequency among a plurality of driver circuits) is integrally formed over a substrate by using a TFT, and a part of the peripheral driver circuit (a plurality of driver circuits). A driver circuit having a high operating frequency of the circuits) may be formed over an IC chip and the IC chip may be mounted on the display panel 900501 by COG (Chip On Glass).
Alternatively, the IC chip may be connected to the glass substrate by using TAB (Tape Auto Bonding) or a printed board. With such a structure, power consumption of the display device can be reduced and usage time of the mobile phone can be extended by one charge. Further, the cost of the mobile phone can be reduced.

The mobile phone shown in FIG. 115 has operation switches 900604 and a microphone 90.
A main body (A) 900601 provided with 0605 and the like, and a display panel (A) 900608,
Main body (B) 9 provided with a display panel (B) 900609, a speaker 900606, and the like
00602 and hinge 900610 are openably and closably connected. Display panel (A) 90
0608 and the display panel (B) 900609 together with the circuit board 900607 are the main body (B) 9
It is housed in a housing 900603 of 00602. The pixel portions of the display panel (A) 900608 and the display panel (B) 900609 are arranged so as to be visible through an opening window formed in the housing 900603.

The display panel (A) 900608 and the display panel (B) 900609 are used for the mobile phone 90.
Specifications such as the number of pixels can be appropriately set according to the function of 0600. For example, the display panel (A) 900608 can be combined as a main screen and the display panel (B) 900609 can be combined as a sub screen.

The mobile phone according to the present embodiment can be transformed into various modes depending on its function and use.
For example, an image sensor may be incorporated in the hinge 900610 to form a mobile phone with a camera. Further, even when the operation switches 900604, the display panel (A) 900608, and the display panel (B) 900609 are housed in one housing, the above-described effects can be obtained. The same effect can be obtained by applying the configuration of this embodiment to an information display terminal having a plurality of display units.

This embodiment can be applied to various electronic devices. Specifically, it can be applied to a display unit of an electronic device. Such electronic devices include video cameras, digital cameras,
Images equipped with goggle type display, navigation system, sound reproducing device (car audio, audio component, etc.), computer, game machine, personal digital assistant (mobile computer, mobile phone, portable game machine or electronic book, etc.), recording medium A reproducing device (specifically, a recording medium such as a Digital Versatile Disc (DVD) is reproduced,
An apparatus including a display capable of displaying the image) and the like.

FIG. 116A shows a display, which includes a housing 900711, a supporting base 900712, a display portion 900713, and the like.

FIG. 116B shows a camera, which includes a main body 900721, a display portion 900722, and an image receiving portion 900.
723, operation key 900742, external connection port 900725, shutter 900726
Including etc.

FIG. 116C illustrates a computer, which includes a main body 900731, a housing 900732, and a display portion 9
0073, a keyboard 900734, an external connection port 900735, a pointing device 900736 and the like.

FIG. 116D shows a mobile computer, which includes a main body 900471 and a display portion 900742.
, A switch 900473, an operation key 900744, an infrared port 900475 and the like.

FIG. 116E shows a portable image reproducing device (for example, DVD reproducing device) provided with a recording medium.
And a main body 900512, a housing 900512, a display unit (A) 900573, and a display unit (B).
) 900754, recording medium (DVD, etc.) reading unit 900755, operation key 900754
, A speaker portion 900857 and the like. The display portion (A) 900573 can mainly display image information, and the display portion (B) 900754 can mainly display text information.

FIG. 116F shows a goggle type display, which includes a main body 900761 and a display portion 90076.
2, including an earphone 900763 and a supporting portion 900764.

FIG. 116G illustrates a portable game machine including a housing 900771, a display portion 900772, a speaker portion 900773, operation keys 900774, a storage medium insertion portion 900775, and the like. A portable game machine in which the display device of this embodiment is used for the display portion 9007772 can express vivid colors.

FIG. 116H illustrates a digital camera with a television image receiving function, which includes a main body 900781, a display portion 900782, operation keys 900783, a speaker 900784, and a shutter 90078.
5, an image receiving unit 900786, an antenna 900787 and the like.

As shown in FIGS. 116A to 116E, the electronic device in this embodiment has a display portion for displaying some information.

Next, an application example of the semiconductor device according to this embodiment will be described.

FIG. 117 shows an example in which the semiconductor device according to this embodiment is incorporated in a structure. FIG. 117 shows a housing 900810, a display unit 900811, and a remote control device 9 which is an operation unit.
008112, a speaker portion 900813 and the like. The semiconductor device according to this embodiment is a wall-mounted type and is integrated with a building, and can be installed without requiring a large installation space.

FIG. 118 shows another example in which the semiconductor device according to this embodiment is incorporated in a structure and is integrated with the structure. The display panel 900901 is attached to the unit bath 900902 so that the bather can view the display panel 900901. Display panel 90
0901 has a function of displaying information when operated by a bather and being usable as an advertisement or an entertainment means.

Note that the semiconductor device according to this embodiment can be installed in various places in addition to the sidewall of the unit bus 900902 shown in FIG. For example, it may be integrated with a part of the mirror surface or the bathtub itself. At this time, the shape of the display panel 900901 may match the shape of a mirror surface or a bathtub.

FIG. 119 shows another example in which the semiconductor device of this embodiment is incorporated in a structure. The display panel 901002 is attached by being curved according to the curved surface of the columnar body 901001. Note that the columnar body 901001 will be described as an electric pole.

A display panel 901002 illustrated in FIG. 119 is provided at a position higher than a human viewpoint.
By installing the display panel 901002 in a building which is repeatedly forested outdoors such as a telephone pole, it is possible to advertise to an unspecified number of viewers. Here, the display panel 90100
In No. 2, it is easy to display the same image and to switch the image instantaneously under the control of the outside, so that extremely efficient information display and advertisement effect can be expected. Further, by providing the display panel 901002 with a self-luminous display element, it can be said that the display panel 901002 is useful as a display medium with high visibility even at night. In addition, by installing it on a telephone pole, the display panel 90
It is easy to secure the power supply means 1002. In addition, in the event of an emergency such as when a disaster occurs, it can be a means of quickly and accurately transmitting information to the victim.

Note that as the display panel 901002, for example, a display panel which displays an image by driving a display element with a switching element such as an organic transistor provided over a film-like substrate can be used.

In the present embodiment, the wall, the columnar body, and the unit bath are taken as an example of the building, but the present embodiment is not limited to this, and the semiconductor device according to the present embodiment can be installed in various buildings. You can

Next, an example in which the semiconductor device according to this embodiment is integrated with a moving object will be described.

FIG. 120 is a diagram showing an example in which the semiconductor device according to this embodiment is incorporated in a vehicle. The display panel 901102 is attached integrally with a car body 901101 of an automobile, and can display the operation of the car body and information input from inside and outside the car body on demand. Further, it may have a navigation function.

The semiconductor device according to this embodiment can be installed not only in the vehicle body 901101 shown in FIG. 120 but also in various places. For example, it may be integrated with a glass window, a door, a handle, a shift lever, a seat, a rearview mirror or the like. At this time, the display panel 901
The shape of 102 may be adapted to the shape of the object to be installed.

FIG. 121 is a diagram showing an example in which the semiconductor device according to this embodiment is integrated with a train car.

FIG. 121 (a) is a diagram showing an example in which a display panel 901202 is provided on the glass of a door 901201 of a train car. Compared to conventional paper advertisements, there is an advantage that labor costs required for advertisement switching are not required. Further, the display panel 901202 can instantaneously switch an image displayed on the display portion by a signal from the outside,
For example, the image on the display panel can be switched at each time when the passenger class of the train passengers is switched, and a more effective advertising effect can be expected.

FIG. 121 (b) shows a glass window 901203 in addition to the glass of the door 901201 of the train car.
And FIG. 10 is a diagram showing an example in which a display panel 901202 is provided on a ceiling 901204.
As described above, the semiconductor device according to the present embodiment can be easily installed in a place where it has been difficult to install the semiconductor device in the related art, and thus an effective advertising effect can be obtained. Further, the semiconductor device according to this embodiment can switch the image displayed on the display portion by an external signal in an instant, so that the cost and time at the time of switching an advertisement can be reduced and the flexibility can be improved. It is possible to operate various advertisements and communicate information.

Note that the semiconductor device according to this embodiment can be installed in various places in addition to the door 901201, the glass window 901203, and the ceiling 901204 shown in FIG. For example, it may be integrated with a strap, a seat, a handrail, a floor, or the like. At this time, the shape of the display panel 901202 may match the shape of the object to be installed.

FIG. 122 is a diagram showing an example in which the semiconductor device according to this embodiment is incorporated in a passenger airplane.

FIG. 122A shows a display panel 90130 on a ceiling 901301 above the seat of a passenger airplane.
It is the figure which showed the shape at the time of use when 2 was provided. The display panel 901302 is
It is integrally attached to the ceiling 901301 via the hinge portion 901303, and the expansion and contraction of the hinge portion 901303 allows passengers to view the display panel 901302. The display panel 901302 can display information by being operated by a passenger. Furthermore, it has a function that can be used as an advertisement or an entertainment means. Further, as shown in FIG. 122 (b), by bending the hinge part and storing it on the ceiling 901301, it is possible to consider safety during takeoff and landing. By turning on the display element of the display panel in an emergency, it can be used as an information transmitting means and a guide light.

Note that the semiconductor device according to this embodiment can be installed in various places in addition to the ceiling 901301 shown in FIG. For example, seats, seat tables, armrests,
It may be integrated with a window or the like. In addition, a large display panel that can be viewed by many people at the same time may be installed on the wall of the machine body. At this time, the shape of the display panel 901302 may match the shape of the object to be installed.

In the present embodiment, the moving body is exemplified by a train car body, an automobile body, and an airplane body, but the moving body is not limited to this. A motorcycle, a four-wheeled vehicle (including a car, a bus, etc.),
It can be installed on various things such as trains (including monorails and railroads), ships, etc. Since the semiconductor device according to this embodiment can switch the display of the display panel in the moving body instantaneously by a signal from the outside, by installing the semiconductor device according to this embodiment in the moving body. The mobile body can be used as an advertisement display board for an unspecified large number of customers, an information display board when a disaster occurs, and the like.

Note that this embodiment can be implemented by being freely combined with any of the other embodiments.

Note that the contents of each drawing in this embodiment can be implemented by freely combining with the contents of other drawings.

(Embodiment 17)
As described above, this specification includes at least the following inventions.

A liquid crystal display device including a pixel having a liquid crystal element and a driver circuit. The driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. This drive circuit includes the following connection relationships at least in part. The first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the sixth wiring, and the second electrode of the second transistor is electrically connected to the third wiring. First of the third transistor
Electrode is electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the gate electrode of the third transistor is the seventh wiring. Electrically connected to. The first electrode of the fourth transistor is electrically connected to the sixth wiring, the second electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor, and The gate electrode is electrically connected to the gate electrode of the first transistor. The first electrode of the fifth transistor is electrically connected to the seventh wiring, the second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and The gate electrode is electrically connected to the first wiring. The first electrode of the sixth transistor is electrically connected to the sixth wiring, and the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor. The gate electrode is electrically connected to the gate electrode of the second transistor. The first electrode of the seventh transistor is electrically connected to the sixth wiring, the second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and The gate electrode is electrically connected to the second wiring.

A liquid crystal display device having a pixel having the liquid crystal element and a driving circuit may include the following structure. Channel length L and channel width W of the first transistor to the seventh transistor
A configuration including a drive circuit that maximizes the W / L value of the first transistor in the ratio W / L value. The W / L value of the first transistor is twice to 5 times the W / L value of the fifth transistor.
A configuration including a doubling drive circuit. A structure in which the channel length L of the third transistor is larger than the channel length L of the fourth transistor is included. A structure including a capacitor in which a capacitor is provided between the second electrode of the first transistor and the gate electrode of the first transistor. First
And the seventh to seventh transistors include N-channel transistors. The first to seventh transistors each include a semiconductor layer using amorphous silicon.

A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit. First
The drive circuit and the second drive circuit at least partially include the following connection relationship.
The first driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. ing. The first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the sixth wiring, and the second electrode of the ninth transistor is electrically connected to the third wiring. The first electrode of the third transistor is electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the third electrode of the third transistor is electrically connected to the gate electrode of the second transistor. The gate electrode is electrically connected to the seventh wiring. The first electrode of the fourth transistor is electrically connected to the sixth wiring,
The second electrode of the transistor is electrically connected to the gate electrode of the second transistor, and the gate electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor. The first electrode of the fifth transistor is electrically connected to the seventh wiring, the second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and The gate electrode is electrically connected to the first wiring. The first electrode of the sixth transistor is electrically connected to the sixth wiring, and the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor. The gate electrode is electrically connected to the gate electrode of the second transistor. The first electrode of the seventh transistor is electrically connected to the sixth wiring, the second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and The gate electrode is electrically connected to the second wiring.
The second driver circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. ing. The first electrode of the eighth transistor is electrically connected to the eleventh wiring, and the second electrode of the eighth transistor is electrically connected to the tenth wiring. The first electrode of the ninth transistor is electrically connected to the thirteenth wiring, and the second electrode of the ninth transistor is electrically connected to the tenth wiring. The first electrode of the tenth transistor is electrically connected to the twelfth wiring, the second electrode of the tenth transistor is electrically connected to the gate electrode of the ninth transistor, and The gate electrode is electrically connected to the 14th wiring. The first electrode of the eleventh transistor is the first
Electrically connected to the third wiring, the second electrode of the eleventh transistor is electrically connected to the gate electrode of the ninth transistor, and the gate electrode of the eleventh transistor is connected to the gate electrode of the eighth transistor. It is electrically connected. The first electrode of the twelfth transistor is first
Electrically connected to the fourth wiring, the second electrode of the twelfth transistor is electrically connected to the gate electrode of the eighth transistor, and the gate electrode of the twelfth transistor is electrically connected to the eighth wire. Has been done. The first electrode of the thirteenth transistor is electrically connected to the thirteenth wiring, the second electrode of the thirteenth transistor is electrically connected to the gate electrode of the eighth transistor, and The gate electrode is electrically connected to the gate electrode of the ninth transistor. The first electrode of the fourteenth transistor is electrically connected to the thirteenth wiring, the second electrode of the fourteenth transistor is electrically connected to the gate electrode of the eighth transistor, and The gate electrode is electrically connected to the ninth wiring.

A liquid crystal display device having a pixel having the liquid crystal element and a driving circuit may include the following structure. The fourth wiring and the eleventh wiring are electrically connected, the fifth wiring and the twelfth wiring are electrically connected, and the sixth wiring and the thirteenth wiring are electrically connected. The configuration in which the seventh wiring and the fourteenth wiring are electrically connected. The fourth wiring and the eleventh wiring are the same wiring, the fifth wiring and the twelfth wiring are the same wiring, and the sixth wiring and the thirteenth wiring are the same wiring. The seventh wiring and the fourteenth wiring are the same wiring. A configuration in which the third wiring and the tenth wiring are electrically connected. A configuration in which the third wiring and the tenth wiring are the same wiring. Among the values of the ratio W / L of the channel length L and the channel width W of the first transistor to the seventh transistor, the value of W / L of the first transistor becomes the maximum, and the value of the eighth transistor to the fourteenth transistor is increased. The structure in which the value of W / L of the eighth transistor is maximum among the values of the ratio W / L of the channel length L and the channel width W of the transistor. W / L of first transistor
Value is 2 to 5 times the W / L value of the fifth transistor, and the W / L value of the 8th transistor is 2 to 5 times the W / L value of the 12th transistor. Will be configured. The channel length L of the third transistor is larger than the channel length L of the fourth transistor,
The channel length L of the transistor is larger than the channel length L of the eleventh transistor. A capacitor is arranged between the second electrode of the first transistor and the gate electrode of the first transistor, and between the second electrode of the eighth transistor and the gate electrode of the eighth transistor. A configuration in which a capacitive element is arranged. The first to fourteenth transistors are N-channel transistors. The first to fourteenth transistors each have a structure in which amorphous silicon is used as a semiconductor layer.

The liquid crystal display device described in this embodiment mode is described in this specification, and thus has the same effects as the other embodiment modes.

S1 signal line Sj signal line VDD power supply potential VSS power supply potential G1 scanning line Gi scanning line Gn scanning line 11 transistor 12 transistor 13 transistor 14 transistor 15 transistor 16 transistor 17 transistor 21 signal line 22 signal line 23 wiring 24 signal line 25 power line 26 Power supply line 32 silicon oxynitride film 41 node 101 transistor 102 transistor 103 transistor 104 transistor 105 transistor 106 transistor 110 wiring 107 transistor 112 wiring 108 transistor 109 transistor 121 wiring 122 wiring 123 wiring 124 wiring 125 wiring 126 wiring 127 wiring 128 wiring 129 wiring 130 Wiring 131 wiring 132 wiring 133 wiring 134 wiring 141 node 142 node 221 signal 222 signal 223 signal 225 signal 226 signal 232 signal 241 potential 242 potential 401 capacitance element 402 transistor 403 resistance element 501 wiring 502 wiring 503 wiring 504 wiring 505 wiring 506 wiring 507 Wiring 508 wiring 509 wiring 510 wiring 701 transistor 702 transistor 711 wiring 81a evaporation source 1001 flip-flop 1007 wiring 1011 wiring 1012 wiring 1013 wiring 1014 wiring 1015 wiring 1016 wiring 1017 wiring 1018 wiring 1111 signal 1112 signal 1113 signal 1117 signal 1118 signal 1212 signal 1211 Signal 1301 Buffer 1602 Scan line driver circuit 1801 Signal line driver circuit 1802 Scan line driver circuit 1803 Pixel 1804 Pixel portion 1805 Insulating substrate 1808 Wiring 2108 Transistor 2132 Wiring 2301 Transistor 2302 Transistor 2303 Transistor 2304 Transistor 2305 Transistor 2306 Transistor 2307 Transistor 2321 Transistor 2322 Wiring 2322 2323 wiring 2324 wiring 2325 wiring 2326 wiring 2327 wiring 2328 wiring 2329 wiring 2330 wiring 2331 wiring 2341 node 2342 node 2421 signal 2422 signal 2423 signal 2425 signal 2426 signal 2441 potential 2442 potential 2501 conductive layer 2502 conductive layer 2503 conductive layer 2504 conductive layer 2 505 conductive layer 2506 conductive layer 2507 conductive layer 2508 conductive layer 2510 conductive layer 2511 conductive layer 2512 conductive layer 2513 conductive layer 2514 conductive layer 2515 conductive layer 2541 wiring 2542 wiring 2543 wiring 2544 wiring 2545 wiring 2546 wiring 2547 wiring 2548 wiring 2549 wiring 2581 semiconductor Layer 2582 semiconductor layer 2583 semiconductor layer 2584 semiconductor layer 2585 semiconductor layer 2586 semiconductor layer 2587 semiconductor layer 2901 flip-flop 2907 wiring 2911 wiring 2912 wiring 2913 wiring 2914 wiring 2915 wiring 2916 wiring 2917 wiring 2918 wiring 2919 wiring 3011 signal 3018 signal 3019 signal 3101 flip-flop 3111 wiring 3120 wiring 3121 signal 3122 signal 3123 signal 3125 signal 3126 signal 3141 potential 3142 potential 3301 flip-flop 3301 wiring 3306 wiring 3311 wiring 3312 wiring 3313 wiring 3314 wiring 3315 wiring 3316 wiring 3317 wiring 3318 wiring 3319 wiring 3320 wiring 3321 wiring 3322 3511 signal 3512 signal 3513 signal 3514 signal 3515 signal 3519 signal 3520 signal 3521 signal 3604 substrate film 3611 signal 3621 signal 5601 driver IC
5602 switch group 5611 wiring 5612 wiring 5613 wiring 5621 wiring 5721 signal 5821 signal 5911 wiring 5912 wiring 5913 wiring 6001 transistor 6002 transistor 6003 transistor 6004 transistor 6005 transistor 6006 transistor 6011 wiring 6012 wiring 6013 wiring 6014 wiring 6015 wiring 6016 wiring 6022 switch group 6221 switch group 6101 6102 transistor 6111 wiring 6112 wiring 6201 transistor 6211 wiring 6401 transistor 6402 transistor 6411 wiring 6412 wiring 8000 buffer 8011 wiring 8012 wiring 802a scanning line driving circuit 802b scanning line driving circuit 8100 buffer 8201 transistor 8202 transistor 8211 wiring 8212 wiring 8213 wiring 8214 wiring 8301 8302 transistor 8303 transistor 8304 transistor 8311 wiring 8312 wiring 8313 wiring 8314 wiring 8315 wiring 8316 wiring 8341 node 8401 transistor 8402 transistor 8403 transistor 8404 transistor 8411 wiring 8412 wiring 8413 wiring 8414 wiring 8415 wiring 8416 wiring 8417 wiring 8441 node 8501 transistor 8502 transistor 8502 transistor 8502 transistor 8502 8511 wiring 8512 wiring 8513 wiring 8514 wiring 8515 wiring 8516 wiring 8541 node 8601 transistor 8602 transistor 8603 transistor 8604 transistor 8611 wiring 8612 wiring 8613 wiring 8614 wiring 8615 wiring 8616 wiring 8641 node 10101 substrate 10102 insulating film 10103 conductive layer 10104 insulating film 10105 semiconductor layer 10106 semiconductor layer 10107 conductive layer 10108 insulating film 10109 conductive layer 10110 alignment film 10112 alignment film 10113 conductive layer 10114 light shielding film 10115 color filter 10116 substrate 10117 spacer 10118 liquid crystal molecule 10121 scanning line 10122 video signal line 10123 capacitance line 10124 TFT
10125 pixel electrode 10126 pixel capacitor 10201 substrate 10202 insulating film 10203 conductive layer 10204 insulating film 10205 semiconductor layer 10206 semiconductor layer 10207 conductive layer 10208 insulating film 10209 conductive layer 10210 alignment film 10212 alignment film 10213 conductive layer 10214 light shielding film 10215 color filter 10216 substrate 10217 Spacer 10218 Liquid crystal molecule 10219 Alignment control protrusion 10221 Scan line 10222 Video signal line 10223 Capacitance line 10224 TFT
10225 pixel electrode 10226 pixel capacitor 10301 substrate 10302 insulating film 10303 conductive layer 10304 insulating film 10305 semiconductor layer 10306 semiconductor layer 10307 conductive layer 10308 insulating film 10309 conductive layer 10310 alignment film 10312 alignment film 10313 conductive layer 10314 light shielding film 10315 color filter 10316 substrate 10317 Spacer 10318 Liquid crystal molecule 10319 Electrode notch 10321 Scan line 10322 Video signal line 10323 Capacitance line 10324 TFT
10325 pixel electrode 10326 pixel capacitor 10401 substrate 10402 insulating film 10403 conductive layer 10404 insulating film 10405 semiconductor layer 10406 semiconductor layer 10407 conductive layer 10408 insulating film 10409 conductive layer 10410 alignment film 10412 alignment film 10414 light shielding film 10415 color filter 10416 substrate 10417 spacer 10418 liquid crystal Molecule 10421 Scanning line 10422 Video signal line 10423 Common electrode 10424 TFT
10425 Pixel electrode 10501 Substrate 10502 Insulating film 10503 Conductive layer 10504 Insulating film 10505 Semiconductor layer 10506 Semiconductor layer 10507 Conductive layer 10508 Insulating film 10509 Conductive layer 10510 Alignment film 10512 Alignment film 10513 Conductive layer 10514 Light shielding film 10515 Color filter 10516 Substrate 10517 Spacer 10518 Liquid crystal Molecule 10519 Insulating film 10521 Scanning line 10522 Video signal line 10523 Common electrode 10524 TFT
10525 pixel electrode 10600 liquid crystal layer 10601 substrate 10602 substrate 10603 layer 10604 layer 10605 electrode 10606 electrode 10607 protrusion 10801 electrode 10802 electrode 10803 electrode 10804 electrode 10901 insulating layer 2002a scanning line driving circuit 2002b scanning line driving circuit 20100 substrate 20101 pixel portion 20102 pixel 20103 Scan line input terminal 20104 Signal line input terminal 20105 Scan line driver circuit 20106 Signal line driver circuit 2015 15 Substrate 20200 FPC
20201 Driver IC
20301 transistor 20302 liquid crystal element 20303 capacitance element 20304 wiring 20305 wiring 20306 capacitance line 20307 counter electrode 20501 insulating film 20502 semiconductor layer 20503 insulating layer 20504 conductive layer 20505 insulating layer 20506 conductive film 20507 insulating layer 20508 conductive layer 20509 insulating layer 20510 liquid crystal layer 20511 insulating Film 20512 Conductive film 20513 Insulating film 20514 Insulating film 20515 Counter substrate 20516 Sealing material 20517 Anisotropic conductor layer 20518 FPC
20521 Transistor 20525 Drive circuit region 20526 Pixel region 20530 IC chip 20531 Spacer 20532 Insulating film 20533 Conductive film 20601 Driver IC
21301 insulating film 21801 insulating film 22001 insulating film 2202a scanning line driving circuit 2202b scanning line driving circuit 22201 insulating film 22601 backlight unit 22602 diffuser plate 22603 light guide plate 22604 reflector plate 22605 lamp reflector 22606 light source 22607 liquid crystal panel 22608 layer 22609 layer 22610 slit Video signal 22702 Control circuit 22703 Signal line drive circuit 22704 Scan line drive circuit 22705 Pixel part 22706 Illumination means 22707 Power source 22708 Drive circuit part 22710 Scan line 22712 Signal line 22731 Shift register 22732 Latch 22733 Latch 22734 Level shifter 22735 Buffer 22741 Shift register 22742 Level shifter 22742 Buffer 22801 Cold cathode tube 22802 Light emitting diode 22803 Light emitting diode 22832 Lamp reflector 22852 Backlight unit 23000 Polarizing film 23001 Protective film 23002 Substrate film 23002 Substrate film 23003 PVA Polarizing film 23004 Substrate film 23005 Adhesive layer 23006 Release film 23100 TFT substrate 23101 Facing Substrate 23102 Sealing material 23103 Pixel portion 23104 Liquid crystal layer 23105 Coloring layer 23106 Layer 23107 Layer 23109 Flexible wiring board 23110 Cold cathode tube 23111 Reflector 23112 Circuit board 23113 Diffuser 23199 Controller 2901i Flip-flop 30101 Encoding circuit 30102 Frame memory 30103 Correction circuit 30104 DA conversion circuit 30112 Frame memory 30113 Correction circuit 30121 Input voltage 30122 Input voltage 30123 Output brightness 30124 Output brightness 30131 Input video signal 30132 Output video signal 30133 Output switching signal 30201 Transistor 30202 Auxiliary capacitor 30203 Display element 30204 Video signal line 30205 Scan line 30206 Common line 30211 Transistor 30212 Auxiliary capacitance 30213 Display element 30214 Video signal line 30215 Scan line 30216 Common line 30217 Common line 30301 Diffusion plate 30302 Cold cathode tube 30311 Diffusion plate 30312 Light source 30400 Frame period 30401 Image 3 0402 intermediate image 30412 intermediate image 30413 intermediate image 5603a switch 5603b switch 5603c switch 5703a timing 5703b timing 5703c timing 5803a timing 5803b timing 5803c timing 5903a transistor 5903b transistor 5903c transistor 60105 TFT
60106 wiring 60107 wiring 60108 TFT
60111 wiring 60112 counter electrode 60113 capacitor 60115 pixel electrode 60116 partition wall 60117 organic conductor film 60118 organic thin film 60119 substrate 60200 substrate 60201 wiring 60202 wiring 60203 wiring 60204 wiring 60205 TFT
60206 TFT
60207 TFT
60208 pixel electrode 60211 partition wall 60212 organic conductor film 60213 organic thin film 60214 counter electrode 60300 substrate 60301 wiring 60302 wiring 60303 wiring 60304 wiring 60305 TFT
60306 TFT
60307 TFT
60308 TFT
60309 pixel electrode 60311 wiring 60312 wiring 60321 partition wall 60322 organic conductor film 60323 organic thin film 60324 counter electrode 60401 anode 60402 cathode 60403 hole transport region 60404 electron transport region 60405 mixed region 60406 region 60407 region 60408 region 60409 region 60560 transport chamber 6056 transport chamber 60562 loading chamber 60563 unloading chamber 60564 intermediate processing chamber 60565 sealing processing chamber 60566 transporting means 60567 transporting means 60568 heat treatment chamber 60569 film deposition processing chamber 60570 film deposition processing chamber 60571 film deposition chamber 60572 plasma processing chamber 60573 film deposition processing chamber 60574 Film forming chamber 60576 Film forming chamber 60680 Evaporation source holder 60681 Evaporation source 60682 Distance sensor 60683 Articulated arm 60684 Material supply pipe 60686 Substrate stage 60687 Substrate chuck 60688 Mask chuck 60689 Substrate 60690 Shadow mask 60691 Top plate 60692 Bottom plate 6301a Transistor 6301b Transistor 6302a Transistor 6302b Transistor 8001a Inverter 8001b Inverter 8001c Inverter 8002a Inverter 8002b Inverter 8002c Inverter 8003a Inverter 8003b Inverter 8003c Inverter 80302 Drive transistor 80400 Drive transistor 80401 Switch 80402 Switch 80403 Switch 80404 Capacitance element 80411 8041 Signal line 80412 Power line 8012 Scan line 80414 Second scan line 80415 Third scan line 80420 Display element 80421 Electrode 80430 Driving transistor 80431 Switch 80432 Switch 80433 Switch 80434 Capacitive element 80441 Signal line 80442 Power supply line 80443 First scan line 80444 Second scan line 80445 third scan line 80450 display element 80451 electrode 80454 scan line 10606a electrode 10801a electrode 10801b electrode 10801c electrode 10801d electrode 10802a electrode 10802b electrode 10802c electrode 10802d electrode 10803a electrode 10803b electrode 10803c electrode 10803d electrode 10 804a electrode 10804b electrode 10804c electrode 10804d electrode 110111 substrate 110112 insulating film 110113 semiconductor film 110114 semiconductor film 110115 semiconductor film 110116 insulating film 110117 gate electrode 110118 insulating film 110119 insulating film 110121 sidewall 110122 mask 110123 conductive film 110131 insulating film 120100 electrode layer 120102 electric field Light-Emitting Layer 120103 Electrode Layer 120104 Insulating Layer 120105 Insulating Layer 120106 Insulating Layer 120200 Electrode Layer 120201 Light Emitting Material 120202 Electroluminescent Layer 120203 Electrode Layer 120204 Insulating Layer 120205 Insulating Layer 120206 Insulating Layer 130100 Rear Projection Display Device 130101 Screen Panel 130102 Speaker 130104 Operation Switch Types 130110 Housing 130111 Projector unit 130112 Mirror 130200 Front projection display device 130201 Projection optical system 130301 Light source unit 130301 Light source unit 130302 Light source lamp 130303 Light source optical system 130304 Modulation unit 130305 Dichroic mirror 130306 Total reflection mirror 130308 Display panel 130309 Prism 130310 Projection optical System 130400 Modulation unit 130401 Dichroic mirror 130402 Dichroic mirror 130403 Total reflection mirror 130404 Polarization beam splitter 130405 Polarization beam splitter 130406 Polarization beam splitter 130407 Reflective display panel 130411 Projection optical system 130501 Dichroic mirror 130502 Dichroic mirror 130503 Red light dichroic mirror 130504 Phase difference Plate 130505 Color filter plate 130506 Microlens array 130507 Display panel 130508 Display panel 130509 Display panel 130511 Projection optical system 20102a Pixel 20102b Pixel 20105a Scan line drive circuit 20105b Scan line drive circuit 20301a Transistor 20301b Transistor 20303a Wiring 20305b Capacitor 20305a Wiring 20305b 203076 Wiring 20502a Semiconductor layer 20502b Semiconductor layer 20503a Insulating layer 20503b Insulating layer 20504a Conductive layer 20504b Conductive layer 20508a Conductive layer 20508b Conductive layer 20602a Driver IC
20602b driver IC
23190a red light source 23190b green light source 23190c blue light source 60577a gate valve 60681a evaporation source 60681b evaporation source 60681c evaporation source 60685a material supply source 60685b material supply source 60685c material supply source 80301a switching transistor 80301b switching transistor 80301c switching transistor 80301d Switching transistor 80302a Driving transistor 80302b Driving transistor 80302c Driving transistor 80302d Driving transistor 80302e Driving transistor 80303c Diode connecting transistor 80303d Diode connecting transistor 80303e Erasing transistor 80304a Capacitive element 80304b Capacitive element 80304c Capacitive element 80304d Capacitive element 80304e Capacitive element 80304e 80306a Rectifying element 80311a Signal line 80311b Signal line 80311c Signal line 80311d Signal line 80311e Signal line 80312a First scanning line 80312b First scanning line 80312c First scanning line 80312d First scanning line 80312e First scanning line 80313a Power source Line 80313b Power line 80313c Power line 80313d Power line 80313e Power line 80314b Second scan line 80314c Second scan line 80314d Second scan line 80320a Display element 80320b Display element 80321a Electrode 80321b Electrode 900101 Display panel 900102 Pixel portion 900103 Scan line Drive circuit 900104 Signal line drive circuit 900111 Circuit board 900112 Control circuit 900113 Signal division circuit 900114 Connection wiring 900201 Tuner 900202 Video signal amplification circuit 900203 Video signal processing circuit 900205 Audio signal amplification circuit 900206 Audio signal processing circuit 900207 Speaker 900208 Control circuit 900209 Input unit 900212 Control circuit 900213 Signal division circuit 900301 Housing 900302 Display screen 900303 Speaker 900304 Operation switch 900310 Charger 900312 Housing 900313 Display unit 900316 Operation key 900317 Speaker unit 900401 Display panel 900402 Printed wiring board 900403 Pixel portion 900404 Scanning line driving circuit 900405 Scanning line driving circuit 900406 Signal line driving circuit 900407 Controller 900408 Central processing unit (CPU)
900409 Memory 900410 Power supply circuit 900411 Audio processing circuit 900412 Transmitter / receiver circuit 900413 Flexible wiring board (FPC)
900414 Interface (I / F) section 900415 Antenna port 900416 VRAM
900417 DRAM
900418 Flash memory 900419 Interface 900420 Control signal generation circuit 900421 Decoder 900422 Register 900423 Operation circuit 900424 RAM
900425 Input means 900426 Microphone 900427 Speaker 900428 Antenna 900501 Display panel 900513 FPC
900530 Housing 900531 Printed circuit board 900532 Speaker 900533 Microphone 900534 Transmission / reception circuit 900535 Signal processing circuit 900536 Input means 900537 Battery 900539 Housing 900600 Mobile phone 900601 Main body (A)
900602 main body (B)
900603 Housing 900604 Operation switches 900605 Microphone 900606 Speaker 900607 Circuit board 900608 Display panel (A)
900609 Display panel (B)
900610 Hinge 900711 Housing 900712 Support base 900713 Display unit 900721 Main body 900722 Display unit 900723 Image receiving unit 900724 Operation key 900725 External connection port 900726 Shutter 900731 Main body 900732 Housing 900733 Display unit 900734 Keyboard 900735 External connection port 900736 Pointing device 900741 Main unit 900741 900473 Switch 900744 Operation Key 900475 Infrared Port 900751 Main Body 900752 Housing 900753 Display (A)
900754 Display (B)
900755 section 900756 operation key 900757 speaker section 900761 body 900762 display section 900763 earphone 900764 support section 900771 housing 900772 display section 900773 speaker section 900774 operation key 900775 storage medium insertion section 900781 body 900782 display section 900783 operation key 900784 speaker 900785 shutter section 90078 900787 Antenna 900810 Housing 900811 Display portion 900812 Remote control device 900813 Speaker portion 900901 Display panel 900902 Unit bath 901001 Columnar body 901002 Display panel 901101 Car body 901102 Display panel 901201 Door 901202 Display panel 901203 Glass window 901204 Ceiling 901301 Ceiling 901302 Display panel 90901

Claims (3)

Having first to sixth transistors,
One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
The other of the source and the drain of the first transistor is electrically connected to the gate of the first transistor,
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
The other of the source and the drain of the third transistor is electrically connected to the gate of the third transistor,
One of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
The other of the source and the drain of the fifth transistor is electrically connected to the gate of the fifth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the fourth transistor,
A semiconductor device in which one of a source and a drain of the third transistor is electrically connected to a gate of the sixth transistor. Having first to twelfth transistors,
One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the third transistor,
The other of the source and the drain of the first transistor is electrically connected to the gate of the first transistor,
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
One of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
One of a source and a drain of the fifth transistor is electrically connected to a gate of the seventh transistor,
The other of the source and the drain of the fifth transistor is electrically connected to the gate of the fifth transistor,
One of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
One of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,
One of a source and a drain of the ninth transistor is electrically connected to a gate of the eleventh transistor,
The other of the source and the drain of the ninth transistor is electrically connected to the gate of the ninth transistor,
One of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor,
One of a source and a drain of the third transistor is electrically connected to a gate of the sixth transistor,
One of a source and a drain of the third transistor is electrically connected to a gate of the eighth transistor,
One of a source and a drain of the seventh transistor is electrically connected to a gate of the tenth transistor,
A semiconductor device in which one of a source and a drain of the seventh transistor is electrically connected to a gate of the twelfth transistor. Has a scanning line drive circuit,
The semiconductor device having the buffer circuit according to any one of claims 1 to 4, wherein the scanning line driving circuit is a semiconductor device.

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