JPH0728428A - Logic circuit - Google Patents

Abstract

PURPOSE:To provide a logic circuit capable of reducing power consumption and constituted of multistage connection of inverters by supplying an input signal to a gate electrode and on the other hand, supplying an inversed input inverting the input signal to the gate electrodes of transistors for loads of odd stages. CONSTITUTION:This circuit is constituted so that the inverter consisting of the transistor 21a for load by a MOSFET and the transistor 22a for driver by the MOSFET are multistage connected. In the logic circuit consisting of the inverter circuit successively applying the output of the inverter of a preceding stage to the gate electrode of the transistor 22a for driver of a poststage, the input signal is supplied to the gate electrode of the transistor 22a for driver of a first stage and the gate electrodes of the transistors 21b, 21d for loads of even stages, and on the other hand, the inverse input signal inverting the input signal is supplied to the gate electrodes of the transistors 21a, 21c for loads of odd stages. Thus, the occurrence of a through current in each inverter is prevented, and useless power consumption is suppressed, and the power consumption is reduced sufficiently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit used, for example, in a drive circuit of a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, a TFT (Thin Film Trans) has been used as a liquid crystal panel used in a liquid crystal television or the like.
An active matrix type using an istor (thin film transistor) is widely used.

The basic structure is shown in FIGS. In the figure,
Reference numerals 101 and 102 denote a pair of transparent substrates made of glass, quartz, or the like. Among the pair of substrates 101 and 102, one surface of one substrate 101 has a large number of pixel electrodes 103 for display.
Further, thin film transistors (hereinafter abbreviated as “pixel TFT”) 104 which are respectively connected to and selectively driven by the pixel electrodes 103 are formed vertically and horizontally.

Although not shown here, the pixel TFT 104 has a structure in which a gate electrode, a gate insulating film, and a semiconductor layer made of amorphous silicon or polysilicon are laminated and a channel portion is further formed thereon. The source electrode and the drain electrode are laminated. These source electrode and drain electrode are each composed of an N ⁺ semiconductor layer and a contact metal layer. The pixel electrode 103 is connected to the source electrode of the pixel TFT 104.

On the surface of the one substrate 101, a large number of gate lines G1 to Gm and the gate lines G1 are formed.
A large number of drain lines D1 to Dn orthogonal to Gm to Gm are arranged, and each gate line G1 to Gm is connected to each pixel T.
Each drain line D connected to the gate electrode of FT104
1 to Dn are connected to the drain electrode of each pixel TFT 104. An alignment film made of an insulating film is formed above the pixel TFT 104.

On the other hand, on the surface of the other substrate 102, facing all of the pixel electrodes 103, or at least facing one row of image electrodes connected to one gate line through the pixel TFTs 104, One or a plurality of divided counter electrodes are formed, and further, both substrates 101,
An alignment film is formed on each electrode forming surface of 102. The pair of substrates 101 and 102 are adhered to each other with their electrode formation surfaces facing each other through a frame-shaped sealing material 108, and liquid crystal is injected between the substrates 101 and 102 by a sealing member. It is enclosed.

In this way, one pixel is formed by one pixel electrode 103, the portion of the counter electrode facing it and the liquid crystal sandwiched between these electrodes, and a plurality of these pixels are arranged in a matrix. Thus, a display area 111 for displaying a desired image is formed.

A drive circuit is provided outside the display area between the pair of substrates 101 and 102 and inside the outer peripheral frame of the sealing material 108. That is, this drive circuit includes a drain line drive circuit 112 for supplying a data signal to the pixel electrode 103 and a gate for controlling the pixel TFT 104 provided for each pixel electrode 103 according to the image data to be displayed. Line drive circuit 113
It has and.

Each of the drain line driving circuit 112 and the gate line driving circuit 113 is an integrated circuit composed of a plurality of TFTs formed on the substrate 101 using amorphous silicon or polysilicon semiconductor. The drain line drive circuit 112 and the gate line drive circuit 113 have their respective edges in the side edge direction of the substrate 101 overlapped with the seal material 108, and the edges in the inner direction of the substrate 101 enter the liquid crystal enclosing region. It is provided in the closed position.

Of the drain lines D1 to Dn, odd-numbered drain lines are connected to a drain-line driving circuit 112 arranged above the substrate 101, and even-numbered drain lines are arranged below the substrate 101. The drain line driving circuit 112 is connected to the drain line driving circuit 112, and the odd-numbered gate lines of the gate lines G1 to Gm are the substrate.
The gate line drive circuit 113 arranged on the left side of the substrate 101 is connected, and the even-numbered gate lines are connected to the gate line drive circuit 113 arranged on the right side of the substrate 101. Then, the drain line driving circuit 112 and the gate line driving circuit 113 are connected by a signal line 114 for supplying a control signal and a data signal, respectively, and the signal line 114 is supplied from the outside of the display device with the control signal and the data signal. Etc. are connected to a terminal 115 to which is supplied.

The drain line drive circuit 112 described above is
A data latch circuit 112a formed of a shift register or the like for sequentially storing the data signal supplied from the signal line 114 every other data, and connected to the data latch circuit 112a,
When the latched data is output, the data signal generating circuit 112b outputs a signal of a desired potential to the drain line based on the supplied clock signal. Further, the gate line drive circuit 113 includes a circulating storage circuit 113a that circulates "1" data in the shift register based on the supplied clock signal, and the circulating storage circuit 113a.
And a gate signal generating circuit 113b for generating a gate signal for selecting every other gate line according to the output of 113a.

In the active matrix type liquid crystal panel having the above-mentioned structure, the image data, the clock signal, etc. are inputted from the terminal 115 to the drain line driving circuit 112 and the gate line driving circuit 113 through the signal line 114, and these Based on the control signal, the gate line driving circuits 113 arranged on the left and right of the substrate 101 alternately generate gate signals and sequentially supply the gate signals to the respective gate lines G1 to Gm, and the gate lines G1 to Gm Are sequentially selected. The drain line driving circuits 112 arranged above and below the substrate 101 supply the data signals to the drain lines D1 to Dn in synchronism with the selected period to turn on the pixel TFT 104 connected to the selected gate line. The data signal supplied to the drain line by the pixel electrode 103
Applied to. On the other hand, a common signal is applied to the counter electrode facing the pixel electrode 103, an electric field is generated between the pixel electrode 103 and the pixel electrode 103, and the liquid crystal interposed between the electrodes is operated by this electric field to display image data. To be done.

Thus, the drain line drive circuit 11
A buffer circuit for generating a signal of a desired potential or a gate signal is provided at the final stage of each of the data signal generating circuit 112b and the gate signal generating circuit 113b of the gate line driving circuit 113. The buffer circuit is configured by arranging logic circuits of inverter circuits as shown in FIG. 5 in the same number as the number of drain lines and gate lines.

FIG. 5 shows the configuration of the inverter circuit. The load transistor 11a and a load transistor 11a are formed by a MOSFET in which the power supply voltage VDD is applied to the drain electrode and the drain electrode and the gate electrode are short-circuited.
An inverter composed of two transistors, a driver transistor 12a formed by a MOSFET in which the drain electrode is connected to the source electrode of 11a and its own source electrode is grounded, is provided in parallel for a plurality of stages, for example, four stages (11b, 12b, 11).
c, 12c, 11d, 12d) are connected. The input terminal 13 is connected to the gate electrode of the first-stage driver transistor 12a.
The drain electrode of the driver transistor 12a is connected to the gate electrode of the second-stage driver transistor 12b as an output terminal of the first-stage inverter. After that, similarly, the second-stage driver transistor 12b
The drain electrode of is the third driver transistor 12b
3rd driver transistor 12c on the gate electrode of
The drain electrode of the driver transistor 12d is the fourth stage
And the drain electrode of the fourth-stage driver transistor 12d is connected as an output terminal 14 of the inverter circuit to a drain line or a gate line not shown here.

In the above configuration, it is assumed that the input terminal 13 is supplied with a signal clock having a waveform as shown in FIG. 6 (1). When the input clock is at "L" level, the driver transistor 12a in the first stage is at the operating point A in the graph shown in FIG. 7 and is in the off state. However, since the gate electrode of the load transistor 11a is at the level of the power supply voltage VDD at this point, the load transistor 11a
The load transistor 11a continues to be turned on until the source electrode of 11a becomes the same level. Therefore, the driver transistor 12 which is the output terminal of the first-stage inverter
a drain electrode to a second-stage driver transistor
The gate electrode of 12b is boosted to the level of the power supply voltage VDD.

Thereafter, when the input signal to the input terminal 13 shown in FIG. 6 (1) changes from "L" level to "H" level, 1
The driver transistor 12a at the stage moves to the operating point B in the graph shown in FIG. 7 and is turned on. At this time, since the load transistor 11a is also on, a steady current does not flow from the drain electrode of the driver transistor 12a, which is the output terminal of the first-stage inverter, to the gate electrode of the second-stage driver transistor 12b. Due to the operation of the load transistor 11a and the driver transistor 12a, the potentials are such that currents flow equally.

Usually, in the load transistor 11a and the driver transistor 12a, the driver transistor 12a is designed to have a higher rating so that the current can flow easily. The currents are balanced so that they become equal at a point slightly lower than the midpoint of the power supply voltage VDD and the ground level. Therefore, the input terminal
When the input signal to 13 is at "H" level, a through current flows through the load transistor 11a and the driver transistor 12a, resulting in wasted power consumption.

[0018]

As described above, the configuration of the inverter circuit as shown in FIG. 5 has a problem of high power consumption. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic circuit configured by multi-stage connection of inverters capable of sufficiently reducing power consumption. It is in.

[0019]

Means for Solving the Problems and Actions That is, the present invention relates to a load transistor and a MOSF by a MOSFET.
In a logic circuit including an inverter circuit configured by connecting invertors composed of driver transistors by ET in multiple stages and sequentially applying the output of the inverter of the previous stage to the gate electrode of the driver transistor of the latter stage, the gate of the driver transistor of the first stage An input signal is supplied to the electrodes and the gate electrodes of the load transistors in the even stages, while an inverted input signal obtained by inverting the input signal is supplied to the gate electrodes of the load transistors in the odd stages.
Generation of a through current in each inverter can be prevented, wasteful power consumption can be suppressed, and power consumption can be made sufficiently low.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the circuit configuration of the load transistor 21a, which is a MOSFET having a drain electrode to which a power supply voltage VDD is applied, and the source electrode of the load transistor 21a is connected to the drain electrode, and its own source electrode is grounded. Inverter composed of two transistors of driver transistor 22a by the MOSFET
Multiple stages in parallel, for example 4 stages (21b, 22b, 21c, 22
c, 21d, 22d) are connected. The input terminal 23 is connected to the gate electrode of the first-stage driver transistor 22a, and the drain electrode of the driver transistor 22a is connected to the second-stage driver transistor 22b gate electrode as the output terminal of the first-stage inverter. To be done. Thereafter, similarly, the drain electrode of the second-stage driver transistor 22b becomes the gate electrode of the third-stage driver transistor 22b,
The drain electrode of the third-stage driver transistor 22c is connected to the gate electrode of the fourth-stage driver transistor 22d, and the drain electrode of the fourth-stage driver transistor 22d becomes the output terminal 24 of this inverter circuit. The gate electrodes of the even-numbered, that is, the second- and fourth-stage load transistors 21b and 21d are connected to the input terminal 23, and the odd-numbered, that is, the first- and third-stage load transistors 21a. An input terminal to which an inverted input signal obtained by inverting the input signal to the input terminal 23 by the gate electrodes of
Connected with 25.

In the above structure, the input signal having the waveform as shown in FIG. 2 (2) is input to the input terminal 23 and the inverted input signal having the waveform as shown in FIG. 2 (1) is input. Input to terminal 25. When the input signal to the input terminal 23 is at "L" level, the driver transistor 22
a is off, but the load transistor 21a
Is turned on by the inverted input signal, the drain electrode of the driver transistor 22a, which is the output terminal of the first-stage inverter, has the power supply voltage VDD, that is, "H".
It becomes a level. Therefore, the second-stage driver transistor 22b is turned on, but the second-stage load transistor 21a is also turned off by the "L" level input signal at this time, and thus the second-stage driver transistor 22b is turned on. The drain electrode of the driver transistor 22b, which is the output terminal of the inverter, becomes "L" level (ground level). As a result, information is successively transmitted to the third and fourth inverters, which is output from the output terminal 24 as an output signal as shown in FIG.

After that, when the input signal to the input terminal 13 shown in FIG. 2 (1) changes from "L" level to "H" level, 1
While the driver transistor 22a of the first stage is turned on, the load transistor 21a is turned off by the inverted input signal of "L" level. Therefore, the driver transistor 22a which is the output terminal of the inverter of the first stage The drain electrode becomes "L" level. In this state, the load transistor 21b of the second stage is turned on by the "H" level input signal, so that the drain electrode of the driver transistor 22b, which is the output terminal of the inverter of the second stage, is driven by the power supply voltage VDD. It becomes H "level. Same as below 3
Information is transmitted through the fourth and fourth inverters, and this is output from the output terminal 24 as an output signal as shown in FIG.

As described above, one of the two transistors forming the inverter of each stage is alternately turned on and the other of them is alternately turned off, so that a through current does not flow in the inverter of each stage and is wasted. It is possible to suppress the consumption of various electric power.

[0024]

As described in detail above, according to the present invention, the MO
A first stage of a logic circuit including an inverter circuit configured by connecting multiple stages of inverters including load transistors formed by SFETs and driver transistors formed by MOSFETs, and sequentially applying the output of the inverter of the previous stage to the gate electrode of the driver transistor of the subsequent stage The input signals are supplied to the gate electrodes of the driver transistors and the load transistors in the even-numbered stages, while the inverted input signals obtained by inverting the input signals are supplied to the gate electrodes of the odd-numbered load transistors. Therefore, it is possible to provide a logic circuit capable of suppressing the generation of shoot-through current in each inverter, suppressing unnecessary power consumption, and sufficiently reducing power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a timing chart showing each signal waveform of FIG.

FIG. 3 is a diagram showing the overall structure of an active matrix type liquid crystal panel using TFTs.

4 is a diagram showing a configuration of a drain line driving circuit and a gate line driving circuit of FIG. 3, in particular.

5 is a diagram showing a configuration of an inverter circuit as a buffer circuit used in the data signal generating circuit and the gate signal generating circuit of FIG.

6 is a timing chart showing each signal waveform of FIG.

FIG. 7 is a diagram showing a drain current characteristic of a MOS-FET with respect to a gate voltage.

[Explanation of symbols]

11a to 11d, 21a to 21d ... Load transistors, 12a to
12d, 22a to 22d ... Driver transistors, 13, 23 ...
Input terminal, 14, 24 ... Output terminal, 25 ... Inverting input terminal, 101
, 102 ... Substrate, 103 ... Pixel electrode, 104 ... Pixel TFT, 1
08 ... Sealing material, 111 ... Display area, 112 ... Drain line driving circuit, 112a ... Data latch circuit, 112b ... Data signal generating circuit, 113 ... Gate line driving circuit, 113a ... Circulating memory circuit, 113b ... Gate signal generating circuit, 114 ... signal line.

Claims (1)

[Claims] 1. A logic circuit comprising an inverter circuit comprising a load transistor formed of a MOSFET and an inverter composed of a driver transistor formed of MOSFETs, which are connected in multiple stages, and which sequentially applies the output of the inverter of the preceding stage to the gate electrode of the driver transistor of the succeeding stage. In, while supplying an input signal to the gate electrodes of the driver transistors of the first stage and the gate electrodes of the load transistors of the even stages, an inverted input signal obtained by inverting the input signal is supplied to the gate electrodes of the load transistors of the odd stages. A logic circuit characterized by supplying.