JP7526845B2 - Semiconductor device, display device - Google Patents

Description

The present invention relates to a display device having a circuit formed using transistors, and more particularly to a display device using electro-optical elements such as liquid crystal or light-emitting elements as a display medium, and a method for driving the same.

In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal televisions. In particular, a technology for integrally forming a pixel circuit and a driver circuit (hereinafter also referred to as an internal circuit) including a shift register, etc., on an insulating substrate using transistors made of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon) is being actively developed because it contributes greatly to reducing power consumption and costs. The internal circuit formed on the insulator is connected to a controller IC, etc. (hereinafter also referred to as an external circuit) via an FPC, etc., and its operation is controlled.

Among the internal circuits shown above, a shift register using transistors made of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon transistors) has been devised.
The configuration of a flip-flop included in a conventional shift register is shown in FIG. 124(A) (Patent Document 1). The flip-flop in FIG. 124(A) includes a transistor 11, a transistor 12,
A transistor 13, a transistor 14, a transistor 15, and a transistor 17 are included.
It is connected to signal line 21, signal line 22, wiring 23, signal line 24, power supply line 25, and power supply line 26. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to signal line 21, signal line 22, signal line 24, power supply line 25, and power supply line 26, respectively. The operation period of the flip-flop in Fig. 124(A) is divided into a set period, a selection period, a reset period, and a non-selection period, as shown in the timing chart of Fig. 124(B), and most of the operation period is the non-selection period.

Here, the transistors 12 and 16 are on during the non-selection period. Therefore, since the semiconductor layers of the transistors 12 and 16 are made of amorphous silicon, the threshold voltage (Vth) fluctuates due to degradation or the like. More specifically, the threshold voltage rises. That is, in the conventional shift register, the threshold voltage of the transistors 12 and 16 rises and the transistors cannot be turned on, so that VSS cannot be supplied to the node 41 and the wiring 23, causing malfunction.

In order to solve this problem, Non-Patent Documents 1, 2, and 3 devise a shift register that can suppress a shift in the threshold voltage of the transistor 12. In Non-Patent Documents 1, 2, and 3, a new transistor (first transistor) is arranged in parallel with the transistor 12 (second transistor), and inverted signals are input to the gate electrode of the first transistor and the gate electrode of the second transistor, respectively, during a non-selection period, thereby suppressing the shift in the threshold voltage of the first transistor and the second transistor.

Furthermore, Non-Patent Document 4 devisees a shift register that can suppress the shift in threshold voltage of not only the transistor 12 but also the transistor 16. In Non-Patent Document 4, a new transistor (first transistor) is arranged in parallel with the transistor 12 (second transistor), and another new transistor (third transistor) is arranged in parallel with the transistor 16 (fourth transistor). In a non-selection period, inverted signals are input to the gate electrodes of the first transistor and the second transistor, respectively, and inverted signals are input to the gate electrodes of the third transistor and the fourth transistor, respectively, thereby suppressing the shift in threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor.

Furthermore, in Non-Patent Document 5, an AC pulse is applied to the gate electrode of the transistor 12 to suppress a shift in the threshold voltage of the transistor 12 .

The display devices of Non-Patent Documents 6 and 7 use a shift register composed of amorphous silicon transistors as a scanning line driving circuit, and further input a video signal to R, G, and B sub-pixels from one signal line, thereby reducing the number of signal lines by one third. In this way, the display devices of Non-Patent Documents 6 and 7 reduce the number of connections between the display panel and the driver IC.

JP 2004-157508 A

Soo Young Yoon, et al. , “Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure”, SOCIETY FOR INFORMATION DIS PLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, p. 348-351 Binn Kim, et al. , “a-Si Gate Driver Integration with Time Shared Data Driving”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p. 1073-1076 Mindoo Chun, et al. , “Integrated Gate Driver Using Highly Stable a-Si TFT’s”, Proceedings of The 12th International Display Workshops in con junction with Asia Display 2005, p. 1077-1080 Chun-Ching, et al. , “Integrated Gate Driver Circuit Using a-Si TFT”, Proceedings of The 12th International Display Workshops in conjunction n with Asia Display 2005, p. 1023-1026 Yong Ho Jang, et al. , “A-Si TFT Integrated Gate Driver with AC-Driven Single Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 ATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p. 208-211 Jin Young Choi, et al. , “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 IN TERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p. 274-276 Yong Soon Lee, et al. , “Advanced TFT-LCD Data Line Reduction Method”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TE CHNICAL PAPERS, Volume XXXVII, p. 1083-1086

According to conventional technology, a shift in the threshold voltage of a transistor that is prone to deterioration is suppressed by applying an AC pulse to the gate of the transistor. However, when amorphous silicon is used as the semiconductor layer of the transistor, a problem arises in that the transistor constituting the circuit that generates the AC pulse also naturally experiences a shift in the threshold voltage.
It has also been proposed to reduce the number of signal lines by one-third to reduce the number of contacts between the display panel and the driver IC (Non-Patent Documents 6 and 7), but for practical purposes it is necessary to further reduce the number of contacts in the driver IC.

That is, problems that cannot be solved by conventional techniques include circuit technology for suppressing fluctuations in the threshold voltage of transistors, technology for reducing the number of contacts of driver ICs mounted on display panels, reducing the power consumption of display devices, and increasing the size or definition of display devices.

The invention disclosed in this specification aims to provide an industrially useful technique by solving one or more of these problems.

The display device according to the present invention suppresses the shift in threshold voltage of the easily degraded transistor and the shift in threshold voltage of the turned-on transistor by inputting a signal to the gate electrode of the easily degraded transistor via the turned-on transistor.
The present invention includes a configuration in which an AC pulse is applied to the gate electrode of a transistor that is susceptible to deterioration via a transistor having a gate electrode to which a high potential (VDD) is applied (or via an element having a resistive component).

The switches shown in this specification can be of various types. Examples include electrical switches and mechanical switches. In other words, any switch that can control the flow of current is acceptable, and is not limited to a specific type. For example, a switch can be a transistor (e.g.,
Bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator
orMetal) Diode, MIS (Metal Insulator Semiconductor)
A switch may be a diode, a diode-connected transistor, a thyristor, or the like. Alternatively, a logic circuit combining these may be used as the switch.

When a transistor is used as a switch, the transistor simply operates as a switch, and therefore the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress the off-current, it is preferable to use a transistor with a polarity that has a smaller off-current. Examples of transistors with a smaller off-current include transistors having an LDD region and transistors having a multi-gate structure. Alternatively, when the potential of the source terminal of a transistor operated as a switch operates in a state close to a low-potential power supply (VSS, GND, 0 V, etc.), it is preferable to use an N-channel transistor. On the other hand, when the potential of the source terminal is
It is desirable to use a P-channel transistor when operating in a state close to a high-potential power supply (such as VDD). This is because, when an N-channel transistor operates in a state where the source terminal is close to a low-potential power supply, and when a P-channel transistor operates in a state where the source terminal is close to a high-potential power supply, the absolute value of the gate-source voltage can be increased, resulting in good switching characteristics. In addition, source follower operation is unlikely to occur, so the magnitude of the output voltage is unlikely to decrease.

A CMOS switch may be used as a switch by using both N-channel transistors and P-channel transistors. When a CMOS switch is used, a current flows if either the P-channel transistor or the N-channel transistor is conductive, so that the switch can function easily as a switch. For example, whether the voltage of the input signal to the switch is high or low, the switch can output an appropriate voltage. Furthermore, the voltage amplitude value of the signal for turning the switch on and off can be reduced, so that power consumption can be reduced.

When a transistor is used as a switch, the switch has an input terminal (either the source terminal or the drain terminal), an output terminal (the other of the source terminal or the drain terminal), and a terminal for controlling conduction (gate terminal). On the other hand, when a diode is used as a switch, the switch may not have a terminal for controlling conduction. For this reason, using a diode as a switch rather than a transistor can reduce the amount of wiring for controlling the terminals.

In this specification, when it is explicitly stated that "A and B are connected," this includes cases where A and B are electrically connected, where A and B are functionally connected, and where A and B are directly connected. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, in the configuration disclosed in this specification, the connection relationship is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and also includes connection relationships other than those shown in a figure or text.

For example, in the case where A and B are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, etc.) that enable the electrical connection between A and B may be disposed between A and B. Alternatively, in the case where A and B are functionally connected, one or more circuits (e.g., a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (power supply circuit (booster circuit,
(e.g. step-down circuit), level shifter circuit that changes the potential level of a signal), voltage source, current source,
Switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current, operational amplifiers,
One or more elements (e.g., differential amplifier circuit, source follower circuit, buffer circuit, signal generating circuit, memory circuit, control circuit, etc.) may be disposed between A and B. Alternatively, in the case where A and B are directly connected, A and B may be directly connected without any other elements or circuits between A and B.
and may be directly connected to each other.

When it is explicitly stated that "A and B are directly connected", this includes the case where A and B are directly connected (i.e., the case where A and B are connected without any other element or circuit between them) and the case where A and B are electrically connected (i.e., the case where A and B are connected with another element or circuit between them).

When it is explicitly stated that "A and B are electrically connected", this includes the cases where A and B are electrically connected (i.e., when they are connected with another element or circuit between them), where A and B are functionally connected (i.e., when they are functionally connected with another circuit between them), and where A and B are directly connected (i.e., when A and B are connected without another element or circuit between them). In other words, when it is explicitly stated that something is electrically connected, this is the same as when it is explicitly stated only that it is connected.

A display element, a display device which is a device having a display element, a light-emitting element, and a light-emitting device which is a device having a light-emitting element can have various forms and various elements. For example, the display element, the display device, the light-emitting element, and the light-emitting device can have an EL element (organic EL element, inorganic EL element, etc.)
element or EL element including organic and inorganic materials), electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP)
A display medium whose contrast, brightness, reflectance, transmittance, etc. change due to an electro-magnetic effect, such as a digital micromirror device (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be used.
Display devices using electron-emitting devices include field emission displays (FEDs) and SED flat panel displays (SED: Surface-conducting
Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays), and examples of display devices using electronic ink or electrophoretic elements include electronic paper.

As the transistor described in this specification, various types of transistors can be used. Therefore, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) having a non-single crystal semiconductor film represented by amorphous silicon, polycrystalline silicon, microcrystalline (also called microcrystal or semi-amorphous) silicon, etc. can be used. When a TFT is used, there are various advantages. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, the manufacturing cost can be reduced and the manufacturing equipment can be enlarged. Since the manufacturing equipment can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Then, the transmission of light in a display element can be controlled by using a transistor on a transparent substrate. Alternatively, since the film thickness of the transistor is thin, a part of the film constituting the transistor can transmit light. Therefore, the aperture ratio can be improved.

By using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. As a result,
A gate driver circuit (scanning line driver circuit), a source driver circuit (signal line driver circuit), and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on the substrate.

When manufacturing microcrystalline silicon, the crystallinity can be further improved by using a catalyst (such as nickel), making it possible to manufacture a transistor with good electrical characteristics.
Crystallinity can be improved by simply applying heat treatment without using a laser. As a result, it is possible to form the gate driver circuit (scanning line driving circuit) and part of the source driver circuit (analog switch, etc.) integrally on the substrate. Furthermore, when a laser is not used for crystallization, unevenness in the crystallinity of the silicon can be suppressed. This allows for clear images to be displayed.

However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, a transistor can be formed using a semiconductor substrate or an SOI substrate. In this case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. This makes it possible to manufacture a transistor with small variations in characteristics, size, shape, etc., high current supply capability, and small size. By using these transistors, it is possible to configure a circuit with low power consumption or to achieve high integration.

Alternatively, a transistor having a compound semiconductor or oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor formed by thinning these compound semiconductors or oxide semiconductors, can be used. This allows the manufacturing temperature to be lowered, and it becomes possible to manufacture a transistor at room temperature, for example. As a result, a transistor can be formed directly on a substrate with low heat resistance, such as a plastic substrate or a film substrate. It should be noted that these compound semiconductors or oxide semiconductors can be formed by:
They can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistor elements, pixel electrodes, and transparent electrodes. Furthermore, they can be formed or deposited simultaneously with transistors, thereby reducing costs.

Alternatively, a transistor formed by inkjet printing or a printing method can be used. This allows manufacturing at room temperature, in a low vacuum, or on a large substrate. In addition, since it is possible to manufacture without using a mask (reticle),
The layout of the transistors can be easily changed. Furthermore, since there is no need to use resist, material costs are lower and the number of processes can be reduced. Furthermore, since the film is applied only to the necessary parts, there is no waste of material and costs are lower than in the case of a method in which a film is formed over the entire surface and then etched.

Alternatively, a transistor having an organic semiconductor or a carbon nanotube can be used, which allows a transistor to be formed on a bendable substrate.
This makes it resistant to impacts.

Various other transistors can also be used.

The type of substrate on which the transistors are formed can be various and is not limited to a specific one. Examples of the substrate on which the transistors are formed include a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate,
Stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester) etc.), leather substrates, rubber substrates, stainless steel substrates, substrates having stainless steel foil etc. can be used. Alternatively, skin of animals such as humans (
Alternatively, a transistor may be formed on a substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Substrates on which transistors are transferred include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates,
Fabric substrates (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester)
or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.)
, leather substrate, rubber substrate, stainless steel substrate, substrate having stainless steel foil, etc. Alternatively, skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. By using such substrate, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are not easily broken, provide heat resistance, or reduce weight.

The transistor configuration can take various forms. It is not limited to a specific configuration. For example, a multi-gate structure with two or more gate electrodes may be used. In the multi-gate structure, the channel regions are connected in series, resulting in a configuration in which multiple transistors are connected in series. The multi-gate structure can reduce the off-current and improve the transistor's withstand voltage, thereby improving reliability. Alternatively, when operating in the saturation region, even if the drain-source voltage changes, the current between the drain and source does not change much, and the slope of the voltage-current characteristic can be made flat. By utilizing the characteristic that the slope of the voltage-current characteristic is flat, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.
Alternatively, a structure in which gate electrodes are arranged above and below the channel may be used. By adopting a structure in which gate electrodes are arranged above and below the channel, the channel region is increased, so that the current value can be increased. Alternatively, a depletion layer is easily formed, so that the S value can be reduced. When gate electrodes are arranged above and below the channel, a structure is formed in which multiple transistors are connected in parallel.

Alternatively, the gate electrode may be disposed above the channel region, or may be disposed below the channel region. Alternatively, the gate electrode may be disposed in a normal staggered structure or an inverse staggered structure, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series.
The channel region (or a part thereof) may overlap with a source electrode or a drain electrode.
By forming a structure in which the source electrode and drain electrode overlap the channel region (or a part of it), it is possible to prevent charge from accumulating in a part of the channel region, which would cause the operation to become unstable. Also, an LDD region may be provided. By providing an LDD region, it is possible to reduce the off-current and improve the reliability by improving the breakdown voltage of the transistor. Alternatively, when operating in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change much, and the slope of the voltage-current characteristic can be made flat.

In this specification, one pixel refers to the smallest unit of an image.
In the case of a full-color display device consisting of (green) and (blue) color elements, one pixel is composed of a dot of the R color element, a dot of the G color element, and a dot of the B color element. The color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of the colors in RGB may be added to RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have slightly different frequencies. Similarly, R1, R2, G, and B may be used. By using such color elements, it is possible to display something closer to the real thing and reduce power consumption. It is also possible for one pixel to have multiple dots of color elements of the same color.
In this case, the multiple color elements may each have a different area size that contributes to the display. Also, gradation may be expressed by controlling each of the multiple dots of the same color element. This is called area gradation. Alternatively, the viewing angle may be widened by using multiple dots of the same color element and slightly differentiating the signals supplied to each dot. In other words, the potentials of the pixel electrodes of the multiple color elements of the same color may each be different. As a result, the voltage applied to the liquid crystal molecules differs for each pixel electrode. This makes it possible to widen the viewing angle.

In this specification, one pixel refers to one element whose brightness can be controlled. Thus, as an example, one pixel refers to one color element, and the brightness is expressed by this one color element. In this case, in the case of a color display device consisting of R (red), G (green), and B (blue) color elements, the minimum unit of an image is composed of three pixels, an R pixel, a G pixel, and a B pixel. Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Also, for example, a color similar to at least one of the RGB colors may be added to RGB. For example, it may be R, G, B1, and B2. B1 and B2 may be added to the RGB.
2 and R1 are both blue, but have slightly different frequencies.
B may be used. By using such color elements, it is possible to perform a display closer to the real thing and reduce power consumption. In addition, as another example, when the brightness of one color element is controlled using multiple regions, one of the regions may be regarded as one pixel. Therefore, as an example, when performing area gradation or when having sub-pixels, there are multiple regions for controlling the brightness of one color element, and the gradation is expressed as a whole, but one region for controlling the brightness may be regarded as one pixel. Therefore, in that case, one color element is composed of multiple pixels. Alternatively, even if there are multiple regions for controlling the brightness in one color element, they may be combined and one color element may be regarded as one pixel. Therefore, in that case, one color element is composed of one pixel. In addition, when the brightness of one color element is controlled using multiple regions, the size of the region contributing to the display may differ depending on the pixel. In addition, the signal supplied to each of the multiple regions for controlling the brightness of one color element may be slightly different to widen the viewing angle. In other words, the potentials of the pixel electrodes of the multiple regions of one color element may be different from each other, so that the voltages applied to the liquid crystal molecules differ from pixel to pixel, thereby making it possible to widen the viewing angle.

When it is explicitly stated that one pixel (three colors) is used, it means that one pixel is considered to consist of three pixels of R, G, and B. When it is explicitly stated that one pixel (one color) is used, it means that when there are multiple regions for one color element, they are collectively considered to be one pixel.

In this specification, pixels may be arranged (distributed) in a matrix. Here, "pixels arranged (distributed) in a matrix" includes cases where the pixels are arranged in a straight line in the vertical or horizontal direction, or in a jagged line. For example, when performing full-color display using three color elements (e.g., RGB), it also includes cases where the pixels are arranged in stripes, or where dots of the three color elements are arranged in a delta configuration. Furthermore,
This also includes the case of a Bayer arrangement. The color elements are not limited to three colors, and may be more than three, for example, RGBW (W is white), or RGB plus one or more colors such as yellow, cyan, and magenta. Also, the size of the display area may differ for each dot of the color elements. This can reduce power consumption. Or, the life of the display element can be extended.

In this specification, an active matrix system in which the pixels have active elements, or a passive matrix system in which the pixels do not have active elements can be used.

In the active matrix method, not only transistors but also various other active elements (non-linear elements) can be used as active elements. For example, MIM (Metal Insulator Metal) and TFD (Thin Film Diode) can be used.
It is also possible to use a 3D inFilmDiode. These elements can be manufactured at low cost because they require fewer manufacturing steps. Alternatively, it is possible to increase the yield. Furthermore, because the size of the element is small, it is possible to improve the aperture ratio, thereby achieving low power consumption and high brightness.

As a non-active matrix type, active elements (active elements, non-linear elements)
It is also possible to use a passive matrix type that does not use active elements (active elements, nonlinear elements). Since no active elements (active elements, nonlinear elements) are used, the number of manufacturing steps is reduced and manufacturing costs can be reduced.
Also, since no active elements (active elements, nonlinear elements) are used, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

A transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and can pass a current through the drain region, the channel region, and the source region. Here, the source and the drain vary depending on the structure and operating conditions of the transistor, so it is difficult to determine which is the source or the drain. Therefore, in this specification, the regions that function as the source and the drain may not be called the source or the drain. In that case, as an example, they may be referred to as the first electrode and the second electrode, respectively.

A transistor may be an element having at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector may be referred to as a first terminal and a second terminal.

The term "gate" refers to the whole including the gate electrode and the gate wiring (also called the gate line, gate signal line, scanning line, scanning signal line, etc.), or a part of them. The term "gate electrode" refers to the conductive film of the part that overlaps the semiconductor forming the channel region with the gate insulating film interposed therebetween. Note that a part of the gate electrode is called an LDD (Lightly Doped Doped)
In some cases, the gate wiring overlaps with the gate electrode of each transistor or the source and drain regions via a gate insulating film. The gate wiring is a wiring for connecting the gate electrodes of the transistors or for connecting the gate electrodes to another wiring.

However, there are also parts (regions, conductive films, wiring, etc.) that function both as gate electrodes and as gate wiring. Such parts (regions, conductive films, wiring, etc.) may be called gate electrodes or gate wiring. In other words, there are also regions in which the gate electrodes and gate wiring cannot be clearly distinguished. For example, when a part of the gate wiring that is extended and arranged overlaps with the channel region, the part (regions, conductive films, wiring, etc.) functions as the gate wiring, but also as the gate electrode. Therefore, such parts (regions, conductive films, wiring, etc.) may be called gate electrodes or gate wiring.

A part (region, conductive film, wiring, etc.) that is made of the same material as the gate electrode and is connected to the gate electrode to form the same island may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) that is made of the same material as the gate wiring and is connected to the gate electrode to form the same island may also be called a gate wiring.
In the strict sense, the insulating layer (region, conductive film, wiring, etc.) does not overlap with the channel region.
However, it may be formed of the same material as the gate electrode or gate wiring and may be located on the same island as the gate electrode or gate wiring.
Such a portion (region, conductive film, wiring, etc.) may also be called a gate electrode or gate wiring.

For example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected by a conductive film made of the same material as the gate electrodes. Such a portion (region, conductive film, wiring, etc.) may be called a gate wiring because it is a portion (region, conductive film, wiring, etc.) for connecting the gate electrodes, but since a multi-gate transistor can also be regarded as one transistor, it may also be called a gate electrode.
In other words, a portion (such as a region, conductive film, or wiring) that is made of the same material as the gate electrode or gate wiring and that is connected to form the same island as the gate electrode or gate wiring may be called a gate electrode or gate wiring. Furthermore, for example, a conductive film that is a portion that connects the gate electrode and gate wiring and is made of a material different from the gate electrode or gate wiring may also be called a gate electrode or a gate wiring.

The gate terminal refers to a part of a gate electrode (such as a region, a conductive film, or a wiring) or a part electrically connected to the gate electrode (such as a region, a conductive film, or a wiring).

When the term "gate wiring", "gate line", "gate signal line", "scanning line", "scanning signal line", etc. is used, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, gate line, gate signal line, scan line, and scan signal line are wiring formed in the same layer as the gate of the transistor,
It may refer to wiring made of the same material as the gate of a transistor or wiring formed at the same time as the gate of a transistor. Examples include storage capacitor wiring, power supply lines, and reference potential supply wiring.

The source refers to the whole including the source region, source electrode, and source wiring (also called source line, source signal line, data line, data signal line, etc.), or a part of them. The source region refers to a semiconductor region that contains a large amount of P-type impurities (such as boron or gallium) or N-type impurities (such as phosphorus or arsenic). Therefore, a region that contains only a small amount of P-type impurities or N-type impurities, a so-called LDD (Lightly Doped Drain) region, is not included in the source region. The source electrode refers to a conductive layer that is formed of a material different from the source region and is disposed in electrical connection with the source region. However, the source electrode is,
The source electrode may also include the source region. The source wiring is a wiring for connecting the source electrodes of each pixel or for connecting the source electrode to another wiring.

However, there are also parts (regions, conductive films, wiring, etc.) that function both as source electrodes and as source wiring. Such parts (regions, conductive films, wiring, etc.) may be called source electrodes or source wiring. In other words, there are also regions in which the source electrode and the source wiring cannot be clearly distinguished. For example, when a part of the source wiring that is extended and arranged overlaps with the source region, the part (region, conductive film, wiring, etc.) functions as a source wiring but also functions as a source electrode. Therefore, such parts (regions, conductive films, wiring, etc.) may be called source electrodes or source wiring.

A portion (region, conductive film, wiring, etc.) that is formed of the same material as the source electrode and is connected to the source electrode to form the same island, and a portion (region, conductive film, wiring, etc.) that connects source electrodes to each other may also be called a source electrode. Furthermore, a portion that overlaps with a source region may also be called a source electrode. Similarly, a region that is formed of the same material as the source wiring and is connected to the source electrode to form the same island may also be called a source wiring. Strictly speaking, such a portion (region, conductive film, wiring, etc.) may not have the function of connecting to another source electrode. However,
There is a portion (such as a region, a conductive film, or a wiring) that is formed of the same material as the source electrode or the source wiring and is connected to the source electrode or the source wiring. Therefore, such a portion (such as a region, a conductive film, or a wiring) may also be called a source electrode or a source wiring.

For example, a conductive film that connects a source electrode and a source wiring and is made of a material different from that of the source electrode or the source wiring may also be called a source electrode.
This may be called the source wiring.

The source terminal refers to a part of the source region, the source electrode, or a portion electrically connected to the source electrode (such as a region, a conductive film, or a wiring).

When referring to source wiring, source line, source signal line, data line, data signal line, etc., the source (drain) of the transistor may not be connected to the wiring. In this case, the source wiring, source line, source signal line, data line, and data signal line may mean wiring formed in the same layer as the source (drain) of the transistor, wiring formed from the same material as the source (drain) of the transistor, or wiring formed at the same time as the source (drain) of the transistor. Examples include storage capacitance wiring, power supply line, and reference potential supply wiring.

The drain is the same as the source.

A semiconductor device refers to a device having a circuit including semiconductor elements (transistors, diodes, thyristors, etc.). Furthermore, any device that can function by utilizing semiconductor characteristics may be called a semiconductor device.

Display elements include optical modulation elements, liquid crystal elements, light-emitting elements, and EL elements (organic EL elements, inorganic EL elements).
element or EL element including organic and inorganic materials), electron emission element, electrophoretic element, discharge element,
This refers to, but is not limited to, an optical reflecting element, an optical diffractive element, a digital micromirror device (DMD), and the like.

The display device refers to a device having a display element. The display device may be a display panel body in which a plurality of pixels including a display element or a peripheral driving circuit for driving the pixels are formed on the same substrate. The display device may include a peripheral driving circuit arranged on a substrate by wire bonding or bumps, so-called an IC chip connected by chip-on-glass (COG), or an IC chip connected by TAB or the like. The display device may include a flexible wiring board (FPC) on which an IC chip, a resistive element, a capacitive element, an inductor, a transistor, or the like is attached. The display device may include a printed wiring board (PWB) connected via a flexible wiring board (FPC) or the like and on which an IC chip, a resistive element, a capacitive element, an inductor, a transistor, or the like is attached. The display device may include an optical sheet such as a polarizing plate or a retardation plate. The display device may include a lighting device, a housing, an audio input/output device, a light sensor, or the like. Here, an illumination device such as a backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source (LED, cold cathode fluorescent lamp, etc.), a cooling device (water-cooled type, air-cooled type), and the like.

The lighting device refers to a device that includes a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source (LED, cold cathode tube, hot cathode tube, etc.), a cooling device, and the like.

Note that a light-emitting device refers to a device that has light-emitting elements, etc.

The reflecting device refers to a device having a light reflecting element, a light diffractive element, a light reflecting electrode, and the like.

A liquid crystal display device is a display device having a liquid crystal element. There are two types of liquid crystal display devices: direct-view type,
There are projection types, transmissive types, reflective types, and semi-transmissive types.

A driving device is a device having semiconductor elements, electric circuits, and electronic circuits. For example, a transistor that controls the input of a signal from a source signal line to a pixel (sometimes called a selection transistor, switching transistor, etc.), a transistor that supplies a voltage or current to a pixel electrode, and a transistor that supplies a voltage or current to a light-emitting element are examples of driving devices. Furthermore, a circuit that supplies a signal to a gate signal line (sometimes called a gate driver, gate line driving circuit, etc.), a circuit that supplies a signal to a source signal line (a source driver,
A pixel electrode driver (sometimes called a source line driver circuit) is an example of a driver device.

There are cases where the display device, the semiconductor device, the lighting device, the cooling device, the light-emitting device, the reflecting device, the driving device, etc. are mutually overlapped. For example, there are cases where the display device has a semiconductor device and a light-emitting device, and the semiconductor device has a display device and a driving device.

In this specification, when it is explicitly stated that B is formed on A, or B is formed on A, it is not limited to B being formed directly on A. It also includes the case where B is not in direct contact with A, that is, the case where another object is interposed between A and B. Here, A and B are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal,
A conductive film, layer, etc.

Therefore, for example, when it is explicitly stated that layer B is formed on layer A (or on layer A), this includes the case where layer B is formed directly on layer A, and the case where another layer (e.g., layer C or layer D) is formed directly on layer A, and layer B is formed directly on the other layer. The other layer (e.g., layer C or layer D) may be a single layer or multiple layers.

The same applies to the case where it is explicitly stated that B is formed above A, and is not limited to B being directly on A, but also includes the case where another object is interposed between A and B. Therefore, for example, when it is stated that layer B is formed above layer A, it includes the case where layer B is formed directly on layer A, and the case where another layer (e.g. layer C or layer D) is formed directly on layer A, and layer B is formed directly on the other layer. The other layer (e.g. layer C or layer D) may be a single layer or multiple layers.

When it is explicitly stated that B is formed directly on A, this includes the case where B is formed directly on A, but does not include the case where another object is interposed between A and B.

The same applies when B is below A, or B is below A.

This makes it possible to suppress deterioration in the characteristics of all the transistors in the shift register, thereby making it possible to suppress malfunctions of semiconductor devices to which the shift register is applied, such as liquid crystal display devices.

1A to 1C are diagrams illustrating a structure of a flip-flop described in Embodiment 1. 2 is a timing chart illustrating the operation of the flip-flop shown in FIG. 1 . 2 is a diagram for explaining the operation of the flip-flop shown in FIG. 1; 1A to 1C are diagrams illustrating a structure of a flip-flop described in Embodiment 1. 1A to 1C are diagrams illustrating a structure of a flip-flop described in Embodiment 1. 4 is a timing chart illustrating the operation of the flip-flop shown in the first embodiment; 1A to 1C are diagrams illustrating a structure of a flip-flop described in Embodiment 1. 1A to 1C illustrate a structure of a display device described in Embodiment 1. 9 is a timing chart illustrating a writing operation of the display device shown in FIG. 8 . 1A to 1C illustrate a structure of a shift register described in Embodiment 1. 11 is a timing chart illustrating the operation of the shift register shown in FIG. 10 . 11 is a timing chart illustrating the operation of the shift register shown in FIG. 10 . 1A to 1C illustrate a structure of a shift register described in Embodiment 1. 1A to 1C illustrate a structure of a shift register described in Embodiment 1. 1A to 1C illustrate a structure of a shift register described in Embodiment 1. 1A to 1C illustrate a structure of a display device described in Embodiment 2. 1A to 1C illustrate a structure of a shift register described in Embodiment 1. 1A to 1C illustrate a structure of a display device described in Embodiment 1. 19 is a timing chart illustrating a writing operation of the display device shown in FIG. 18 . 1A to 1C illustrate a structure of a display device described in Embodiment 1. 1A to 1C are diagrams illustrating a structure of a flip-flop described in Embodiment 1. 1A to 1C are diagrams illustrating a structure of a flip-flop described in Embodiment 2. 13A to 13C are diagrams illustrating a structure of a flip-flop described in Embodiment 4; 24 is a timing chart illustrating the operation of the flip-flop shown in FIG. 23 . FIG. 2 is a top view of the flip-flop shown in FIG. FIG. 14 is a diagram for explaining the configuration of a buffer shown in FIG. 13 . 13A to 13C are diagrams illustrating a structure of a flip-flop described in Embodiment 3. 28 is a timing chart illustrating the operation of the flip-flop shown in FIG. 27 . 10A to 10C illustrate a structure of a shift register described in Embodiment 3. 30 is a timing chart illustrating the operation of the shift register shown in FIG. 29 . 11 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 2. 11 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 2. 1A to 1C illustrate a structure of a shift register described in Embodiment 2. 1A to 1C illustrate a structure of a shift register described in Embodiment 2. 34 is a timing chart illustrating the operation of the shift register shown in FIG. 33 . 34 is a timing chart illustrating the operation of the shift register shown in FIG. 33 . 13A to 13C illustrate a configuration of a signal line driver circuit described in Embodiment 5. 38 is a timing chart illustrating an operation of the signal line driver circuit shown in FIG. 37 . 13A to 13C illustrate a configuration of a signal line driver circuit described in Embodiment 5. 40 is a timing chart illustrating an operation of the signal line driver circuit shown in FIG. 39 . 13A to 13C illustrate a configuration of a signal line driver circuit described in Embodiment 5. 13A to 13C are diagrams illustrating a structure of a protection diode described in Embodiment 6. 13A to 13C are diagrams illustrating a structure of a protection diode described in Embodiment 6. 13A to 13C are diagrams illustrating a structure of a protection diode described in Embodiment 6. 13A to 13C illustrate a structure of a display device described in Embodiment 7. 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device. 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device. 1A and 1B are cross-sectional views of a pixel layout example of a semiconductor device. 1A and 1B are cross-sectional views of a pixel layout example of a semiconductor device. 1A and 1B are cross-sectional views of a pixel layout example of a semiconductor device. FIG. 1 is a cross-sectional view of a display element of a semiconductor device. FIG. 1 is a cross-sectional view of a display element of a semiconductor device. FIG. 1 is a cross-sectional view of a display element of a semiconductor device. FIG. 2 is a top view of a display element of a semiconductor device. FIG. 2 is a top view of a display element of a semiconductor device. FIG. 2 is a top view of a display element of a semiconductor device. FIG. 2 illustrates a peripheral circuit configuration of a semiconductor device. FIG. 2 illustrates a peripheral circuit configuration of a semiconductor device. 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device. 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device. FIG. FIG. 2 illustrates a peripheral circuit configuration of a semiconductor device. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. 2A to 2C are diagrams illustrating peripheral components of a semiconductor device. FIG. 2 illustrates a peripheral circuit configuration of a semiconductor device. 2A to 2C are diagrams illustrating peripheral components of a semiconductor device. 2A to 2C are diagrams illustrating peripheral components of a semiconductor device. 2A to 2C are diagrams illustrating peripheral components of a semiconductor device. 1A to 1C are diagrams illustrating a semiconductor device. 1A to 1C are diagrams illustrating one method for driving a semiconductor device. 1A to 1C are diagrams illustrating one method for driving a semiconductor device. 1A to 1C are diagrams illustrating one method for driving a semiconductor device. 1A to 1C are diagrams illustrating one method for driving a semiconductor device. 1A and 1B are cross-sectional views of a pixel layout example of a semiconductor device. 1A and 1B are cross-sectional views of a pixel layout example of a semiconductor device. 1A and 1B are cross-sectional views of a pixel layout example of a semiconductor device. FIG. 1 is a cross-sectional view of a display element of a semiconductor device. 1A to 1C are diagrams illustrating a device for forming a display element of a semiconductor device. 1A to 1C are diagrams illustrating a device for forming a display element of a semiconductor device. 1A to 1C are diagrams illustrating one method for driving a semiconductor device. 1A to 1C are diagrams illustrating one method for driving a semiconductor device. FIG. 2 illustrates one pixel circuit of a semiconductor device. FIG. 2 illustrates one pixel circuit of a semiconductor device. 1A to 1C are diagrams illustrating a process for manufacturing a semiconductor device. 1A to 1C are diagrams illustrating a display element of a semiconductor device. 1A to 1C are diagrams illustrating a display element of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating a structure of a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. FIG. 14 is a diagram for explaining the configuration of a buffer shown in FIG. 13 . 1A and 1B are diagrams for explaining the configuration and timing chart of a flip-flop according to the prior art;

Hereinafter, the embodiments of the present invention will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the present invention can be implemented in many different forms, and that the form and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the present embodiment.

(Embodiment 1)
In this embodiment mode, a flip-flop, a driver circuit including the flip-flop, and a structure and a driving method of a display device including the driver circuit will be described.

A basic structure of a flip-flop of this embodiment mode will be described with reference to FIG 1. The flip-flop shown in FIG 1 includes a first transistor 101, a second transistor 102, a third transistor 103, and a fourth transistor 104.
The first transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107.
the first transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor
The transistor 107 is an N-channel transistor, and the gate-source voltage (V
gs) exceeds a threshold voltage (Vth).

The connection relationship of the flip-flop in FIG.
The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to the third wiring 12
A first electrode of the second transistor 102 is connected to a fourth wiring 124, and a second electrode of the second transistor 102 is connected to a third wiring 123. A first electrode of the third transistor 103 is connected to a sixth wiring 126, and a second electrode of the third transistor 103 is connected to a gate electrode of the second transistor 102, and a third electrode of the third transistor 103 is connected to a gate electrode of the second transistor 102.
A gate electrode of the fourth transistor 103 is connected to the seventh wiring 127. A first electrode of the fourth transistor 104 is connected to the ninth wiring 129, a second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and a gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 101. A first electrode of the fifth transistor 105 is connected to the eighth wiring 128, a second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and a gate electrode of the fifth transistor 105 is connected to the first wiring 121. A first electrode of the sixth transistor 106 is connected to the tenth wiring 129, a second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and a gate electrode of the fifth transistor 105 is connected to the first wiring 121.
30, a second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101, and a gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 101.
A first electrode of the seventh transistor 107 is connected to a gate electrode of the first transistor 101. A second electrode of the seventh transistor 107 is connected to an eleventh wiring 131.
a gate electrode of the seventh transistor 107 is connected to a second wiring 122 .

Note that a connection point between the gate electrode of the first transistor 101, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the second electrode of the seventh transistor 107 is a node 141.
A connection point of the gate electrode of the first transistor 102 , the second electrode of the third transistor 103 , the second electrode of the fourth transistor 104 , and the gate electrode of the sixth transistor 106 is a node 142 .

The fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 13
The seventh wiring 127 and the eighth wiring 128 may be connected to each other or may be the same wiring.

The first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 may be called the first signal line, the second signal line, the third signal line, the fourth signal line, and the fifth signal line, respectively. Furthermore, the fourth wiring 124, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 may be called the first power supply line, the second power supply line, the third power supply line, the fourth power supply line, the fifth power supply line, and the sixth power supply line, respectively.

The seventh wiring 127 and the eighth wiring 128 are supplied with a potential of V1.
A potential of V2 is supplied to each of the first wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131. Furthermore, V1>V2.

Note that signals are input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126. The signal input to the first wiring 121 is a start signal, the signal input to the second wiring 122 is a reset signal, the signal input to the fifth wiring 125 is a first clock signal, and the signal input to the sixth wiring 126 is a second clock signal. Furthermore, the signals input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126 are digital signals in which the potential of the H signal is V1 (hereinafter also referred to as the H level) and the potential of the L signal is V2 (hereinafter also referred to as the L level).

Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the second wiring 122 to the eleventh wiring 131, respectively.

Note that a signal is output from the third wiring 123. The signal output from the third wiring 123 is an output signal of the flip-flop of each stage and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop of the next stage. Furthermore, the signal output from the third wiring 123 has a potential of V1 (hereinafter also referred to as an H level) and a potential of V2
(hereinafter also referred to as L level) digital signal.

Next, the operation of the flip-flop shown in Fig. 1 will be described with reference to the timing chart of Fig. 2 and Fig. 3. Furthermore, the timing chart of Fig. 2 will be explained by dividing it into a selection period and a non-selection period. Furthermore, the non-selection period will be explained by dividing it into a first non-selection period, a second non-selection period, a set period, and a reset period. Furthermore, in the non-selection period, the set period,
In the operation period excluding the selection period and the reset period, a first non-selection period and a second non-selection period are repeated in sequence.

In FIG. 2, the signal 221, the signal 225, the signal 226, the potential 241, the potential 242,
Signal 222 and signal 223 respectively represent a signal input to the first wiring 121, a signal input to the fifth wiring 125, a signal input to the sixth wiring 126, the potential of node 141, the potential of node 142, a signal input to the second wiring 122, and a signal output from the third wiring 123.

First, in the set period shown in FIG. 2A and FIG. 3A, the signal 221 is at H level, so the fifth transistor 105 is turned on, and the signal 222 is at L level, so the seventh transistor 107 is turned off.
The electrode of the eighth wiring 128 becomes a source electrode, and the potential of the eighth wiring 128 becomes a value obtained by subtracting the threshold voltage of the fifth transistor 105, so that the potential becomes V1-Vth(105) (Vth(105): threshold voltage of the fifth transistor 105). Therefore, the first transistor 101 and the fourth transistor 104 are turned on, and the fifth transistor 105 is turned off. At this time, the potential of the node 142 (potential 242) is the potential of the third transistor 103 and the fourth transistor 104.
The resistance ratio (L/W and applied voltage) between the second transistor 104 and the first transistor 102 is V2+β (β: any positive number).
In other words, the potential of the ninth wiring 129 (V2) and the potential of the sixth wiring 126 (V1
The potential difference (V1-V2) between the third transistor 103 and the fourth transistor 104
Therefore, the second transistor 102 and the sixth transistor 106
In this way, during the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is being input, and therefore the potential of the third wiring 123 becomes V2.
The L signal is output from the third wiring 123. Furthermore, the potential of the node 141 is V1-Vt
The electrode is kept at h(105) and is in a floating state.

In the selection period shown in FIG. 2B and FIG. 3B, the signal 221 becomes L level, so that the fifth transistor 105 is turned off, and the signal 222 remains at L level, so that the seventh transistor 10
At this time, the potential of the node 141 is maintained at V1-Vth (105). Therefore, the first transistor 101 and the fourth transistor 104 are maintained on. At this time, the potential of the node 142 is V
2. Therefore, the second transistor 102 and the sixth transistor 106 remain off. Here, an H signal is input to the fifth wiring 125, so that the potential of the third wiring 123 starts to rise. At this time, the potential of the node 141 is increased to V
The voltage Vth(105) rises from 1-Vth(105) to V1+Vth(101)+α (Vth(101): threshold voltage of the first transistor 101, α: any positive number).
The potential of the third wiring 123 is equal to that of the fifth wiring 125 and is therefore V1. Note that this bootstrap operation is performed by capacitive coupling of a parasitic capacitance between the gate electrode and the second electrode of the first transistor 101. In this manner, during the selection period, the potential of the third wiring 123 is V2.
Since the third wiring 123 is electrically connected to the fifth wiring 125 to which the H signal is being input, the potential of the third wiring 123 becomes V1.

In the reset period shown in FIG. 2C and FIG. 3C, the signal 221 remains at the L level, so that the fifth transistor 105 remains off, and the signal 222 becomes the H level, so that the seventh transistor 107 is turned on. At this time, the potential of the node 141 is the potential of the 11th wiring (
V2) is supplied through the seventh transistor 107, so that the node 142 becomes V2. Therefore, the first transistor 101 and the fourth transistor 104 are turned off.
The second electrode of the third transistor 103 serves as a source electrode, and the potential of the sixth wiring 1
Since the potential of the third wiring 123 is equal to the potential (V1) of the third wiring 123 minus the threshold voltage of the third transistor 103, the potential becomes V1-Vth(103) (Vth(103): threshold voltage of the third transistor 103). Therefore, the second transistor 102 and the sixth transistor 106 are turned on. In this manner, during the reset period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, and the potential of the third wiring 123 becomes V2. Therefore, an L signal is output from the third wiring 123.

In the first non-selection period shown in FIG. 2D and FIG. 3D, the signal 221 remains at the L level, so that the fifth transistor 105 remains off, and the signal 222 becomes the L level, so that the seventh transistor 105 becomes the L level.
At this time, the potential of the node 142 is
Since an L signal is input to the node 141, the potential of the node 141 becomes V2. Therefore, the second transistor 102 and the sixth transistor 106 are turned off. At this time, the node 141 is in a floating state, so the potential of the node 141 is V
The potential of the third wiring 123 is maintained at V2. Therefore, the first transistor 101 and the fourth transistor 104 remain off. In this manner, in the first non-selection period, the third wiring 123 is in a floating state, and the potential of the third wiring 123 is maintained at V2.

In the second non-selection period shown in FIG. 2E and FIG. 3E, the signal 221 remains at the L level, so the fifth transistor 105 remains off, and the signal 222 remains at the L level, so the seventh transistor 107 remains off.
Since an H signal is input to the wiring 126 and the transistor 104 is off, V1-Vth
As a result, the second transistor 102 and the sixth transistor 106 are turned on. At this time, the potential of the node 141 is the potential (V2) of the tenth wiring 130, which is the potential of the sixth transistor 106.
Since the L signal is supplied through the fourth transistor 106, the potential of the third wiring 123 remains at V2. Therefore, the first transistor 101 and the fourth transistor 104 remain off. In this manner, during the second non-selection period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 remains at V2. Therefore, the L signal is supplied to the third wiring 12
3 is output.

1, the potential of the third wiring 123 can be set to V1 by making the potential of the node 141 higher than V1+Vth(101) using a bootstrap operation during a selection period. Furthermore, the flip-flop in FIG. 1 can obtain merits such as a reduction in the layout area and the number of elements by performing the bootstrap operation using capacitive coupling of the parasitic capacitance between the second electrode and gate electrode of the first transistor 101.

Furthermore, in the flip-flop of FIG. 1, the second transistor 102 and the sixth transistor 106 are turned on only during the second non-selection period, so that shifts in the threshold voltages of the second transistor 102 and the sixth transistor 106 can be suppressed.

In addition, in the flip-flop of FIG. 1, by supplying V1 to the gate electrode of the third transistor 103 and inputting the second clock signal to the first electrode of the third transistor 103, a shift in the threshold voltage of the third transistor 103 can also be suppressed.

Furthermore, the flip-flop of FIG.
Since the first transistor 104, the fifth transistor 105, and the seventh transistor 107 are not turned on in the first non-selection period and the second non-selection period, shifts in the threshold voltages of the first transistor 101, the fourth transistor 104, the fifth transistor 105, and the seventh transistor 107 can be suppressed.

1 can reset the potential of the node 141 and the potential of the third wiring 123 to V2 by supplying V2 to the node 141 and the third wiring 123 in the next second non-selection period, even if the potential of the node 141 and the potential of the third wiring 123 fluctuate in the first non-selection period. Therefore, the flip-flop in FIG. 1 can suppress malfunction caused by the node 141 and the wiring 123 being in a floating state and the potentials of the node 141 and the third wiring 123 fluctuating.

Furthermore, the flip-flop of FIG. 1 can suppress the threshold shift of the transistor,
It is possible to suppress malfunctions caused by a shift in the threshold voltage of a transistor.

Furthermore, in the flip-flop in Fig. 1, the first transistor 101 to the seventh transistor 107 are all configured as N-channel transistors. Therefore, the flip-flop in Fig. 1 can use amorphous silicon for the semiconductor layers of the transistors, so that the manufacturing process can be simplified, and the manufacturing cost can be reduced and the yield can be improved. Furthermore, it is possible to manufacture a large display device. However, the manufacturing process can also be simplified even if polysilicon or polycrystalline silicon is used for the semiconductor layers of the transistors.

Note that even if amorphous silicon, which exhibits significant characteristic degradation (shift in threshold voltage), is used as a semiconductor layer of a transistor, the flip-flop in FIG. 1 can suppress characteristic degradation of the transistor, so that a display device with a long life can be manufactured.

Here, functions of the first transistor 101 to the eighth transistor 108 will be described. The first transistor 101 has a function of selecting the timing for supplying the potential of the fifth wiring 125 to the third wiring 123 and increasing the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor.
The sixth transistor 102 has a function of selecting the timing at which the potential of the fourth wiring 124 is supplied to the third wiring 123 and functions as a switching transistor.
The fourth transistor 104 has a function of dividing the potential of the first wiring 102 and the potential of the ninth wiring 129, and functions as a resistor or a transistor having a resistance component.
The fifth transistor 105 has a function of selecting the timing at which the potential of the eighth wiring 130 is supplied to the node 142, and functions as a switching transistor. The fifth transistor 106 has a function of selecting the timing at which the potential of the tenth wiring 130 is supplied to the node 141, and functions as an input transistor. The sixth transistor 106 has a function of selecting the timing at which the potential of the tenth wiring 130 is supplied to the node 141, and functions as a switching transistor.
The second transistor 102 functions as a switching transistor by selecting the timing at which the potential of the eleventh wiring 131 is supplied to the node 141. However, the first transistor 101 to the seventh transistor 107 are not limited to transistors as long as they have the above-described functions. For example, the second transistor 102 functions as a switching transistor.
, a fourth transistor 104, a sixth transistor 106, and a seventh transistor 107
As long as the fifth transistor 105 functions as an input transistor, it is sufficient that the fifth transistor 105 has a function of increasing the potential of the node 141 and selecting the timing of turning off the node 141, and may be a PN junction diode or a diode-connected transistor.

The third transistor 103 and the fourth transistor 104 constitute an AC pulse generating circuit. The AC pulse generating circuit outputs a signal inputted from the first electrode of the third transistor 103 to a node 142. However, when the gate electrode of the fourth transistor 104 is at an H level, the AC pulse generating circuit outputs an L signal to the node 142 regardless of the signal inputted from the first electrode of the third transistor 103.

In the flip-flop of this embodiment mode, when the W/L value of the first transistor 101 is set to be maximum among the W/L values of the first transistor 101 to the seventh transistor 107, the fall time and rise time of the signal 223 can be shortened. As a result, the flip-flop of this embodiment mode can output a signal with little distortion or delay even when a large load is connected to the wiring 123.

Furthermore, in the flip-flop of this embodiment, the W/L of the first transistor 101
The value of is preferably 2 to 5 times, and more preferably 3 to 4 times, the value of W/L of the fifth transistor 105. As a result, the flip-flop of Embodiment 1 can output a signal with little distortion or delay even if a large load is connected to the wiring 123.

Furthermore, in the flip-flop of this embodiment, the W/L of the fourth transistor 104
The potential of the node 142 in the set period can be reduced by making the value of W/L larger than the value of W/L of the third transistor 103. As a result, the flip-flop of this embodiment can reliably turn off the sixth transistor 106 in the set period, thereby suppressing malfunction.

Furthermore, in the flip-flop of this embodiment mode, the value of L of the third transistor 103 is preferably larger than the value of L of the fourth transistor 104, and more preferably, is 2
As a result, in the flip-flop of this embodiment, the value of W/L of the third transistor 103 is small, so that the value of W of the fourth transistor 104 can be made small, and the layout area can be reduced.

Note that the arrangement and number of each transistor are not limited to those shown in Fig. 1 as long as the same operation as that shown in Fig. 1 is performed. As can be seen from Fig. 3, which explains the operation of the flip-flop in Fig. 1, in this embodiment mode, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period may be connected as shown by the solid lines in Fig. 3A to 3E. Therefore, as long as the transistors and the like are arranged to satisfy this and can be operated, transistors, other elements (resistance elements, capacitance elements, etc.), diodes, switches, various logic circuits, etc. may be newly arranged.

For example, in the flip-flop shown in FIG. 4A, a capacitor 401 is disposed between the gate electrode and the second electrode of the first transistor 101, so that the bootstrap operation can be performed more stably during the selection period.
Since the parasitic capacitance between the gate electrode and the second electrode of the transistor 101 can be reduced,
Each transistor can be switched at high speed. Alternatively, as shown in FIG. 4B, a transistor 402 may be used as the capacitor 401. The transistor 402 can function as a capacitor having a large capacitance component by connecting a gate electrode to the node 141 and connecting a first electrode and a second electrode to the third wiring 123. However, the transistor 402 can function as a capacitor even if one of the first electrode and the second electrode is floating. Note that common parts to the configuration in FIG. 1 are designated by common reference numerals and description thereof will be omitted.

Note that the capacitor 401 may use a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as a conductive layer, or may use a gate insulating film as an insulating layer and a gate electrode layer and a semiconductor layer to which an impurity is added as a conductive layer, or may use an interlayer film (insulating film) as an insulating layer.
Alternatively, a wiring layer and a transparent electrode layer may be used as the conductive layer. However, when the gate electrode layer and the wiring layer are used as the conductive film of the capacitor 401, it is preferable that the gate electrode layer is connected to the gate electrode of the first transistor 101 and the wiring layer is connected to the second electrode of the first transistor 101. More preferably, when the gate electrode layer and the wiring layer are used as the conductive film, it is preferable that the gate electrode layer is directly connected to the gate electrode of the first transistor 101 and the wiring layer is directly connected to the second electrode of the first transistor 101. This is because an increase in the layout area of the flip-flop due to the arrangement of the capacitor 401 is reduced.

As another example, the flip-flop illustrated in FIG. 4C has a first transistor 101.
1 is used and the description thereof is omitted.

As another example, in the flip-flop shown in FIG. 4D, a resistor 403 is used instead of the third transistor 103, so that the number of wirings and power sources can be reduced by one.
The flip-flop in FIG. 4D sets the potential of the node 142 to the sixth potential during the second non-selection period.
Since the potential (V1) of the wiring 126 can be made equal to the potential of the wiring 126, the driving capability can be improved.
In addition, the same reference numerals are used for the components common to the configuration in FIG. 1, and the description thereof will be omitted.

As another example, in the flip-flop illustrated in FIG. 7A, the gate electrode of the second transistor 102 is connected to a wiring 711 to which an arbitrary signal is input.
A reverse bias can be applied to the gate electrode of the second transistor 102.
Therefore, it is possible to further suppress the threshold shift of the second transistor 102. Note that the same reference numerals are used for the components common to the configuration in FIG.

As another example, in the flip-flop shown in FIG. 7B, the gate electrode of the second transistor 102 is connected to the sixth wiring 126, so that the second transistor 102 can be turned on even during the set period, and thus the driving capability can be improved.
It is possible to reduce noise in the filter 23. Note that the same reference numerals are used for the components common to those in FIG.

7C, a flip-flop can reduce the number of wirings and power supplies by one by using a diode-connected transistor 701 and a diode-connected transistor 702 instead of the third transistor 103.
26, and a second electrode of the transistor 701, a second electrode of the transistor 702, and a gate electrode of the transistor 702 are connected to the node 141. That is, the sixth wiring 1
Two diodes in opposite directions are connected in parallel between the resistor 26 and the node 141.
The same reference numerals are used for the components common to those in the configuration of , and the description thereof will be omitted.

As another example, as shown in Fig. 21A, the sixth transistor 106 is not necessarily required. This is because the sixth transistor 106 is not necessarily required as long as the potential of the node 141 can be maintained at the L level during the non-selection period. Therefore, the flip-flop in Fig. 21A can reduce the number of transistors, and thus can obtain an advantage such as a reduction in layout area. Note that the same reference numerals are used for the parts common to the configuration in Fig. 1, and the description thereof will be omitted.

As another example, as shown in FIG. 21B, instead of the fourth transistor 104,
A first electrode of the eighth transistor 2108 is connected to the twelfth wiring 2132, and a second electrode of the eighth transistor 2108 is connected to the node 14.
2, and the gate electrode of the eighth transistor 2108 is connected to the first wiring 121. Furthermore, V2 is supplied to the twelfth wiring 2132.
21B ) can shorten the fall time of the potential of the node 142 in the set period because the on/off of the eighth transistor 2108 is controlled by a start signal, and can also shorten the time when the second transistor 102 and the sixth transistor 106 are turned off. Furthermore, in the flip-flop of FIG. 21B , the sixth transistor 106 is turned off earlier, so the rise time of the potential of the node 141 in the set period can be shortened. Thus, the flip-flop of FIG. 21B can improve the driving ability of the flip-flop. Note that the same reference numerals are used for the parts common to the configuration of FIG. 1, and the description thereof will be omitted.

The eighth wiring 128 is a wiring that is connected to the fourth wiring 124, the ninth wiring 129, and the tenth wiring 130.
Alternatively, it may be connected to the eleventh wiring 131 .

As another example, as shown in FIG. 21C, an eighth transistor 2108 may be added. The eighth transistor 2108 only needs to set the potential of the node 142 to an L level when the start signal is at an H level, so that the transistor size can be reduced.
In the flip-flop of Fig. 22(C), the on/off of the eighth transistor 2108 is controlled by a start signal, so that the driving ability of the flip-flop can be improved, similarly to the flip-flop of Fig. 22(B). Note that the same reference numerals are used for the components common to Fig. 1 and Fig. 21(B), and the description thereof will be omitted.

It should be noted that the connection relationship of each wire is not limited to that shown in FIG. 1 so long as the same operation as that shown in FIG. 1 is performed.
1, in this embodiment mode, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period may be connected as shown by the solid lines in FIGS. 3A to 3E. Therefore, each wiring may be arranged or connected so as to satisfy this.

For example, as shown in FIG. 5A, the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, the first electrode of the sixth transistor 106, and the first electrode of the seventh transistor 107 may be connected to the sixth wiring 506. Furthermore, the first electrode of the third transistor 103 and the first electrode of the fifth transistor 105 may be connected to the seventh wiring 507. Thus, the flip-flop of FIG. 5A can reduce the number of wirings from 11 to 7 compared to the flip-flop of FIG. 1. Furthermore, the flip-flop of FIG. 5A can improve the yield of the shift register by reducing the number of wirings. Furthermore, the flip-flop of FIG. 5A can reduce the wiring routing area and the layout area of the shift register. Furthermore, the flip-flop of FIG. 5A can increase the width of each wiring, so that the voltage drop can be reduced and the driving ability of the shift register can be improved. In addition, the same reference numerals are used for the components common to the configuration in FIG. 1, and the description thereof will be omitted.

5A corresponds to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG.
5A corresponds to the seventh wiring 127 and the eighth wiring 128 shown in FIG. 1. Furthermore, the first wiring 501, the second wiring 502, and the third wiring 503 shown in FIG.
The third, fourth and fifth wirings 504 and 505 are the same as the first wiring 121 shown in FIG.
, the second wiring 122 , the third wiring 123 , the fifth wiring 125 , and the sixth wiring 126 .

The sixth wiring 506 and the seventh wiring 507 may be called a first power supply line and a second power supply line, respectively. Furthermore, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 may be called a first signal line, a second signal line, a third signal line, a fourth signal line, and a fifth signal line, respectively.

As another example, as shown in FIG. 5B, the first electrode of the fourth transistor 104 may be
5B can suppress malfunction due to a voltage drop in the sixth wiring 506 by causing an instantaneous current generated in the fourth transistor 104 to flow to the eighth wiring 508 during the set period.
The same reference numerals are used for the components common to those in the configuration of , and the description thereof will be omitted.

As another example, as shown in FIG. 5C, the first electrode of the second transistor 102 may be a ninth
5B, the flip-flop 102 may be connected to the sixth wiring 509 by causing an instantaneous current generated in the second transistor 102 to flow to the ninth wiring 509 during the reset period.
It is possible to suppress malfunction due to a voltage drop in the wiring 506 of FIG.
) will be designated by the same reference numerals and their explanation will be omitted.

As another example, as shown in FIG. 5D, the gate electrode of the third transistor 103 is
The flip-flop in FIG. 5D may be connected to the tenth wiring 510.
5A , common reference numerals are used to designate the same transistors as those in FIG. 1 and FIG. 5A , and description thereof will be omitted.

Note that the power supply potential, signal amplitude, and signal timing are not limited to those in the timing chart of Fig. 2 as long as the same operation as in Fig. 1 is performed. As can be seen from Fig. 3, which explains the operation of the flip-flop in Fig. 1, in this embodiment mode, it is sufficient that the set period, selection period, reset period, first non-selection period, and second non-selection period are conductive as shown by the solid lines in Fig. 3A to 3E. Therefore, the power supply potential, signal amplitude, and signal timing may be changed to satisfy this.

For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the fifth wiring 125
6, the period during which the H level signal is switched from the L level to the H level is shorter than the period Ta
6 is delayed by a period Ta2, and the timing at which the signal switches from H level to L level is earlier by a period Ta2.
) is shorter by period Ta1+period Ta2. Therefore, the flip-flop to which the timing chart of FIG. 6 is applied can achieve power saving, suppression of malfunction, and improvement of driving ability, because the instantaneous current of each wiring is small. Furthermore, the flip-flop to which the timing chart of FIG. 6 is applied can shorten the fall time of the signal output from the third wiring 123 during the reset period. This is because the timing at which the potential of the node 141 becomes L level is delayed by period Ta1+period Ta2, so that the L signal input to the fifth wiring 125 is supplied to the third wiring 123 via the first transistor 101 having a large current capacity (large channel width). Note that the parts common to the timing chart of FIG. 2 are designated by common reference numerals and their description is omitted.

The relationship between the periods Ta1, Ta2, and Tb is ((Ta1+Tb)/(Ta1+
It is preferable that ((Ta2+Tb))×100<10[%].
a1+Tb)/(Ta1+Ta2+Tb)×100<5[%].
Furthermore, it is preferable that the period Ta1 is approximately equal to the period Ta2.

As another example, when Va (V2<Va<V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va-Vth(103) during the reset period and the second non-selection period, so that the threshold voltage shifts of the second transistor 102 and the sixth transistor 106 can be suppressed.

As another example, when Vb (V1+Vth(103)<Vb) is supplied to the seventh wiring 127, the potential of the node 142 becomes V1 during the reset period and the second non-selection period, which makes it easier to turn on the second transistor 102 and the sixth transistor 106.

As another example, the potential of an L signal input to the sixth wiring 126 is set to Vc (Vc<V2) and the potential of an H signal is set to Vd (V1>Vd>V2).
This is because the potential of the node 142 becomes Vc during the set period and the first non-selection period, and a reverse bias is applied to the second transistor 102 and the sixth transistor 106. Furthermore, the potential of the node 142 becomes Vd during the reset period and the second non-selection period, and a threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed.
This is because the Vgs of the first transistor 102 and the sixth transistor 106 become smaller.

25 shows an example of a top view of the flip-flop shown in FIG. 5A. The conductive layer 2501 includes a portion functioning as the gate electrode of the second transistor 102 and the gate electrode of the sixth transistor 106, and is connected to the conductive layer 2502 through a wiring 2547.
2502 includes a portion functioning as the second electrode of the third transistor 103 and the second electrode of the fourth transistor 104. The conductive layer 2503 includes a portion functioning as the first electrode of the second transistor 102, the first electrode of the sixth transistor 106, and the first electrode of the fourth transistor 104, and is connected to a sixth wiring 506. The conductive layer 2504 includes a portion functioning as the second electrode of the second transistor 102, and is connected to the third wiring 503 through a wiring 2548. The conductive layer 2505 includes a portion functioning as the second electrode of the fifth transistor 105,
The conductive layer 2506 includes a portion functioning as a second electrode of the seventh transistor 107, and is connected to the conductive layer 2510 through a wiring 2549. The conductive layer 2506 includes a portion functioning as a first electrode of the seventh transistor 107, and is connected to the sixth wiring 506. The conductive layer 2507 includes a portion functioning as a first electrode of the first transistor 101, and is connected to the fourth wiring 504 through a wiring 2541. The conductive layer 2508 includes a portion functioning as a second electrode of the first transistor 101, and is connected to the third wiring 503 through a wiring 2548.
The conductive layer 2510 is a gate electrode of the first transistor 101 and a gate electrode of the fourth transistor 104.
The conductive layer 2511 includes a portion that functions as a gate electrode of the seventh transistor 107.
The conductive layer 2512 includes a portion that functions as a gate electrode of the third transistor 103 and is connected to the second wiring 502 through a wiring 2546. The conductive layer 2512 includes a portion that functions as a gate electrode of the third transistor 103 and is connected to the seventh wiring 507 through a wiring 2544.
The conductive layer 2514 includes a portion functioning as a first electrode of the fifth transistor 103 and is connected to the fifth wiring 505 through a wiring 2543. The conductive layer 2514 includes a portion functioning as a gate electrode of the fifth transistor 105 and is connected to the first wiring 501 through a wiring 2545. The conductive layer 2515 includes a portion functioning as a second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 through a wiring 2547.

Note that the portions functioning as the gate electrode, the first electrode, and the second electrode of the first transistor 101 are portions formed by overlapping a conductive layer including each of the electrodes with the semiconductor layer 2581. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are portions formed by overlapping a conductive layer including each of the electrodes with the semiconductor layer 2582. The portions functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions formed by overlapping a conductive layer including each of the electrodes with the semiconductor layer 2583. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions formed by overlapping a conductive layer including each of the electrodes with the semiconductor layer 2584. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 are portions formed by overlapping a conductive layer including each of the electrodes with the semiconductor layer 2585. The portions functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 are portions formed by overlapping a conductive layer including each of the electrodes with the semiconductor layer 2586. Portions functioning as a gate electrode, a first electrode, and a second electrode of the seventh transistor 107 are formed by overlapping conductive layers including each of the electrodes with the semiconductor layer 2587 .

A structure and a driving method of the shift register having the flip-flop of the above-described embodiment mode will be described.

A configuration of a shift register in this embodiment mode will be described with reference to Fig. 10. The shift register in Fig. 10 has n flip-flops (flip-flops 1001_1 to 1001_n).

The connection relationship of the shift register in Fig. 10 will be described. In the shift register in Fig. 10, a flip-flop 1001_i (one of the flip-flops 1001_1 to 1001_n) in the i-th stage is connected to a second wiring 1012, a third wiring 1013, a fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, an eighth wiring 1018_i-1, an eighth wiring 1018_i-2, an eighth wiring 1018_i-3, an eighth wiring 1018_i-4, an eighth wiring 1018_i-5, an eighth wiring 1018_i-6, an eighth wiring 1018_i-7, an eighth wiring 1018_i-8, an eighth wiring 1018_i-9, an eighth wiring 1018_i-
18_i and an eighth wiring 1018_i+1. Note that the first-stage flip-flop 1001_1 is connected to a first wiring 1011, a second wiring 1012, a third wiring 1013,
The fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, and the eighth wiring 1018_
1 and the eighth wiring 1018_2. Furthermore, the n-th flip-flop 100
1_n is connected to the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, the seventh wiring 1017, the eighth wiring 1018_n-1, and the eighth wiring 1018_n.

The first wiring 1011 is connected to the first wiring 121 shown in FIG. 1 of the flip-flop 1001_1. The second wiring 1012 is connected to the fifth wiring 125 shown in FIG. 1 in the odd-numbered flip-flops, and is connected to the sixth wiring 126 shown in FIG. 1 in the even-numbered flip-flops. The third wiring 1013 is connected to the sixth wiring 126 shown in FIG. 1 in the odd-numbered flip-flops, and is connected to the fifth wiring 125 shown in FIG. 1 in the even-numbered flip-flops. The fourth wiring 1014 is connected to the seventh wiring 121 shown in FIG. 1 in all the flip-flops.
1 in all the flip-flops. The sixth wiring 1016 is connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. 1 in all the flip-flops. The eighth wiring 1018_i is connected to the second wiring 122 shown in FIG. 1 of the flip-flop 1001_i-1, the third wiring 123 shown in FIG. 1 of the flip-flop 1001_i, and the first wiring 121 shown in FIG. 1 of the flip-flop 1001_i+1. However,
The eighth wiring 1018_1 corresponds to the third wiring 12 shown in FIG.
1 of the flip-flop 1001_n. The eighth wiring 1018_n is connected to the second wiring 122 of the flip-flop 1001_n-1 shown in FIG. 1 and the third wiring 123 of the flip-flop 1001_n shown in FIG. 1.

A potential of V1 is supplied to the fourth wiring 1014 and the fifth wiring 1015.
A potential of V2 is supplied to the sixth wiring 1016.

The first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1014 are
A signal is input to each of the first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1017. The signal input to the first wiring 1011 is a start signal, the signal input to the second wiring 1012 is a first clock signal, the signal input to the third wiring 1013 is a second clock signal, and the signal input to the seventh wiring 1017 is a reset signal.
The signals input to the third wiring 1013 and the seventh wiring 1017 are digital signals whose H signal potential is V1 and whose L signal potential is V2.

Note that various signals, power supply potentials, or currents may be input to the first wiring 1011 to the seventh wiring 1017 .

Note that signals are output from the eighth wirings 1018_1 to 1018_n. For example, the signal output from the eighth wiring 1018_i is the output signal of the flip-flop 1001_i. Furthermore, the signal output from the eighth wiring 1018_i is also the start signal of the flip-flop 1001_i+1 and the reset signal of the flip-flop 1001_i-1.

In addition, when the signal input or the voltage supplied to the first wiring 1011 to the seventh wiring 1017 are the same, the first wiring 1011 to the seventh wiring 1017 may be connected to each other or may be the same wiring.

Next, the operation of the shift register shown in Fig. 10 will be described with reference to the timing charts of Fig. 11 and 12. Here, the timing chart of Fig. 11 is divided into a scanning period and a blanking period. The scanning period is a period from when the output of the selection signal from the eighth wiring 1018_1 starts to when the output of the selection signal from the eighth wiring 1018_n ends. The blanking period is a period from when the output of the selection signal from the eighth wiring 1018_n ends to when the output of the selection signal from the eighth wiring 1018_1 starts.

In FIG. 11, a signal 1111 is input to the first wiring 1011, and a signal 1112 is input to the second wiring 10
A signal 1112 input to the wiring 1012, a signal 1113 input to the third wiring 1013, a signal 1117 input to the seventh wiring 1017, and a signal 1118 output to the eighth wiring 1018_1.
12 shows a signal 1211 input to the first wiring 1011, a signal 1218_1 output to the eighth wiring 1018_1, a signal 1218_i output to the eighth wiring 1018_i+1, and a signal 1218_n output to the eighth wiring 1018_n.

As shown in FIG. 12, for example, when the flip-flop 1001_i is in the selection period, an H signal is output from the eighth wiring 1018_i.
The flip-flop 1001_i+1 is in a set period. After that, the flip-flop 1001_i is in a reset period, and an L signal is output from the eighth wiring 1018_i.
001_i+1 is in a selection period. After that, the flip-flop 1001_i is in a first non-selection period, and the eighth wiring 1018_i is in a floating state and maintains the potential at an L level. At this time, the flip-flop 1001_i+1 is in a reset period. After that, the flip-flop 1001_i is in a second non-selection period, and an L signal is output from the eighth wiring 1018_i. At this time, the flip-flop 1001_i+1 is in a first non-selection period. In this way, the flip-flop 1001_i repeats the first non-selection period and the second non-selection period until the next set period.

As described above, the shift register in Fig. 10 can output the selection signal from the eighth wiring 1018_1 to the eighth wiring 1018_n in order. That is, the shift register in Fig. 10 can scan the eighth wirings 1018_1 to 1018_n. Therefore, the shift register in Fig. 10 can fully function as a shift register.

Furthermore, a reset signal input to the flip-flop 1001_n in the final stage is input via a seventh wiring 1017. In this way, the shift register in Fig. 10 does not require a dummy flip-flop, and the layout area can be reduced. However, a dummy flip-flop may be disposed.

Furthermore, the shift register in FIG. 10 can freely determine the blanking period by the timing of the signal input to the first wiring 1011 .

Furthermore, by applying the flip-flop described in this embodiment to the shift register in FIG. 10, a threshold shift of a transistor can be suppressed. Furthermore, the shift register in FIG. 10 can have a longer life. Furthermore, the shift register in FIG. 10 can have an improved driving capability. Furthermore, malfunction can be suppressed. Furthermore,
The shift register of FIG. 10 can simplify the manufacturing process.

Note that the configuration is not limited to that shown in FIG. 10 as long as it performs the same operation as that shown in FIG. 10.

For example, as shown in Fig. 13, the output signal of each flip-flop may be output via a buffer. In the shift register of Fig. 13, the flip-flops 1001_1 to 1001_n are connected to the eighth wirings 1018_1 to 1018_n via the buffers 1301_1 to 1301_n, respectively, so that a wide driving capability can be obtained. This is because, when a large load is connected to each of the eighth wirings 1018_1 to 1018_n, delays and distortions occur in the signals output from each of the eighth wirings 1018_1 to 1018_n. In other words, the eighth wirings 1018_1 to
This is because delays and rounding of signals output from the eighth wirings 1018_n do not affect the operation of the shift register. Note that common reference numerals are used to designate parts common to the configuration in FIG.

Each of the buffers 1301_1 to 1301_n can be a logic circuit such as a NAND or NOR, an operational amplifier, or a combination of these. That is, an inverter or an analog buffer can be used.
When the flip-flop is composed of N-channel transistors, each of the buffers 301_1 to 1301_n is preferably composed of N-channel transistors.
Furthermore, it is desirable that each of the buffers 1301_1 to 1301_n is configured to perform a bootstrap operation.
It is preferable that the driving voltage is larger than the driving voltage of each of the flip-flops 001_1 to 1001_n.

Here, the buffers 1301_1 to 1301_2 of the shift register shown in FIG.
An example of the ._n will be described with reference to FIGS. 123(A) and 123(B).
The buffer 8000 shown in A) has an inverter 8001 between a wiring 8011 and a wiring 8012.
By connecting the inverters 8001a, 8001b, and 8001c, an inverted signal of a signal input to the wiring 8011 is output from the wiring 8012. However, the number of inverters connected between the wiring 8011 and the wiring 8012 is not limited.
When an even number of inverters are connected between the wiring 8011 and the wiring 8012, a signal having the same polarity as the signal input to the wiring 8011 is output from the wiring 8012.
As shown in FIG. 1, inverters 8002a, 8002b, and 8002c are connected in series, and inverters 8003a, 8003b, and 8003c are connected in series.
and an inverter 8003c may be connected in parallel.
Since the inverter 8000 can average out the variations in the characteristics of the transistors, it is possible to reduce the delay and distortion of the signal output from the wiring 8012.
The output of inverter 8002a and the outputs of inverter 8002b and inverter 8002b may be connected to each other.

In FIG. 123A, it is preferable that W of the transistor included in inverter 8001a is smaller than W of the transistor included in inverter 8001b and W of the transistor included in inverter 8001c. This is because the driving capability of the flip-flop (specifically, the value of W/L of transistor 101 in FIG. 1) can be reduced by reducing W of inverter 8001a, and therefore the layout area of the shift register of this embodiment can be reduced. Similarly, in FIG. 123B, it is preferable that W of the transistor included in inverter 8002a is smaller than W of the transistor included in inverter 8002b and W of the transistor included in inverter 8002c. Similarly, in FIG. 123B, it is preferable that W of the transistor included in inverter 8003a is smaller than W of the transistor included in inverter 8003b and W of the transistor included in inverter 8003c. Furthermore, in FIG. 123B, it is preferable that W of the transistor included in inverter 8003a is smaller than W of the transistor included in inverter 8003b and W of the transistor included in inverter 8003c.
It is preferable that the W of the transistors in inverter 8002a=the W of the transistors in inverter 8003a, the W of the transistors in inverter 8002b=the W of the transistors in inverter 8003b, and the W of the transistors in inverter 8002c=the W of the transistors in inverter 8003c.

Note that the inverters shown in Figures 123A and 123B are not particularly limited as long as they can invert and output an input signal. For example, as shown in Figure 123C, an inverter may be configured using a first transistor 8201 and a second transistor 8202. Furthermore, a signal is input to the first wiring, a signal is output from the second wiring 8212, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. When an H signal is input to the first wiring 8211, the inverter in Figure 123C divides V1-V2 into a potential (W/L of the first transistor 8201<W/L of the second transistor 8202) and outputs it as follows:
123C, when an L signal is input to the first wiring 8211, V1-Vth(8201) (Vth(8201): first
The threshold voltage of the transistor 8201 is output from the second wiring 8212.
The first transistor 8201 may be a PN junction diode as long as it is an element having a resistance component, or may simply be a resistance element.

123D, an inverter may be configured by a first transistor 8301, a second transistor 8302, a third transistor 8303, and a fourth transistor 8304. A signal is input to a first wiring 8311, a signal is output from a second wiring 8312, V1 is supplied to a third wiring 8313 and a fifth wiring 8315, and V2 is supplied to a fourth wiring 8314 and a sixth wiring 8316.
When an H signal is input to the first wiring 8311, the inverter of (D) outputs V2 to the second wiring 8
At this time, the potential of the node 8341 is set to the L level, so that the first transistor 8301 is turned off.
When an L signal is input to the third transistor 8303, V1 is output from the second wiring 8312. At this time, when the potential of the node 8341 becomes V1-Vth(8303) (Vth(8303): threshold voltage of the third transistor 8303), the node 8341 becomes floating, and
The potential of V1+Vth(8301) (Vth(8301)
Since the voltage Vcc of the first transistor 8301 becomes higher than the threshold voltage Vcc of the first transistor 8301, the first transistor 8301 is turned on. Furthermore, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode of the first transistor 8301.

26A, an inverter may be configured by a first transistor 8401, a second transistor 8402, a third transistor 8403, and a fourth transistor 8404. The inverter in FIG. 26A is a two-input inverter and is capable of a bootstrap operation. A signal is input to a first wiring 8411, an inverted signal is input to a second wiring 8412, and a signal is output from a third wiring 8413.
V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. When an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, the inverter in FIG.
At this time, the potential of the node 8441 becomes V2, and the first transistor 8401 is turned off.
When an L signal is input to the second wiring 8412, V1 is output from the third wiring 8413. At this time, the potential of the node 8441 becomes V1-Vth(8403) (Vth(8403)
: the threshold voltage of the third transistor 8403), the node 8441 is in a floating state, and the potential of the node 8441 becomes V1+Vth(8401) by the bootstrap operation.
Since the first transistor 8401 is turned on because the first transistor 8401 has a voltage higher than the threshold voltage (Vth(8401): threshold voltage of the first transistor 8401), a capacitance element may be disposed between the second electrode and the gate electrode of the first transistor 8401 since the first transistor 8401 functions as a bootstrap transistor. Furthermore, one of the first wiring 8411 and the second wiring 8412 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG. 1.

Furthermore, as shown in FIG. 26B, an inverter may be configured using a first transistor 8501, a second transistor 8502, and a third transistor 8503.
The inverter of 6(B) is a two-input inverter and is capable of a bootstrap operation. A signal is input to a first wiring 8511, an inverted signal is input to a second wiring 8512, a signal is output from a third wiring 8513, and a fourth wiring 8514 and a sixth wiring 8515 are connected to the first wiring 8511 and the sixth wiring 8515.
The first wiring 8516 is supplied with V2, and the fifth wiring 8515 is supplied with V2.
26B outputs V2 from the third wiring 8513 when an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512. At this time, the potential of the node 8541 becomes V2, so that the first transistor 8501 is turned off. Furthermore, when an H signal is input to the first wiring 8511 and an L signal is input to the second wiring 8512, the inverter of FIG.
1 is output from the third wiring 8513. At this time, the potential of the node 8541 is V1-Vth
When Vth(8503) (Vth(8503): threshold voltage of the third transistor 8503) is reached, the node 8541 is in a floating state, and the potential of the node 8541 is V1+Vth(8501) (Vth(8501): threshold voltage of the first transistor 8501) by the bootstrap operation.
Since the threshold voltage of the first transistor 8501 becomes higher than the threshold voltage of the first transistor 8502, the first transistor 8501 is turned on.
A capacitance element may be disposed between the second electrode and the gate electrode.
1 may be connected to one of the first wiring 8511 and the second wiring 8512, and the node 142 shown in FIG.

26C, an inverter may be configured by a first transistor 8601, a second transistor 8602, a third transistor 8603, and a fourth transistor 8604. The inverter in FIG. 26C is a two-input inverter and is capable of a bootstrap operation. A signal is input to a first wiring 8611, an inverted signal is input to a second wiring 8612, and a signal is output from a third wiring 8613.
V1 is supplied to the fourth wiring 8614, and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. In the inverter of FIG.
When an H signal is input to the third wiring 8612, V2 is output from the third wiring 8613. At this time, the potential of the node 8641 becomes V2, and the first transistor 8601 is turned off.
Furthermore, the inverter of FIG. 26C has a first wiring 8611 connected to a H signal and a second wiring 861
When an L signal is input to node 8, V1 is output from the third wiring 8613.
The potential of the third transistor 8603 is V1-Vth(8603) (Vth(8603):
When the potential of the node 8641 becomes V1+Vth(8601) (Vth(8601):
Since the threshold voltage of the first transistor 8601 becomes higher than the threshold voltage of the first transistor 8601, the first transistor 8601 is turned on. Furthermore, since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode of the first transistor 8601. Furthermore, one of the first wiring 8611 and the second wiring 8612 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG. 1.

As another example, the reset signal input to the flip-flop 1001_n can be another input signal or output signal of the shift register.
By generating a reset signal to be input to flip-flop 1001_n inside the shift register, one wiring and one signal can be eliminated. For example, when flip-flop 1001_n is an even-numbered stage, it may be connected to the eighth wiring 1018_1 as shown in FIG. 14. As another example, when flip-flop 1001_n is an even-numbered stage, it may be connected to the first wiring 1018_1 as shown in FIG.
17, a reset signal to be input to the flip-flop 1001_n may be generated using a dummy flip-flop 1001_d. The dummy flip-flop 1001_d may be the same as the flip-flop 1001_n-1. However, the second wiring 122 of the dummy flip-flop 1001_d shown in FIG. 1 is connected to the sixth wiring 1016 in FIG. 17. Note that common reference numerals are used to designate parts common to the configuration in FIG. 10, and description thereof will be omitted.

Next, a structure and a driving method of a display device having the shift register of the above-described embodiment mode will be described. Note that the display device of this embodiment mode only needs to have at least the flip-flop of this embodiment mode.

The structure of the display device of this embodiment mode will be described with reference to Fig. 18. The display device of Fig. 18 has a signal line driver circuit 1801, a scanning line driver circuit 1802, and a pixel portion 1804. The pixel portion 1804 has a plurality of signal lines S1, S2, and S3 extending from the signal line driver circuit 1801 in the column direction.
1 to Sm, and a plurality of scanning lines G1 to Gm arranged extending in the row direction from a scanning line driving circuit 1802.
The pixel 1803 has a plurality of pixels 1803 arranged in a matrix corresponding to the signal lines Sj (signal lines S1 to S
The scanning line driver circuit 1802 is connected to a scanning line Gi (one of the scanning lines G1 to Gn).

Note that the shift register of this embodiment mode can be applied to the scanning line driver circuit 1802. Of course, the shift register of this embodiment mode may also be used for the signal line driver circuit 1801.

Note that the scanning lines G1 to Gn are connected to the eighth wirings 1808_1 to 1808_n shown in FIGS.

The signal lines and the scanning lines may be simply called wirings.
and the scanning line driver circuit 1802 may each be called a driver circuit.

Note that the pixel 1803 has at least one switching element, one capacitor element, and a pixel electrode. However, the pixel 1803 may have a plurality of switching elements or a plurality of capacitor elements. Furthermore, the capacitor element is not necessarily required.
The pixel 1803 may further include a transistor that operates in the saturation region.
may have a display element such as a liquid crystal element or an EL element. Here, a transistor and a PN junction diode can be used as the switching element. However, when a transistor is used as the switching element, it is preferable that the transistor operates in a linear region. Furthermore, when the scanning line driver circuit 1802 is composed of only N-channel transistors, it is preferable to use an N-channel transistor as the switching element. Furthermore, when the scanning line driver circuit 1802 is composed of only P-channel transistors, it is preferable to use a P-channel transistor as the switching element.

Note that the scanning line driver circuit 1802 and the pixel portion 1804 are formed on an insulating substrate 1805, and the signal line driver circuit 1801 is not formed on the insulating substrate 1805. The signal line driver circuit 1801 is formed on a single crystal substrate, an SOI substrate, or an insulating substrate other than the insulating substrate 1805. The signal line driver circuit 1801 is connected to signal lines S1 to Sm via a printed board such as an FPC. However, the signal line driver circuit 1801 may be formed on the insulating substrate 1805, or a circuit constituting a part of the function of the signal line driver circuit 1801 may be formed on the insulating substrate 1805.

The wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (T
a), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd)
, chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (C
u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn)
, niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), and oxygen (O), or a compound or alloy material containing one or more elements selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
Aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium (
It is preferable that the wiring, electrodes, conductive layers, conductive films, terminals, etc. are formed of a material that is a combination of these compounds. It is preferable that the wiring, electrodes, conductive layers, conductive films, terminals, etc. are formed of a compound (silicide) of one or more elements selected from the above group and silicon (e.g., aluminum silicon, molybdenum silicon, nickel silicide, etc.), or a compound of one or more elements selected from the above group and nitrogen (e.g., titanium nitride, tantalum nitride, molybdenum nitride, etc.).

Silicon (Si) can contain n-type impurities (such as phosphorus) or p-type impurities (such as boron).
When silicon contains impurities, its electrical conductivity can be improved. Alternatively, it can behave similarly to a normal conductor. Therefore, it can be easily used as wiring, electrodes, etc.

Silicon having various crystallinity such as single crystal, polycrystalline (polysilicon), and microcrystalline (microcrystalline silicon) can be used.
It is also possible to use single crystal silicon or polycrystalline silicon. By using single crystal silicon or polycrystalline silicon, it is possible to reduce the resistance of wiring, electrodes, conductive layers, conductive films, terminals, etc. By using amorphous silicon or microcrystalline silicon, it is possible to form wiring, etc. in a simple process.

Incidentally, aluminum or silver has high electrical conductivity, and therefore can reduce signal delay.
Furthermore, since it is easy to etch, it is easy to pattern and can be subjected to fine processing.

In addition, copper has high conductivity, so it can reduce signal delay. When using copper,
In order to improve adhesion, a laminated structure is preferable.

Molybdenum or titanium is preferable because it has advantages such as not causing defects even when in contact with an oxide semiconductor (ITO, IZO, etc.) or silicon, being easy to etch, and having high heat resistance.

Tungsten is preferable because it has advantages such as high heat resistance.

Neodymium is desirable because it has the advantage of being highly heat resistant. In particular, when neodymium is alloyed with aluminum, the heat resistance is improved and aluminum is less likely to develop hillocks.

Silicon is preferable because it has advantages such as being able to be formed simultaneously with a semiconductor layer of a transistor and having high heat resistance.

In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
Since the thin film transistor (nO) has a light-transmitting property, it can be used in a portion through which light passes, for example, as a pixel electrode or a common electrode.

The wiring, electrodes, conductive layers, conductive films, terminals, etc. may have a single-layer structure or a multi-layer structure. By forming the wiring, electrodes, conductive layers, conductive films, terminals, etc. into a single-layer structure, the manufacturing process can be simplified, the number of process days can be reduced, and the cost can be reduced. Alternatively, by forming the wiring, electrodes, etc. into a multi-layer structure, the merits of each material can be utilized while reducing the demerits, and good performance of the wiring, electrodes, etc. can be formed. For example, by including a low resistance material (aluminum, etc.) in the multi-layer structure, the resistance of the wiring can be reduced. In addition, by forming a laminated structure in which a low heat-resistant material is sandwiched between high heat-resistant materials, the heat resistance of the wiring, electrodes, etc. can be increased while utilizing the merits of the low heat-resistant material. For example, it is desirable to form a laminated structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, etc.

Furthermore, when wiring, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, etc. may penetrate into the material of the other wiring, electrode, etc., changing the properties and making it impossible to fulfill its original purpose. Alternatively, a high resistance portion may be formed. Alternatively, problems may occur during manufacturing, making it impossible to manufacture normally. In such cases, it is advisable to sandwich or cover the highly reactive material in the laminated structure with a less reactive material. For example, when connecting ITO and aluminum, the ITO
It is preferable to sandwich a titanium, molybdenum, or neodymium alloy between the aluminum and the copper.
In addition, when connecting silicon and aluminum, between ITO and aluminum,
It is preferable to use titanium, molybdenum, or neodymium alloys.

The term "wiring" refers to an arrangement of conductors. The wiring may extend linearly or may be arranged short and not extend. Therefore, electrodes are included in the wiring.

The above-described wiring and electrodes can also be applied to other display devices, shift registers, and pixels.

The signal line driver circuit 1801 inputs a voltage or current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Furthermore, the video signal may be inverted between positive and negative polarities for each frame (frame inversion driving), may be inverted between positive and negative polarities for each row (gate line inversion driving), or may be inverted between positive and negative polarities for each column (gate line inversion driving).
The negative polarity may be inverted (source line inversion driving), or the positive and negative polarities may be inverted for each row and column (dot line inversion driving). Furthermore, the video signals may be input to the signal lines S1 to Sm in a dot sequential driving manner or in a line sequential driving manner. Furthermore, the signal line driver circuit 1801 supplies not only the video signals but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm.
It is desirable to input a constant voltage such as a precharge voltage every gate selection period and every frame.

The scanning line driver circuit 1802 inputs signals to the scanning lines G1 to Gn.
The scanning line driving circuit 180 selects (hereinafter, also referred to as scanning) the first row in order.
2 selects a plurality of pixels 1803 connected to a selected scanning line. Here, a period during which one scanning line is selected is called one gate selection period, and a period during which the scanning line is not selected is called a non-selection period. Furthermore, a signal output from the scanning line driver circuit 1802 to a scanning line is called a scanning signal. Furthermore, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

When the pixel 1803 is selected, a video signal is input from the signal line driver circuit 1801 to the pixel 1803 via a signal line. Furthermore, when the pixel 1803 is not selected, the pixel 1803 receives the video signal (potential corresponding to the video signal) input during the selection period.
holds.

Although not shown, a plurality of potentials and a plurality of signals are supplied to the signal line driver circuit 1801 and the scanning line driver circuit 1802 .

Next, the operation of the display device shown in Fig. 18 will be described with reference to the timing chart of Fig. 19. Furthermore, Fig. 19 shows one frame period corresponding to the period for displaying one screen's worth of image. However, although there are no particular limitations on one frame period, it is preferable that it be at least 1/60 seconds or less so that a person viewing the image does not perceive flicker.

In the timing chart of FIG. 19, the first scanning line G1, the i-th scanning line Gi,
This shows the timing when the +1th row scanning line Gi+1 and the nth row scanning line Gn are selected.

In FIG. 19, for example, the scanning line Gi in the i-th row is selected, and a plurality of pixels 1803 connected to the scanning line Gi are selected. Then, the plurality of pixels 1803 connected to the scanning line Gi each input a video signal and hold a potential corresponding to the video signal. After that, the scanning line Gi in the i-th row is deselected, the scanning line Gi+1 in the i+1-th row is selected, and a plurality of pixels 1803 connected to the scanning line Gi+1 are selected. Then, the plurality of pixels 1803 connected to the scanning line Gi+1 each input a video signal and hold a potential corresponding to the video signal. In this way, during one frame period, the scanning lines G1 to Gn are selected in order, and the pixels 1803 connected to each scanning line are also selected in order. Then, the plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal.

From the above, the display device of FIG. 18 can input video signals independently to all pixels, and therefore can fully function as an active matrix display device.

Furthermore, since the display device in FIG. 18 uses the shift register of this embodiment mode as the scanning line driver circuit 1802, a threshold shift of a transistor can be suppressed. The display device in FIG. 18 can have a longer life. The display device in FIG. 18 can have an improved driving capability. The display device in FIG. 18 can suppress malfunction. The display device in FIG. 18 can be manufactured through a simplified process.

Furthermore, in the display device of FIG. 18, the signal line driver circuit 1801, which requires high-speed operation, and the scanning line driver circuit 1802 and pixels 1803 are formed on separate substrates.
Amorphous silicon can be used for the semiconductor layers of the transistors in the pixel 1802 and the pixel 1803. This allows simplification of the manufacturing process and reduction in manufacturing costs. Furthermore, the display device in FIG. 18 allows an improvement in yield. Furthermore, the display device of this embodiment mode can be enlarged. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon for the semiconductor layers of the transistors.

In addition, when the signal line driver circuit 1801, the scanning line driver circuit 1802, and the pixels 1803 are formed over the same substrate, polysilicon or polycrystalline silicon may be used for semiconductor layers of the transistors included in the scanning line driver circuit 1802 and the transistors included in the pixels 1803.

As shown in FIG. 18, if pixels can be selected and video signals can be written to the pixels independently, the number and arrangement of the driving circuits are not limited to those shown in FIG.

For example, as shown in FIG. 20, the scanning lines G1 to Gn are connected to a first scanning line driving circuit 2002.
The first scanning line driver circuit 2002a and the second scanning line driver circuit 2002b may be the same as the scanning line driver circuit 1 shown in FIG.
The first scanning line driver circuit 2002a and the second scanning line driver circuit 2002b may be called a first driver circuit and a second driver circuit, respectively.

The display device of FIG. 20 includes a first scanning line driving circuit 2002a and a second scanning line driving circuit 200
18, the display device of FIG. 20 has a load (wiring resistance of the scanning lines and parasitic capacitance of the scanning lines) of the first scanning line driving circuit 2002a and the load of the second scanning line driving circuit 2002b.
20, the load of the first scanning line driving circuit 2002a and the load of the second scanning line driving circuit 2002b are reduced, so that the delay and rounding of the signals input to the scanning lines G1 to Gn can be reduced. Furthermore, in the display device of FIG. 20, the load of the first scanning line driving circuit 2002a and the load of the second scanning line driving circuit 2002b are reduced, so that the scanning lines G1 to Gn can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the resolution of the panel. Furthermore, the merit of the display device of FIG. 20 is even more effective when amorphous silicon is used for the semiconductor layers of the transistors of the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. Note that the same reference numerals are used for the parts common to the configuration of FIG. 18, and the description thereof will be omitted.

As another example, Fig. 8 shows a display device capable of writing video signals to pixels at high speed. In the display device of Fig. 8, video signals are input to pixels 1803 in odd-numbered rows from signal lines in odd-numbered columns, and video signals are input to pixels 1803 in even-numbered rows from signal lines in even-numbered columns. Furthermore, in the display device of Fig. 8, odd-numbered scanning lines among the scanning lines G1 to Gn are scanned by a first scanning line driver circuit 802a, and even-numbered scanning lines among the scanning lines G1 to Gn are scanned by a second scanning line driver circuit 802b. Furthermore, the first scanning line driver circuit 802
The start signal input to the first scanning line driving circuit 802b is delayed by ¼ period of the clock signal from the start signal input to the first scanning line driving circuit 802a.

The display device of FIG. 8 can perform dot inversion driving by simply inputting a positive video signal and a negative video signal to each signal line for each column during one frame period.
The display device in FIG. 8 can perform frame inversion driving by inverting the polarity of the video signal input to each signal line every frame period.

The operation of the display device of Fig. 8 will be described with reference to the timing chart of Fig. 9. The timing chart of Fig. 9 shows the timings at which the 1st row scanning line G1, the (i-1)th row scanning line Gi-1, the i-th row scanning line Gi, the (i+1)th row scanning line Gi+1, and the nth row scanning line Gn are selected. Furthermore, in the timing chart of Fig. 9, one selection period is divided into selection period a and selection period b. Furthermore, in the timing chart of Fig. 9, the timings at which the 1st row scanning line G1, the (i-1)th row scanning line Gi-1, the (i+1)th row scanning line Gi+1, and the nth row scanning line Gn are selected are shown.
A case where the display device performs dot inversion driving and frame inversion driving will be described.

In FIG. 9, for example, the selection period a of the i-th row scanning line Gi is
The selection period Tb of the scanning line Gi of the i-th row overlaps with the selection period a of the scanning line Gi+1 of the i+1th row.
The same video signal as that input to pixel 1803 in the j+1th column is input to pixel 1804 in the i-th row and j-th column.
803. Furthermore, in the selection period b, a video signal similar to that input to the pixel 1803 in the i-th row and j-th column is input to the pixel 1803 in the i+1th row and j+1th column. Note that the video signal input to the pixel 1803 in the selection period b is the original video signal, and the video signal input to the pixel 1803 in the selection period a is a video signal for precharging the pixel 1803. Therefore, each pixel 1803 receives i
After precharging with a video signal input to the pixel 1803 in the -1th row and j+1th column, the original video signal (in the ith row and jth column) is input during a selection period b.

As described above, the display device of FIG. 8 can easily realize a larger display or higher resolution because video signals can be written to the pixels 1803 at high speed. Furthermore, in the display device of FIG. 8, video signals of the same polarity are input to each signal line during one frame period.
The charge and discharge of each signal line is small, and low power consumption can be realized. Furthermore, in the display device of FIG. 8, the load of the IC for supplying the video signal is significantly reduced, so that heat generation and power consumption of the IC can be reduced. Furthermore, in the display device of FIG. 8, the drive frequency of the first scanning line driver circuit 802a and the second scanning line driver circuit 802b can be reduced by about half.

Note that the display device of this embodiment mode can be driven by various methods depending on the structure and driving method of the pixel 1803. For example, in one frame period, the scan line driver circuit may scan the scan line a plurality of times.

8, 18, and 20 may have additional wirings or the like added depending on the configuration of the pixel 1803. For example, a power supply line, a capacitance line, and a new scan line that are kept at a constant potential may be added. However, when a new scan line is added, a scan line driver circuit to which the shift register of this embodiment mode is applied may be newly added. As another example, a dummy scan line, a signal line, a power supply line, or a capacitance line may be disposed in the pixel portion.

In this embodiment, various figures have been used to describe the present invention, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, in the figures described so far,
By combining different parts, more figures can be constructed.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

In addition, this embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment. Or, they can be combined.

(Embodiment 2)
This embodiment mode will describe a flip-flop different from that in Embodiment Mode 1, a driver circuit having the flip-flop, and a structure and a driving method of a display device having the driver circuit. Note that the same components as those in Embodiment Mode 1 are denoted by the same reference characters, and detailed description of the same components or components having similar functions will be omitted.

The flip-flop of this embodiment can have the same structure as that of the flip-flop of the first embodiment. However, the timing of driving the flip-flop is different from that of the first embodiment.
Therefore, in this embodiment, the description of the configuration of the flip-flop is omitted.

The drive timing of this embodiment will be described in the case where it is applied to the flip-flop of FIG. 1. The drive timing of this embodiment will be described in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), and 7(B).
The drive timing of this embodiment mode can be freely combined with the drive timing of the flip-flop of FIG. 7C, FIG. 21A, FIG. 21B, or FIG. 21C. The drive timing of this embodiment mode can be freely combined with the drive timing of the first embodiment mode.

Next, the operation of the flip-flop of this embodiment mode will be described with reference to the flip-flop of FIG. 1 and the timing chart of FIG. 31. Furthermore, the timing chart of FIG. 31 will be described by dividing it into a selection period and a non-selection period. Furthermore, the non-selection period includes a first non-selection period,
The period will be explained by dividing it into a second non-selection period, a set period a, a set period b, and a reset period.
Further, the selection period will be described by dividing it into a selection period a and a selection period b. Furthermore, in the non-selection period, the operation period excluding the set period a, the set period b, the selection period a, the selection period b, and the reset period is a repetition of a first non-selection period and a second non-selection period.

31, a signal 3121, a signal 3125, a signal 3126, a potential 3141, a potential 3142, a signal 3122, and a signal 3123 respectively represent a signal input to the first wiring 121, a signal input to the fifth wiring 125, a signal input to the sixth wiring 126, a potential of the node 141, a potential of the node 142, a signal input to the second wiring 122, a potential of the third wiring 123, and a potential of the third wiring 124.
23.

Note that signals 3121, 3125, 3126, potential 3141, potential 3142, signal 3122, and signal 3123 correspond to signals 221, 225, 226, potential 241, potential 242, signal 222, and signal 223 shown in FIG. 2, and have similar characteristics.

Note that the flip-flop of this embodiment basically operates in the same manner as the flip-flop described in the embodiment 1. However, the flip-flop of this embodiment differs from the flip-flop of the embodiment 1 in that the timing at which an H signal is input to the first wiring 121 is delayed by ¼ cycle of the clock signal.

Note that the flip-flop of this embodiment operates in the first non-selection period and the second non-selection period in the same manner as the flip-flop described in embodiment 1 operates in the first non-selection period and the second non-selection period. Furthermore, the flip-flop of this embodiment operates in the set period a in the same manner as the flip-flop described in embodiment 1 operates in the reset period. Furthermore, the flip-flop of this embodiment operates in the selection period a and the selection period b in the same manner as the flip-flop described in embodiment 1 operates in the selection period. However, the flip-flop of this embodiment differs from the flip-flop of embodiment 1 in that an H signal is input to the first wiring 121 in the selection period a. However, even if an H signal is input to the first wiring 121 in the selection period a, the fifth transistor 105 is off, so there is almost no effect on the operation of this embodiment. Therefore, the set period a, the set period b, the selection period a, the selection period b, the reset period, the first non-selection period, and the second non-selection period are not affected by the set period a, the set period b, the selection period a, the selection period b, the reset period, the first non-selection period, and the second non-selection period.
A detailed description of the flip-flop in this embodiment during the non-selection period will be omitted.

Note that the flip-flop of this embodiment mode can reduce the layout area, similarly to the flip-flop described in embodiment mode 1. Furthermore, the flip-flop of this embodiment mode can suppress a threshold voltage shift of a transistor. Furthermore, the flip-flop of this embodiment mode can simplify the process.

32 to the flip-flop of this embodiment mode, the fall time of the output signal of the flip-flop of this embodiment mode can be significantly shortened because an L signal can be input to the third wiring 123 through the first transistor 101 by shifting the timing at which the signal 3122 (reset signal) becomes H level.

Next, a configuration and a driving method of the shift register having the flip-flop of the above-described embodiment mode will be described.

A configuration of a shift register in this embodiment mode will be described with reference to Fig. 33. The shift register in Fig. 33 has n flip-flops (flip-flops 3301_1 to 3301_n).

The connection relationship of the shift register in Fig. 33 will be described. The shift register in Fig. 33 includes a flip-flop 3301_i (any one of the flip-flops 3301_1 to 3301_n) in the i-th stage, and a flip-flop 3301_i in the 4N-3-th stage (N is a natural number of 1 or more).
The flip-flops 3301_4N-1 in the 1_4N-3 and 4N-1-th stages are connected to the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, the eleventh wiring 3321_i-1, the eleventh wiring 3321_i ...
Further, the flip-flop 3301_4N in the 4N-2th stage is connected to the
The flip-flop 3301_4N in the −2th and 4Nth stages is connected to the third wiring 3313, the fifth wiring 3315, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, the eleventh wiring 3319, the eighth wiring 3320, the eighth wiring 3321, the eighth wiring 3322, the eighth wiring 3323, the eighth wiring 3324, the eighth wiring 3325, the eighth wiring 3326, the eighth wiring 3327, the eighth wiring 3328, the eighth wiring 3329, the eighth wiring 3330, the eighth wiring 3331, the eighth wiring 3332, the eighth wiring 3333, the eighth wiring 3334, the eighth wiring 3335, the eighth wiring 3336,
The flip-flop 3301_1 in the first stage is connected to the first wiring 3111, the eleventh wiring 3321_i, and the eleventh wiring 3321_i+2.
A second wiring 3312, a fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317,
The n-1th flip-flop 3101_n-1 is connected to the eighth wiring 3318, the eleventh wiring 3321_1, and the eleventh wiring 3321_3.
A fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318,
The tenth wiring 3320, the eleventh wiring 3321_n-2, and the eleventh wiring 3321_n-1
Furthermore, the n-th flip-flop 3301_n is connected to the third wiring 3313
, a fifth wiring 3315, a sixth wiring 3316, a seventh wiring 3317, and an eighth wiring 3318.
, the ninth wiring 3319, the eleventh wiring 3321_n-1, and the eleventh wiring 3321_n.

The first wiring 3311 is connected to the first wiring 121 shown in FIG. 1 of the flip-flop 3301_1. The second wiring 3312 is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N-3, and is connected to the sixth wiring 126 shown in FIG. 1 in the flip-flop 3301_4N-1. The third wiring 3313 is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N-3.
1 in the flip-flop 3301_4N. The fourth wiring 3314 is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N.
301_4N-3 is connected to the sixth wiring 126 shown in FIG.
1 in the flip-flop 3301_4N-1. The fifth wiring 3315 is connected to the sixth wiring 126 shown in FIG. 1 in the flip-flop 3301_4N-2, and is connected to the fifth wiring 125 shown in FIG. 1 in the flip-flop 3301_4N.
1 in all the flip-flops. The seventh wiring 3317 is connected to the eighth wiring 128 in all the flip-flops.
The eighth wiring 3318 is connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. 1 in all the flip-flops.
9 is connected to the second wiring 122 of the flip-flop 3301_n shown in FIG.
The wiring 3120 of the flip-flop 3301_n-1 corresponds to the second wiring 122 shown in FIG.
The eleventh wiring 3321_i is connected to the flip-flop 3301_i-2 shown in FIG.
1 of the flip-flop 3301_i, and the third wiring 123 of the flip-flop 3301_i shown in FIG.
, and the first wiring 121 of the flip-flop 3301_i+1 shown in FIG.
However, the eleventh wiring 3321_1 is the third wiring of the flip-flop 3301_1 shown in FIG.
1 of the flip-flop 3301_2 and the first wiring 121 of the flip-flop 3301_3 shown in FIG. 1. Furthermore, the eleventh wiring 3321_2 is connected to the third wiring 123 of the flip-flop 3301_2 shown in FIG. 1 and the first wiring 121 of the flip-flop 3301_3 shown in FIG.
1. Furthermore, the eleventh wiring 3321_n is connected to the flip-flop 3301_n
1. The third wiring 123 shown in FIG.

A potential of V1 is supplied to each of the sixth wiring 3316 and the seventh wiring 3317.
A potential of V2 is supplied to the eighth wiring 3318.

The first wiring 3311, the second wiring 3312, the third wiring 3314, and the fifth wiring 33
Signals are input to the first wiring 3311, the ninth wiring 3319, and the tenth wiring 3320. The signal input to the first wiring 3311 is a start signal, the signal input to the second wiring 3312 is a first clock signal, the signal input to the third wiring 3313 is a second clock signal, the signal input to the fourth wiring 3314 is a third clock signal,
The signal input to the fifth wiring 3315 is the fourth clock signal, and the signal input to the ninth wiring 3319 is the fourth clock signal.
The signal input to the 10th wiring 3320 is a first reset signal, and the signal input to the 10th wiring 3320 is a second reset signal.
Signals input to the first wiring 3314, the fifth wiring 3315, the ninth wiring 3319, and the tenth wiring 3320 are digital signals whose H signal potential is V1 and whose L signal potential is V2.

Note that various signals, currents, or voltages may be input to each of the first wiring 3311 to the tenth wiring 3320 .

Note that signals are output from the eleventh wirings 3321_1 to 3321_n.
For example, the signal output from the eleventh wiring 3321_i is
Further, the signal output from the eleventh wiring 3321_i is also an input signal to the flip-flop 3301_i+1 and a reset signal to the flip-flop 3301_i-2.

Next, the operation of the shift register shown in Fig. 33 will be described with reference to the timing charts of Fig. 35 and 36. Here, the timing chart of Fig. 35 is divided into a scanning period and a blanking period. The scanning period is a period from when the output of the selection signal from the eleventh wiring 3311_1 starts to when the output of the selection signal from the eleventh wiring 3311_n ends. The blanking period is a period from when the output of the selection signal from the eleventh wiring 3311_n ends to when the output of the selection signal from the eleventh wiring 3311_1 starts.

In FIG. 35, a signal 3511 is input to the first wiring 3311, and a signal 3512 is input to the second wiring 33
A signal 3512 input to the terminal 12, a signal 3513 input to the third wiring 3313, a signal 3514 input to the fourth wiring 3314, and a signal 3515 input to the fifth wiring 3315.
36 shows a signal 3519 input to the ninth wiring 3319, a signal 3520 input to the tenth wiring 3320, a signal 3521_1 output to the eleventh wiring 3321_1, and a signal 3521_n output to the eleventh wiring 3321_n. Furthermore, in FIG. 36, a signal 3611 input to the first wiring 3311, a signal 3621_1 output to the eleventh wiring 3321_1, a signal 3621_i-1 output to the eleventh wiring 3321_i-1, a signal 3621_i output to the eleventh wiring 3321_i, a signal 3621_i+1
and a signal 3621_i+1 output to the eleventh wiring 3321_n.
21_n.

As shown in FIG. 36, for example, when the flip-flop 3301_i-1 is in the selection period a, an H signal is output from the eleventh wiring 3321_i-1.
The flip-flop 3301_i is in the set period a. After that, the flip-flop 3301_i-1 is in the selection period b, and the H signal is still output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i is in the selection period a. After that, the flip-flop 33
The flip-flop 3301_i-1 is in the reset period and an H signal is output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i is in the selection period b. That is, in the shift register of this embodiment, the H signal is output from the flip-flop 3301_i-1 in order, but the selection period b of the flip-flop 3301_i-1 and the selection period
i has a period that overlaps with the selection period a.

32 is applied to the flip-flop of this specification, the shift register may have a configuration as shown in FIG. 34. In the shift register of FIG. 34, for example, the wiring 122 of the flip-flop 3301_i in the i-th stage shown in FIG. 1 is connected to the eleventh wiring 33
1 of the flip-flop 3301_n-2 is connected to a twelfth wiring 3322 to which a third reset signal is input.
It should be noted that the same reference numerals are used for the parts common to FIG. 33 and the description thereof will be omitted.

Since the flip-flop of this embodiment is applied to the shift register of this embodiment, it is possible to suppress threshold shifts of transistors, extend the life, improve driving capability, suppress malfunctions, simplify the process, and the like.

The shift register of this embodiment can be freely combined with the shift register described in the embodiment 1. For example, the shift register of this embodiment can be implemented by using the shift register shown in FIG.
The shift register of this embodiment can be freely combined with the shift registers of Fig. 15 and Fig. 17. Specifically, in the shift register of this embodiment, a buffer may be connected to the eleventh wiring 3321_1 to the eleventh wiring 3321_n, a reset signal may be generated internally, or a dummy flip-flop may be disposed. Note that, as already described, the same reference numerals are used for the parts common to the first embodiment, and the description thereof will be omitted.

Next, a structure and a driving method of a display device having the shift register of the above-described embodiment mode will be described. Note that the display device of this embodiment mode only needs to have at least the flip-flop of this embodiment mode.

The structure of the display device of this embodiment will be described with reference to FIG. 16. In the display device of FIG. 16, scanning lines G1 to Gn are scanned by a scanning line driver circuit 1602.
In the display device of FIG. 6, video signals are input to the pixels 1803 in odd-numbered rows from signal lines in odd-numbered rows, and video signals are input to the pixels 1803 in even-numbered rows from signal lines in even-numbered rows.
The same reference numerals are used for the components common to those in the configuration of 8, and the description thereof will be omitted.

Note that the display device in FIG. 16 can perform the same operation as the display device in FIG. 8 with one scanning line driver circuit by applying the shift register of this embodiment mode to the scanning line driver circuit 1602. Therefore, the display device in FIG. 16 can write video signals to pixels at high speed. Furthermore, the display device in FIG. 16 can be enlarged or have high definition. Furthermore, the display device in FIG. 16 can reduce power consumption. Furthermore, the display device in FIG. 16 can suppress heat generation of an IC. Furthermore, the display device in FIG. 16 can reduce power consumption of an IC.

As shown in FIG. 22, the scanning lines G1 to Gn are connected to a first scanning line driving circuit 2202a.
The first scanning line driver circuit 2002a and the second scanning line driver circuit 2002b may be the same as the scanning line driver circuit 16 shown in FIG.
02, and scans the scanning lines G1 to Gn at the same timing. Furthermore, the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b may be called a first driver circuit and a second driver circuit, respectively.

The display device of FIG. 22 includes a first scanning line driver circuit 2202a and a second scanning line driver circuit 220
Even if a defect occurs in one of the scanning line driver circuits 2202a and 2202b, the other of the scanning line driver circuits 2202a and 2202b can scan the scanning lines G1 to Gn, so that redundancy can be provided. Furthermore, in the display device of FIG. 22, since the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b scan the scanning lines G1 to Gn, the load of the first scanning line driver circuit 2202a (wiring resistance of the scanning line and parasitic capacitance of the scanning line) and the load of the second scanning line driver circuit 2202b can be reduced by half compared to FIG. 18. Therefore, in the display device of FIG. 22, the load of the first scanning line driver circuit 2202a and the load of the second scanning line driver circuit 2202b are reduced, so that the delay and distortion of the signals (output signals of the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b) input to the scanning lines G1 to Gn can be reduced. Furthermore, in the display device of FIG. 22, the load of the first scanning line driver circuit 2202a and the load of the second scanning line driver circuit 2202b are reduced, so that the scanning lines G1 to Gn
Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or to increase the resolution of the panel. Furthermore, the display device in FIG. 22 has the advantage that, when amorphous silicon is used for the semiconductor layers of the transistors included in the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b,
It is more effective. Note that the same reference numerals are used for the components common to those in FIG.

In this embodiment, various figures have been used to describe the present invention, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, in the figures described so far,
By combining different parts, more figures can be constructed.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

In addition, this embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment. Or, they can be combined.

(Embodiment 3)
In this embodiment mode, a flip-flop different from those in Embodiment Mode 1 and Embodiment Mode 2, a driver circuit having the flip-flop, and a structure and a driving method of a display device having the driver circuit will be described. The flip-flop in this embodiment mode is characterized in that an output signal of the flip-flop and a transfer signal of the flip-flop are output from separate wirings by separate transistors. Note that the same reference symbols are used for components similar to those in Embodiment Mode 1 and Embodiment Mode 2, and detailed descriptions of the same parts or parts having similar functions will be omitted.

The basic structure of a flip-flop of this embodiment will be described with reference to FIG.
The flip-flop shown in FIG. 7 includes a first transistor 101, a second transistor 102,
The semiconductor device includes a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, a seventh transistor 107, an eighth transistor 108, and a ninth transistor 109. In this embodiment mode, the eighth transistor 108 and the ninth transistor 109 are N-channel transistors that are turned on when a voltage between a gate and a source (Vgs) exceeds a threshold voltage (Vth).

The flip-flop of FIG. 27 is the flip-flop of FIG. 1 with an eighth transistor 10
1 is added, the eighth and ninth transistors 109 are added, and therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 can be the same as those in FIG.

27 will be described. A first electrode (one of a source electrode and a drain electrode) of the first transistor 101 is connected to a fifth wiring 125, and a second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to a third wiring 126.
23. A first electrode of the second transistor 102 is connected to a fourth wiring 124, and a second electrode of the second transistor 102 is connected to a third wiring 123. A first electrode of the third transistor 103 is connected to a sixth wiring 126, and a second electrode of the third transistor 103 is connected to a sixth wiring 127.
The second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate electrode of the third transistor 103 is connected to the seventh wiring 127.
The first electrode of the fifth transistor 105 is connected to the ninth wiring 129, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 101.
A first electrode of the sixth transistor 106 is connected to a tenth wiring 130, a second electrode of the sixth transistor 106 is connected to a gate electrode of the first transistor 101, and a gate electrode of the fifth transistor 105 is connected to the first wiring 121. A first electrode of the sixth transistor 106 is connected to a tenth wiring 130, and a second electrode of the sixth transistor 106 is connected to a gate electrode of the first transistor 101.
A first electrode of the seventh transistor 107 is connected to an eleventh wiring 131, and a second electrode of the seventh transistor 107 is connected to a gate electrode of the first transistor 102.
The gate electrode of the seventh transistor 107 is connected to the second wiring 122.
A first electrode of the eighth transistor 108 is connected to a thirteenth wiring 133, a second electrode of the eighth transistor 108 is connected to a twelfth wiring, and a gate electrode of the eighth transistor 108 is connected to a gate electrode of the first transistor 101. A first electrode of the ninth transistor 109 is connected to a fourteenth wiring 134, and a second electrode of the ninth transistor 109 is connected to a fourteenth wiring 135.
A second electrode of the ninth transistor 109 is connected to a twelfth wiring 132 , and a gate electrode of the ninth transistor 109 is connected to a gate electrode of the second transistor 102 .

The twelfth wiring 132 and the third wiring 133 may be called a sixth signal line and a seventh signal line, respectively. Furthermore, the fourteenth wiring may be called a seventh power supply line.

Note that V2 is supplied to the 14th wiring 134.

A signal is input to the thirteenth wiring 133. The signal input to the third wiring is the same as that input to the fifth wiring 134.
A signal similar to that input to the wiring 125 can be used.

Note that a signal is output from the twelfth wiring 132. Furthermore, as described in the first embodiment, a signal is also output from the third wiring 123.

Note that a signal input or a potential supplied to each of the first wiring 121, the second wiring 122, the fourth wiring 124, the fifth wiring 125, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 is the same as that shown in FIG.
is the same as:

The flip-flop of FIG. 27 is the flip-flop of FIG. 1 with an eighth transistor 10
The case where the eighth and ninth transistors 109 are added is shown in FIG.
An eighth transistor 108 and a ninth transistor 109 may be added to the flip-flops shown in Figures 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), and 21(C).

Next, the operation of the flip-flop shown in Fig. 1 will be described with reference to the timing chart of Fig. 28. Furthermore, parts common to the timing chart of Fig. 2 are denoted by the same reference numerals and description thereof will be omitted.

Note that a signal 232 indicates a signal output from the twelfth wiring 132. Furthermore, the signals 221, 225, 226, the potential 241, the potential 242, the signal 222, and the signal 22
3 is the same as in FIG. 2 except that the signal 221, the signal 225, the signal 226, the potential 241,
As the potential 242, the signal 222, and the signal 223, the same ones as those in FIG. 6, FIG. 31, or FIG. 32 can be used.

As already described, this embodiment mode is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. That is, the flip-flop in FIG. 27 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and outputs a signal from the eighth transistor 108.
A signal is output from the twelfth wiring 132 by the eighth and ninth transistors.
The second transistor 108 and the ninth transistor are connected in the same manner as the first transistor 101 and the second transistor 102. Therefore, as shown in FIG.
The signal output from the third wiring 123 (signal 223) is
) is a waveform similar to that of the signal 232. Here, the signal 232 is an output signal of the flip-flop, and the signal 223 is a transfer signal of the flip-flop. However, the signal 223 may be an output signal of the flip-flop, and the signal 232 may be a transfer signal of the flip-flop.

Note that the eighth transistor 108 and the ninth transistor 109 have functions similar to those of the first transistor 101 and the second transistor 102. Furthermore, the eighth transistor 108 and the ninth transistor 109 may be referred to as a buffer portion.

27 can prevent malfunction even if a large load is connected to the third wiring 132 and a delay or distortion occurs in the signal 232. This is because the flip-flop in FIG 27 outputs the output signal of the flip-flop and the transfer signal of the flip-flop from separate wirings by separate transistors, so that delay or distortion of the output signal does not affect the operation of the flip-flop.

Furthermore, like the flip-flops shown in Embodiments 1 and 2, the flip-flop in FIG. 27 can provide advantages such as a reduced layout area, suppression of a threshold shift of a transistor, simplification of the process, and fabrication of a semiconductor device such as a large display device and a semiconductor device such as a long-life display panel.

Note that the operation timing described in Embodiment 2 can also be applied to the flip-flop of this embodiment mode.

A structure and a driving method of the shift register having the flip-flop of the above-described embodiment mode will be described.

A configuration of a shift register in this embodiment mode will be described with reference to Fig. 29. The shift register in Fig. 29 has n flip-flops (flip-flops 2901_1 to 2901_n).

The connection relationship of the flip-flop in Fig. 29 will be described. The flip-flop in Fig. 29 has the following:
The flip-flop 2901_i in the i-th stage (flip-flops 2901_1 to 2901_n
Any one of the second wiring 2912, the third wiring 2913, and the fourth wiring 2914
, a fifth wiring 2915, a sixth wiring 2916, an eighth wiring 2918_i-1, an eighth wiring 2918_i, an eighth wiring 2918_i+1, and a ninth wiring 2919_i.
However, the flip-flop 2901_1 in the first stage is connected to the first wiring 2911 and the second wiring 2912.
912, a third wiring 2913, a fourth wiring 2914, a fifth wiring 2915, and a sixth wiring 2
916, an eighth wiring 2918_1, an eighth wiring 2918_2, and a ninth wiring 2919_1. Furthermore, the n-th flip-flop 2901_n is connected to the second wiring 2912,
A third wiring 2913, a fourth wiring 2914, a fifth wiring 2915, a sixth wiring 2916,
The seventh wiring 2917, the eighth wiring 2918_n-1, the eighth wiring 2918_n, and the ninth wiring 2919_n are connected.

The first wiring 2911 corresponds to the first wiring 121 shown in FIG.
The second wiring 2912 is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the odd-numbered flip-flops, and is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the even-numbered flip-flops.
27. The third wiring 2913 is connected to the sixth wiring 126 shown in FIG. 27 in the odd-numbered flip-flops, and is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the even-numbered flip-flops. The fourth wiring 2914 is
The flip-flops in all stages are connected to the seventh wiring 127 shown in FIG.
27 in all the flip-flops. The sixth wiring 2916 is connected to the fourth wiring 124, the ninth wiring 129, the twenty-ninth wiring 130, and the eleventh wiring 131 shown in FIG. 27 in all the flip-flops.
27 of the flip-flop 2901_i-1, the third wiring 123 of the flip-flop 2901_i, and the flip-flop 2901i
27 of the flip-flop 2901_1 and the first wiring 121 of the flip-flop 2901_2 shown in FIG. 27. The eighth wiring 2918_1 is connected to the third wiring 123 of the flip-flop 2901_1 shown in FIG. 27 and the first wiring 121 of the flip-flop 2901_2 shown in FIG. 27.
The ninth wiring 2901_n is connected to the second wiring 122 of the flip-flop 2901_n-1 shown in FIG. 27 and the third wiring 123 of the flip-flop 2901_n shown in FIG.
The ninth wiring 2919_1 to the ninth wiring 2919_n are connected to the twelfth wiring 132 shown in FIG. 27 of the flip-flops 2901_1 to 2901_n, respectively.

Note that the flip-flops 2901_1 to 2901_n and the first wiring 29
11, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, and the fifth wiring 29
15, the fifth wiring 2916, and the seventh wiring 2907 correspond to the flip-flops 1001_1 to 1001_n, the first wiring 1011, the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the fifth wiring 1016, and the seventh wiring 1007 shown in FIG. 10, respectively, and are supplied with similar signals or potentials.

Next, the operation of the shift register shown in FIG. 29 will be described with reference to the timing chart of FIG.

In FIG. 30, a signal 3011 is input to the first wiring 2911, and
A signal 3018_1 output to the eighth wiring 2918_i.
i, a signal 3018_i+1 output to the eighth wiring 2918_i+1,
A signal 3018_n output to the ninth wiring 2919_1, and a signal 301
9_1, a signal 3019_i output to the ninth wiring 2918_i,
2A shows a signal 3019_i+1 output to the i+1 wiring and a signal 3018_n output to the ninth wiring 2919_n.

As shown in FIG. 30, for example, when the flip-flop 2901_i is in the selected period,
An H signal is output from the first wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i+1 is in the set period.
The flip-flop 2901_i+1 is in a reset period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i+1 is in a selected period. After that, the flip-flop 2901_i is in a first unselected period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i.
The eighth wiring 2918_i and the ninth wiring 2919_i are in a floating state and the potential is maintained at an L level. At this time, the flip-flop 2901_i+1 is in a reset period. After that, the flip-flop 2901_i is in a second non-selection period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i+1
In this manner, the flip-flop 2901_i repeats the first non-selection period and the second non-selection period until the next set period.

From the above, the shift register in Fig. 29 can output a transfer signal from the eighth wiring 2918_1 to the eighth wiring 2918_n in order. Furthermore, the shift register in Fig. 29 can output a selection signal from the ninth wiring 2919_1 to the ninth wiring 2919_n in order. In other words, the shift register in Fig. 29 can scan the ninth wirings 2919_1 to 2919_n. Therefore, the shift register in Fig. 29 can fully obtain the function as a shift register.

Further, the shift register in FIG. 29 includes ninth wirings 2919_1 to ninth wirings 2919_n.
Even if a large load (such as a resistor and a capacitor) is connected to the ninth wiring 2919_1 to the ninth wiring 2919_2, the shift register in FIG.
29_n is shorted to the power supply line or signal line, normal operation can be continued. Therefore, the shift register in Fig. 29 can improve the driving capability because the shift register in Fig. 29 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

Furthermore, by applying the flip-flop described in this embodiment to the shift register of FIG. 29, the layout area can be reduced, the threshold shift of the transistor can be suppressed, the process can be simplified,
This provides advantages such as the manufacture of semiconductor devices such as large-sized display devices and semiconductor devices such as long-life display panels.

Note that the configuration is not limited to that shown in FIG. 29 as long as it performs the same operation as that shown in FIG. 29. For example,
By freely combining with the shift registers in FIGS. 13, 14, 15, and 17, the same advantages as those in FIGS. 13, 14, 15, and 17 can be obtained.

The structure and driving method of a display device having the shift register of this embodiment mode will be described below. Note that the display device of this embodiment mode only needs to have at least the flip-flop of this embodiment mode.

As the display device of this embodiment, the display devices of FIG. 8, FIG. 18, FIG. 16, FIG. 20, and FIG. 22 can be used. Therefore, if the shift register of this embodiment is applied as a scanning line driving circuit, the layout area of the display device of this embodiment can be reduced. Furthermore, the display device of this embodiment can suppress the threshold shift of the transistor. Furthermore, the display device of this embodiment can simplify the process. Furthermore, the display device of this embodiment can be enlarged or highly fine. Furthermore, the display device of this embodiment can be extended in life. In particular, if the shift register of this embodiment is applied as a scanning line driving circuit to the display devices of FIG. 8, FIG. 16, and FIG. 22, the display device can be enlarged or highly fine. Furthermore, the display device of FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can reduce power consumption. Furthermore, the display device of FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can suppress heat generation of IC. Furthermore, the display device of FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can reduce I
It is possible to reduce the power consumption of C.

In this embodiment, various figures have been used for the description, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, by combining each part of the figures described so far with another part, even more figures can be configured.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

This embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts, etc. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it.

(Embodiment 4)
In this embodiment mode, a case where a P-channel transistor is used as a transistor constituting a flip-flop in this specification will be described. Furthermore, a structure and a driving method of a driver circuit having the flip-flop and a display device having the driver circuit will be described.

The flip-flop of this embodiment mode will be described with reference to the case where the polarity of the transistor included in the flip-flop of FIG. 1 is a P-channel type.
(C), FIG. 4(D), FIG. 5(A), FIG. 5(B), FIG. 5(C), FIG. 5(D), FIG. 7(A),
The polarity of the transistor included in the flip-flop shown in Fig. 7B, Fig. 7C, Fig. 21A, Fig. 21B, Fig. 21C, or Fig. 27 can be a P-channel type. Furthermore, the flip-flop of this embodiment mode can be freely combined with the description of Embodiment Modes 1 to 3.

The basic structure of a flip-flop of this embodiment will be described with reference to FIG.
The flip-flop shown in FIG. 3 includes a first transistor 2301, a second transistor 230
2, a third transistor 2303, a fourth transistor 2304, and a fifth transistor 2
In this embodiment, the semiconductor device includes a first transistor 2301, a second transistor 2302, a third transistor 2303, a fourth transistor 2304, a fifth transistor 2305, a sixth transistor 2306, and a seventh transistor 2307.
The first transistor 2306 and the seventh transistor 2307 are P-channel transistors, and the absolute value of the gate-source voltage (|Vgs|) is equal to or larger than the absolute value of the threshold voltage (|Vt
h|) (when Vgs falls below Vth), the transistor is in a conductive state.

23 will be described. A first electrode (one of a source electrode and a drain electrode) of the first transistor 2301 is connected to a fifth wiring 2325, and a second electrode (the other of the source electrode and the drain electrode) of the first transistor 2301 is connected to a third wiring 2323. A first electrode of the second transistor 2302 is connected to a fourth wiring 2324.
24, and a second electrode of the second transistor 2302 is connected to a third wiring 2323. A first electrode of the third transistor 2303 is connected to a sixth wiring 2326, a second electrode of the third transistor 2303 is connected to a gate electrode of the second transistor 2302, and a gate electrode of the third transistor 2303 is connected to a seventh wiring 2327.
A first electrode of the fourth transistor 2304 is connected to a ninth wiring 2329, a second electrode of the fourth transistor 2304 is connected to a gate electrode of the second transistor 2302,
A gate electrode of the fourth transistor 2304 is connected to a gate electrode of the first transistor 2301. A first electrode of the fifth transistor 2305 is connected to an eighth wiring 2328, a second electrode of the fifth transistor 2305 is connected to a gate electrode of the first transistor 2301, and a gate electrode of the fifth transistor 2305 is connected to a first wiring 2321. A first electrode of the sixth transistor 2306 is connected to a tenth wiring 2330, and a gate electrode of the sixth transistor 2306 is connected to a tenth wiring 2330.
A second electrode of the sixth transistor 2306 is connected to a gate electrode of the first transistor 2301, and a gate electrode of the sixth transistor 2306 is connected to a gate electrode of the second transistor 2302. A first electrode of the seventh transistor 2307 is connected to an eleventh wiring 2331, a second electrode of the seventh transistor 2307 is connected to a gate electrode of the first transistor 2301, and a gate electrode of the seventh transistor 2307 is connected to the second wiring 2322.

Note that a connection point of the gate electrode of the first transistor 2301, the gate electrode of the fourth transistor 2304, the second electrode of the fifth transistor 2305, the second electrode of the sixth transistor 2306, and the second electrode of the seventh transistor 2307 is a node 2341.
Further, the gate electrode of the second transistor 2302, the second
A connection point of the first electrode of the fourth transistor 2304 , and the gate electrode of the sixth transistor 2306 is a node 2342 .

The fourth wiring 2324, the ninth wiring 2329, the tenth wiring 2330 and the eleventh wiring 23
31 may be connected to each other or may be the same wiring.
The eighth wiring 2327 and the eighth wiring 2328 may be connected to each other, or may be the same wiring.

Note that a first transistor 2301 to a seventh transistor 2307 correspond to the first transistor 101 to the seventh transistor 107 in FIG. 1, respectively, and have similar functions.

The first wiring 2321 to the eleventh wiring 2331 are the same as the first wiring 121 in FIG.
131 to 11th wiring 1321.
A signal input to the first wiring 121 in FIG.
The H level and L level of the signal input to the eleventh wiring 131 are inverted compared with the potential supplied thereto or the signal output therefrom.

Note that a potential of V2 is supplied to each of the seventh wiring 2327 and the eighth wiring 2328.
The fourth wiring 2324, the ninth wiring 2329, the tenth wiring 2330 and the eleventh wiring 23
31 are each supplied with the potential V1.

The first wiring 2321, the second wiring 2322, the fifth wiring 2325, and the sixth wiring 2326 are
A signal is input to each of the first wiring 2321 and the second wiring 2322. A signal is input to the fifth wiring 2325. A signal is input to the sixth wiring 2326. A signal is input to the first wiring 2321. A signal is input to the second wiring 2322. A signal is input to the fifth wiring 2325. A signal is input to the sixth wiring 2326.
The potential of the H signal is V1 (hereinafter also referred to as the H level), and the potential of the L signal is V2 (hereinafter also referred to as the L level).
It is a digital signal.

The first wiring 2321, the second wiring 2322, the second wiring 2322 to the eleventh wiring 2323 are
Various signals, currents or voltages may be input to 331 .

Note that a signal is output from the third wiring 2323. The signal output from the third wiring 2323 is an output signal of the flip-flop of each stage, and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop of the next stage.
The signal output from is a digital signal in which the potential of an H signal is V1 (hereinafter also referred to as an H level) and the potential of an L signal is V2 (hereinafter also referred to as an L level).

Next, the operation of the flip-flop shown in FIG. 23 will be described with reference to the timing chart of FIG. 24. The timing chart of FIG. 24 will be further divided into a selection period and a non-selection period. The non-selection period will be further divided into a first non-selection period, a second non-selection period, a set period, and a reset period. As shown in the timing chart of FIG. 24, the periods are arranged in the following order: set period, selection period, reset period, first non-selection period, second non-selection period, first non-selection period, and second non-selection period. That is, the set period,
In the operation period excluding the selection period and the reset period, a first non-selection period and a second non-selection period are repeated in sequence. Furthermore, the period before the set period is the second non-selection period.

The timing chart in FIG. 24 is similar to the timing chart in FIG. 2, with the H and L levels inverted.

In addition, for the flip-flop of this embodiment, not only the flip-flop with the H level and L level inverted in FIG. 2 but also the flip-flop with the H level and L level inverted in the timing charts of FIG. 6, FIG. 28, FIG. 31 and FIG. 32 may be used.

In FIG. 24 , a signal 2421, a signal 2425, a signal 2426, a potential 2441, a potential 2442, a signal 2422, and a signal 2423 are a signal input to a first wiring 2321, a signal input to a fifth wiring 2325, a signal input to a sixth wiring 2326,
The potential of the node 2341, the potential of the node 2342, a signal input to the second wiring 2322,
A signal output from the third wiring 2323 is shown.

Note that the signals 2421, 2425, 2426, potentials 2441, 2442, 2422, and 223 correspond to the signals 221, 225, 226, potentials 241, 242, 222, and 223 in Fig. 2, respectively. However, as already described, the H level and L level are inverted.

First, in the set period shown in FIG. 24A, the signal 2421 is at the L level, so the fifth transistor 2305 is turned on, and the signal 2422 is at the H level, so the seventh transistor 230
At this time, the potential of the node 2341 is the second potential of the fifth transistor 2305.
The electrode of the fifth transistor 2305 serves as a source electrode, and the potential of the eighth wiring 2328 and the potential of the fifth transistor 2305
Since it is the sum of the absolute value of the threshold voltage of V2+|Vth(2305)|(Vth(23
05): the threshold voltage of the fifth transistor 2305). Therefore, the first transistor 2301 and the fourth transistor 2304 are turned on, and the fifth transistor 2305 is turned off. At this time, the potential of the node 2342 (potential 2442) is the same as that of the third transistor 2302.
The resistance ratio (L/W and applied voltage) between the first transistor 2303 and the fourth transistor 2304 is determined as V1-θ (θ: any positive number).
h(2302): threshold voltage of the second transistor 2302) and θ<|Vth(23
06)|(threshold voltage of the sixth transistor 2306).
A potential difference (V1-V2) between the potential (V1) of the input terminal 329 and the potential (V2) of the sixth wiring 2326 is divided by the third transistor 2303 and the fourth transistor 2304. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned off. In this manner, during the set period, the third wiring 2323 is connected to the fifth wiring 2325 to which an H signal is input.
Therefore, the potential of the third wiring 2323 becomes V1. Therefore, an H signal is output from the third wiring 2323. Furthermore, the potential of the node 2341 becomes V2+|Vth(23
05) | and becomes floating.

In the selection period shown in FIG. 24B, the signal 2421 is at H level to turn on the fifth transistor 2
305 is turned off, and the signal 2422 remains at the H level, so the seventh transistor 2307 remains off. At this time, the potential of the node 2341 is maintained at V2+|Vth(2305)|. Therefore, the first transistor 2301 and the fourth transistor 2304 remain on. At this time, the potential of the node 2342 is V1 because the sixth wiring 2326 is at the H level. Therefore, the second transistor 2302 and the sixth transistor 23
06 remains off. Here, since an L signal is input to the fifth wiring 2325,
The potential of the wiring 2323 starts to decrease. Then, the potential of the node 2341 drops from V2+|Vth(2305)| to V2-|Vth(230
1) |-γ(Vth(2301): threshold voltage of the first transistor 2301, γ: any positive number). Therefore, the potential of the third wiring 2323 becomes equal to that of the fifth wiring 2325, and is therefore V2. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and second electrode of the first transistor 2301.
In this manner, during the selection period, the third wiring 2323 is connected to the fifth wiring 2323 to which the L signal is input.
325, the potential of the third wiring 2323 becomes V2. Therefore, an L signal is output from the third wiring 2323.

In the reset period shown in FIG. 24C, the signal 2421 remains at H level, so that the fifth transistor 2305 remains off, and the signal 2422 becomes L level, so that the seventh transistor 2307 is turned on. At this time, the potential of the node 2341 is the potential of the 11th wiring (V
1) is supplied through the seventh transistor 2307, so that it becomes V1. Therefore, the first transistor 2301 and the fourth transistor 2304 are turned off. At this time, the node 2
The potential of the sixth transistor 342 is supplied to the sixth transistor 2303 through the second electrode of the sixth transistor 2303 serving as a source electrode.
Since the potential of the third wiring 2326 is V2 minus the threshold voltage of the third transistor 2303, the potential is V2+|Vth(2303)|(Vth(2303): threshold voltage of the third transistor 2303). Therefore, the second transistor 2302 and the sixth transistor 2306 are turned on. In this manner, during the reset period, the third wiring 2323 is V
1 is supplied to the fourth wiring 2324, the potential of the third wiring 2323 becomes V
Therefore, an H signal is output from the third wiring 2323.

In the first non-selection period shown in FIG. 24D, the signal 2421 remains at H level, so that the fifth transistor 2305 remains off, and the signal 2422 becomes H level, so that the seventh transistor 2307 is turned off. At this time, the potential of the node 2342 is
Since an H signal is input to the node 2341, the potential of the node 2341 becomes V1. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned off. At this time, the node 2341 is in a floating state, so the potential of the node 2341 is maintained at V1. Therefore, the first transistor 2301 and the fourth transistor 23
04 remains off. In this manner, in the first non-selection period, the third wiring 2323 is in a floating state, and therefore the potential of the third wiring 2323 is maintained at V1.

24E, the signal 2421 remains at H level, so the fifth transistor 2305 remains off, and the signal 2422 remains at H level, so the seventh transistor 2307 remains off. At this time, the potential of the node 2342 is V2+|V
th(2303)|. Therefore, the second transistor 2302 and the sixth transistor 2306 are turned on. At this time, the potential of the node 2341 remains at V1 because the potential (V1) of the tenth wiring 2330 is supplied via the sixth transistor 2306. Therefore, the first transistor 2301 and the fourth transistor 2304 remain off. In this manner, during the second non-selection period, the third wiring 2323 remains at the fourth transistor to which V1 is supplied.
Since the third wiring 2323 is electrically connected to the wiring 2324, the potential of the third wiring 2323 remains at V1. Therefore, an H signal is output from the third wiring 2323.

23, the potential of the third wiring 2323 can be set to V2 by making the potential of the node 2341 lower than V2-|Vth(2301)| using the bootstrap operation during the selection period. Furthermore, the flip-flop in FIG. 23 can obtain merits such as a reduction in the layout area and the number of elements by performing the bootstrap operation using the capacitive coupling of the parasitic capacitance between the second electrode and gate electrode of the first transistor 2301.

Furthermore, in the flip-flop of FIG. 23, the second transistor 2302 and the sixth transistor 2306 are turned on only during the second non-selection period.
In this way, the shift in the threshold voltage of the second and sixth transistors 2306 can be suppressed.

In addition, in the flip-flop of FIG. 23, V2 is supplied to the gate electrode of the third transistor 2303 and the second clock signal is input to the first electrode of the third transistor 2303.
The shift in threshold voltage of 3 can also be suppressed.

Furthermore, in the flip-flop of FIG. 23, the first transistor 2301, the fourth transistor 2304, the fifth transistor 2305, and the seventh transistor 2307 are not turned on during the first non-selection period and the second non-selection period.
7, the shift in the threshold voltage can be suppressed.

Furthermore, in the flip-flop of FIG. 23, even if the potential of the node 2341 and the potential of the third wiring 2323 change during the first non-selection period, the potential of the node 2341 and the potential of the third wiring 2323 do not change during the next second non-selection period.
23 can suppress malfunction caused by fluctuations in the potentials of the node 2341 and the third wiring 2323 due to the node 2341 and the wiring 2323 being in a floating state.

Furthermore, the flip-flop of FIG. 23 can suppress the threshold voltage shift of the transistor, and therefore can suppress malfunctions caused by the threshold voltage shift of the transistor.

23 is characterized in that the first transistor 2301 to the seventh transistor 2307 are all P-channel transistors. Therefore, the flip-flop in FIG 23 can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

If the operation is the same as that shown in FIG. 24, the arrangement and number of each transistor may be the same as that shown in FIG.
24. Therefore, transistors, other elements (resistance elements, capacitance elements, etc.), diodes, switches, various logic circuits, etc. may be newly arranged in the flip-flop of FIG.

Note that the shift register of this embodiment mode can be implemented by freely combining the flip-flop of this embodiment mode with the shift register described in any of the embodiment modes 1 to 3. For example, the shift register of this embodiment mode can be implemented by freely combining the flip-flop of this embodiment mode with the shift register described in the embodiment modes 1 to 3.
13, 14, 15, 17, 29, 33, and 34. However, the shift register of this embodiment has an inverted H level and L level compared to the shift registers described in the first to third embodiments.

Note that the display device of this embodiment mode can be implemented by freely combining the shift register of this embodiment mode with the display devices described in any of Embodiments 1 to 3. For example, the display device of this embodiment mode can be implemented by freely combining with the display devices of Fig. 8, Fig. 18, Fig. 16, Fig. 20, and Fig. 22. However, the H level and the L level of the display device of this embodiment mode are inverted compared to the display devices described in any of Embodiments 1 to 3.

In this embodiment, various figures have been used to describe the present invention, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, in the figures described so far,
By combining different parts, more figures can be constructed.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

In addition, this embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment. Or, they can be combined.

(Embodiment 5)
In this embodiment mode, a signal line driver circuit included in the display device described in any of Embodiments 1 to 4 will be described.

The signal line driver circuit shown in FIG. 37 is a driver I
C5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b, and a third switch 5603c.

The driver IC 5601 includes a first wiring 5611, a second wiring 5612, and a third wiring 5613.
and are connected to wirings 5621_1 to 5621_M.
5602_M are a first wiring 5611, a second wiring 5612, a third wiring 561
3 and wirings 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively.
The wirings 5621_1 to 5621_M are connected to the first switch 5603a, the second switch 5603b, and the third switch 5603c.
For example, the wiring 5621_J in the Jth column (one of the wirings 5621_1 to 5621_M) is connected to the first switch 5603a, the second switch 5603b, and the third switch 5603c of the switch group 5602_J.
, and are connected to signal line Sj−1, signal line Sj, and signal line Sj+1 via.

Note that signals are input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed on a single crystal substrate or a glass substrate using a polycrystalline semiconductor. Furthermore, the switch group 5602 is preferably formed on the same substrate as the pixel portion shown in any one of the first to fourth embodiments.
The driver IC 5601 and the switch group 5602 may be connected via an FPC or the like.

Next, the operation of the signal line driver circuit shown in Fig. 37 will be described with reference to the timing chart of Fig. 38. Note that the timing chart of Fig. 38 shows a timing chart when the scanning line Gi of the i-th row is selected. Furthermore, the selection period of the scanning line Gi of the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driver circuit of Fig. 37 operates in the same manner as in Fig. 38 even when scanning lines of other rows are selected.

In the timing chart of FIG. 38, the wiring 5621_J in the Jth column is connected to the first switch 56
03a, the signal line Sj through the second switch 5603b and the third switch 5603c.
13 shows the case where the signal line Sj is connected to signal line Sj+1.

38 shows the timing when the scanning line Gi of the i-th row is selected, the timing 5703a when the first switch 5603a is turned on and off, and the timing 5703b when the second switch 5603 is turned on and off.
5 shows an on/off timing 5703b of the third switch 5603c, an on/off timing 5703c of the third switch 5603c, and a signal 5721_J input to the wiring 5621_J in the J-th column.

Note that different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj, and a video signal input to the wiring 5621_M in the third sub-selection period T3 is input to the signal line Sj-2.
A video signal input to the wiring 5621_J is input to a signal line Sj+1. Furthermore, in the selection period T1, the second sub-selection period T2, and the third sub-selection period T3, video signals input to the wiring 5621_J are designated as Dataj-1, Dataj, and Dataj+1, respectively.

As shown in FIG. 38, in the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time,
Dataj input to the wiring 5621_J is input to the signal line Sj via the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on.
The first switch 5603a and the second switch 5603b are turned off. At this time, the wiring 5
Dataj+1 input to 621_J is transmitted to the signal line S via the third switch 5603c.
j+1.

From the above, the signal line driver circuit in Fig. 37 can input a video signal from one wiring 5621 to three signal lines during one gate selection period by dividing one gate selection period into three. Therefore, the signal line driver circuit in Fig. 37 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1/3 of the number of signal lines. By reducing the number of connections to about 1/3, the signal line driver circuit in Fig. 37 can improve reliability, yield, and the like.

By applying the signal line driver circuit of this embodiment to the display devices shown in any of the embodiments 1 to 4, the number of connections between the substrate on which the pixel portion is formed and the external substrate can be further reduced. Therefore, the display device of this embodiment can improve the reliability. Furthermore, the display device of this embodiment can increase the yield.

Next, the first switch 5603a, the second switch 5603b and the third switch 560
A case where an N-channel transistor is applied to 3c will be described with reference to FIG.
Note that the same parts as those in FIG. 37 are denoted by the same reference numerals, and detailed descriptions of the same parts or parts having similar functions will be omitted.

The first transistor 5903a corresponds to the first switch 5603a, the second transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the third switch 5603c.

For example, in the case of the switch group 5602_J, the first transistor 5903a has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj-1, and a gate electrode connected to the first wiring 5611. The second transistor 5903b has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj, and a gate electrode connected to the second wiring 5612. The third transistor 5903c has a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj-1, and a gate electrode connected to the second wiring 5612.
J, the second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the third wiring 561
3 is connected.

Note that the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as a switching transistor.
Each of the transistors c is turned on when the signal input to its gate electrode is at H level, and is turned off when the signal input to its gate electrode is at L level.

The first switch 5603a, the second switch 5603b and the third switch 560
By using an N-channel transistor as 3c, amorphous silicon can be used for the semiconductor layer of the transistor, which can simplify the manufacturing process, reduce manufacturing costs, and improve yields. Furthermore, it is possible to manufacture a semiconductor device such as a large display panel. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon for the semiconductor layer of the transistor.

In the signal line driver circuit of FIG.
In the above description, n-channel transistors are used as the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c.
A P-channel transistor may be used as the third transistor 5903c. In this case, the transistor is turned on when a signal input to the gate electrode is at an L level, and is turned off when a signal input to the gate electrode is at an H level.

As shown in FIG. 37 , as long as one gate selection period can be divided into multiple sub-selection periods and a video signal can be input from one wiring to each of multiple signal lines in each of the multiple sub-selection periods, the arrangement, number, driving method, etc. of the switches are not limited.

For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, when one gate selection period is divided into four or more sub-selection periods, each sub-selection period becomes shorter. Therefore, it is desirable to divide one gate selection period into two or three sub-selection periods.

As another example, one selection period may be divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3, as shown in the timing chart of Fig. 40. Furthermore, the timing chart of Fig. 40 shows the timing when the i-th row scanning line Gi is selected, the on/off timing 5803a of the first switch 5603a,
The on/off timing 5803b of the switch 5603b, the on/off timing 5803c of the third switch 5603c, and the signal 58 input to the wiring 5621_J of the Jth column
40, in the precharge period Tp, the first switch 5603a, the second switch 5603b, and the third switch 5603c are turned on.
At this time, the precharge voltage Vp input to the wiring 5621_J is
In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned on to the signal line Sj−1, the signal line Sj, and the signal line Sj+1.
At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off.
At this time, Dataj input to the wiring 5621_J is input to the signal line Sj via the second switch 5603b.
The switch 5603c is turned on, and the first switch 5603a and the second switch 5603
At this time, Dataj+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third switch 5603c.

From the above, the signal line driver circuit of Fig. 37 to which the timing chart of Fig. 40 is applied can precharge the signal lines by providing a precharge selection period before the sub-selection period, and therefore can write video signals to pixels at high speed. Note that the same parts as those in Fig. 38 are denoted by the same reference numerals, and detailed descriptions of the same parts or parts having similar functions will be omitted.

In FIG. 41, as in FIG. 37, one gate selection period is divided into a plurality of sub-selection periods,
In each of the sub-selection periods, a video signal can be input from one wiring to each of the signal lines. Note that FIG. 41 shows only the switch group 6022_J in the J-th column of the signal line driver circuit. The switch group 6022_J includes the first transistor 60
6001, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 6006.
, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 60
The switch group 6022_J is connected to the first wiring 60
11, the second wiring 6012, the third wiring 6013, the fourth wiring 6014, and the fifth wiring 60
15, the sixth wiring 6016, the wiring 5621_J, the signal line Sj-1, the signal line Sj, the signal line S
j+1.

A first electrode of the first transistor 6001 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj-1, and a gate electrode is connected to the first wiring 6011. A first electrode of the second transistor 6002 is connected to the wiring 5621_J, and a second electrode is connected to the signal line Sj.
-1, and the gate electrode is connected to the second wiring 6012.
A first electrode of a fourth transistor 6003 is connected to a wiring 5621_J, a second electrode of the fourth transistor 6004 ... signal line Sj, and a gate electrode of the fourth transistor 6014. A first electrode of a fifth transistor 6005 is connected to a wiring 5621_J, a second electrode of the fifth transistor 6005 is connected to a wiring 5621_J, a gate electrode of the fifth transistor 6005 is connected to a wiring 5621_J.
A first electrode of the sixth transistor 6006 is connected to a wiring 5621_J, a second electrode of the sixth transistor 6006 is connected to a signal line Sj+1, and a gate electrode of the sixth transistor 6006 is connected to a wiring 5621_J, a second electrode of the sixth transistor 6006 is connected to a signal line Sj+1, and a gate electrode of the sixth transistor 6006 is connected to a wiring 5621_J.

Note that the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as a switching transistor.
The first transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 are turned on when a signal input to their gate electrodes is at H level, and are turned off when a signal input to their gate electrodes is at L level.

The first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. 39. The third wiring 6013 and the fourth wiring 6014 correspond to the second wiring 5912 in FIG. 39. The fifth wiring 6015 and the sixth wiring 6016 correspond to the third wiring 5913 in FIG.
The first transistor 6001 and the second transistor 6002 correspond to the first transistor 5903a in FIG.
39. The fifth transistor 6005 and the sixth transistor 6006 correspond to the third transistor 5903c in FIG.

In FIG. 41, in the first sub-selection period T1 shown in FIG.
In the pre-charge period Tp shown in FIG. 40, either the first transistor 6001, the third transistor 6003, or the fifth transistor 6004 is turned on. In the second sub-selection period T2, either the third transistor 6003 or the fourth transistor 6004 is turned on. In the third sub-selection period T3, either the fifth transistor 6005 or the sixth transistor 6006 is turned on.
Either the second transistor 6002, the fourth transistor 6004, or the sixth transistor 6006 is turned on.

41, the ON time of each transistor can be shortened, and therefore the deterioration of the characteristics of each transistor can be suppressed. This is because, for example, in the first sub-selection period T1 shown in FIG.
This is because a video signal can be input to the signal line Sj-1 if either one of the transistors 6001 and 6002 is on. Note that, for example, in the first sub-selection period T1 shown in FIG. 38, a video signal can be input to the signal line Sj-1 at high speed by simultaneously turning on the first transistor 6001 and the second transistor 6002.

41 illustrates a case where two transistors are connected in parallel between the wiring 5621 and the signal line. However, the present invention is not limited to this. Three or more transistors may be connected in parallel between the wiring 5621 and the signal line.
Alternatively, the transistors 21 may be connected in parallel between the transistors 21 and the signal line. This can further suppress the deterioration of the characteristics of the transistors.

In this embodiment, various figures have been used to describe the present invention, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, in the figures described so far,
By combining different parts, more figures can be constructed.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

In addition, this embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment. Or, they can be combined.

(Embodiment 6)
In this embodiment mode, a structure for preventing defects due to electrostatic breakdown of the display devices described in any of Embodiment Modes 1 to 4 will be described.

Electrostatic breakdown occurs when positive or negative charges accumulated on a human body or object are instantly discharged through the input/output terminals of a semiconductor device when the device comes into contact with the positive or negative charges, causing a large current to flow inside the device.

Fig. 42A shows a structure for preventing electrostatic breakdown occurring in a scan line by a protective diode. Fig. 42A shows a structure in which a protective diode is disposed between a wiring 6111 and a scan line. Although not shown, a plurality of pixels are connected to the i-th row scan line Gi. A transistor 6101 is used as the protective diode.
Reference numeral 6101 denotes an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6101 may be the same as that of a transistor included in a scanning line driver circuit or a pixel.

Although only one protection diode is provided, a plurality of protection diodes may be provided in series, in parallel, or in series-parallel.

A first electrode of the transistor 6101 is connected to the i-th scan line Gi, a second electrode of the transistor 6101 is connected to a wiring 6111, and a gate electrode of the transistor 6101 is connected to the i-th scan line Gi.

The operation of Fig. 42A will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the i-th scanning line Gi. When positive or negative charges are not discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi is H level or L level, and the transistor 6101 is off. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, the potential of the i-th scanning line Gi drops from the potential of the wiring 6111 to the potential of the transistor 61
42A, when the voltage Vcc becomes lower than the value obtained by subtracting the threshold voltage of 01, the transistor 6101 is turned on, and a current flows to the wiring 6111 through the transistor 6101. Therefore, the structure shown in FIG. 42A can prevent a large current from flowing into the pixel, thereby preventing electrostatic damage to the pixel.

Note that FIG. 42B shows a configuration for preventing electrostatic breakdown when a positive charge is discharged to the i-th scan line Gi. A transistor 6102 functioning as a protective diode is disposed between the scan line and a wiring 6112. Note that only one protective diode is disposed, but a plurality of protective diodes may be disposed in series, in parallel, or in series-parallel. Note that the transistor 6102 is an N-channel transistor. However, a P-channel transistor may also be used, and the polarity of the transistor 6102 may be the same as that of a transistor included in a scan line driver circuit or a pixel. The transistor 6102 has a first electrode connected to the i-th scan line Gi and a second electrode connected to the i-th scan line Gi.
The electrode of the transistor 6102 is connected to a wiring 6112, and the gate electrode is connected to the wiring 6112. Note that a potential higher than the H level of a signal input to the i-th row scanning line Gi is input to the wiring 6112. Therefore, the transistor 6102 is turned off when no charge is discharged to the i-th row scanning line Gi. On the other hand, when a positive charge is discharged to the i-th row scanning line Gi, the potential of the i-th row scanning line Gi rises instantaneously. At this time, the i-th row scanning line Gi
When the potential of the wiring 6112 becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on, and a current flows through the wiring 61
42B, it is possible to prevent a large current from flowing into the pixel, thereby preventing electrostatic damage to the pixel.

As shown in Fig. 42C, by combining Fig. 42A and Fig. 42B, it is possible to prevent electrostatic damage to pixels even when a positive charge is discharged to the i-th scanning line Gi or when a negative charge is discharged to the i-th scanning line Gi.
2(A) and 2(B) will be indicated using the same reference numerals, and detailed descriptions of the same parts or parts having similar functions will be omitted.

43A shows a configuration in which a transistor 6201 functioning as a protection diode is connected between a scan line and a storage capacitance line. Although only one protection diode is disposed, a plurality of protection diodes may be disposed in series, in parallel, or in series-parallel. The transistor 6201 is an N-channel transistor. However, a P-channel transistor may also be used, and the polarity of the transistor 6201 may be the same as that of a transistor included in a scan line driver circuit or a pixel. The wiring 6211 functions as a storage capacitance line. The transistor 6201
The first electrode of the pixel is connected to the scanning line Gi of the i-th row, and the second electrode of the pixel is connected to the wiring 6211.
The gate electrode is connected to the i-th scanning line Gi. Note that a potential lower than the L level of a signal input to the i-th scanning line Gi is input to the wiring 6211. Therefore, the transistor 6201 is turned off when no charge is discharged to the i-th scanning line Gi. On the other hand, when negative charge is discharged to the i-th scanning line Gi,
At this time, when the potential of the i-th row scanning line Gi becomes lower than the potential of the wiring 6211 minus the threshold voltage of the transistor 6201, the potential of the transistor 62
43A, a large current can be prevented from flowing into the pixel, and electrostatic damage to the pixel can be prevented. Furthermore, in the configuration shown in FIG. 43A, since the storage capacitance line is used as a wiring for dissipating electric charge, there is no need to add a new wiring.

43B shows a structure for preventing electrostatic breakdown when a positive charge is discharged to the i-th scanning line Gi. Here, a potential higher than the H level of a signal input to the i-th scanning line Gi is input to the wiring 6211. Therefore, the transistor 6201
When no charge is discharged to the i-th scanning line Gi, the transistor 6211 is turned off. On the other hand, when a positive charge is discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, the potential of the i-th scanning line Gi is equal to the potential of the wiring 6211 and the transistor 62
When the threshold voltage of the transistor 6201 becomes higher than the sum of the threshold voltages of the transistors 6202 and 6211, the transistor 6201 turns on and a current flows to the wiring 6211 via the transistor 6201. Therefore, the configuration shown in FIG. 43B can prevent a large current from flowing into the pixel, thereby preventing electrostatic damage to the pixel. Furthermore, in the configuration shown in FIG. 43B, since the storage capacitance line is used as a wiring for dissipating electric charge, it is not necessary to add a new wiring.
The same parts as those in B) are designated by the same reference numerals, and detailed descriptions of the same parts or parts having similar functions are omitted.

Next, a configuration for preventing electrostatic breakdown occurring in a signal line by a protective diode is shown in FIG.
44A shows a configuration in which a protective diode is disposed between a wiring 6411 and a signal line. Although not shown, a plurality of pixels are connected to the j-th column signal line Sj. A transistor 6401 is used as the protective diode. The transistor 6401 is an N-channel transistor. However, a P-channel transistor may also be used, and the polarity of the transistor 6401 may be the same as that of a transistor included in a signal line driver circuit or a pixel.

Although only one protection diode is provided, a plurality of protection diodes may be provided in series, in parallel, or in series-parallel.

A first electrode of the transistor 6401 is connected to the j-th signal line Sj, a second electrode of the transistor 6401 is connected to a wiring 6411, and a gate electrode of the transistor 6401 is connected to the j-th signal line Sj.

The operation of Fig. 44A will be described. A certain potential is input to the wiring 6411, and the potential is a potential that is lower than the minimum value of the video signal input to the jth signal line Sj. When a positive or negative charge is not discharged to the jth signal line Sj, the potential of the jth signal line Sj is the same potential as the video signal, and the transistor 6401 is off. On the other hand, when a negative charge is discharged to the jth signal line Sj, the potential of the jth signal line Sj drops instantaneously.
At this time, when the potential of the signal line Sj on the jth row becomes lower than the potential of the wiring 6411 minus the threshold voltage of the transistor 6401, the transistor 6401 is turned on and a current flows through the transistor 6401 to the wiring 6411. Therefore, the structure shown in FIG 44A can prevent a large current from flowing into the pixel, thereby preventing electrostatic damage to the pixel.

Note that FIG. 44B shows a structure for preventing electrostatic breakdown when a positive charge is discharged to the j-th signal line Sj. A transistor 6402 functioning as a protective diode is disposed between the scan line and the wiring 6412. Note that only one protective diode is disposed, but a plurality of protective diodes may be disposed in series, in parallel, or in series-parallel. Note that the transistor 6402 is an N-channel transistor. However, a P-channel transistor may also be used, and the polarity of the transistor 6402 may be the same as that of a transistor included in a scan line driver circuit or a pixel. The transistor 6402 has a first electrode connected to the j-th signal line Sj and a second electrode connected to the j-th signal line Sj.
The electrode of the transistor 6402 is connected to a wiring 6412, and the gate electrode is connected to the wiring 6412. Note that a potential higher than the maximum value of a video signal input to the j-th signal line Sj is input to the wiring 6412. Therefore, the transistor 6402 is turned off when no charge is discharged to the j-th signal line Sj. On the other hand, when a positive charge is discharged to the j-th signal line Sj, the potential of the j-th signal line Sj rises instantaneously. At this time, when the potential of the j-th signal line Sj becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on and a current flows to the wiring 6412 through the transistor 6402. Therefore, the configuration shown in FIG. 44B can prevent a large current from flowing into the pixel, and thus electrostatic damage to the pixel can be prevented.

As shown in Fig. 44C, by combining Fig. 44A and Fig. 44B, it is possible to prevent electrostatic damage to the pixel even when a positive charge is discharged to the jth signal line Sj or when a negative charge is discharged to the jth signal line Sj.
4(A) and 4(B) will be indicated using the same reference numerals, and detailed descriptions of the same parts or parts having similar functions will be omitted.

In this embodiment mode, a configuration for preventing electrostatic breakdown of pixels connected to scanning lines and signal lines has been described. However, the configuration of this embodiment mode is not only applied to preventing electrostatic breakdown of pixels connected to scanning lines and signal lines. For example, when this embodiment mode is applied to wiring to which a signal or potential is input and which is connected to the scanning line driver circuit and the signal line driver circuit shown in Embodiment Modes 1 to 4, electrostatic breakdown of the scanning line driver circuit and the signal line driver circuit can be prevented.

In this embodiment, various figures have been used to describe the present invention, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, in the figures described so far,
By combining different parts, more figures can be constructed.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

In addition, this embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment. Or, they can be combined.

(Seventh embodiment)
In this embodiment mode, a new structure of a display device that can be applied to the display devices described in any of Embodiments 1 to 4 will be described.

45A shows a configuration in which a diode-connected transistor is arranged between a certain scan line and another scan line. In FIG. 45A, a diode-connected transistor 6301a is arranged between the i-1th scan line Gi-1 and the i-th scan line Gi, and a diode-connected transistor 6302 is arranged between the i-th scan line Gi and the i+1th scan line Gi+1.
6 shows a configuration in which the transistor 6301a and the transistor 6301b are arranged in the scanning line driver circuit and the pixel. Note that the transistors 6301a and 6301b are n-channel transistors. However, p-channel transistors may be used, and the polarities of the transistors 6301a and 6301b may be similar to those of the transistors in the scanning line driver circuit and the pixel.

In addition, in Figure 45 (A), the scanning line Gi-1 in the (i-1)th row, the scanning line Gi in the i-th row, and the scanning line Gi+1 in the (i+1)th row are shown as representatives, but diode-connected transistors are similarly arranged in the other scanning lines as well.

A first electrode of the transistor 6301a is connected to the i-th scan line Gi, and a second electrode of the transistor 6301a is connected to the i-th scan line Gi.
A first electrode of the transistor 6301b is connected to the scanning line Gi-1 of the -1th row, and a gate electrode of the transistor 6301b is connected to the scanning line Gi+1 of the Gi-1th row. A first electrode of the transistor 6301b is connected to the scanning line Gi+1 of the (i+1)th row, a second electrode of the transistor 6301b is connected to the scanning line Gi of the i-th row, and a gate electrode of the transistor 6301b is connected to the scanning line Gi of the i-th row.

The operation of FIG. 45A will be described. In the scanning line driver circuits shown in the first to fourth embodiments, the (i-1)th scanning line Gi-1, the i-th scanning line Gi, and the (i+1)th scanning line Gi+1 are maintained at the L level during the non-selection period.
301a and the transistor 6301b are off. However, for example, when the potential of the scanning line Gi of the i-th row rises due to noise or the like, the scanning line Gi of the i-th row does not select a pixel, and an incorrect video signal is written to the pixel. Therefore, by disposing a diode-connected transistor between the scanning lines as shown in FIG. 45A, it is possible to prevent an incorrect video signal from being written to a pixel. This is because, when the potential of the scanning line Gi of the i-th row rises to or above the sum of the potential of the scanning line Gi-1 of the i-1-th row and the threshold voltage of the transistor 6301a, the transistor 6301a is turned on, and the potential of the scanning line Gi of the i-th row falls. Therefore, a pixel is not selected by the scanning line Gi of the i-th row.

45A is particularly advantageous when the scanning line driver circuit and the pixel portion are integrally formed on the same substrate, because in a scanning line driver circuit composed only of N-channel transistors or P-channel transistors, the scanning lines may be in a floating state, which makes it easy for noise to occur in the scanning lines.

45B shows a configuration in which the orientation of the diode-connected transistors arranged between the scan lines is reversed.
is an N-channel transistor. However, a P-channel transistor may be used, and the polarity of the transistor 6302a and the transistor 6302b may be the same as that of the transistors included in the scan line driver circuit or the pixel. In FIG. 45B, the first electrode of the transistor 6302a is connected to the i-th scan line Gi, the second electrode is connected to the i-1-th scan line Gi-1, and the gate electrode is connected to the i-th scan line Gi. The first electrode of the transistor 6302b is connected to the i+1-th scan line Gi+1, the second electrode is connected to the i-th scan line Gi, and the gate electrode is connected to the i+1-th scan line Gi+1. In FIG. 45B, as in FIG. 44A, when the potential of the i-th scan line Gi rises to or above the sum of the potential of the i-1-th scan line Gi+1 and the threshold voltage of the transistor 6302b,
The transistor 6302b is turned on, and the potential of the i-th row scanning line Gi drops.
No pixel is selected by the i-th row scanning line Gi, and it is possible to prevent an incorrect video signal from being written to the pixel.

45C, by combining the configurations of FIG. 45A and FIG. 45B, even if the potential of the i-th row scanning line Gi rises, the transistors 6301a and 6302b are turned on, so that the potential of the i-th row scanning line Gi falls.
In (C), since the current flows through two transistors, it is possible to remove larger noise. Note that the same reference numerals are used for the same parts as in Figures 45 (A) and (B), and detailed descriptions of the same parts or parts having similar functions will be omitted.

As shown in FIGS. 43A and 43B, even if a diode-connected transistor is placed between the scanning line and the storage capacitance line, the same effect as in FIGS. 45A, 45B, and 45C can be obtained.

In this embodiment, various figures have been used to describe the present invention, but the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or, they can be combined. Furthermore, in the figures described so far,
By combining different parts, more figures can be constructed.

Similarly, the contents or part of the contents described in each drawing of this embodiment can be applied to the contents or part of the contents described in the drawings of another embodiment, or can be combined.
Furthermore, in the figures of this embodiment, each part can be combined with a part of another embodiment to form even more figures.

In addition, this embodiment shows an example of the case where the contents described in the other embodiments are embodied, slightly modified, partially changed, improved, described in detail, applied, and related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment. Or, they can be combined.

(Embodiment 8)
In this embodiment, a pixel structure of a display device will be described, and in particular, a pixel structure of a liquid crystal display device will be described.

Fig. 46 shows a cross-sectional view and a top view of a pixel in a case where a thin film transistor (TFT) is combined with a pixel structure called a TN type among pixel structures of a liquid crystal display device. Fig. 46(A) is a cross-sectional view of a pixel, and Fig. 46(B) is a top view of a pixel. The cross-sectional view of the pixel shown in Fig. 46(A) corresponds to the line segment a-a' in the top view of the pixel shown in Fig. 46(B). By applying this embodiment to a liquid crystal display device having the pixel structure shown in Fig. 46, it is possible to manufacture the liquid crystal display device at low cost.

The pixel structure of a TN type liquid crystal display device will be described with reference to Fig. 46(A). A liquid crystal display device has a key part for displaying images, called a liquid crystal panel. The liquid crystal panel includes:
The two processed substrates are bonded together with a gap of several micrometers, and liquid crystal material is injected between the two substrates. In FIG. 46A, the two substrates are a first substrate 10101 and a second substrate 10116. The first substrate has a TFT.
and a pixel electrode are formed on the second substrate.
5, a fourth conductive layer 10113, a spacer 10117, and a second alignment film 10112 may be fabricated.

It is possible to carry out the present embodiment without fabricating a TFT on the first substrate 10101. When carrying out this embodiment mode without fabricating a TFT, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved.
When a TFT is fabricated and this embodiment is carried out, a larger display device can be obtained.

The TFT shown in FIG. 46 is a bottom-gate type TFT using an amorphous semiconductor. A liquid crystal panel that uses a TFT using an amorphous semiconductor has the advantage that it can be manufactured inexpensively using a large-area substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used for a bottom-gate type TFT includes a channel etch type and a channel protection type. A top-gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

It should be noted that this embodiment can be implemented without forming the light-shielding film 10114 on the second substrate 10116. When this embodiment is implemented without forming the light-shielding film 10114, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment is implemented by forming the light-shielding film 10114, a display device with little light leakage during black display can be obtained.

It should be noted that this embodiment mode can be implemented without fabricating the color filter 10115 on the second substrate 10116. When this embodiment mode is implemented without fabricating the color filter 10115, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without fabricating the color filter 10115, a display device capable of color display by field sequential driving can be obtained. On the other hand, when this embodiment mode is implemented by fabricating the color filter 10115, a display device capable of color display can be obtained.

This embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10117 on the second substrate 10116. When this embodiment mode is implemented by dispersing spherical spacers, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, the structure is simple, and therefore the yield can be improved. On the other hand, the spacers 101
When the present embodiment is carried out by manufacturing the substrate 17, the position of the spacer does not vary, so that
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, processing to be performed on the first substrate 10101 will be described. The first substrate 10101 is preferably a substrate having light-transmitting properties, and may be, for example, a quartz substrate, a glass substrate, or a plastic substrate. Note that the first substrate 10101 may be a light-shielding substrate, such as a semiconductor substrate or an SOI (S
A silicon on insulator (SiC) substrate may also be used.

First, a first insulating film 10102 may be formed on a first substrate 10101. The first insulating film 10102 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxN
Alternatively, the first insulating film 10102 may be an insulating film having a laminated structure in which two or more films selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiOxNy), and the like are combined. When the first insulating film 10102 is formed to implement this embodiment, it is possible to prevent impurities from the substrate from affecting the semiconductor layer and causing changes in the properties of the TFT. In addition, since changes in the properties of the TFT can be suppressed,
A display device with high reliability can be obtained. In addition, when this embodiment mode is implemented without forming the first insulating film 10102, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved.

Next, a first conductive layer 1010 is formed on the first substrate 10101 or the first insulating film 10102.
The first conductive layer 10103 may be formed by processing the shape. The process for processing the shape is preferably as follows. First, the first conductive layer 101
At this time, the first conductive layer 10103 is formed by a sputtering device or a C
The film may be formed using a film forming apparatus such as a VD apparatus. Next, a photosensitive resist material is formed on the entire surface of the first conductive layer formed on the entire surface. Next, the resist material is exposed to light according to the shape to be formed by photolithography, laser direct writing, or the like. Next, either the exposed resist material or the unexposed resist material is removed by etching to obtain a mask for processing the shape of the first conductive layer 10103. Thereafter, the first conductive layer 10103 is patterned according to the formed mask pattern.
By removing the conductive layer 10103 by etching, the first conductive layer 10103 can be shaped into a desired pattern. Methods for etching the first conductive layer 10103 include chemical methods (wet etching) and physical methods (dry etching), and the method is appropriately selected taking into consideration the material of the first conductive layer 10103 and the properties of the material below the first conductive layer 10103. Materials used for the first conductive layer 10103 include Mo, Ti, Al, and the like.
Alternatively, a laminated structure in which two or more of Mo, Ti, Al, Nd, Cr, etc. are combined may be used.

Next, the second insulating film 10104 is formed. At this time, the second insulating film 10104 may be formed using a film forming apparatus such as a sputtering apparatus or a CVD apparatus. The material used for the second insulating film 10104 is preferably a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Alternatively, the second insulating film 10104 may have a laminated structure in which two or more of the thermal oxide film, the silicon oxide film, the silicon nitride film, the silicon oxynitride film, or the like are combined.
It is particularly preferable that the second insulating film 10104 in contact with the first semiconductor layer 10105 is a silicon oxide film. This is because the silicon oxide film is too thick for the semiconductor layer 10.
This is because the number of trap levels at the interface with the first conductive layer 105 is reduced.
When the second insulating film 103 is made of Mo, the portion of the second insulating film 103 that contacts the first conductive layer 10103 is
A silicon nitride film is preferable for 0104 because the silicon nitride film does not oxidize Mo.

Next, a first semiconductor layer 10105 is formed. After that, it is preferable to continuously form a second semiconductor layer 10106. Note that the first semiconductor layer 10105 and the second semiconductor layer 10106 are
The first semiconductor layer 10105 may be formed by processing the shape. The process of processing the shape is preferably a method such as the photolithography method described above. The material used for the first semiconductor layer 10105 is preferably silicon or silicon germanium (SiGe). The material used for the second semiconductor layer 10106 is preferably silicon containing phosphorus or the like.

Next, the second conductive layer 10107 is formed. At this time, the second conductive layer 10107 is preferably formed by sputtering or printing.
The material used for 107 may be transparent or reflective. If it is transparent, it may be, for example, indium tin oxide (ITO), which is a mixture of indium oxide and tin oxide.
Examples of the film that can be used include an indium tin oxide (ITO) film, an indium tin silicon oxide (ITSO) film obtained by mixing silicon oxide with indium tin oxide (ITO), an indium zinc oxide (IZO) film obtained by mixing indium oxide with zinc oxide, a zinc oxide film, or a tin oxide film.
It is a transparent conductive material formed by sputtering using a target containing 20 wt% zinc oxide (ZnO). On the other hand, when it has reflectivity, it is made of Ti, Mo, Ta, Cr, etc.
, W, Al, etc. can be used. A two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, or a three-layer structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr, and W may also be used. The second conductive layer 10107 may be formed by processing the shape. The method for processing the shape is preferably the above-mentioned photolithography method or the like. The etching method is preferably dry etching. Dry etching can be performed using ECR (Electron Cyclotron Resonance) or ICP (In
Alternatively, the etching may be performed by a dry etching apparatus using a high-density plasma source such as a high-inductive coupled plasma.

Next, a channel region of the TFT is formed. At this time, the second conductive layer 10107 may be used as a mask for etching the second semiconductor layer 10106, or a mask (resist) for etching the second conductive layer 10107 may be used. In this way, the number of masks can be reduced, and therefore the manufacturing cost can be reduced. By etching the conductive second semiconductor layer 10106, the removed portion becomes the TFT.
The first semiconductor layer 10105 and the second semiconductor layer 10106 are not formed continuously, but after the formation of the first semiconductor layer 10105, a film serving as a stopper is formed and patterned in the portion that will become the channel region of the TFT, and then the second semiconductor layer 10
In addition, the first semiconductor layer 10105 and the second semiconductor layer 10106 may be formed.
The second conductive layer 10107 is etched using the same mask when the second conductive layer 10107 is shaped by the above-mentioned photolithography method or the like.
Since the channel region of the TFT can be formed without using the mask 7, the degree of freedom of the layout pattern is increased. In addition, since the first semiconductor layer 10105 is not etched when the second semiconductor layer 10106 is etched, there is an advantage that the channel region of the TFT can be reliably formed without causing etching defects.

Next, a third insulating film 10108 is formed. The third insulating film is preferably transparent. Note that the material used for the third insulating film 10108 is an inorganic material (silicon oxide,
Silicon nitride, silicon oxynitride, etc.) or a low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material) is suitable. A material containing siloxane may also be used. Siloxane is a material whose skeletal structure is formed by bonding silicon (Si) and oxygen (O). An organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as the substituent. Alternatively, a fluoro group may also be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may also be used as the substituent. A contact hole is selectively formed in the third insulating film 10108 by etching. The contact hole is formed at least on the second conductive layer 10107.
By etching the second insulating film 10104 at the same time as etching the third insulating film 10108, it is possible to form contact holes with not only the second conductive layer 10107 but also the first conductive layer 10103. It is preferable that the surface of the third insulating film 10108 is as flat as possible, because the alignment of the liquid crystal molecules is affected by unevenness on the surface with which the liquid crystal comes into contact.

Next, the third conductive layer 10109 is formed. At this time, the third conductive layer 10109 is preferably formed by sputtering or printing.
The material used for the third conductive layer 10109 may be transparent or reflective, like the second conductive layer 10107.
The third conductive layer 10109 may be formed by processing its shape. The method for processing the shape may be the same as that for the second conductive layer 10107.

Next, a first alignment film 10110 is formed. A polymer film such as polyimide can be used for the alignment film 10110. After the first alignment film 10110 is formed, rubbing may be performed to control the alignment of the liquid crystal molecules. Rubbing is a process of rubbing the alignment film with a cloth to create lines in the alignment film. By rubbing, it is possible to impart alignment to the alignment film.

The first substrate 10101, the light-shielding film 10114, and the color filter 10102 are formed as described above.
The second substrate 10116 on which the second alignment film 10112, the fourth conductive layer 10113, the spacer 10117 and the second alignment film 10112 are formed is attached to the second substrate 10116 with a gap of several μm by a sealant. Then, a liquid crystal material is injected between the two substrates to manufacture a liquid crystal panel. In the TN type liquid crystal panel shown in FIG. 46, the fourth conductive layer 101
13 may be fabricated on the entire surface of the second substrate 10116 .

Next, the characteristics of the pixel structure of a TN type liquid crystal panel shown in FIG.
The liquid crystal molecule 10118 shown in (A) of FIG. 46 is a long and thin molecule with a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecule 10118, it is expressed by its length in (A) of FIG. 46. That is, the longer the liquid crystal molecule 10118 is expressed, the longer its long axis is parallel to the paper surface, and the shorter the liquid crystal molecule 10118 is expressed, the closer its long axis is to the normal direction to the paper surface. In other words, the liquid crystal molecule 10118 shown in (A) of FIG. 46 has a 90° difference in the orientation of its long axis between the one closer to the first substrate 10101 and the one closer to the second substrate 10116.
The liquid crystal molecules 10118 located between them have a long axis that is oriented in such a way as to smoothly connect them.
18 is in an orientation state in which it is twisted 90 degrees between the first substrate 10101 and the second substrate 10116.

Next, an example of a pixel layout when this embodiment is applied to a TN type liquid crystal display device will be described with reference to Fig. 46B. A pixel of the TN type liquid crystal display device to which this embodiment is applied is composed of a scanning line 10121, a video signal line 10122, and a capacitance line 10123.
, a TFT 10124 , a pixel electrode 10125 , and a pixel capacitance 10126 .

Since the scanning line 10121 is electrically connected to the gate electrode of the TFT 10124 , it is preferable that the scanning line 10121 is made of the first conductive layer 10103 .

The video signal line 10122 is preferably made of the second conductive layer 10107 since it is electrically connected to the source electrode or drain electrode of the TFT 10124. In addition, since the scanning line 10121 and the video signal line 10122 are arranged in a matrix, at least
It is preferably formed of different conductive layers.

The capacitance line 10123 is arranged in parallel with the pixel electrode 10125, so that the pixel capacitance 1012
46B, the capacitance line 10123 may be extended along the video signal line 10122 so as to surround the video signal line 10122. This can reduce the phenomenon of the potential of an electrode that should hold a potential changing with a potential change of the video signal line 10122, that is, so-called crosstalk. In order to reduce the cross capacitance with the video signal line 10122, the first semiconductor layer 10105 may be formed as shown in FIG. 46B.
may be provided in the intersecting region of the capacitance line 10123 and the video signal line 10122 .

The TFT 10124 operates as a switch that connects the video signal line 10122 and the pixel electrode 10125. As shown in FIG. 46B, either the source region or the drain region of the TFT 10124 may be disposed so as to surround the other of the source region or the drain region. In this way, a large channel width can be obtained in a small area, and the switching capability can be increased. As shown in FIG. 46B, the TFT
The gate electrode 10124 may be disposed to surround the first semiconductor layer 10105 .

The pixel electrode 10125 is electrically connected to one of the source electrode or the drain electrode of the TFT 10124. The pixel electrode 10125 is an electrode for applying a signal voltage transmitted by the video signal line 10122 to the liquid crystal element. In addition, by arranging the capacitance line 10123,
A pixel capacitor 10126 may be formed. This allows the pixel electrode 10125 to easily hold the signal voltage transmitted by the video signal line 10122.
46B, the pixel electrode 25 may be rectangular. This allows the aperture ratio of the pixel to be increased, thereby improving the efficiency of the liquid crystal display device.
When the pixel electrode 10125 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. When the pixel electrode 10125 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in bright environments such as outdoors, and does not require a backlight, so that power consumption can be greatly reduced. When the pixel electrode 10125 is made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device that combines the advantages of both can be obtained. When the pixel electrode 10125 is made of a reflective material, the surface of the pixel electrode 10125 may be made uneven. Alternatively, the pixel electrode 10125 can be made uneven by making the surface of the third insulating film 10108 uneven. This has the advantage that the reflected light is diffused, so that the angle dependency of the intensity distribution of the reflected light is reduced. In other words, a reflective liquid crystal display device with a constant brightness can be obtained regardless of the angle at which it is viewed.

Next, a case where this embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described with reference to Fig. 47. Fig. 47 shows a so-called MVA (Multi-domain Ver.) liquid crystal display device in which, by using an alignment control protrusion in the pixel structure of a VA mode liquid crystal display device, liquid crystal molecules are controlled to have various orientations and the viewing angle is increased.
47A and 47B are a cross-sectional view and a top view of a pixel when this embodiment is applied to a vertical alignment type liquid crystal display device. FIG. 47A is a cross-sectional view of a pixel, and FIG. 47B is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 47A corresponds to the line segment a-a' in the top view of the pixel shown in FIG. 47B. By applying this embodiment to a liquid crystal display device having the pixel structure shown in FIG. 47, a liquid crystal display device having a wide viewing angle, a fast response speed, and a high contrast can be obtained.

The pixel structure of an MVA type liquid crystal display device will be described with reference to Fig. 47A. A liquid crystal display device has a key part for displaying images, called a liquid crystal panel. A liquid crystal panel is made by bonding two processed substrates with a gap of several micrometers between them.
The liquid crystal display is fabricated by injecting a liquid crystal material between two substrates. In FIG. 47A, the two substrates are a first substrate 10201 and a second substrate 10216. The first substrate is a TF
The second substrate is provided with a light-shielding film 10214, a color filter 102, and a pixel electrode.
15, a fourth conductive layer 10213, a spacer 10217, a second alignment film 10212, and an alignment control protrusion 10219 may be formed.

It should be noted that this embodiment mode can be implemented without fabricating a TFT on the first substrate 10201. When this embodiment mode is implemented without fabricating a TFT, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when this embodiment mode is implemented by fabricating a TFT, a larger display device can be obtained.

The TFT shown in FIG. 47 is a bottom-gate type TFT using an amorphous semiconductor. A liquid crystal panel that uses a TFT using an amorphous semiconductor has the advantage that it can be manufactured inexpensively using a large-area substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used for a bottom-gate type TFT includes a channel etch type and a channel protection type. A top-gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

It should be noted that this embodiment can be implemented without forming the light-shielding film 10214 on the second substrate 10216. When this embodiment is implemented without forming the light-shielding film 10214, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment is implemented by forming the light-shielding film 10214, a display device with little light leakage during black display can be obtained.

It should be noted that this embodiment mode can be implemented without fabricating the color filter 10215 on the second substrate 10216. When this embodiment mode is implemented without fabricating the color filter 10215, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without fabricating the color filter 10215, a display device capable of color display by field sequential driving can be obtained. On the other hand, when this embodiment mode is implemented by fabricating the color filter 10215, a display device capable of color display can be obtained.

This embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10217 on the second substrate 10216. When this embodiment mode is implemented by dispersing spherical spacers, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, the spacers 102
When the present embodiment is carried out by manufacturing the substrate 17, the position of the spacer does not vary, so that
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, the processing of the first substrate 10201 may be performed by the method described in FIG. 46, so the description will be omitted. Here, the first substrate 10201, the first insulating film 10202, the first conductive layer 10203, the second insulating film 10204, the first semiconductor layer 10205, the second semiconductor layer 10206, the second conductive layer 10207, the third insulating film 10208, the third conductive layer 10209, the third insulating film 10210, the third conductive layer 10211, the third insulating film 10212, the third conductive layer 10213, the third conductive layer 10214, the third insulating film 10215, the third conductive layer 10216, the third conductive layer 10217, the third conductive layer 10218, the third conductive layer 10219, the third conductive layer 10220
46. The first alignment film 10210 corresponds to the first substrate 10101 and the first alignment film 10210 in FIG.
The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, and the third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Although not shown, an alignment control protrusion may be provided on the first substrate as well. This makes it possible to more reliably control the alignment of the liquid crystal molecules.
The alignment film 10212 may be a vertical alignment film, which allows the liquid crystal molecules 10218 to be aligned vertically.

The first substrate 10201, the light-shielding film 10214, and the color filter 10202 thus prepared are then stacked.
215, a fourth conductive layer 10213, a spacer 10217, and a second alignment film 10212
The second substrate 10216 on which the fourth conductive layer 102 is formed is attached to the second substrate 10216 with a gap of several micrometers by a sealant, and a liquid crystal material is injected between the two substrates, thereby manufacturing a liquid crystal panel.
The fourth conductive layer 10 may be formed on the entire surface of the second substrate 10216.
An alignment control protrusion 10219 may be fabricated in contact with the alignment control protrusion 10213.
Although there is no limitation on the shape of the protrusions 10219, a shape with a smooth curved surface is preferable. This makes the alignment of adjacent liquid crystal molecules 10218 very close to each other, thereby reducing alignment defects. In addition, defects in the alignment film caused by the step of the second alignment film 10212 caused by the protrusions 10219 for alignment control can also be reduced.

Next, the characteristics of the pixel structure of the MVA type liquid crystal panel shown in FIG.
The liquid crystal molecule 10218 shown in FIG. 47A is a long and thin molecule with a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecule 10218, it is expressed by its length in FIG. 47A. That is, the longer the liquid crystal molecule 10218 is expressed, the longer its long axis is parallel to the paper surface, and the shorter the liquid crystal molecule 10218 is expressed, the closer its long axis is to the normal direction to the paper surface. In other words, the liquid crystal molecule 10218 shown in FIG. 47A is oriented so that its long axis is oriented in the normal direction to the alignment film. Therefore, the alignment control protrusion 1021
The liquid crystal molecules 10218 in the portion of the alignment control panel 9 are aligned radially around the alignment control protrusion 10219. By achieving this state, a liquid crystal display device with a wide viewing angle can be obtained.

Next, an example of a pixel layout when this embodiment is applied to an MVA type liquid crystal display device will be described with reference to Fig. 47B. A pixel of the MVA type liquid crystal display device to which this embodiment is applied is composed of a scanning line 10221, a video signal line 10222, and a capacitance line 102
23, a TFT 10224, a pixel electrode 10225, a pixel capacitor 10226, and a protrusion for alignment control 10219.

Since the scanning line 10221 is electrically connected to the gate electrode of the TFT 10224 , it is preferable that the scanning line 10221 is made of the first conductive layer 10203 .

The video signal line 10222 is preferably made of the second conductive layer 10207 since it is electrically connected to the source electrode or drain electrode of the TFT 10224. In addition, since the scanning line 10221 and the video signal line 10222 are arranged in a matrix, at least
It is preferably formed of different conductive layers.

The capacitance line 10223 is arranged in parallel with the pixel electrode 10225, so that the pixel capacitance 1022
47B, the capacitance line 10223 may be extended along the video signal line 10222 so as to surround the video signal line 10222. This can reduce the phenomenon of the potential of an electrode that should hold a potential changing with a potential change of the video signal line 10222, that is, so-called crosstalk. In order to reduce the cross capacitance with the video signal line 10222, the first semiconductor layer 10205 may be formed as shown in FIG. 47B.
may be provided in the intersecting region of the capacitance line 10223 and the video signal line 10222.

The TFT 10224 operates as a switch that connects the video signal line 10222 and the pixel electrode 10225. As shown in FIG. 47B, either the source region or the drain region of the TFT 10224 may be disposed so as to surround the other of the source region or the drain region. In this way, a large channel width can be obtained in a small area, and the switching ability can be increased. As shown in FIG. 47B, the TFT
The gate electrode 10224 may be disposed to surround the first semiconductor layer 10205 .

The pixel electrode 10225 is electrically connected to one of the source electrode or the drain electrode of the TFT 10224. The pixel electrode 10225 is an electrode for applying a signal voltage transmitted by the video signal line 10222 to the liquid crystal element. In addition, by arranging the capacitance line 10223,
A pixel capacitor 10226 may be formed. This allows the pixel electrode 10225 to easily hold the signal voltage transmitted by the video signal line 10222.
47B, the pixel electrode 25 may be rectangular. This allows the aperture ratio of the pixel to be increased, thereby improving the efficiency of the liquid crystal display device.
When the pixel electrode 10225 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. When the pixel electrode 10225 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in bright environments such as outdoors, and does not require a backlight, so that power consumption can be greatly reduced. When the pixel electrode 10225 is made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device that combines the advantages of both can be obtained. When the pixel electrode 10225 is made of a reflective material, the surface of the pixel electrode 10225 may be made uneven. Alternatively, the pixel electrode 10225 can be made uneven by making the surface of the third insulating film 10208 uneven. This has the advantage that the reflected light is diffused, so that the angle dependency of the intensity distribution of the reflected light is reduced. In other words, a reflective liquid crystal display device with a constant brightness can be obtained regardless of the angle at which it is viewed.

Next, with reference to Fig. 48, another example in which the present embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described. Fig. 48 shows a so-called PVA (PolyValuable Alignment) liquid crystal display device in which the liquid crystal molecules are controlled to have various orientations by patterning the fourth conductive layer 10313 in the pixel structure of the VA mode liquid crystal display device, thereby increasing the viewing angle.
48A and 48B are a cross-sectional view and a top view of a pixel in the case where this embodiment is applied to an alternating vertical alignment type liquid crystal display. FIG. 48A is a cross-sectional view of a pixel, and FIG. 48B is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 48A corresponds to the line segment a-a' in the top view of the pixel shown in FIG. 48B. By applying this embodiment to a liquid crystal display device having the pixel structure shown in FIG. 48, a liquid crystal display device having a wide viewing angle, a fast response speed, and a high contrast can be obtained.

The pixel structure of a PVA type liquid crystal display device will be described with reference to Fig. 48A. A liquid crystal display device has a key part for displaying images, called a liquid crystal panel. A liquid crystal panel is made by bonding two processed substrates with a gap of several micrometers between them.
The liquid crystal display is fabricated by injecting a liquid crystal material between two substrates. In FIG. 48A, the two substrates are a first substrate 10301 and a second substrate 10316. The first substrate is a T
The FT and pixel electrodes are formed on the second substrate, and the second substrate is provided with a light-shielding film 10314, a color filter 10315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10318.
312 may be fabricated.

It should be noted that this embodiment mode can be implemented without fabricating a TFT on the first substrate 10301. When this embodiment mode is implemented without fabricating a TFT, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when this embodiment mode is implemented by fabricating a TFT, a larger display device can be obtained.

The TFT shown in FIG. 48 is a bottom-gate type TFT using an amorphous semiconductor. A liquid crystal panel that uses a TFT using an amorphous semiconductor has the advantage that it can be manufactured inexpensively using a large-area substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used for a bottom-gate type TFT includes a channel etch type and a channel protection type. A top-gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

It should be noted that this embodiment can be implemented without forming the light-shielding film 10314 on the second substrate 10316. When this embodiment is implemented without forming the light-shielding film 10314, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment is implemented by forming the light-shielding film 10314, a display device with little light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without fabricating the color filter 10315 on the second substrate 10316. When this embodiment mode is implemented without fabricating the color filter 10315, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without fabricating the color filter 10315, a display device capable of color display by field sequential driving can be obtained. On the other hand, when this embodiment mode is implemented by fabricating the color filter 10315, a display device capable of color display can be obtained.

This embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10317 on the second substrate 10316. When this embodiment mode is implemented by dispersing spherical spacers, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, the structure is simple, and therefore the yield can be improved. On the other hand, the spacers 103
When the present embodiment is carried out by manufacturing the substrate 17, the position of the spacer does not vary, so that
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, the processing of the first substrate 10301 may be performed by the method described in FIG. 46, so the description will be omitted. Here, the first substrate 10301, the first insulating film 10302, the first conductive layer 10303, the second insulating film 10304, the first semiconductor layer 10305, the second semiconductor layer 10306, the second conductive layer 10307, the third insulating film 10308, the third conductive layer 10309, the third insulating film 10310, the third conductive layer 10311, the third insulating film 10312, the third conductive layer 10313, the third conductive layer 10314, the third insulating film 10315, the third conductive layer 10316, the third conductive layer 10317, the third conductive layer 10318, the third conductive layer 10319 ... first conductive layer 10319, the first conductive layer 10319, the second conductive layer 10319, the third conductive layer 10319, the first conductive layer 10319, the first conductive layer 10319, the second
46. The first alignment film 10310 corresponds to the first substrate 10101 and the first alignment film 10310 in FIG.
The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, and the third insulating film 10
108, a third conductive layer 10109, and a first alignment film 10110. An electrode cutout may be provided in the third conductive layer 10309 on the first substrate 10301 side. This makes it possible to more reliably control the alignment of the liquid crystal molecules.
The first alignment film 310 and the second alignment film 10312 may be vertical alignment films, which allows the liquid crystal molecules 10318 to be vertically aligned.

The first substrate 10301, the light-shielding film 10314, and the color filter 10
315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10312
The second substrate 10316 on which the above-mentioned is prepared is bonded with a gap of several μm by a sealant, and liquid crystal material is injected between the two substrates to prepare a liquid crystal panel. In the PVA type liquid crystal panel shown in FIG. 48, the fourth conductive layer 10313 may be patterned to prepare an electrode cutout 10319. The shape of the electrode cutout 10319 is not limited, but it is preferable that the shape is a combination of multiple rectangles with different orientations. In this way, multiple regions with different orientations can be formed, so that a liquid crystal display device with a large viewing angle can be obtained. In addition, it is preferable that the shape of the fourth conductive layer 10313 at the boundary between the electrode cutout 10319 and the fourth conductive layer 10313 is a smooth curve. In this way, the orientation of the adjacent liquid crystal molecules 10318 becomes very close, so that alignment defects are reduced. In addition, when the second alignment film 10312 is formed in the electrode cutout 10319, the electrode cutout 10319 is formed in a shape that is different from the shape of the fourth conductive layer 10313.
It is also possible to reduce defects in the alignment film caused by step breaks caused by the step 319.

Next, the characteristics of the pixel structure of the PVA type liquid crystal panel shown in FIG.
The liquid crystal molecule 10318 shown in FIG. 48(A) is a long and thin molecule with a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecule 10318, it is expressed by its length in FIG. 48(A). That is, the longer the liquid crystal molecule 10318 is expressed, the longer its long axis is parallel to the paper surface, and the shorter the liquid crystal molecule 10318 is expressed, the closer its long axis is to the normal direction to the paper surface. In other words, the liquid crystal molecule 10318 shown in FIG. 48(A) is oriented so that its long axis is oriented in the normal direction to the alignment film. Therefore, the electrode cutout portion 1031
The liquid crystal molecules 10318 in the portion where the fourth conductive layer 103 is located are in contact with the electrode cutout portion 10319 and the fourth conductive layer 103
The molecules are aligned radially from the boundary of 13. In this state, a liquid crystal display device with a wide viewing angle can be obtained.

Next, an example of a pixel layout when this embodiment is applied to a PVA type liquid crystal display device will be described with reference to Fig. 48B. A pixel of the PVA type liquid crystal display device to which this embodiment is applied is composed of a scanning line 10321, a video signal line 10322, and a capacitance line 1033.
23, a TFT 10324, a pixel electrode 10325, a pixel capacitance 10326, and an electrode cutout portion 10319.

Since the scanning line 10321 is electrically connected to the gate electrode of the TFT 10324 , it is preferable that the scanning line 10321 is made of the first conductive layer 10303 .

The video signal line 10322 is preferably made of the second conductive layer 10307 since it is electrically connected to the source electrode or drain electrode of the TFT 10324. In addition, since the scanning line 10321 and the video signal line 10322 are arranged in a matrix, at least
It is preferably formed of different conductive layers.

The capacitance line 10323 is arranged in parallel with the pixel electrode 10325, so that the pixel capacitance 1032
48B, the capacitance line 10323 may be extended along the video signal line 10322 so as to surround the video signal line 10322. This can reduce so-called crosstalk, a phenomenon in which the potential of an electrode that should hold a potential changes with a change in potential of the video signal line 10322. In order to reduce the intersection capacitance with the video signal line 10322, the capacitance line 10323 may be extended along the video signal line 10322 so as to surround the video signal line 10322.
may be provided in the intersecting region of the capacitance line 10323 and the video signal line 10322.

The TFT 10324 operates as a switch that connects the video signal line 10322 and the pixel electrode 10325. As shown in FIG. 48B, either the source region or the drain region of the TFT 10324 may be disposed so as to surround the other of the source region or the drain region. In this way, a large channel width can be obtained in a small area, and the switching capability can be increased. As shown in FIG. 48B, the TFT
The gate electrode 10324 may be disposed to surround the first semiconductor layer 10305 .

The pixel electrode 10325 is electrically connected to one of the source electrode or the drain electrode of the TFT 10324. The pixel electrode 10325 is an electrode for applying a signal voltage transmitted by the video signal line 10322 to the liquid crystal element. In addition, by arranging the capacitance line 10323,
A pixel capacitor 10326 may be formed. This makes it easier for the pixel electrode 10325 to hold the signal voltage transmitted by the video signal line 10322.
48B, the pixel electrode 103 is formed in a portion where there is no electrode cutout 10319 in accordance with the shape of the electrode cutout 10319 provided in the fourth conductive layer 10313.
It is preferable to form a cutout portion 25. In this way, the liquid crystal molecule 10318
Since it is possible to form a plurality of regions in which the orientation of the liquid crystal molecules is different, it is possible to obtain a liquid crystal display device having a wide viewing angle.
A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. In addition, when the pixel electrode 10325 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in bright environments such as outdoors, and does not require a backlight, so that power consumption can be very small. When the pixel electrode 10325 is made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device that combines the advantages of both can be obtained. When the pixel electrode 10325 is made of a reflective material, the surface of the pixel electrode 10325 may be made uneven. Alternatively, the pixel electrode 10325 can be made uneven by making the surface of the third insulating film 10308 uneven. This has the advantage that the reflected light is diffused, so that the angle dependency of the intensity distribution of the reflected light is reduced. In other words, a reflective liquid crystal display device with a constant brightness can be obtained regardless of the angle at which it is viewed.

Next, with reference to FIG. 49, a case where this embodiment is applied to a liquid crystal display device of a horizontal electric field type will be described. FIG. 49 shows a cross-sectional view and a top view of a pixel when this embodiment is applied to a so-called IPS (In-Plane-Switching) type, which is a type of a liquid crystal display device in which an electric field is applied in the horizontal direction by performing comb-teeth patterning on the pixel electrode 10425 and the common electrode 10423, among pixel structures of the type of liquid crystal display device in which switching is performed so that the orientation of liquid crystal molecules is always horizontal to the substrate. FIG. 49(A) is a cross-sectional view of a pixel, and FIG. 49(B) is a top view of a pixel. The cross-sectional view of the pixel shown in FIG. 49(A) corresponds to the line segment a-a' in the top view of the pixel shown in FIG. 49(B). By applying this embodiment to a liquid crystal display device having the pixel structure shown in FIG. 49, a liquid crystal display device with a large viewing angle and small grayscale dependency of response speed can be obtained in principle.

The pixel structure of an IPS type liquid crystal display device will be described with reference to Fig. 49A. A liquid crystal display device has a core part for displaying images, called a liquid crystal panel. A liquid crystal panel is fabricated by bonding two processed substrates with a gap of several μm between them and injecting liquid crystal material between the two substrates. In Fig. 49A, the two substrates are a first substrate 10401 and a second substrate 10416. TFTs and pixel electrodes are fabricated on the first substrate, and a light-shielding film 10414, a color filter 10415, and a color filter 10416 are fabricated on the second substrate.
, spacers 10417, and a second alignment film 10412 may be fabricated.

It should be noted that this embodiment mode can be implemented without fabricating a TFT on the first substrate 10401. When this embodiment mode is implemented without fabricating a TFT, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when this embodiment mode is implemented by fabricating a TFT, a larger display device can be obtained.

The TFT shown in FIG. 49 is a bottom-gate type TFT using an amorphous semiconductor. A liquid crystal panel that uses a TFT using an amorphous semiconductor has the advantage that it can be manufactured inexpensively using a large-area substrate. However, this embodiment is not limited to this. The structure of the TFT that can be used for a bottom-gate type TFT includes a channel etch type and a channel protection type. A top-gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

It should be noted that this embodiment can be implemented without forming the light-shielding film 10414 on the second substrate 10416. When this embodiment is implemented without forming the light-shielding film 10414, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment is implemented by forming the light-shielding film 10414, a display device with little light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without fabricating the color filter 10415 on the second substrate 10416. When this embodiment mode is implemented without fabricating the color filter 10415, the number of steps is reduced, and therefore the manufacturing cost can be reduced. However, even when this embodiment mode is implemented without fabricating the color filter 10415, a display device capable of color display by field sequential driving can be obtained. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment mode is implemented by fabricating the color filter 10415, a display device capable of color display can be obtained.

This embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10417 on the second substrate 10416. When this embodiment mode is implemented by dispersing spherical spacers, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, the spacers 104
When the present embodiment is carried out by manufacturing the substrate 17, the position of the spacer does not vary, so that
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, the processing of the first substrate 10401 may be performed by the method described in FIG. 46, so the description will be omitted. Here, the first substrate 10401, the first insulating film 10402, the first conductive layer 10403, the second insulating film 10404, the first semiconductor layer 10405, the second semiconductor layer 10406, the second conductive layer 10407, the third insulating film 10408, the third conductive layer 10409, the third insulating film 10410, the third conductive layer 10411, the third insulating film 10412, the third conductive layer 10413, the third conductive layer 10414, the first insulating film 10415, the first conductive layer 10416, the second conductive layer 10417, the third insulating film 10418, the third conductive layer 10419, the third conductive layer 10420
46. The first alignment film 10410 corresponds to the first substrate 10101 and the first alignment film 10410 in FIG.
The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, and the third insulating film 10
The third conductive layer 10409 on the first substrate 10401 side is patterned to form two interlocking electrodes.
Alternatively, one of the comb-shaped electrodes may be electrically connected to one of the source electrode and the drain electrode of the TFT 10424, and the other comb-shaped electrode may be electrically connected to the common electrode 10423.
Therefore, a lateral electric field can be effectively applied to the

The first substrate 10401, the light-shielding film 10414, and the color filter 10414 are fabricated as described above.
415, a spacer 10417, and a second alignment film 10412 are formed on the second substrate 10
The liquid crystal panel can be manufactured by bonding the two substrates 416 together with a gap of several micrometers using a sealant and injecting liquid crystal material between the two substrates.
A conductive layer may be formed on the second substrate 10416 side. By forming a conductive layer on the second substrate 10416 side, the device can be less susceptible to the influence of external electromagnetic noise.

Next, the characteristics of the pixel structure of the IPS liquid crystal panel shown in FIG.
The liquid crystal molecule 10418 shown in FIG. 49(A) is a long and thin molecule with a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecule 10418, it is expressed by its length in FIG. 49(A). That is, the longer the liquid crystal molecule 10418 is expressed, the longer its long axis is parallel to the paper surface, and the shorter the liquid crystal molecule 10418 is expressed, the closer its long axis is to the normal direction to the paper surface. In other words, the liquid crystal molecule 10418 shown in FIG. 49(A) is oriented so that its long axis always faces the direction horizontal to the substrate. In FIG. 49(A),
Although the orientation is shown in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10418, the direction of the long axis of the molecules rotates within the horizontal plane while always maintaining a direction parallel to the substrate. This state allows a liquid crystal display device with a wide viewing angle to be obtained.

Next, an example of a pixel layout when this embodiment is applied to an IPS liquid crystal display device will be described with reference to Fig. 49B. A pixel of the IPS liquid crystal display device to which this embodiment is applied is composed of a scanning line 10421, a video signal line 10422, and a common electrode 1043.
423, a TFT 10424, and a pixel electrode 10425.

Since the scanning line 10421 is electrically connected to the gate electrode of the TFT 10424 , it is preferable that the scanning line 10421 is made of the first conductive layer 10403 .

The video signal line 10422 is preferably made of the second conductive layer 10407 since it is electrically connected to the source electrode or drain electrode of the TFT 10424. In addition, since the scanning line 10421 and the video signal line 10422 are arranged in a matrix, at least
It is preferable that the image signal line 10422 is formed of a conductive layer of a different layer. As shown in Fig. 49B, the image signal line 10422 may be bent in the pixel so as to match the shapes of the pixel electrode 10425 and the common electrode 10423. This can increase the aperture ratio of the pixel, thereby improving the efficiency of the liquid crystal display device.

The common electrode 10423 is an electrode for generating a horizontal electric field by being disposed in parallel with the pixel electrode 10425, and is preferably composed of a first conductive layer 10403 and a third conductive layer 10409. As shown in FIG. 49B, the common electrode 1042
3 may be provided extending along the video signal line 10422 so as to surround the video signal line 10422. In this way, it is possible to reduce a phenomenon in which the potential of an electrode that is to hold a potential changes in accordance with a change in the potential of the video signal line 10422, that is, so-called crosstalk.
In order to reduce the intersection capacitance with the video signal line 10422, a first semiconductor layer 10405 may be provided in the intersection region between the common electrode 10423 and the video signal line 10422 as shown in FIG.

The TFT 10424 operates as a switch that connects the video signal line 10422 and the pixel electrode 10425. As shown in FIG. 49B, either the source region or the drain region of the TFT 10424 may be disposed so as to surround the other of the source region or the drain region. In this way, a large channel width can be obtained in a small area, and the switching capability can be increased. As shown in FIG. 49B, the TFT
The gate electrode 10424 may be disposed to surround the first semiconductor layer 10405 .

The pixel electrode 10425 is electrically connected to one of the source electrode or the drain electrode of the TFT 10424. The pixel electrode 10425 is an electrode for applying a signal voltage transmitted by the video signal line 10422 to the liquid crystal element. A pixel capacitance may be formed by disposing a common electrode 10423. In this way, the pixel electrode 10325 is connected to the video signal line 10422.
422, the signal voltage transmitted by the common electrode 10423 is easily retained. It is preferable to form the pixel electrode 10425 and the comb-shaped common electrode 10423 in a bent comb-like shape, as shown in FIG. 49B. This makes it possible to form a plurality of regions in which the orientation of the liquid crystal molecules 10418 is different, and therefore it is possible to obtain a liquid crystal display device with a wide viewing angle. Furthermore, when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a transparent material, it is possible to obtain a transmissive liquid crystal display device. A transmissive liquid crystal display device has the following features:
It is possible to display images with high color reproducibility and high image quality. Furthermore, in a transmissive liquid crystal display device, the pixels have a high aperture ratio, and light efficiency can be improved. However, even if the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a material that is not transparent and does not have reflectivity, a transmissive liquid crystal display device can be obtained. In this transmissive liquid crystal display device, light is transmitted only through the liquid crystal molecules 10418 in the portion where a lateral electric field exists, so that it is possible to display images with high color reproducibility and high image quality. Furthermore, when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a material that has reflectivity,
A semi-transmissive liquid crystal display device can be obtained. The semi-transmissive liquid crystal display device has high visibility in bright environments such as outdoors, and can consume very little power.
A semi-transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. However, a semi-transmissive liquid crystal display device can also be obtained when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of both a transparent material and a reflective material. When the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a reflective material, the pixel electrode 10425 and the comb-shaped common electrode 10423 can be made of a reflective material.
Alternatively, the surface of the third insulating film 10408 may be made uneven, so that the pixel electrode 10425 and the comb-shaped common electrode 10423 can also be made uneven. This has the advantage that the reflected light is diffused, so that the angle dependency of the intensity distribution of the reflected light is reduced. In other words, it is possible to obtain a reflective liquid crystal display device that has a constant brightness regardless of the viewing angle.

In addition, although both the comb-shaped pixel electrode 10425 and the comb-shaped common electrode 10423 are formed of the third conductive layer 10409, the pixel configuration to which this embodiment can be applied is not limited to this and can be appropriately selected. For example, both the comb-shaped pixel electrode 10425 and the comb-shaped common electrode 10423 may be formed of the second conductive layer 10407, or both may be formed of the first conductive layer 10403, or one of them may be formed of the third conductive layer 10409 and the other of the second conductive layer 10407, or one of them may be formed of the third conductive layer 10409 and the other of the first conductive layer 10407, or one of them may be formed of the second conductive layer 10409 and the other of the first conductive layer 10407.

Next, with reference to Fig. 50, a case where this embodiment is applied to another horizontal electric field type liquid crystal display device will be described. Fig. 50 is a diagram showing another pixel structure of a liquid crystal display device in which an electric field is applied in the horizontal direction in order to perform switching so that the orientation of liquid crystal molecules is always horizontal to the substrate. More specifically, this is a type in which either one of the pixel electrode 10525 or the common electrode 10523 is patterned in a comb-like shape, and the other is uniformly formed in an area overlapping the comb-like shape, thereby applying an electric field in the horizontal direction, a so-called FFS (Fringe Field Switching) type.
50A is a cross-sectional view of a pixel, and FIG. 50B is a top view of a pixel when this embodiment mode is applied to a switching method.
Also, the cross-sectional view of the pixel shown in Fig. 50A corresponds to the line segment a-a' in the top view of the pixel shown in Fig. 50B. By applying this embodiment to a liquid crystal display device having the pixel structure shown in Fig. 50, it is possible to obtain a liquid crystal display device which has a large viewing angle and small grayscale dependency of the response speed in principle.

The pixel structure of an FFS-type liquid crystal display device will be described with reference to Fig. 50A. A liquid crystal display device has a core portion for displaying images, called a liquid crystal panel. A liquid crystal panel is fabricated by bonding two processed substrates together with a gap of several micrometers between them, and injecting liquid crystal material between the two substrates. In Fig. 50A, the two substrates are a first substrate 10501 and a second substrate 10516. The first substrate has a TFT
and a pixel electrode are formed on the second substrate.
5, a spacer 10517, and a second alignment film 10512 may be fabricated.

It should be noted that this embodiment mode can be implemented without fabricating a TFT on the first substrate 10501. When this embodiment mode is implemented without fabricating a TFT, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment mode is implemented by fabricating a TFT, a larger display device can be obtained.

The TFT shown in FIG. 50 is a bottom-gate type TFT using an amorphous semiconductor. A liquid crystal panel that uses a TFT using an amorphous semiconductor has the advantage that it can be manufactured inexpensively using a large-area substrate. However, this embodiment is not limited to this. Examples of the structure of the TFT that can be used for bottom-gate type TFTs include a channel-etch type and a channel-protected type. A top-gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

It should be noted that this embodiment can be implemented without forming the light-shielding film 10514 on the second substrate 10516. When this embodiment is implemented without forming the light-shielding film 10514, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when this embodiment is implemented by forming the light-shielding film 10514, a display device with little light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without fabricating the color filter 10515 on the second substrate 10516. When this embodiment mode is implemented without fabricating the color filter 10515, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without fabricating the color filter 10515, a display device capable of color display by field sequential driving can be obtained. On the other hand, when this embodiment mode is implemented by fabricating the color filter 10515, a display device capable of color display can be obtained.

This embodiment mode can also be implemented by dispersing spherical spacers instead of forming the spacers 10517 on the second substrate 10516. When this embodiment mode is implemented by dispersing spherical spacers, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, the spacers 105
When the present embodiment is carried out by manufacturing the substrate 17, the position of the spacer does not vary, so that
The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained.

Next, the processing of the first substrate 10501 may be performed by the method described in FIG. 46, so the description will be omitted. Here, the first substrate 10501, the first insulating film 10502, the first conductive layer 10503, the second insulating film 10504, the first semiconductor layer 10505, the second semiconductor layer 10506, the second conductive layer 10507, the third insulating film 10508, the third conductive layer 10509, the third insulating film 10510, the third conductive layer 10511, the third conductive layer 10512, the third insulating film 10513, the third conductive layer 10514, the third conductive layer 10515, the third conductive layer 10516, the third conductive layer 10517, the third conductive layer 10518, the third conductive layer 10519 ... first conductive layer 10519, the first conductive layer 10519, the second conductive layer 10519, the third conductive layer 10519, the first conductive layer 10519, the first
46. The first alignment film 10510 corresponds to the first substrate 10101 and the first alignment film 10510 in FIG.
The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, and the third insulating film 10
108, a third conductive layer 10109, and a first alignment film 10110.

However, the difference from FIG. 46 is that a fourth insulating film 10519 and a fourth conductive layer 10513 may be formed on the first substrate 10501 side. More specifically, after the third conductive layer 10509 is patterned, the fourth insulating film 10519 is formed, patterned to form contact holes, and then the fourth conductive layer 10513 is formed and similarly patterned, and then the first alignment film 10510 may be formed. Note that the materials and processing methods usable for the fourth insulating film 10519 and the fourth conductive layer 10513 may be the same as those used for the third insulating film 10508 and the third conductive layer 10509. In addition, one comb-shaped electrode may be electrically connected to one of the source electrode or drain electrode of the TFT 10524, and the other uniform electrode may be electrically connected to the common electrode 10523. This allows a lateral electric field to be effectively applied to the liquid crystal molecules 10518.

The first substrate 10501, the light-shielding film 10514, and the color filter 10
515, a spacer 10517, and a second alignment film 10512 are formed on the second substrate 10
A liquid crystal panel can be manufactured by bonding the two substrates 10516 with a gap of several micrometers using a sealant and injecting a liquid crystal material between the two substrates. Although not shown, a conductive layer may be formed on the second substrate 10516 side. By forming a conductive layer on the second substrate 10516 side, it is possible to reduce the influence of electromagnetic noise from the outside.

Next, the characteristics of the pixel structure of the FFS type liquid crystal panel shown in FIG.
The liquid crystal molecule 10518 shown in FIG. 50(A) is a long, thin molecule with a long axis and a short axis. In order to indicate the orientation of the liquid crystal molecule 10518, it is expressed by its length in FIG. 50(A). That is, the longer the liquid crystal molecule 10518 is expressed, the longer its long axis is parallel to the paper surface, and the shorter the liquid crystal molecule 10518 is expressed, the closer its long axis is to the normal direction to the paper surface. In other words, the liquid crystal molecule 10518 shown in FIG. 50(A) is oriented so that its long axis always faces a direction horizontal to the substrate. In FIG. 50(A),
Although the orientation is shown in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10518, the direction of the long axis of the molecules rotates within the horizontal plane while always maintaining a direction parallel to the substrate. This state allows a liquid crystal display device with a wide viewing angle to be obtained.

Next, an example of a pixel layout when this embodiment is applied to an FFS-type liquid crystal display device will be described with reference to Fig. 50B. A pixel of the FFS-type liquid crystal display device to which this embodiment is applied is composed of a scanning line 10521, a video signal line 10522, and a common electrode 10523.
523, a TFT 10524, and a pixel electrode 10525.

Since the scanning line 10521 is electrically connected to the gate electrode of the TFT 10524 , it is preferable that the scanning line 10521 is made of the first conductive layer 10503 .

Since the video signal line 10522 is electrically connected to the source electrode or drain electrode of the TFT 10524, it is preferable that the video signal line 10522 is made of the second conductive layer 10507. In addition, since the scanning line 10521 and the video signal line 10522 are arranged in a matrix, at least
It is preferable that the image signal line 10522 is formed of a conductive layer of a different layer. As shown in FIG. 50B, the image signal line 10522 may be bent in the pixel so as to match the shape of the pixel electrode 10525. This can increase the aperture ratio of the pixel.
The efficiency of the liquid crystal display device can be improved.

The common electrode 10523 is preferably composed of a first conductive layer 10503 and a third conductive layer 10509. In order to reduce the cross capacitance with the video signal line 10522,
As shown in FIG. 50B, the first semiconductor layer 10505 may be provided in the intersecting region of the common electrode 10523 and the video signal line 10522 .

The TFT 10524 operates as a switch that connects the video signal line 10522 and the pixel electrode 10525. As shown in FIG. 50B, either the source region or the drain region of the TFT 10524 may be disposed so as to surround the other of the source region or the drain region. In this way, a large channel width can be obtained in a small area, and the switching capability can be increased. As shown in FIG. 50B, the TFT
The gate electrode 10524 may be disposed to surround the first semiconductor layer 10505 .

The pixel electrode 10525 is electrically connected to one of the source electrode or the drain electrode of the TFT 10524. The pixel electrode 10525 is an electrode for applying a signal voltage transmitted by the video signal line 10522 to the liquid crystal element. In addition, a pixel capacitance may be formed by disposing a common electrode 10523. In this way, the pixel electrode 10525 is connected to the video signal line 10522.
The pixel electrode 10525 is easily able to hold the signal voltage transmitted by the pixel electrode 10522.
As shown in Fig. 50B, it is preferable to form the pixel electrode 1052 in a bent comb shape. This makes it possible to form a plurality of regions in which the liquid crystal molecules 10518 are aligned differently, thereby making it possible to obtain a liquid crystal display device with a wide viewing angle.
5 and the common electrode 10523 are made of a transparent material, a transmissive liquid crystal display device can be obtained. However, even if the comb-tooth pixel electrode 10525 is made of a material that does not have reflectivity and the common electrode 10523 is made of a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display images with high image quality. Furthermore, if the comb-tooth pixel electrode 10525 and the common electrode 10523 are made of a reflective material, a reflective liquid crystal display device can be obtained. However, if at least the common electrode 10523 is made of a reflective material, a reflective liquid crystal display device can be obtained. A reflective liquid crystal display device has high visibility in a bright environment such as outdoors, and does not require a backlight, so that power consumption can be made very small. Note that, if the comb-tooth pixel electrode 10525 and the common electrode 10523 are made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device that combines the advantages of both can be obtained. However, if the comb-tooth pixel electrode 10525 and the common electrode 10523 are made of a material that does not have reflectivity, a transmissive liquid crystal display device that combines the advantages of both can be obtained.
Even if the third insulating film 10508 is made of a reflective material and the pixel electrode 10525 is made of a transparent material, a semi-transmissive liquid crystal display device can be obtained. When the pixel electrode 10525 and the comb-shaped common electrode 10523 are made of a reflective material, the surfaces of the comb-shaped pixel electrode 10525 and the common electrode 10523 may be made uneven. Alternatively, the comb-shaped pixel electrode 10525 and the common electrode 10523 can be made uneven by making the surface of the third insulating film 10508 uneven. This has the advantage that the reflected light is diffused, so that the angle dependency of the intensity distribution of the reflected light is reduced. In other words, a reflective liquid crystal display device with a constant brightness can be obtained regardless of the angle at which it is viewed.

Although the comb-shaped pixel electrode 10525 is formed of the fourth conductive layer 10513 and the uniform common electrode 10523 is formed of the third conductive layer 10509, the pixel configuration to which this embodiment can be applied is not limited to this, and can be appropriately selected as long as certain conditions are satisfied. More specifically, it is sufficient that the comb-shaped electrode is located closer to the liquid crystal than the uniform electrode when viewed from the first substrate 10501. This is because the horizontal electric field is always generated in the opposite direction to the uniform electrode when viewed from the comb-shaped electrode. In other words, in order to apply a horizontal electric field to the liquid crystal, the comb-shaped electrode must be located closer to the liquid crystal than the uniform electrode.

To satisfy this condition, for example, a comb-shaped electrode may be formed of the fourth conductive layer 10513 and a uniform electrode may be formed of the third conductive layer 10509, or a comb-shaped electrode may be formed of the fourth conductive layer 10514 and a uniform electrode may be formed of the third conductive layer 10509.
Alternatively, a comb-tooth-shaped electrode may be formed with the fourth conductive layer 10513 and a uniform electrode may be formed with the first conductive layer 10503, a comb-tooth-shaped electrode may be formed with the third conductive layer 10509 and a uniform electrode may be formed with the second conductive layer 10507, a comb-tooth-shaped electrode may be formed with the third conductive layer 10509 and a uniform electrode may be formed with the first conductive layer 10503, or a comb-tooth-shaped electrode may be formed with the third conductive layer 10509 and a uniform electrode may be formed with the first conductive layer 10503.
0507, and the uniform electrode may be formed of the first conductive layer 10503. Note that the comb-shaped electrode is electrically connected to one of the source region or the drain region of the TFT 10524, and the uniform electrode is electrically connected to the common electrode 10523, but this connection may be reversed. In that case, the uniform electrode may be formed independently for each pixel.

Next, we will explain various liquid crystal modes that can be applied to the liquid crystal display device of this embodiment.

First, Figure 51 (A1) and (A2) show schematic diagrams of a TN mode liquid crystal display device.

As in the above embodiment, a liquid crystal layer 10600 is sandwiched between a first substrate 10601 and a second substrate 10602 that are arranged to face each other.
A layer 10603 including a first polarizer is laminated on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side.
The layer 603 and the layer including the second polarizer 10604 are arranged in a crossed Nicol state.

Although not shown, a backlight or the like is disposed outside the layer including the second polarizer.
A second electrode 10606 is provided on the opposite side to the backlight, that is, the first electrode 10605 which is an electrode on the viewing side, is formed to have at least light-transmitting properties.

In a liquid crystal display device having a structure as shown in Fig. 51 (A1) and (A2), in the case of a normally white mode, when a voltage is applied to the first electrode 10605 and the second electrode 10606 (called a vertical electric field mode), black display is performed as shown in Fig. 51 (A1). At this time, the liquid crystal molecules are vertically aligned. Then, light from the backlight cannot pass through the substrate, and black display is performed.

Then, as shown in FIG. 51A2, the first electrode 10605 and the second electrode 10606
When no voltage is applied between the liquid crystal molecules, the liquid crystal displays white.
As a result, light from the backlight can pass through the layer including a pair of polarizers arranged in a crossed Nicol state (the layer including a first polarizer 10603 and the layer including a second polarizer 10604), and a predetermined image is displayed.

A liquid crystal display device having a structure as shown in FIG. 51 (A1) (A2) can perform full color display by providing a color filter. The color filter is a filter that is formed on the first substrate 10.
The second substrate 10602 may be provided on either the first substrate 10601 side or the second substrate 10602 side.
A liquid crystal display device having a configuration such as that shown in FIG. 1 (A1) or (A2) can perform full color display by field sequential driving as long as the light from the backlight changes with time, even without providing a color filter.

The liquid crystal material used in TN mode can be any known material.

51(B1) is a schematic diagram of a VA mode liquid crystal display device. The VA mode is a mode in which liquid crystal molecules are aligned perpendicular to the substrate when no electric field is applied.

51A1 and 51A2, a first electrode 10605 and a second electrode 10606 are provided on a first substrate 10601 and a second substrate 10602, respectively. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, on the viewing side, is formed to have at least light-transmitting properties. A layer 10603 including a first polarizer is laminated on the first substrate 10601 side, and a layer 10606 including a second polarizer is laminated on the second substrate 10602 side.
The first polarizer-including layer 10603 and the second polarizer-including layer 10604 are disposed in a crossed Nicol state.

In the liquid crystal display device having the structure shown in FIG. 51 (A1) and (A2), the first electrode 106
When a voltage is applied to the first electrode 10605 and the second electrode 10606 (vertical electric field method),
As shown in FIG. 1, the liquid crystal molecules are aligned horizontally in the on-state, and the light from the backlight is polarized through a pair of layers including polarizers arranged in a crossed Nicol state (a layer including a first polarizer 10603 and a layer including a second polarizer 10604).
) can pass through the first substrate 10, and a desired image can be displayed. At this time, by providing a color filter, full color display can be performed. The color filter is
It can be provided on either the 601 side or the second substrate 10602 side.

Then, as shown in FIG. 51B2, the first electrode 10605 and the second electrode 10606
When no voltage is applied between the substrates, the display shows black, i.e., the OFF state. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrates, and the display shows black.

In the off state, the liquid crystal molecules stand vertically to the substrate, resulting in a black display, and in the on state, the liquid crystal molecules lie horizontally to the substrate, resulting in a white display. Because the liquid crystal molecules stand up in the off state, polarized light from the backlight passes through the cell without being affected by the birefringence of the liquid crystal molecules, and can be blocked by the layer containing the polarizer on the opposing substrate side.

Here, an example in which a layer including stacked polarizers according to this embodiment mode is applied to an MVA mode in which the alignment of liquid crystal is divided is shown in Figs. 51C1 and 51C2. The MVA mode is a method of mutually compensating for the viewing angle dependence of each part. As shown in Fig. 51C1, in the MVA mode, protrusions 10607 and 10608 with triangular cross sections are provided on the first electrode 10605 and the second electrode 10606 for alignment control.
When a voltage is applied to the electrode 10606 (vertical electric field type), the liquid crystal is turned on to display white as shown in FIG.
8. Then, light from the backlight can pass through a layer including a pair of polarizers arranged to be crossed Nicols (a layer including a first polarizer 10603 and a layer including a second polarizer 10604), and a predetermined image is displayed. Note that a liquid crystal display device having a structure as shown in FIG. 51C1 or C2 can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in FIG. 51C1 or C2 can perform full-color display by field sequential driving even without providing a color filter.

Then, as shown in FIG. 51C2, the first electrode 10605 and the second electrode 1060
When no voltage is applied between the substrates 6, a black display is produced, i.e., the OFF state. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrates, resulting in a black display.

Another example of the MVA mode is shown in a top view and a cross-sectional view in Fig. 54. As shown in Fig. 54(A), the second electrodes 10606a, 10606b, and 10606c may be formed in a bent pattern like a dogleg. Also, insulating layers 10901 and 10902 are formed in the vicinity of the liquid crystal layer 10600. Note that the insulating layers 10901 and 10902 may be alignment films. As shown in Fig. 54(B), a protrusion 1 is formed in the vicinity of the first electrode 10605.
The protrusions 10607 may be formed corresponding to the second electrodes 10606a, 10606b, and 10606c.
By forming the second electrodes 10606a, 10606b, 10606
The openings c function as protrusions and can effectively align the liquid crystal molecules. Note that the order in which the first electrode 10605 and the protrusions 10607 are formed may be reversed from that shown in FIG.

52(A1) and (A2) are schematic diagrams of an OCB mode liquid crystal display device. In the OCB mode, the alignment of liquid crystal molecules in the liquid crystal layer forms an optically compensated state, which is called a bend alignment.

As in Fig. 51, a first electrode 10605 and a second electrode 10606 are provided on a first substrate 10601 and a second substrate 10602, respectively. Although not shown, a backlight or the like is disposed outside the layer 10604 including a second polarizer. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, the viewing side, is formed to have at least light transmitting properties. The layer 10604 including a first polarizer is disposed on the first substrate 10601 side.
A layer including a second polarizer 10603 is laminated on the second substrate 10602 side, and a layer including a second polarizer 10604 is disposed on the second substrate 10602 side.
The optical fiber 604 is disposed in a crossed Nicol state.

In the liquid crystal display device having the structure shown in FIG. 52(A1) and (A2), the first electrode 106
When a constant on-voltage is applied to the first electrode 10605 and the second electrode 10606 (vertical electric field method),
2 (A1), black display is performed. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, and black display is performed.

Then, as shown in FIG. 52A2, the first electrode 10605 and the second electrode 1060
When a constant off voltage is applied between the electrodes 10603 and 10604, a white display is obtained. At this time, the liquid crystal molecules are in a bend alignment state. As a result, light from the backlight can pass through a layer including a pair of polarizers arranged in a crossed Nicol state (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer), and a predetermined image is displayed.
A liquid crystal display device having the structure as shown in FIG. 52 (A1) or (A2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side.
1) A liquid crystal display device having a configuration such as (A2) can perform full color display by field sequential driving without providing a color filter.

In the OCB mode as shown in Figures 52 (A1) and (A2), the arrangement of liquid crystal molecules can be optically compensated within the liquid crystal layer, so there is little viewing angle dependence, and further, the contrast ratio can be increased by using a layer including a pair of stacked polarizers.

Figures 52 (B1) and (B2) show schematic diagrams of liquid crystal in FLC mode and AFLC mode.

51, a first electrode 10605 and a second electrode 10606 are provided on a first substrate 10601 and a second substrate 10602, respectively. The first electrode 10605, which is an electrode on the side opposite to the backlight, that is, the viewing side, is formed to have at least light transmitting properties. A layer 10603 including a first polarizer is formed on the first substrate 10601 side.
are laminated, and a layer including a second polarizer 10604 is disposed on the side of the second substrate 10602. Note that the layer including the first polarizer 10603 and the layer including the second polarizer 10604 are disposed to be in a crossed Nicol state.

In the liquid crystal display device having the structure shown in FIG. 52(B1) and (B2), the first electrode 106
When a voltage is applied to the first electrode 10605 and the second electrode 10606 (called a vertical electric field method), the
As shown in FIG. 1), white is displayed. At this time, the liquid crystal molecules are aligned horizontally in a direction shifted from the rubbing direction. Therefore, light from the backlight can pass through the layer including a pair of polarizers arranged in a crossed Nicol state (the layer including the first polarizer 10603 and the layer including the second polarizer 10604), and a predetermined image is displayed.

Then, as shown in FIG. 52B2, the first electrode 10605 and the second electrode 1060
When no voltage is applied between the substrates 6 and 7, black is displayed. The liquid crystal molecules are aligned horizontally along the rubbing direction. As a result, light from the backlight cannot pass through the substrates, resulting in a black display.

Note that a liquid crystal display device having a structure as shown in Fig. 52B1 or 52B2 can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in Fig. 52B1 or 52B2 can perform full-color display by field sequential driving even without providing a color filter.

The liquid crystal material used in the FLC mode and AFLC mode may be any known material.

53A1 and 53A2 are schematic diagrams of an IPS mode liquid crystal display device. The IPS mode is a mode in which liquid crystal molecules are always rotated in a plane relative to the substrate, and adopts a lateral electric field method in which electrodes are provided only on one of the substrates.

The IPS mode is characterized in that the liquid crystal is controlled by a pair of electrodes provided on one of the substrates. For this purpose, a pair of electrodes 10801 and 10802 are provided on a second substrate 10602. The pair of electrodes 10801 and 10802 may each have a light-shielding property. A layer 10603 including a first polarizer is laminated on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. The layer 10603 including the first polarizer and the layer 10604 including the second polarizer may be disposed in a crossed Nicol state.

In a liquid crystal display device having a configuration as shown in FIG. 53(A1)(A2), a pair of electrodes 10
When a voltage is applied to 801 and 10802, the liquid crystal molecules are oriented along electric field lines shifted from the rubbing direction, as shown in Fig. 53 (A1), resulting in an on-state in which white display is performed. Then, light from the backlight can pass through a layer including a pair of polarizers arranged in a crossed Nicol state (a layer including a first polarizer 10603 and a layer including a second polarizer 10604), and a predetermined image is displayed.

Note that a liquid crystal display device having a structure as shown in Figures 53A1 and 53A2 can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having a structure as shown in Figures 53A1 and 53A2 can perform full-color display by field sequential driving even without providing a color filter.

53A2, when no voltage is applied between the pair of electrodes 10801 and 10802, the liquid crystal display is in black, that is, in the off state. At this time, the liquid crystal molecules are aligned horizontally along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, and the liquid crystal display is in black.

An example of a pair of electrodes 10801 and 10802 that can be used in the IPS mode is shown in FIG. 55. In FIG. 55(A) to (D), the electrode 10801 is an electrode 10801a, an electrode 10801b, and an electrode 10802c.
801b, electrode 10801c, and electrode 10801d.
In Fig. 55A, the electrodes 10801a and 10802a have a wavy shape having undulations, in Fig. 55B, the electrodes 10801b and 10802b have a shape having concentric circular openings, and in Fig. 55C, the electrodes 10801c and 10802c have a shape having concentric circular openings.
In FIG. 55D, an electrode 10801d and an electrode 10802d have a comb-like shape and are partially overlapped with each other, and in FIG. 55D, an electrode 10801d and an electrode 10802d have a comb-like shape and are interdigitated with each other.

In addition to the IPS mode, the FFS mode can also be used. In the IPS mode, a pair of electrodes are formed on the same insulating film, whereas in the FFS mode, as shown in FIG.
As shown in 2), a pair of electrodes 10803 and 10804 may be formed on insulating films of different layers.

In a liquid crystal display device having a structure as shown in Fig. 53B1 and Fig. 53B2, when a voltage is applied to a pair of electrodes 10803 and 10804, the device is turned on to display white color as shown in Fig. 53B1. Then, light from the backlight can pass through a layer including a pair of polarizers arranged in a crossed Nicol state (a layer including a first polarizer 10603 and a layer including a second polarizer 10604), and a predetermined image is displayed.

Note that a liquid crystal display device having the structure shown in Fig. 53B1 or 53B2 can perform full color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, a liquid crystal display device having the structure shown in Fig. 53B1 or 53B2 can perform full color display by field sequential driving even without providing a color filter.

53B2, when no voltage is applied between the pair of electrodes 10803 and 10804, the liquid crystal display is in a black display, that is, in an off state. At this time, the liquid crystal molecules are aligned horizontally and rotated within the plane. As a result, the light from the backlight cannot pass through the substrate, and the liquid crystal display is in a black display.

An example of a pair of electrodes 10803 and 10804 that can be used in the FFS mode is shown in FIG. 56. In FIG. 56(A) to (D), the electrode 10803 is an electrode 10803a, an electrode 10803b, and an electrode 10804c.
803b, electrode 10803c, and electrode 10803d.
In FIG. 56A, the electrode 10803a has a bent L-shape, and the electrode 10804a has a bent L-shape.
4a does not have to be patterned in the pixel area.
56(C), the electrode 10803c is in a comb-like shape in which the electrodes interdigitate with each other, and the electrode 10804c does not have to be patterned in the pixel region.
In FIG. 56D, an electrode 10803d has a comb-like shape, and an electrode 10804d does not need to be patterned in the pixel region.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
The transparent film may have light-transmitting properties, which allows a transmissive display device with a large aperture ratio to be obtained.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
The film may have light-shielding or reflecting properties. By having light-shielding or reflecting properties, a reflective display device that does not require a backlight and consumes little power can be obtained.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
The display device may have both a light-transmitting region and a light-shielding or reflective region. By having both regions, it is possible to obtain a semi-transmissive display device that performs transmissive display with high display quality in a dark environment such as indoors and performs reflective display with low power consumption without requiring a backlight in a bright environment such as outdoors.

The liquid crystal materials used in IPS mode and FFS mode can be any known material.

In addition to the above-mentioned liquid crystal modes, ASM (Axially Symmetrically Aligned Micro-
cell) mode, PDLC (Polymer Dispersed Liquid Crystal
rystal mode, etc.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 9)
In this embodiment, the display panel configuration and peripheral configuration of a display device capable of implementing this embodiment will be described, in particular the display panel (also referred to as a liquid crystal panel) configuration and peripheral configuration of a liquid crystal display device will be described.

First, a simple configuration of the liquid crystal panel will be described with reference to FIG.
7(A) is a top view of the liquid crystal panel.

In the liquid crystal panel shown in FIG. 57A, a pixel portion 20101, a scanning line input terminal 20103, and a signal line input terminal 20104 are formed on a substrate 20100.
03, a scanning line is formed on the substrate 20100 in the row direction, and a signal line input terminal 201
Signal lines extend in the column direction from pixel portion 20104 on the substrate 20100.
In the pixel 0101, pixels 20102 are arranged in a matrix at the intersections of scanning lines and signal lines. Also, in the pixel 20102, a switching element and a pixel electrode layer are arranged.

As shown in the liquid crystal panel of FIG. 57A, the scanning line input terminal 20103 is
The signal line input terminals 20104 are formed on one side of the substrate 20100 in the column direction. The scanning lines extending from one scanning line input terminal 20103 and the scanning lines extending from the other scanning line input terminal 20103 are formed alternately.

In each of the pixels 20102 in the pixel section 20101, a first terminal of the switching element is connected to a signal line, and a second terminal is connected to a pixel electrode layer.
02 can be independently controlled by a signal input from the outside. The on/off of the switching elements is controlled by a signal supplied to the scanning line.

In addition, by arranging the scanning line input terminals 20103 on both sides of the row direction of the substrate 20100, the pixels 20102 can be arranged at a high density.
By arranging the substrate 20100 in one of the column directions, the frame of the liquid crystal panel is made smaller,
The area of the pixel portion 20101 can be increased.

As already mentioned, the substrate 20100 can be a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate having stainless steel foil, or the like.

As already mentioned, the switching elements may be transistors, diodes (for example, PN diodes, PIN diodes, Schottky diodes, diode-connected transistors, etc.), thyristors, logic circuits combining these, etc.

In addition, when a TFT is used as a switching element, the gate of the TFT is connected to a scanning line, the first terminal is connected to a signal line, and the second terminal is connected to the pixel electrode layer, so that each pixel 20102 can be independently controlled by a signal input from outside.

Note that the scanning line input terminal 20103 may be disposed on one side of the row direction of the substrate 20100. By disposing the scanning line input terminal 20103 on one side of the row direction of the substrate 20100, the frame of the liquid crystal panel can be made smaller and the area of the pixel portion 20101 can be made larger.

The scanning line extending from one scanning line input terminal 20103 and the scanning line extending from the other scanning line input terminal 20104 are connected to each other.
The scanning lines extending from the first scanning line 0103 may be common.

The scanning line input terminals 20103 may be disposed on both sides of the column direction of the substrate 20100. By disposing the scanning line input terminals 20103 on both sides of the column direction of the substrate 20100, the pixels 20102 can be disposed at a high density.

A capacitor may be further formed in the pixel 20102. When a capacitor is provided in the pixel 20102, a capacitor line may be formed on the substrate 20100. When a capacitor line is formed on the substrate 20100, a first electrode of the capacitor is connected to the capacitor line, and a second terminal is connected to the pixel electrode layer. When a capacitor line is not formed on the substrate 20100, a first electrode of the capacitor is connected to a scanning line different from the pixel 20102 in which the capacitor is arranged, and a second terminal is connected to the pixel electrode layer.

Here, the liquid crystal panel shown in FIG. 57A shows a configuration in which signals supplied to the scanning lines and signal lines are controlled by an external driving circuit, but as shown in FIG. 58A,
The driver IC 20201 may be mounted on the substrate 20100 by a chip on glass method.
The driver IC 20201 is attached to the FPC 2 by the Automated Bonding (ABD) method.
It may also be implemented on 0200 (Flexible Printed Circuit).
In addition, in FIG. 58, the driver IC 20201 is connected to the FPC 20200 .

The driver IC 20201 may be formed on a single crystal semiconductor substrate, or may be formed by forming a circuit with TFTs on a glass substrate.

In the liquid crystal panel shown in Fig. 57(A), a scanning line driver circuit 20105 may be formed over a substrate 20100 as shown in Fig. 57(B). In addition, a scanning line driver circuit 20105 and a signal line driver circuit 20106 may be formed over a substrate 20100 as shown in Fig. 57(C).

The scanning line driver circuit 20105 and the scanning line driver circuit 20105 are composed of a large number of N-channel transistors and a large number of P-channel transistors. However, they may be composed of only a large number of N-channel transistors or only a large number of P-channel transistors.

Next, details of the pixel 20102 will be described with reference to the circuit diagrams of Figures 59 and 60.

59A includes a transistor 20301, a liquid crystal element 20302, and a capacitor 20303. A gate of the transistor 20301 is connected to a wiring 20305, and a first terminal of the transistor 20301 is connected to a wiring 20304. A first electrode of the liquid crystal element 20302 is connected to a counter electrode 20307, and a second electrode of the liquid crystal element 20302 is connected to a second terminal of the transistor 20301. A first electrode of the capacitor 20303 is connected to a capacitor line 20306, and a second electrode of the capacitor 20303 is connected to a second terminal of the transistor 20301.

The wiring 20304 is a signal line, the wiring 20305 is a scanning line, and the capacitance line 2030
The transistor 20301 is a switching transistor and may be a P-channel transistor or an N-channel transistor.
0302 has TN (Twisted Nematic) mode as an operation mode, IPS
(In-Plane-Switching) mode, FFS (Fringe Field
Switching mode, MVA (Multi-domain Vertical)
Alignment mode, PVA (Patterned Vertical Al
ignment), ASM (Axially Symmetrically aligned M
icro-cell) mode, OCB (Optical Compensated Bi
reference mode, FLC (Ferroelectric Liquid)
Crystal) mode, AFLC (AntiFerroelectric Liquor)
id Crystal) can be used.

A video signal and a scanning signal are input to the wiring 20304 and the wiring 20305, respectively. The video signal is an analog voltage signal, and the scanning signal is a digital voltage signal of H level or L level. However, the video signal may be a current signal or a digital signal. In addition, the H level and L level of the scanning signal may be potentials that can control the on/off of the transistor 20301.

A constant power supply voltage is supplied to the capacitance line 20306. However, a pulsed signal may be supplied to the capacitance line 20306.

59A. First, when the wiring 20305 becomes H level, the transistor 20301 is turned on, and a video signal is supplied from the wiring 20304 to the second electrode of the liquid crystal element 20302 and the capacitor 2030
The potential is supplied to the second electrode of the wiring 203076. The capacitor 20303 holds a potential difference between the potential of the wiring 203076 and the potential of the video signal.

Next, when the wiring 20305 becomes L level, the transistor 20301 is turned off and the wiring 20
304 is electrically insulated from the second electrode of the liquid crystal element 20302 and the second electrode of the capacitor 20303. However, since the capacitor 20303 holds a potential difference between the potential of the wiring 203076 and the potential of the video signal, the potential of the second electrode of the capacitor 20303 can be maintained at the same potential as the video signal.

Thus, the pixel 20102 in FIG. 59A can maintain the potential of the second electrode of the liquid crystal element 20302 at the same potential as the video signal, and can maintain the liquid crystal element 20302 at a transmittance according to the video signal.

Although not shown, if the liquid crystal element 20302 has a capacitance component large enough to hold a video signal, the capacitance element 20303 is not necessarily required.

59B, the first electrode of the liquid crystal element 20302 may be connected to a capacitance line 20306. For example, when the liquid crystal mode of the liquid crystal element 20302 is the FFS mode, the liquid crystal element 20302 uses the configuration of FIG.

60, the first electrode of the capacitor 20303 may be connected to the wiring 20305a in the previous row. When the wiring 20305a is the n-th (n is a positive integer) scanning line, the wiring 20305b is the n+1-th scanning line.
When the pixel 20102a and the capacitor element 20303a are elements in the nth row, the transistor 2
60. The pixel 20102b, the pixel 20102b, and the capacitor 20303b are elements in the n+1th row. In this manner, the first electrode of the capacitor 20303b is connected to the wiring 20305a in the front column, thereby making it possible to reduce the number of wirings.
b can increase the aperture ratio.

Next, a more detailed configuration of the liquid crystal panel than that described with reference to Fig. 57 and Fig. 58 will be described with reference to Fig. 61. Specifically, the liquid crystal panel includes a TFT substrate, an opposing substrate,
The structure of a liquid crystal panel having a liquid crystal layer sandwiched between a counter substrate and a TFT substrate will be described. Also, Fig. 61(A) is a top view of the liquid crystal panel. Fig. 61(B) is a top view of the liquid crystal panel.
61(B) is a cross-sectional view of a top-gate type transistor formed on a substrate 20100 using a crystalline semiconductor film (polysilicon film) as a semiconductor film.

In the liquid crystal panel shown in FIG. 61A, a pixel portion 20101, a scanning line driver circuit 20105a, a scanning line driver circuit 20105b, and a signal line driver circuit 20106 are formed on a substrate 20100.
The signal line driver circuit 20106 and the signal line driver circuit 20107 are sealed between the substrate 20100 and the opposing substrate 20515 by a sealant 20516.
8 and an IC chip 20530 are disposed on the substrate 20100.

The cross-sectional structure taken along line CD in FIG. 61A will be described with reference to FIG.
On a substrate 20100, a pixel section 20101 and its peripheral driving circuit section (scanning line circuit 20105
20, a driver circuit region 20525 (scanning line driver circuit 20105a and scanning line driver circuit 20105b, and signal line driver circuit 20106) are formed, but only a driver circuit region 20525 (scanning line driver circuit 20105a and scanning line driver circuit 20105b) and a pixel region 20526 (pixel portion 20101) are shown here.

First, an insulating film 20501 is formed as a base film on a substrate 20100. The insulating film 20501 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Si
Alternatively, a single layer of an insulating film such as OxNy may be used, or a laminate structure having at least two of these films may be used.

It is better to use a silicon oxide film in the portion in contact with the semiconductor. As a result, it is possible to suppress electron trapping in the base film and hysteresis in the transistor characteristics.
It is desirable to have at least one nitrogen-rich film as the undercoat film, which can reduce impurities from the glass.

Next, a semiconductor layer 20502 is formed on the insulating film 20501 by photolithography, ink-jet printing, printing, or the like.

Next, an insulating layer 20501 is formed on the insulating film 20501 and the semiconductor layer 20502 as a gate insulating film.
0503 is formed.

Note that the insulating layer 20503 can have a single layer or a stacked layer structure of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like.
The insulating layer 20503 in contact with the semiconductor layer 20502 is preferably a silicon oxide film. This is because the number of trap levels at the interface with the semiconductor layer 20502 is reduced when the silicon oxide film is used. In addition, when the gate electrode is made of Mo, the gate insulating film in contact with the gate electrode is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo. In this embodiment, the insulating layer 20503 is
A silicon oxynitride film (composition ratio Si=3) having a thickness of 115 nm was deposited by plasma CVD.
2%, O=59%, N=7%, H=2%).

Next, a conductive layer 20504 is formed as a gate electrode on the insulating layer 20503 by a photolithography method, an ink-jet method, a printing method, or the like.

The conductive layer 20504 may be made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, or A.
Examples of the gate electrode include Mo, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements. Alternatively, the gate electrode may be formed by laminating these elements or alloys of these elements. Here, the gate electrode is formed by Mo. Mo is suitable because it is easy to etch and has heat resistance.

Note that the semiconductor layer 20502 is doped with an impurity element using the conductive layer 20504 or a resist as a mask, and a channel formation region and impurity regions which become a source region and a drain region are formed.

The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration.

Note that the conductive layer 20504 of the transistor 20521 has a dual-gate structure.
The transistor 20521 has a dual gate structure.
The off-state current of the transistor can be reduced. Note that the dual-gate structure is a structure having two gate electrodes. However, a plurality of gate electrodes may be provided over a channel region of the transistor.

Next, an insulating layer 20505 is formed as an interlayer film over the insulating layer 20503 and the conductive layer 20504.
is formed.

The insulating layer 20505 can be made of an organic material or an inorganic material, or a laminated structure thereof. For example, the insulating layer 20505 can be made of a material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide or aluminum oxide having a nitrogen content higher than the oxygen content, diamond-like carbon (DLC), polysilazane, nitrogen-containing carbon (CN), PSG (phosphorus glass), BPSG (borophosphorus glass), alumina, and other inorganic insulating materials. An organic insulating material may also be used, and the organic material may be either photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimideamide, resist, benzocyclobutene, siloxane resin, or the like may be used. The siloxane resin is Si-
It corresponds to a resin containing an O-Si bond. The skeleton structure of siloxane is composed of bonds between silicon (Si) and oxygen (O). An organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Note that contact holes are selectively formed in the insulating layer 20503 and the insulating layer 20505. For example, the contact holes are formed in the upper surface of the impurity region of each transistor.

Next, a conductive film 20506 is formed over the insulating layer 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like.

The conductive film 20506 is made of a material such as Ti, Mo, Ta, Cr, W, Al, or N.
Examples of the metals include Zn, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements. Alternatively, a laminated structure of these elements or alloys of these elements can be used.

In addition, in a portion where the contact holes of the insulating layer 20503 and the conductive layer 20504 are formed, the conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected.

Next, an insulating layer 20507 is formed as a planarizing film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505 .

Note that the insulating layer 20507 is often formed using an organic material because it is desirable for the insulating layer 20507 to have good flatness and coverage. Note that the insulating layer 20507 may have a multi-layer structure, and an organic material may be formed on an inorganic material (silicon oxide, silicon nitride, silicon oxynitride).

Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed in the upper surface of the drain electrode of the transistor 20521.

Next, a conductive layer 20508 is formed as a pixel electrode on the insulating layer 20507 by a photolithography method, an ink-jet method, a printing method, or the like.

As the conductive layer 20508, a transparent electrode that transmits light and a reflective electrode that reflects light can be used.

In the case of transparent electrodes, for example, indium tin oxide (
ITO film, indium tin silicon oxide (ITSO) film made by mixing indium tin oxide (ITO) with silicon oxide, indium zinc oxide (IZO) film made by mixing indium oxide with zinc oxide
) film, zinc oxide film, tin oxide film, or the like can be used.
It is a transparent conductive material formed by sputtering using a target in which 2 to 20 wt % zinc oxide (ZnO) is mixed into TO, but is not limited to this.

In the case of the reflective electrode, for example, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, A
Examples of the usable materials include U, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys thereof. In addition, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, and Al is laminated with Ti,
A three-layer laminate structure in which the metal is sandwiched between metals such as Mo, Ta, Cr, and W may also be used.

Next, on the insulating layer 20507 and the conductive layer 20508 formed on the insulating layer 20507,
An insulating layer 20509 is formed as an alignment film.

Next, a sealant 20516 is formed on the periphery of the pixel portion 20101 or on the periphery of the pixel portion 20101 and its peripheral driver circuit portion by an ink-jet method or the like.

Next, an opposing substrate 20515 on which an insulating film 20514, an insulating film 20513, a conductive film 20512, an insulating film 20511, etc. are formed is bonded to the substrate 20100 via a spacer 20531, and a liquid crystal layer 20510 is disposed in the gap.

The substrate 20115 may function as a counter substrate.
The insulating film 20513 may function as a black matrix (light-shielding film). The insulating film 20513 may function as a color filter. The spacer 20531 may be formed by dispersing particles of several μm, or by forming a resin film on the entire surface of the substrate and then etching the resin film. The conductive film 20512 may function as a counter electrode. The conductive film 20512 may be the same as the conductive layer 20508.
The insulating film 20511 may also function as an alignment film.

Note that an insulating film 20532 may be formed as a planarizing film between the insulating films 20513 and 20514 and the conductive film 20512. Note that the insulating film 20532 is not illustrated in FIG.

Any known liquid crystal can be used as the liquid crystal layer 20510. For example, ferroelectric liquid crystal or antiferroelectric liquid crystal may be used as the liquid crystal layer 20510. The liquid crystal driving method may be a TN (Twisted Nematic) mode, an IPS (IPS) mode, or the like.
In-Plane-Switching mode, FFS (Fringe Field)
Switching mode, MVA (Multi-domain Vertical)
Alignment mode, PVA (Patterned Vertical Ali
gnment), ASM (Axially Symmetric aligned Mi
cro-cell) mode, OCB (Optical Compensated Bi
effringence) mode, FLC (Ferroelectric Liquid)
Crystal) mode, AFLC (AntiFerroelectric Liqui)
d Crystal) etc. can be freely used.

Next, a conductive film 205 electrically connected to the pixel portion 20101 and its peripheral driving circuit portion is formed.
33, an FPC 20200 is disposed via an anisotropic conductive layer 20517. Also, an IC chip is disposed on the FPC 20200 via an anisotropic conductive layer 20517. That is, the FPC 20200, the conductive film 20533, and the IC chip 20530 are electrically connected.

Note that the conductive film 20533 has a function of transmitting a signal and a potential input from the FPC 20200 to pixels and peripheral circuits. As the conductive film 20533, a film similar to the conductive film 20506, a film similar to the conductive layer 20504, a film similar to the impurity region of the semiconductor layer 20502, or a combination of at least two layers of these may be used.

In addition, the IC chip 20530 can effectively utilize the substrate area by forming functional circuits (memory and buffers).

The liquid crystal panels of FIGS. 61A and 61B include a scanning line driving circuit 20105a and a scanning line driving circuit 20105b.
Although the configuration in which the signal line driver circuit 20105b and the signal line driver circuit 20106 are formed on the substrate 20100 has been described, as shown in the liquid crystal panel of Fig. 62(A), a driver circuit equivalent to the signal line driver circuit 20106 may be formed in a driver IC 20601 and mounted on the liquid crystal panel by a COG method or the like. By forming the signal line driver circuit 20106 in the driver IC 20601, power saving can be achieved. In addition, by forming the driver IC 20601 as a semiconductor chip such as a silicon wafer, the liquid crystal panel of Fig. 62(A) can achieve higher speed and lower power consumption.

62B, driver circuits corresponding to the scanning line driver circuit 20105a, the scanning line driver circuit 20105b, and the signal line driver circuit 20106 may be formed in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively, and mounted on the liquid crystal panel by a COG method or the like. Also, by forming the driver circuits corresponding to the scanning line driver circuit 20105a, the scanning line driver circuit 20105b, and the signal line driver circuit 20106 in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively, cost reduction can be achieved.

The transistor 20521 has a dual gate structure.
26, the transistor 20521 may have a single gate structure. However, FIG. 63 shows only the pixel region 20526.

Next, a cross-sectional view in the case where a bottom-gate transistor is formed over a substrate 20100 will be described with reference to Fig. 64. However, Fig. 64 shows only the pixel region 20526.

First, an insulating film 20501 is formed as a base film on a substrate 20100. Next,
A conductive layer 20504 is formed as a gate electrode over the insulating film 20501 by a photolithography method, an ink-jet method, a printing method, or the like.
The conductive layer 20504 of the first transistor 20521 has a dual gate structure. This is because, as already described, the transistor 20521 has a dual gate structure.
Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504. Next,
The semiconductor layer 20502 is formed by a photolithography method, an inkjet method, a printing method, or the like.
502 is doped with an impurity element to form a channel formation region and impurity regions that become source and drain regions. The impurity regions may be formed into high-concentration regions and low-concentration regions by controlling the impurity concentration. Next, an insulating layer 20505 is formed as an interlayer film on the insulating layer 20503 and the semiconductor layer 20502. Contact holes are selectively formed in the insulating layer 20505. For example, the contact holes are formed on the upper surface of the impurity region of each transistor. Next, the insulating layer 2050
A conductive film 20506 is formed on the insulating layer 205 as a drain electrode, a source electrode, and a wiring by a photolithography method, an ink-jet method, a printing method, or the like.
In the portion where the contact hole of 20505 is formed, the conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected. Next, an insulating layer 20507 is formed as a planarization film on the insulating layer 20505 and the conductive film 20506. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode on the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film on the insulating layer 20507 and the conductive layer 20508. Next, the insulating film 20507 is formed as a planarization film.
A liquid crystal layer 20510 is disposed in the gap between the substrate 20100 and an opposing substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, etc. are formed.

In FIG. 64, the transistor 20521 has a dual gate structure.
As shown in a pixel region 20526 in FIG. 65, the transistor 20521 may have a single gate structure.

Next, a cross-sectional view in the case where a double-gate transistor is formed over a substrate 20100 will be described with reference to Fig. 66. However, Fig. 66 shows only the pixel region 20526.

A double-gate transistor is a transistor having a structure in which gate electrodes are disposed above and below a semiconductor film. In addition, a double-gate transistor can pass twice as much current as a top-gate transistor or a bottom-gate transistor if the transistor has the same size and is subjected to the same applied voltage. In other words, a double-gate transistor can pass more current with a small transistor size.

First, an insulating film 20501 is formed as a base film on a substrate 20100. Next,
A conductive layer 20504a is formed as a first gate electrode over the insulating film 20501 by a photolithography method, an ink-jet method, a printing method, or the like.
The conductive layer 20504 may be made of the same material and have the same structure as the conductive layer 20504.
An insulating layer 20501 is formed on the insulating film 20501 and the conductive layer 20504a as a first gate insulating film.
0503a is formed. Note that the insulating layer 20503a may be made of a material and have a structure similar to those of the insulating layer 20503. Next, a semiconductor layer 20502 is formed on the insulating layer 20503a by photolithography, inkjet printing, printing, or the like. Next, an insulating layer 20503b is formed as a second gate insulating film on the insulating layer 20503a and the semiconductor layer 20502. Note that the insulating layer 20503b is formed by forming the insulating layer 20503b on the insulating layer 20503a.
A conductive layer 20504b having the same material and structure as the conductive layer 20503 can be used. Next, a conductive layer 20504b is formed as a second gate electrode on the insulating layer 20503b by a photolithography method, an inkjet method, a printing method, or the like.
The same material and structure as those of the semiconductor layer 20504 can be used.
In the semiconductor layer 20502, an impurity element is doped into the semiconductor layer 20502 using a conductive layer 20504b or a resist as a mask, and a channel formation region and impurity regions that become a source region and a drain region are formed. Note that the impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration. Note that the semiconductor layer 20502 is formed by doping an insulating layer 20503.
Before the formation of the conductive layer 20504b and the semiconductor layer 2050
An impurity element may be doped into the insulating layer 20503b and the conductive layer 202 to form a channel forming region and impurity regions that become a source region and a drain region.
An insulating layer 20505 is formed as an interlayer film on the insulating layer 204b.
Contact holes are selectively formed in the insulating layer 20505 and the insulating layer 20505. For example, the contact holes are formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed on the insulating layer 20505 as a drain electrode, a source electrode, and a wiring by photolithography, inkjet printing, printing, or the like.
In the portion where the contact holes of the insulating layer 20503 and the insulating layer 20505 are formed,
The conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected to each other. Next, an insulating layer 205 is formed as a planarizing film on the insulating layer 20505 and the conductive film 20506.
07 is formed. In addition, a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode on the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film on the insulating layer 20507 and the conductive layer 20508. Next, a liquid crystal layer 20510 is disposed in the gap between the substrate 20100 and the opposing substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, and the insulating film 20511 are formed.

61 and 63 to 66 have been described with reference to cross-sectional views in which an insulating layer 20507 is formed as a flat film on an insulating layer 20505 and on a conductive film 20506 formed on the insulating layer 20505. However, the insulating layer 20507 is not necessarily required, as shown in FIG.

Note that although the cross-sectional view in FIG. 67 shows the case of a top-gate transistor, the same applies to the cases of a bottom-gate transistor and a double-gate transistor.

Next, a non-crystalline semiconductor film (amorphous silicon film) is formed on the substrate 20100 as a semiconductor film.
A cross-sectional view of a transistor using the above structure will be described with reference to Fig. 68. The cross-sectional view shown in Fig. 68 is a cross-sectional view of a transistor having an inverted staggered channel etch structure.

First, an insulating film 20501 is formed as a base film on a substrate 20100. Next,
A conductive layer 20504 is formed as a gate electrode on the insulating film 20501 by photolithography, inkjet, printing, or the like. Next, an insulating layer 20503 is formed as a gate insulating film on the insulating film 20501 and the conductive layer 20504. Next, a semiconductor layer 20502 is formed on the insulating layer 20503 by photolithography, inkjet, printing, or the like. Note that the semiconductor layer 20502 has a first semiconductor film and a second semiconductor film, and the second semiconductor film is formed on the first semiconductor film. Also, the first semiconductor film and the second semiconductor film may be formed in succession and patterned by photolithography at the same time. Also, the second semiconductor film contains an impurity element. Next, a conductive film 20506 is formed on the insulating layer 20503 and the semiconductor layer 20502 by photolithography, inkjet, printing, or the like. Note that,
The semiconductor layer 20502 is etched using the conductive film 20506 as a mask, so that a channel formation region and impurity regions that become a source region and a drain region are formed. That is, the second semiconductor film containing an impurity element is removed in the channel region. However, the semiconductor layer 20502 may be etched using a resist for etching the conductive film 20506 as a mask. Next, an insulating layer 20507 is formed as a planarization film on the insulating layer 20503, the semiconductor layer 20502, and the conductive film 20506. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode on the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film on the insulating layer 20507 and the conductive layer 20508. Next, insulating film 2
A liquid crystal layer 20510 is disposed in the gap between the substrate 20100 and an opposing substrate 20515 on which a transparent electrode 20514, an insulating film 20513, a conductive film 20512, an insulating film 20511, etc. are formed.

Although a transistor having a channel etch structure has been described, an insulating film 21301 may be provided on a semiconductor layer 20502 as shown in FIG. 69. The insulating film 21301 is formed between a first semiconductor film and a second semiconductor film. The semiconductor layer 20502 is formed between a conductive film 20
When 506 is formed, it is etched at the same time.

The transistor 20521 in FIG. 68 is called a channel etch structure, and the transistor 20521 in FIG. 69 is called a channel protection structure.

Next, a cross-sectional view in the case where a top-gate transistor is formed using an amorphous semiconductor film as a semiconductor film over a substrate 20100 will be described with reference to FIG.

First, an insulating film 20501 is formed as a base film on a substrate 20100. Next,
A conductive film 20506 is formed on the insulating film 20501 by photolithography, inkjet, printing, or the like. Next, a semiconductor layer 20502a is formed on the conductive film 20506 by photolithography, inkjet, printing, or the like. Note that the semiconductor layer 20502a may be made of the same material and have the same structure as the semiconductor layer 20502. The semiconductor layer 20502a contains an impurity element. Next, a semiconductor layer 20502b is formed on the insulating film 20501 and the semiconductor layer 20502a by photolithography, inkjet, printing, or the like. Note that the semiconductor layer 20502b may be made of the same material and have the same structure as the semiconductor layer 20502.
The semiconductor layer 0502 b can be made of the same material and have the same structure as the semiconductor layer 20502 .
Next, an insulating layer 20503 is formed as a gate insulating film on the insulating film 20501, the semiconductor layer 20502b, and the conductive film 20506. Next, a conductive layer 20504 is formed as a gate electrode on the insulating layer 20503 by photolithography, inkjet, printing, or the like. Next, an insulating layer 20507 is formed as a planarization film on the insulating layer 20503 and on the conductive layer 20504 formed on the insulating layer 20503. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode on the insulating layer 20507 by photolithography, inkjet, printing, or the like. Next, an insulating layer 20509 is formed as an alignment film on the insulating layer 20507 and the conductive layer 20508. Next, a liquid crystal layer 20510 is disposed in the gap between the substrate 20100 and an opposing substrate 20515 on which an insulating film 20514, an insulating film 20513, a conductive film 20512, an insulating film 20511, etc. are formed.

69 and 70 show cross-sectional views in which the insulating layer 20507 is formed as a flat film on the insulating layer 20505 and on the conductive film 20506 formed on the insulating layer 20505. However, the insulating layer 20507 is not necessarily required, as shown in FIG.

Although the cross-sectional view shown in FIG. 71 shows a case of a transistor having an inverse staggered channel etch structure, the same applies to a case of a transistor having an inverse staggered channel protection structure.
A top-gate transistor may also be used, and cross-sectional views of the top-gate transistor are shown in FIGS.

In the case of the cross-sectional view shown in FIG. 72, a conductive layer 20502 is formed as a pixel electrode on the insulating film 20501 and the conductive film 20506 by photolithography, ink-jet printing, printing, or the like.
The conductive layer 20508 is formed after the conductive film 20506 is formed and before the insulating layer 20503 is formed.

73, a conductive layer 20508 is formed as a pixel electrode by photolithography, ink-jet printing, or the like on an insulating film 20501. The conductive layer 20508 is formed after the insulating film 20501 is formed.

Next, a cross-sectional view of a semi-transmissive liquid crystal panel will be described with reference to Figure 74.

74 is a cross-sectional view of a liquid crystal panel in which a transistor uses a polycrystalline semiconductor as a semiconductor film. However, the transistor may be a bottom gate type or a double gate type. The gate electrode of the transistor may be a single gate type or a double gate type.
A dual gate structure may also be used.

74 is similar to FIG. 63 up to the formation of the conductive film 20506. Therefore, the process and structure after the formation of the conductive film 20506 will be described.

First, on the insulating layer 20505 and the conductive film 20506 formed on the insulating layer 20505, an insulating film 21801 is formed by photolithography, inkjet, printing, or the like as a film for thinning the thickness (so-called cell gap) of the liquid crystal layer 20510. Note that the insulating film 21801 is often formed using an organic material because it is desirable for it to have good flatness and coverage. Note that an organic material may be formed on an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to form a multilayer structure. Note that a contact hole is selectively formed in the insulating film 21801. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508a is formed as a first pixel electrode on the insulating layer 20505 and the insulating layer 20507 by photolithography, inkjet, printing, or the like. Note that a transparent electrode that transmits light similar to the conductive layer 20508 can be used as the conductive layer 20508a. Next, a conductive layer 20508b is formed on the conductive layer 20508a as a second pixel electrode by photolithography, inkjet printing, printing, or the like. Note that a reflective electrode that reflects light similar to the conductive layer 20508 can be used as the conductive layer 20508b. Note that a region in which the conductive layer 20508b is formed is called a reflective region. Also, a region in which the conductive layer 20508a is formed and the conductive layer 20508b is not formed on the conductive layer 20508a is called a transmissive region. Next, an insulating layer 20509 is formed as an alignment film on the insulating film 21801, the conductive layer 20508a, and the conductive layer 20508b. Next, a liquid crystal layer 20510 is disposed in a gap between the substrate 20100 and the opposing substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, and the insulating film 20511 are formed.

In FIG. 74, the conductive layer 20508a is formed, and then the conductive layer 20508b is formed. However, as shown in FIG. 75, the conductive layer 20508b is formed, and then the conductive layer 20508
a may be formed.

In addition, in Fig. 74 and Fig. 75, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive layer 20508a and under the conductive layer 20508b.
76, the insulating film 22001 may be formed on the opposing substrate 20515 side. The insulating film 22001, like the insulating film 21801, is an insulating film for adjusting the liquid crystal layer 20510 (cell gap).

In addition, in Fig. 76, the case where the insulating layer 20507 is formed as a planarizing film has been described, but as shown in Fig. 77, the insulating layer 20507 does not have to be formed. In the case of Fig. 77, the conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that the insulating film 22001 may be formed between the conductive film 20512 and the insulating film 20511 , or may be formed between the insulating film 20511 and the liquid crystal layer 20510 .

Next, a cross-sectional view of a semi-transmissive liquid crystal panel in which a polycrystalline semiconductor is used for the semiconductor film of a transistor is shown in FIG.

78 is a cross-sectional view of a liquid crystal panel having a transistor using an inverse staggered channel etch structure. However, the transistor may be a top gate type, or may use an inverse staggered channel protection structure.

78 is the same as Fig. 78 up to the formation of the conductive film 20506. Therefore, the process and structure after the conductive film 20506 is formed will be described.

First, a liquid crystal layer 20502 is formed on the semiconductor layer 20502, the insulating layer 20503, and the conductive film 20506.
As a layer for thinning the thickness of the insulating film 22201 (so-called cell gap), an insulating film 22201 is formed by photolithography, inkjet printing, printing, or the like. Note that the insulating film 22201 is often formed using an organic material because it is desirable for it to have good flatness and coverage. Note that an organic material may be formed on an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to form a multi-layer structure. Note that the insulating film 22201 may be formed by forming an organic material on an inorganic material (silicon oxide, silicon nitride, silicon oxynitride).
A contact hole is selectively formed in the insulating layer 201. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, the insulating layer 205
A conductive layer 20508a is formed as a first pixel electrode on the insulating film 2203 and the insulating film 22201 by photolithography, inkjet printing, or the like. Next, a conductive layer 20508b is formed as a second pixel electrode on the conductive layer 20508a by photolithography, inkjet printing, or the like.
The region where the conductive layer 20508b is formed is called a reflective region. Also, among the regions where the conductive layer 20508a is formed, the region where the conductive layer 20508b is not formed on the conductive layer 20508a is called a transmissive region. Next, on the insulating film 22201, the conductive layer 20508a, and the conductive layer 20508b,
An insulating layer 20509 is formed as an alignment film.
0513, a counter substrate 20515 on which a conductive film 20512 and an insulating film 20511 are formed,
A liquid crystal layer 20510 is disposed in the gap between the substrate 20100 and the liquid crystal layer 20510 .

In FIG. 78, the conductive layer 20508b is formed after the conductive layer 20508a is formed. However, as shown in FIG. 79, the conductive layer 20508b is formed after the conductive layer 20508a is formed.
a may be formed.

In addition, in Fig. 78 and Fig. 79, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive layer 20508a and under the conductive layer 20508b.
80, the insulating film 22001 may be formed on the opposing substrate 20515 side. The insulating film 22001, like the insulating film 22201, is an insulating film for adjusting the liquid crystal layer 20510 (cell gap).

79 and 80, the case where the insulating layer 20507 is formed as a planarizing film has been described, but as shown in Fig. 81, the insulating layer 20507 does not have to be formed. In the case of Fig. 81, the conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

In addition, in FIG. 61 and FIG. 63 to FIG. 81, a pair of electrodes (
In this example, the conductive layer 20508 and the conductive film 20512 are formed on different substrates. However, the conductive film 20512 may be provided on the substrate 20100. In this manner, an IPS (In-Plane-Switching) mode can be used as a liquid crystal driving method. Depending on the liquid crystal layer 20510, one or both of the two alignment films (the insulating layer 20509 and the insulating film 20511) can be omitted.

In addition, in FIG. 61 and FIG. 63 to FIG. 81, a conductive layer 20508 (conductive layer 20508b) is formed as a reflective pixel electrode, and it is preferable that the shape of the conductive layer 20508 is uneven. This is because the reflective pixel electrode is for reflecting external light to perform display. This is because the external light that enters the reflective electrode can be diffused by the reflective electrode in order to efficiently utilize the light and increase the display brightness. Note that the film under the conductive layer 20508 (insulating layer 20
By making the shape of the insulating layer 20505, the insulating layer 20507, the insulating film 21801, or the insulating film 22201, etc. uneven, the shape of the conductive layer 20508 becomes uneven.

Next, a liquid crystal display device having the liquid crystal panel described with reference to FIGS. 61 to 81 will be described with reference to FIG.

First, the liquid crystal display device shown in FIG. 82 includes a backlight unit 22601, a liquid crystal panel 22607, a layer 22608 including a first polarizer, and a layer 22609 including a second polarizer.

The liquid crystal panel 22607 may be the same as that described in this embodiment. Although the liquid crystal panel of this embodiment has been described as having an active type structure in which a switching element is provided in each pixel, the liquid crystal panel of Fig. 82 may have a passive type structure.

The structure of the backlight unit 22601 will be described.
01 includes a diffusion plate 22602, a light guide plate 22603, a reflector 22604, and a lamp reflector 2
The light source 22605 is a cold cathode fluorescent lamp, a hot cathode fluorescent lamp, a light emitting diode, an inorganic EL, an organic EL, or the like.
The lamp reflector 22605 is a light source 2260
6 to the light guide plate 22603. The light guide plate 22603 has a function of totally reflecting the fluorescence and guiding the light to the entire surface. The diffusion plate 22602 has a function of reducing unevenness in brightness. The reflection plate 22604 reflects the light downward from the light guide plate 22603 (toward the liquid crystal panel 2
2607) and reuses the leaked light.

By disposing a prism sheet between the diffusion plate 22602 and the layer including the second polarizer 22609, the liquid crystal display device of this embodiment can improve the brightness of the screen of the liquid crystal panel.

A control circuit for adjusting the luminance of the light source 22606 is connected to the backlight unit 22601. The luminance of the light source 22606 can be adjusted by a signal supplied from the control circuit.

A layer 22609 including a second polarizer is provided between the liquid crystal panel 22607 and the backlight unit 22601.
2607 also has a layer 22608 including a first polarizer.

Note that the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in a TN mode. Also, the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in a VA mode. Also, the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in a VA mode.
When the liquid crystal elements of the liquid crystal panel 22607 are driven in IPS mode or FFS mode, the liquid crystal elements 22609 may be arranged in a crossed Nicol state or in a parallel Nicol state.

A retardation plate may be provided between the liquid crystal panel 22607 and either or both of the layer including the first polarizer 22608 and the layer including the second polarizer 22609 .

As shown in FIG. 85, the second polarizer-containing layer 22609 and the backlight unit 2
By disposing a slit (grating) 22610 between the first and second electrodes 2601, the liquid crystal display device of this embodiment can perform three-dimensional display.

The slit 22610 having an opening arranged on the backlight unit side transmits light incident from a light source in a stripe shape and causes the light to enter the display device.
By using slit 22610, parallax can be created between the eyes of the viewer on the viewing side, so that the viewer sees only the right-eye pixels with his/her right eye and only the left-eye pixels with his/her left eye at the same time. Thus, the viewer can see a three-dimensional display. In other words, light given a specific viewing angle by slit 22610 passes through the pixels corresponding to the right-eye image and the left-eye image,
The right-eye image and the left-eye image are separated into images with different viewing angles, and a three-dimensional display is performed.

If electronic devices such as television sets and mobile phones are manufactured using the liquid crystal display device of FIG. 85, it is possible to provide high-performance, high-quality electronic devices capable of performing three-dimensional display.

Next, a detailed configuration of the backlight will be described with reference to Fig. 84. The backlight is provided in the liquid crystal display device as a backlight unit having a light source, and the light source is surrounded by a reflector so that the backlight unit efficiently scatters light.

As shown in FIG. 84(A), the backlight unit 22852 uses cold cathode fluorescent lamps 2 as light sources.
2801 can be used. Also, a lamp reflector 22832 can be provided to efficiently reflect the light from the cold cathode tube 22801. The cold cathode tube 22801 is often used in large display devices. This is due to the intensity of the luminance from the cold cathode tube. Therefore, a backlight unit having a cold cathode tube can be used in the display of a personal computer.

As shown in FIG. 84B, the backlight unit 22852 can use light emitting diodes 22802 (LED) as a light source. For example, light emitting diodes 22802 (W) that emit white light are arranged at predetermined intervals.
A lamp reflector 22832 may be provided to efficiently reflect light from 802.

As shown in FIG. 84C, the backlight unit 22852 uses R
By using the light emitting diodes 22803, 22804, and 22805 of the respective colors RGB, it is possible to improve color reproducibility compared to using only the light emitting diode 22802 (W) that emits white light.
832 may be provided.

Furthermore, as shown in FIG. 84(D), a light source is a light emitting diode 2280 of each color RGB.
When using 22803, 22804, and 22805, their number and arrangement do not need to be the same.
For example, a plurality of colors with low emission intensity (such as green) may be arranged.

Further, a light emitting diode 22802 that emits white light and a light emitting diode 2280 of each color RGB are
3, 22804, and 22805 may also be used in combination.

In addition, in the case where RGB light emitting diodes are provided, a color display can be achieved by applying a field sequential mode, in which the RGB light emitting diodes are sequentially lit according to time.

Light-emitting diodes are suitable for large display devices because of their high brightness. In addition, they have excellent color reproducibility compared to cold cathode fluorescent lamps because of their high color purity for each of the RGB colors, and they can be used in small display devices because they can reduce the area in which they are installed, making it possible to narrow the frame.

Also, the light source does not necessarily have to be arranged as a backlight unit as shown in Fig. 84. For example, when a backlight having light emitting diodes is mounted on a large display device, the light emitting diodes can be arranged on the back surface of the substrate. In this case, the light emitting diodes can be arranged at a predetermined interval and the light emitting diodes of each color can be arranged in order. The arrangement of the light emitting diodes can improve color reproducibility.

Next, an example of a layer including a polarizer (also called a polarizing plate or a polarizing film) will be described with reference to FIG.

The polarizing film 23000 in FIG. 86 includes a protective film 23001, a substrate film 23002, and a
, a PVA polarizing film 23003 , a substrate film 23004 , an adhesive layer 23005 and a release film 23006 .

The PVA polarizing film 23003 has the function of producing light that vibrates in only one direction (linearly polarized light). Specifically, the PVA polarizing film 23003 contains molecules (polarizers) whose electron densities differ greatly between the vertical and horizontal directions. The PVA polarizing film 23003 can produce linearly polarized light by aligning the directions of the molecules whose electron densities differ greatly between the vertical and horizontal directions.

As an example, the PVA polarizing film 23003 is made of polyvinyl alcohol (Poly V
By doping a polymer film of polyvinyl alcohol (PVA) with an iodine compound and pulling the PVA film in a certain direction, a film in which iodine molecules are aligned in a certain direction can be obtained. Light parallel to the long axis of the iodine molecules is absorbed by the iodine molecules. In addition, a dichroic dye may be used instead of iodine for high durability and high heat resistance applications. It is preferable that the dye is used in liquid crystal display devices that require durability and heat resistance, such as LCDs for vehicles and LCDs for projectors.

The PVA polarizing film 23003 is a film having a substrate on both sides (substrate film 23002
The reliability can be increased by sandwiching the PVA polarizing film 23003 between a highly transparent and highly durable triacetylacetonate (TAC) film. The substrate film and the TAC film function as protective layers for the polarizer of the PVA polarizing film 23003.

An adhesive layer 23005 for adhering to a glass substrate of a liquid crystal panel is attached to one of the substrate films (substrate film 23004). The adhesive layer 23005 is formed by applying an adhesive to one of the substrate films (substrate film 23004). The adhesive layer 23005 is also provided with a release film 23006 (separate film).

The other substrate film (substrate film 23002) is provided with a protective film.

A hard coat scattering layer (anti-glare layer) may be provided on the surface of the polarizing film 23000. The hard coat scattering layer has fine irregularities formed on the surface by AG treatment and has an anti-glare function of scattering external light, so that it can prevent external light from being reflected on the liquid crystal panel or surface reflection.

In addition, a plurality of optical thin film layers having different refractive indexes may be multi-layered (also called anti-reflection treatment or AR treatment) on the surface of the polarizing film 23000. The multi-layered optical thin film layers having different refractive indexes can reduce the reflectance of the surface by the optical interference effect.

Next, the operation of each circuit in the liquid crystal display device will be explained with reference to Figure 83.

FIG. 83 shows a system block diagram of a pixel portion 22705 and a driver circuit portion 22708 of a display device.

The pixel portion 22705 has a plurality of pixels, and each pixel is connected to a signal line 22712 and a scanning line 22713.
A switching element is provided at the intersection region with 710. The switching element can control the application of a voltage for controlling the tilt of the liquid crystal molecules. A structure in which a switching element is provided at each intersection region in this manner is called an active type. The pixel portion of this embodiment is not limited to such an active type, and may have a passive type configuration. The passive type has a simple process because there is no switching element in each pixel.

The driver circuit portion 22708 includes a control circuit 22702, a signal line driver circuit 22703, and a scanning line driver circuit 22704. The control circuit 22702 to which a video signal 22701 is input has a function of performing gray scale control according to the display contents of the pixel portion 22705.
The generated signal is transmitted to a signal line driver circuit 22703 and a scanning line driver circuit 22704.
When a switching element is selected via a scanning line 22710 based on the scanning line driving circuit 22704, a voltage is applied to the pixel electrode of the selected intersection area. The value of this voltage is determined based on a signal input from the signal line driving circuit 22703 via a signal line.

Furthermore, the control circuit 22702 generates a signal for controlling the power supplied to the lighting means 22706, and the signal is input to a power source 22707 for the lighting means 22706. The backlight unit shown in the above embodiment mode can be used as the lighting means. Note that the lighting means can also be a frontlight in addition to a backlight. A frontlight is a plate-shaped light unit that is attached to the front side of a pixel portion and is composed of a light-emitting body and a light guide for illuminating the entire portion. Such lighting means can illuminate the pixel portion evenly with low power consumption.

As shown in Fig. 83B, the scanning line driver circuit 22704 has circuits functioning as a shift register 22741, a level shifter 22742, and a buffer 22743. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 22741. Note that the scanning line driver circuit of this embodiment mode is not limited to the configuration shown in Fig. 83B.

As shown in FIG. 83C, the signal line driver circuit 22703 includes a shift register 22731.
The circuit functioning as the buffer 22735 is a circuit having a function of amplifying a weak signal, and includes an operational amplifier or the like. A signal such as a start pulse (SSP) is input to the level shifter 22734, and data (DATA) such as a video signal is input to the first latch 22732. A latch (L
AT) signal can be temporarily held and input to the pixel portion 22705 all at once. This is called line sequential driving. Therefore, if the pixel performs point sequential driving instead of line sequential driving,
In this way, the signal line driver circuit of this embodiment mode can be configured as shown in FIG.
The present invention is not limited to the configuration shown in FIG.

Such a signal line driver circuit 22703, a scanning line driver circuit 22704, and a pixel portion 22705 can be formed by using semiconductor elements provided on the same substrate. The semiconductor elements can be formed by using thin film transistors provided on a glass substrate. In this case, a crystalline semiconductor film is preferably used for the semiconductor elements. The crystalline semiconductor film has high electrical characteristics, particularly mobility, and therefore can be used to form a circuit included in the driver circuit portion. In addition, the signal line driver circuit 2
The scanning line driver circuit 2703 and the scanning line driver circuit 22704 are integrated circuits (ICs).
In this case, an amorphous semiconductor film can be applied to the semiconductor element of the pixel portion.

Here, the liquid crystal display module of this embodiment will be described with reference to Figures 87(A) and 87(B).

FIG. 87A shows an example of a liquid crystal display module, which includes a TFT substrate 23100 and an opposing substrate 23
101 is fixed by a sealant 23102, and a pixel portion 23103 including a TFT and the like is provided between them.
A liquid crystal layer 23104 is provided to form a display area. A colored layer 23105 is necessary for color display, and in the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided for each pixel. On the outside of the TFT substrate 23100 and the counter substrate 23101, a layer 23106 including a first polarizer, a layer 23107 including a second polarizer, and a diffusion plate 23113 are provided.
The light source is composed of a cold cathode fluorescent lamp 23110 and a reflector 23111, and the circuit board 23112 is connected to the TFT board 23100 by a flexible wiring board 23109, and has external circuits such as a control circuit and a power supply circuit built in.

Between the TFT substrate 23100 and the backlight serving as a light source, a layer 2310 including a second polarizer is provided.
A layer including a first polarizer 23106 is also laminated on the opposing substrate 23101. On the other hand, the absorption axis of the layer including a second polarizer 23107 and the absorption axis of the layer including a first polarizer 23106 provided on the viewing side are arranged to be in a crossed Nicol state.

The layer 23107 including the stacked second polarizer and the layer 2310 including the stacked first polarizer
6 is bonded to the TFT substrate 23100 and the counter substrate 23101. The laminate may be laminated with a retardation plate between the laminated polarizer-containing layer and the substrate. If necessary, the first polarizer-containing layer 23106 on the viewing side may be subjected to an anti-reflection treatment.

The liquid crystal display module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode,
n-Plane-Switching mode, FFS (Fringe Field Switching) mode
switching mode, MVA (Multi-domain Vertical A)
ligment) mode, PVA (Patterned Vertical Alignment)
nment), ASM (Axially Symmetric aligned Mic)
ro-cell) mode, OCB (Optical Compensated Bire
fringe) mode, FLC (Ferroelectric Liquid C)
rystal) mode, AFLC (AntiFerroelectric Liquid
Crystal), PDLC (Polymer Dispersed Liquid
Crystal mode, etc. can be used.

FIG. 87B shows an example in which the OCB mode is applied to the liquid crystal display module of FIG. 87A, and is an FS-LCD (Field sequential-LCD).
CD emits red light, green light, and blue light in one frame period, respectively, and can synthesize images to display in color using time division. In addition, since each light emission is performed by a light-emitting diode or a cold cathode fluorescent lamp, color filters are not required. Therefore, it is not necessary to arrange color filters of the three primary colors and limit the display area of each color, and all three colors can be displayed in any area. On the other hand, high-speed response of the liquid crystal is required because three colors are emitted in one frame period. By applying the FLC mode and OCB mode using the FS method to the display device of this embodiment, a high-performance and high-quality display device and a liquid crystal television device can be completed.

The liquid crystal layer in the OCB mode has a so-called pi cell structure. The pi cell structure is a structure in which the pretilt angle of the liquid crystal molecules is oriented in a plane-symmetrical relationship with respect to the center plane between the active matrix substrate and the opposing substrate. The orientation state of the pi cell structure is splay orientation when no voltage is applied between the substrates, and transitions to bend orientation when voltage is applied. This bend orientation results in a white display. When further voltage is applied, the bend-oriented liquid crystal molecules are oriented perpendicular to both substrates, resulting in a state in which light is not transmitted. The OCB mode can achieve high-speed response that is approximately 10 times faster than the conventional TN mode.

In addition, as a mode corresponding to the FS method, a ferroelectric liquid crystal (FLC:Fe) capable of high-speed operation is also available.
HV (Half V) using rroelectric liquid crystal
)-FLC, SS (Surface Stabilized)-FLC, etc. can also be used.

In addition, the optical response speed of the liquid crystal display module can be increased by narrowing the cell gap of the liquid crystal display module. In addition, the speed can also be increased by reducing the viscosity of the liquid crystal material. Increasing the speed is more effective when the pixel pitch of the pixel region of the TN mode liquid crystal display module is 30 μm or less. In addition, the speed can be increased by using an overdrive that momentarily increases (or decreases) the voltage applied to the liquid crystal layer from the normal voltage.

The liquid crystal display module of Fig. 87B shows a transmissive liquid crystal display module, and is provided with a red light source 23190a, a green light source 23190b, and a blue light source 23190c as light sources. A control unit 23199 is provided to control the on/off of each of the red light source 23190a, the green light source 23190b, and the blue light source 23190c.
The light emission of each color is controlled by the light emitting diode 9, the light is incident on the liquid crystal, and an image is synthesized using time division to display a color image.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 10)
In this embodiment, a method for driving a display device capable of implementing this embodiment will be described, and in particular, a method for driving a liquid crystal display device will be described.

First, the overdrive operation will be described with reference to FIG.
This shows the time change in output luminance of a display element relative to an input voltage. The time change in output luminance of a display element relative to an input voltage 30121 shown by a dashed line is shown by an output luminance 30123 also shown by a dashed line. That is, the voltage required to obtain the target output luminance Lo is Vi, but if Vi is directly input as the input voltage, it will take a time corresponding to the response speed of the element to reach the target output luminance Lo.

Overdrive is a technology to speed up this response speed.
This method involves applying a voltage Vo that is greater than Vi to the element for a certain period of time to increase the response speed of the output luminance until it approaches the desired output luminance Lo, and then returning the input voltage to Vi.
At this time, the input voltage is represented by an input voltage 30122, and the output luminance is represented by an output luminance 30124. In the graph of output luminance 30124, the time required to reach the target luminance Lo is shorter than that in the graph of output luminance 30123.

Although the case where the output luminance changes positively with respect to the input voltage has been described in FIG. 88A, this embodiment also includes the case where the output luminance changes negatively with respect to the input voltage.

A circuit for realizing such driving will be described with reference to Fig. 88B and Fig. 88C. First, with reference to Fig. 88B, a case will be described in which the input video signal 30131 is a signal having an analog value (which may be a discrete value) and the output video signal 30132 is also a signal having an analog value. The overdrive circuit shown in Fig. 88B includes an encoding circuit 30101, a frame memory 30102, a correction circuit 30103, a DA conversion circuit 30104, and a DAC 30105.
104.

An input video signal 30131 is first input to an encoding circuit 30101 and encoded. That is, the analog signal is converted into a digital signal with an appropriate number of bits. The converted digital signal is then input to a frame memory 30102 and a correction circuit 30103. The video signal of the previous frame held in the frame memory 30102 is also input to the correction circuit 30103 at the same time. Then, the correction circuit 30103 outputs a corrected video signal from the video signal of the current frame and the video signal of the previous frame according to a numerical table prepared in advance. At this time, an output switching signal 30133 may be input to the correction circuit 30103 so that the corrected video signal and the video signal of the current frame can be switched and output. Next, the corrected video signal or the video signal of the current frame is input to a DA conversion circuit 30104. Then, an output video signal 30132, which is an analog signal having a value according to the corrected video signal or the video signal of the current frame, is output. In this manner, overdrive driving can be realized.

Next, with reference to (C) of Fig. 88, a case will be described in which the input video signal 30131 is a signal having a digital value, and the output video signal 30132 is also a signal having a digital value.
The overdrive circuit shown in FIG. 8(C) includes a frame memory 30112, a correction circuit 301
13.

The input video signal 30131 is a digital signal. First, the input video signal 30131 is fed to a frame memory 30112 and
The image signal of the previous frame held in the frame memory 30112 is also input to the correction circuit 30113 at the same time. The correction circuit 30113 then outputs a corrected image signal from the image signal of the current frame and the image signal of the previous frame in accordance with a numerical value table prepared in advance. At this time, an output switching signal 30133 may be input to the correction circuit 30113 so that the corrected image signal and the image signal of the current frame can be switched and output. In this way, overdrive driving can be realized.

In addition, the overdrive circuit in this embodiment also includes a case where the input video signal 30131 is an analog signal and the output video signal 30132 is a digital signal. In this case,
The DA conversion circuit 30104 can be omitted from the circuit shown in Fig. 88B. The overdrive circuit in this embodiment also includes a case where the input video signal 30131 is a digital signal and the output video signal 30132 is an analog signal. In this case, the encoding circuit 30101 can be omitted from the circuit shown in Fig. 88B.

Next, the driving for controlling the potential of the common line will be described with reference to FIG.
89A) is a diagram showing a plurality of pixel circuits when one common line is arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. The pixel circuit shown in Fig. 89A includes a transistor 30201, an auxiliary capacitance 30202, a display element 30203, a video signal line 30204, a scanning line 30205, and a common line 30206.

A gate electrode of the transistor 30201 is electrically connected to a scanning line 30205, one of a source electrode or a drain electrode of the transistor 30201 is electrically connected to a video signal line 30204, and the other of the source electrode or the drain electrode of the transistor 30201 is electrically connected to one electrode of the auxiliary capacitance 30202 and one electrode of the display element 30203. In addition, the other electrode of the auxiliary capacitance 30202 is electrically connected to a common line 30206.

First, in a pixel selected by a scanning line 30205, a transistor 30201 is turned on, and a voltage corresponding to a video signal is applied to a display element 30203 and an auxiliary capacitor 30202 via a video signal line 30204. At this time, the video signal is applied to a common line 3
If all pixels connected to common line 30206 are to display the lowest gradation, or if all pixels connected to common line 30206 are to display the highest gradation, there is no need to write a video signal to each pixel via video signal line 30204.
Instead of writing a video signal through the video signal line 30204 , the voltage applied to the display element 30203 can be changed by changing the potential of the common line 30206 .

Next, Fig. 89B is a diagram showing a plurality of pixel circuits when two common lines are arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. The pixel circuit shown in Fig. 89B includes a transistor 30211, an auxiliary capacitance 30212, a display element 30213, a video signal line 30214, a scanning line 30215, a first common line 30216, and a second common line 30217.

A gate electrode of the transistor 30211 is electrically connected to a scanning line 30215, one of a source electrode or a drain electrode of the transistor 30211 is electrically connected to a video signal line 30214, and the other of the source electrode or the drain electrode of the transistor 30211 is electrically connected to one electrode of an auxiliary capacitance 30212 and one electrode of a display element 30213. The other electrode of the auxiliary capacitance 30212 is electrically connected to a first common line 30216. In addition, in a pixel adjacent to the pixel, the auxiliary capacitance 30212
The other electrode is electrically connected to the second common line 30217.

In the pixel circuit shown in FIG. 89B, since there are few pixels electrically connected to one common line, instead of writing a video signal through a video signal line 30214, the potential of the first common line 30216 or the second common line 30217 is changed to change the potential of the display element 30213.
The frequency with which the voltage applied to the pixel can be changed is significantly increased. In addition, source inversion driving or dot inversion driving is possible. By using the source inversion driving or dot inversion driving, the reliability of the element can be improved while flicker can be suppressed.

Next, the scanning backlight will be described with reference to Fig. 90. Fig. 90(A) is a diagram showing a scanning backlight in which cold cathode tubes are arranged in a row. The scanning backlight shown in Fig. 90(A) includes a diffusion plate 30301 and N cold cathode tubes 30302-1 to 30302-N. By arranging the N cold cathode tubes 30302-1 to 30302-N in a row behind the diffusion plate 30301, the N cold cathode tubes 30302-1 to 30302-N can be scanned by changing their luminance.

The change in luminance of each cold cathode tube during scanning will be described with reference to FIG. 90C. First, the luminance of the cold cathode tube 30302-1 is changed for a certain period of time. Then, the luminance of the cold cathode tube 30302-2 is changed for a certain period of time.
The luminance of the cold cathode tube 30302-2 arranged next to the cold cathode tube 30302-1 is changed for the same period of time. In this manner, the luminance is changed in order from the cold cathode tube 30302-1 to 30302-N. Note that, although the luminance changed for a certain period of time is set to be smaller than the original luminance in FIG. 90C, it may be larger than the original luminance.
Although scanning is performed up to cold cathode fluorescent tube 30302-N in the above embodiment, scanning may be performed in the reverse direction from cold cathode fluorescent tube 30302-N to 30302-1.

90, the average luminance of the backlight can be reduced, and therefore the power consumption of the backlight, which accounts for most of the power consumption of a liquid crystal display device, can be reduced.

Note that LEDs may be used as the light source of the scanning backlight. In that case, the scanning backlight will be as shown in Fig. 90B. The scanning backlight shown in Fig. 90B includes a diffusion plate 30311 and light sources 30312-1 to 30312-N in which LEDs are arranged side by side. When LEDs are used as the light source of the scanning backlight, the backlight can be made thin and
The light source 30312-1 to 30312-N in which LEDs are arranged in parallel has an advantage of being lighter. The light source 30312-1 to 30312-N in which LEDs are arranged in parallel have an advantage of being lighter.
D can also be scanned in the same manner, so that a point-scanning type backlight can also be used.
If a point scanning type is used, the image quality of the moving image can be further improved.

When an LED is used as the light source of the backlight, the LED can be driven with its luminance changed as shown in FIG.

Next, high-frequency driving will be described with reference to Fig. 91. Fig. 91(A) is a diagram showing a case where one image and one intermediate image are displayed in one frame period 30400.
30401 is the image of the current frame, 30402 is an intermediate image of the current frame, 30403 is the image of the next frame, and 30404 is an intermediate image of the next frame.

The intermediate image 30402 of the frame may be an image created based on the video signals of the frame and the next frame. The intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. The intermediate image 30402 of the frame may be a black image. This can improve the image quality of the moving image of the hold-type display device. In addition, when one image and one intermediate image are displayed in one frame period 30400, there is an advantage that it is easy to achieve consistency with the frame rate of the video signal and the image processing circuit does not become complicated.

91B is a diagram showing a case where one image and two intermediate images are displayed during two consecutive periods (two frame periods) of one frame period 30400. 30411 is the image of the frame, 30412 is the intermediate image of the frame, 30413 is the intermediate image of the next frame, 30440 is the intermediate image of the next frame,
0414 is an image of the next frame.

The intermediate image 30412 of the current frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the current frame, the next frame, and the frame after the next frame.
A black image may be used. When one image and two intermediate images are displayed in two frame periods, there is an advantage that the image quality of a moving image can be effectively improved without significantly increasing the operating frequency of the peripheral driving circuits.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 11)
In this embodiment, a pixel structure of a display device in which this embodiment can be implemented will be described, in particular, a pixel structure of a display device using an organic EL element will be described.

FIG. 92A shows an example of a layout of pixel elements having two TFTs in one pixel.
Moreover, a cross-sectional view of a portion indicated by XX' in FIG. 92(A) is shown in FIG. 92(B).

As shown in FIG. 92A, the pixel in this embodiment mode includes a first TFT 60105,
A first wiring 60106, a second wiring 60107, a second TFT 60108, a third wiring 6
0111, counter electrode 60112, capacitor 60113, pixel electrode 60115, partition wall 60
The first TFT 60105 may have a first wiring 601 as a switching TFT.
06 is a gate signal line, a second wiring 60107 is a source signal line, and a second TFT
It is preferable that 60108 is used as a driving TFT, and the third wiring 60111 is used as a current supply line.

As shown in FIG. 92A, the gate electrode of the first TFT 60105 is connected to the first wiring 60
It is preferable that the first TFT 60105 is electrically connected to the second wiring 60106, one of the source electrode or the drain electrode of the first TFT 60105 is electrically connected to the second wiring 60107, and the other of the source electrode or the drain electrode of the first TFT 60105 is electrically connected to the gate electrode of the second TFT 60108 and one electrode of the capacitor 60113.
92A, the gate electrode of the first TFT 60105 may be composed of a plurality of gate electrodes, which can reduce the leakage current when the first TFT 60105 is in the off state.

In addition, one of the source electrode and the drain electrode of the second TFT 60108 is connected to the third wiring 6
It is preferable that the other of the source electrode or drain electrode of the second TFT 60108 is electrically connected to the pixel electrode 60115. In this way, the current flowing through the pixel electrode 60115 can be controlled by the second TFT 60108.

An organic conductive film 60117 is provided on the pixel electrode 60115, and an organic thin film 601
A counter electrode 60112 may be provided on the organic thin film 60118 (organic compound layer). The counter electrode 60112 may be formed in a solid form so that it is commonly connected to all pixels, or may be formed in a pattern using a shadow mask or the like.

Light emitted from the organic thin film 60118 (organic compound layer) is emitted after passing through either the pixel electrode 60115 or the counter electrode 60112. In this case, in Fig. 92(B), when light is emitted toward the pixel electrode side, i.e., the side where TFTs and the like are formed, it is called bottom emission, and when light is emitted toward the counter electrode side, it is called top emission.

In the case of bottom emission, the pixel electrode 60115 is preferably formed from a transparent conductive film.
Conversely, in the case of top emission, the counter electrode 60112 is preferably formed from a transparent conductive film.

In a light-emitting device for color display, EL elements having the respective luminous colors of R, G, and B may be painted separately, or single-color EL elements may be painted in a solid manner and R may be separated by a color filter.
It is also possible to obtain G and B light emission.

It should be noted that the configuration shown in Fig. 92 is merely one example, and various configurations can be used with respect to the pixel layout, cross-sectional configuration, stacking order of electrodes of the EL element, etc., other than the configuration shown in Fig. 92. Also, for the light-emitting layer, in addition to the element constituted by the illustrated organic thin film, various elements can be used, such as a crystalline element such as an LED, an element constituted by an inorganic thin film, etc.

Next, an example of the layout of pixel elements having three TFTs in one pixel will be described with reference to Fig. 93(A). Also, Fig. 93(B) shows a cross-sectional view of the portion indicated by XX' in Fig. 93(A).

As shown in FIG. 93A, the pixel in this embodiment mode includes a substrate 60200, a first wiring 60201, a second wiring 60202, a third wiring 60203, a fourth wiring 60204, a first TFT 60205, a second TFT 60206, a third TFT 60207, a pixel electrode 60208, and a second TFT 60209.
0208, partition wall 60211, organic conductive film 60212, organic thin film 60213, counter electrode 6
The first wiring 60201 may be used as a source signal line, the second wiring 60202 as a write gate signal line, the third wiring 60203 as an erase gate signal line, the fourth wiring 60204 as a current supply line, the first TFT 60205 as a switching TFT, the second TFT 60206 as an erase TFT, and the third TFT 60207 as a switching TFT.
T60207 is preferably used as a driving TFT.

As shown in FIG. 93A, the gate electrode of the first TFT 60205 is connected to the second wiring 602.
93A. It is preferable that the first TFT 60205 is electrically connected to the first wiring 60202, one of the source electrode or drain electrode of the first TFT 60205 is electrically connected to the first wiring 60201, and the other of the source electrode or drain electrode of the first TFT 60205 is electrically connected to the gate electrode of the third TFT 60207. Note that the gate electrode of the first TFT 60205 may be composed of a plurality of gate electrodes as shown in FIG. 93A. This can reduce leakage current when the first TFT 60205 is in an off state.

The gate electrode of the second TFT 60206 is electrically connected to the third wiring 60203, and one of the source electrode and the drain electrode of the second TFT 60206 is electrically connected to the fourth wiring 60
204, and the other of the source electrode or drain electrode of the second TFT 60206 is preferably electrically connected to the gate electrode of the third TFT 60207. Note that the gate electrode of the second TFT 60206 may be composed of a plurality of gate electrodes as shown in Fig. 93(A). This makes it possible to reduce the leakage current when the second TFT 60206 is in the off state.

In addition, one of the source electrode and the drain electrode of the third TFT 60207 is connected to the fourth wiring 6
It is preferable that the other of the source electrode or the drain electrode of the third TFT 60207 is electrically connected to the pixel electrode 60208. In this way, the current flowing through the pixel electrode 60208 can be controlled by the third TFT 60207.

An organic conductive film 60212 is provided on the pixel electrode 60208, and an organic thin film 602
A counter electrode 60214 may be provided on the organic thin film 60213 (organic compound layer). The counter electrode 60214 may be formed in a solid form so as to be commonly connected to all pixels, or may be formed in a pattern using a shadow mask or the like.

Light emitted from the organic thin film 60213 (organic compound layer) is emitted through either the pixel electrode 60208 or the counter electrode 60214. In this case, in Fig. 93(B), when light is emitted toward the pixel electrode side, i.e., the side where TFTs and the like are formed, it is called bottom emission, and when light is emitted toward the counter electrode side, it is called top emission.

In the case of bottom emission, the pixel electrode 60208 is preferably formed from a transparent conductive film.
Conversely, in the case of top emission, the counter electrode 60214 is preferably formed from a transparent conductive film.

In a light-emitting device for color display, EL elements having the respective luminous colors of R, G, and B may be painted separately, or single-color EL elements may be painted in a solid manner and R may be separated by a color filter.
, G, and B light emission may be obtained.

It should be noted that the configuration shown in Fig. 93 is merely one example, and various configurations can be adopted with respect to the pixel layout, cross-sectional configuration, stacking order of electrodes of the EL element, etc., other than the configuration shown in Fig. 93. Also, for the light-emitting layer, in addition to the element constituted by the illustrated organic thin film, various elements can be used, such as a crystalline element such as an LED, an element constituted by an inorganic thin film, etc.

Next, an example of the layout of pixel elements having four TFTs in one pixel will be described with reference to Fig. 94(A). Also, Fig. 94(B) shows a cross-sectional view of the portion indicated by XX' in Fig. 94(A).

As shown in FIG. 94A, the pixel in this embodiment mode includes a substrate 60300, a first wiring 60301, a second wiring 60302, a third wiring 60303, a fourth wiring 60304, a first TFT 60305, a second TFT 60306, a third TFT 60307, a fourth TFT 60308, a second TFT 60309, a third TFT 60310, a fourth TFT 60311, and a fourth TFT 60312.
The pixel electrode 60309 may include a T 60308, a pixel electrode 60309, a fifth wiring 60311, a sixth wiring 60312, a partition wall 60321, an organic conductive film 60322, an organic thin film 60323, and a counter electrode 60324. The first wiring 60301 may be connected to the second wiring 60324 as a source signal line.
The reference numeral 302 denotes a gate signal line for writing, the third wiring 60303 denotes an erase gate signal line, the fourth wiring 60304 denotes a reverse bias signal line, the first TFT 60305 denotes a switching TFT, the second TFT 60306 denotes an erase TFT, and the third TFT
The fourth TFT 60308 is a reverse bias TFT.
It is preferable that the fifth wiring 60311 is used as a current supply line, and the sixth wiring 60312 is used as a reverse bias power supply line.

As shown in FIG. 94A, the gate electrode of the first TFT 60305 is connected to the second wiring 603.
94A, the gate electrode of the first TFT 60305 may be electrically connected to the gate electrode of the third TFT 60307. Preferably, the gate electrode of the first TFT 60305 is electrically connected to the first wiring 60301, and one of the source electrode and drain electrode of the first TFT 60305 is electrically connected to the gate electrode of the third TFT 60307. Note that the gate electrode of the first TFT 60305 may be composed of a plurality of gate electrodes as shown in FIG. 94A. This can reduce leakage current when the first TFT 60305 is in an off state.

The gate electrode of the second TFT 60306 is electrically connected to the third wiring 60303, and one of the source electrode and the drain electrode of the second TFT 60306 is electrically connected to the fifth wiring 60311.
and the other of the source electrode or drain electrode of the second TFT 60306 is preferably electrically connected to the gate electrode of the third TFT 60307. Note that the gate electrode of the second TFT 60306 may be composed of a plurality of gate electrodes as shown in Fig. 94 (A). This makes it possible to reduce the leakage current when the second TFT 60306 is in an off state.

One of the source electrode and the drain electrode of the third TFT 60307 is connected to the fifth wiring 6031.
It is preferable that the other of the source electrode or the drain electrode of the third TFT 60307 is electrically connected to the pixel electrode 60309. In this way, the current flowing through the pixel electrode 60309 can be controlled by the third TFT 60307.

The gate electrode of the fourth TFT 60308 is electrically connected to the fourth wiring 60304, and one of the source electrode and the drain electrode of the fourth TFT 60308 is electrically connected to the sixth wiring 60312.
and the other of the source electrode or the drain electrode of the fourth TFT 60308 is preferably electrically connected to the pixel electrode 60309. In this way, the potential of the pixel electrode 60309 can be controlled by the fourth TFT 60308,
A reverse bias can be applied to the organic conductor film 60322 and the organic thin film 60323. By applying a reverse bias to a light-emitting element constituted by the organic conductor film 60322 and the organic thin film 60323, etc., the reliability of the light-emitting element can be greatly improved.

For example, it has been found that a light-emitting element whose brightness half-life is approximately 400 hours when driven with a DC voltage (3.65 V) will have a brightness half-life of 700 hours or more when driven with an AC voltage (forward bias: 3.7 V, reverse bias: 1.7 V, duty 50%, AC frequency 60 Hz).

An organic conductive film 60322 is provided on the pixel electrode 60309, and an organic thin film 603
A counter electrode 60324 may be provided on the organic thin film 60323 (organic compound layer). The counter electrode 60324 may be formed in a solid form so as to be commonly connected to all pixels, or may be formed in a pattern using a shadow mask or the like.

Light emitted from the organic thin film 60323 (organic compound layer) is emitted through either the pixel electrode 60309 or the counter electrode 60324. In this case, in Fig. 94(B), when light is emitted toward the pixel electrode side, i.e., the side where TFTs and the like are formed, it is called bottom emission, and when light is emitted toward the counter electrode side, it is called top emission.

In the case of bottom emission, the pixel electrode 60309 is preferably formed from a transparent conductive film.
Conversely, in the case of top emission, the counter electrode 60324 is preferably formed from a transparent conductive film.

In a light-emitting device for color display, EL elements having the respective luminescent colors of R, G, and B may be painted separately, or single-color EL elements may be painted in a solid form and R, G, and B may be colored by color filters.
It is also possible to obtain B light emission.

It should be noted that the configuration shown in Fig. 94 is merely one example, and various configurations can be adopted with respect to the pixel layout, cross-sectional configuration, stacking order of electrodes of the EL element, etc., other than the configuration shown in Fig. 94. Also, for the light-emitting layer, in addition to the element constituted by the illustrated organic thin film, various elements can be used, such as a crystalline element such as an LED, an element constituted by an inorganic thin film, etc.

Next, we will explain the structure of the EL element that can be applied to this embodiment.

The EL element applicable to the present embodiment does not have a laminated structure in which a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, etc. are clearly distinguished from each other, but may have a structure having a layer (mixed layer) in which a plurality of materials such as a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material are mixed (hereinafter, referred to as a mixed junction type EL element).

A schematic diagram showing the structure of a mixed junction EL element is shown in FIG.
The EL element has an anode 1 and a cathode 60402. A layer sandwiched between the anode 60401 and the cathode 60402 corresponds to an EL layer.

In FIG. 95(A), the EL layer includes a hole transport region 60403 made of a hole transport material and an electron transport region 60404 made of an electron transport material. The hole transport region 60403 is located closer to the anode than the electron transport region 60404. A mixed region 60404 containing both the hole transport material and the electron transport material is located between the hole transport region 60403 and the electron transport region 60404.
405 may be provided.

In addition, it may be characterized in that, in the direction from the anode 60401 to the cathode 60402, the concentration of the hole transport material in the mixed region 60405 decreases and the concentration of the electron transport material in the mixed region 60405 increases.

In the above-mentioned configuration, the hole transport region 60403 made only of the hole transport material may not exist, and the concentration ratio of each functional material may change (have a concentration gradient) inside the mixed region 60405 containing both the hole transport material and the electron transport material.
Alternatively, the concentration ratio of each functional material may be changed (having a concentration gradient) within the mixed region 60405 that contains both the hole transport material and the electron transport material, without the presence of a hole transport material. The concentration ratio may be changed depending on the distance from the anode or the cathode. Furthermore, the change in the concentration ratio may be continuous. The method of setting the concentration gradient can be freely set.

The mixed region 60405 has a region 60406 to which a light-emitting material is added. The light-emitting color of the EL element can be controlled by the light-emitting material. Furthermore, the light-emitting material can trap carriers. As the light-emitting material, metal complexes containing a quinoline skeleton, metal complexes containing a benzoxazole skeleton, metal complexes containing a benzothiazole skeleton, and various fluorescent dyes can be used. By adding these light-emitting materials, the light-emitting color of the EL element can be controlled.

For the anode 60401, an electrode material having a large work function is preferably used in order to efficiently inject holes. For example, a transparent electrode such as tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), ZnO, SnO ₂ , or In ₂ O ₃ can be used. If there is no need for light transmission, the anode 60401 may be an opaque metal material.

Aromatic amine compounds and the like can be used as hole transport materials.

As the electron transport material, a metal complex having a quinoline derivative, 8-quinolinol or a derivative thereof as a ligand (particularly, tris(8-quinolinolite)aluminum (Alq ₃ )) or the like can be used.

For the cathode 60402, it is preferable to use an electrode material with a small work function in order to efficiently inject electrons. Metals such as aluminum, indium, magnesium, silver, calcium, barium, and lithium can be used alone. In addition, alloys of these metals or alloys of these metals with other metals may also be used.

A schematic diagram of an EL element having a different structure from that shown in FIG.
The same parts as those in A) are designated by the same reference numerals, and the explanation thereof will be omitted.

In FIG. 95B, there is no region doped with light-emitting material. However, the electron transport region 604
As a material to be added to the compound 04, a material having both an electron transporting property and a light emitting property (electron transporting light emitting material), for example, tris(8-quinolinolite)aluminum (Alq ₃ ) may be used, which can emit light.

Alternatively, a material having both hole transport properties and light emitting properties (hole transport light emitting material) may be used as the material to be added to the hole transport region 60403 .

Fig. 95(C) is a schematic diagram of an EL element having a different structure from those in Fig. 95(A) and Fig. 95(B). Note that the same parts as those in Fig. 95(A) and Fig. 95(B) are denoted by the same reference numerals, and the description thereof will be omitted.

95C, a region 60407 is provided in the mixed region 60405 to which a hole blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital than that of the hole transporting material is added. By disposing the region 60407 to which the hole blocking material is added closer to the cathode 60402 side than the region 60406 to which the light emitting material is added in the mixed region 60405, the recombination rate of carriers can be increased, and the light emitting efficiency can be improved. The above-mentioned structure in which the region 60407 to which the hole blocking material is added is provided is particularly effective in an EL element that utilizes light emission (phosphorescence) due to triple photoexcitons.

FIG. 9 shows a schematic diagram of an EL element having a different structure from those shown in FIG. 95(A), FIG. 95(B), and FIG. 95(C).
95(A), 95(B) and 95(C) are denoted by the same reference numerals and the description thereof will be omitted.

95D, a region 60408 is provided in the mixed region 60405 to which an electron blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital than that of the electron transporting material is added. By disposing the region 60408 to which the electron blocking material is added closer to the anode 60401 than the region 60406 to which the light emitting material is added in the mixed region 60405, the carrier recombination rate can be increased, and the light emitting efficiency can be improved. The above-mentioned configuration in which the region 60408 to which the electron blocking material is added is provided is particularly effective in an EL element that utilizes light emission (phosphorescence) due to triple photoexcitons.

Fig. 95(E) is a schematic diagram showing the configuration of a mixed junction type EL element different from Fig. 95(A), Fig. 95(B), Fig. 95(C) and Fig. 95(D). Fig. 95(E) shows an example of a configuration having a region 60409 to which a metal material is added in the portion of the EL layer that contacts the electrode of the EL element. In Fig. 95(E), the same parts as Fig. 95(A) to Fig. 95(D) are indicated by the same reference numerals and the description will be omitted. The configuration shown in Fig. 95(E) uses, for example, MgA
Alternatively, the electron transport region 60404 may be made of Mg—Ag alloy, and the region in contact with the cathode 60402 may have a region 60409 to which an Al (aluminum) alloy is added, the region being in contact with the cathode 60402. With the above-mentioned structure, it is possible to prevent oxidation of the cathode and to increase the efficiency of injection of electrons from the cathode. In this way, the life of the mixed junction EL element can be extended. Also, the driving voltage can be reduced.

The above-mentioned mixed junction EL element can be fabricated by a co-evaporation method or the like.

In the mixed junction EL element as shown in Figures 95(A) to 95(E), there is no clear layer interface, and the charge accumulation can be reduced, thus extending the lifetime of the element, and the driving voltage can be reduced.

The configurations shown in Figures 95(A) to 95(E) can be freely combined and implemented.

The structure of the mixed junction EL element is not limited to this, and any known structure can be freely used.

The organic material constituting the EL layer of the EL element may be a low molecular weight material or a high molecular weight material. In addition, both of these materials may be used. When a low molecular weight material is used as the organic compound material, a film can be formed by a deposition method. On the other hand, when a high molecular weight material is used as the EL layer, the high molecular weight material is dissolved in a solvent and a film can be formed by a spin coating method or an inkjet method.

The EL layer may be made of a medium molecular weight material. In this specification, a medium molecular weight organic light emitting material refers to an organic light emitting material that does not have sublimation properties and has a degree of polymerization of about 20 or less. When a medium molecular weight material is used as the EL layer, the film can be formed by an inkjet method or the like.

A combination of low molecular weight materials, high molecular weight materials, and medium molecular weight materials may also be used.

The EL element may be either one that utilizes light emission from singlet excitons (fluorescence) or one that utilizes light emission from triplet excitons (phosphorescence).

Next, a deposition apparatus for manufacturing a display device to which the present embodiment can be applied will be described with reference to the drawings.

The display device to which the present embodiment can be applied may be manufactured by forming an EL layer.
The EL layer is formed by at least partially containing a material that exhibits electroluminescence. The EL layer may be composed of a plurality of layers with different functions. In this case, the EL layer may be composed of a combination of layers with different functions, which are also called hole injection transport layers, light emitting layers, electron injection transport layers, etc.

The configuration of a deposition apparatus for forming an EL layer on an element substrate on which a transistor is formed is shown in FIG.
In this deposition apparatus, multiple processing chambers are connected to transfer chambers 60560 and 60561. The processing chambers include a load chamber 60562 for supplying substrates, an unload chamber 60563 for recovering substrates, and a
63, and other chambers include a heat treatment chamber 60568, a plasma treatment chamber 60572, film formation chambers 60569 to 60575 for depositing an EL material, and a film formation chamber 60576 for forming an aluminum or aluminum-based conductive film as one electrode of an EL element. Gate valves 60577a to 60577m are provided between the transfer chamber and each treatment chamber, and the pressure of each treatment chamber can be controlled independently to prevent mutual contamination between the treatment chambers.

The substrate introduced from the load chamber 60562 into the transfer chamber 60560 is carried into a predetermined processing chamber by a rotatably mounted arm-type transfer means 60566. The substrate is also transferred from one processing chamber to another processing chamber by the transfer means 60566. The transfer chamber 60560 and the transfer chamber 60561 are connected by a film forming processing chamber 60570, where the transfer means 60566 and the transfer means 60567 transfer the substrate.

Each processing chamber connected to the transfer chamber 60560 and the transfer chamber 60561 is maintained in a reduced pressure state. Therefore, in this deposition apparatus, the EL layer is continuously formed on the substrate without being exposed to the atmosphere. Since the display panel after the EL layer formation process may deteriorate due to water vapor, etc., in this deposition apparatus, a sealing treatment chamber 60565 is connected to the transfer chamber 60561 to perform a sealing treatment before exposing the display panel to the atmosphere in order to maintain quality.
Since the pressure in the chamber 65 is atmospheric pressure or a reduced pressure close to atmospheric pressure, an intermediate processing chamber 60564 is also provided between the transfer chamber 60561 and the sealing processing chamber 60565.
is provided for transferring the substrate and for buffering the pressure between the chambers.

The load chamber, unload chamber, transfer chamber and film forming chamber are provided with exhaust means for maintaining the interior of the chamber at a reduced pressure. As the exhaust means, various types of vacuum pumps such as a dry pump, a turbo molecular pump and a diffusion pump can be used.

96, the number and configuration of the processing chambers connected to the transfer chamber 60560 and the transfer chamber 60561 can be appropriately combined according to the laminated structure of the EL element. An example of such a combination is shown below.

The heat treatment chamber 60568 first heats the substrate on which the lower electrode, insulating partition wall, etc. are formed to perform degassing treatment. The plasma treatment chamber 60572 performs rare gas or oxygen plasma treatment on the surface of the base electrode. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state of the surface (e.g., work function, etc.).

The film forming processing chamber 60569 is a processing chamber for forming an electrode buffer layer that contacts one electrode of the EL element. The electrode buffer layer has a carrier injection property (hole injection or electron injection), and
Typically, the electrode buffer layer is made of an organic/inorganic mixed material, has a resistivity of 5×10 ⁴ to 1×10 ⁶ Ωcm, and has a resistivity of 30 to 300 Ωcm.
The film formation chamber 60571 is a treatment chamber for forming a hole transport layer.

The light-emitting layer in an EL element has a different structure depending on whether it emits a single color or white light. It is preferable to arrange the film-forming chamber in the deposition apparatus accordingly. For example,
When forming three types of EL elements with different light emission colors on a display panel, it is necessary to form a light emitting layer corresponding to each light emission color. In this case, the film formation treatment chamber 60570 can be used for forming the first light emitting layer, the film formation treatment chamber 60573 can be used for forming the second light emitting layer, and the film formation treatment chamber 60574 can be used for forming the third light emitting layer. By separating the film formation treatment chambers for each light emitting layer, mutual contamination by different light emitting materials can be prevented, and the throughput of the film formation process can be improved.

Three types of EL materials with different luminescent colors may be sequentially deposited in the deposition treatment chambers 60570, 60573, and 60574. In this case, a shadow mask is used, and deposition is performed by shifting the mask according to the region to be deposited.

When forming an EL element that emits white light, light-emitting layers of different colors are stacked vertically. In this case, too, the element substrate is moved sequentially through the deposition chambers to deposit each light-emitting layer. Also, different light-emitting layers can be deposited consecutively in the same deposition chamber.

An electrode is formed on the EL layer in the film formation treatment chamber 60576. The electrode can be formed by electron beam evaporation or sputtering, but is preferably formed by resistance heating evaporation.

The element substrate on which the electrodes have been formed is passed through an intermediate processing chamber 60564 and then into a sealing processing chamber 60565.
The sealing treatment chamber 60565 is filled with an inert gas such as helium, argon, neon, or nitrogen, and a sealing plate is attached to the side of the element substrate on which the EL layer is formed in this atmosphere to seal the element substrate.
The sealing chamber 6 may be filled with an inert gas or a resin material.
The device 0565 is equipped with a dispenser for applying a sealant, mechanical elements such as a fixed stage or arm for fixing a sealing plate opposite to the element substrate, and a dispenser or spin coater for filling a resin material.

Fig. 97 shows the internal structure of the film forming processing chamber. The film forming processing chamber is kept under reduced pressure, and in Fig. 97, the inside of the chamber is sandwiched between a top plate 60691 and a bottom plate 60692, and the chamber is kept under reduced pressure.

One or more evaporation sources are provided in the processing chamber. When forming multiple layers with different compositions or when co-evaporating different materials, it is preferable to provide multiple evaporation sources. In Fig. 97, evaporation sources 60681a, 60681b, and 60681c are attached to an evaporation source holder 60680. The evaporation source holder 60680 is held by an articulated arm 60683. The articulated arm 60683 extends and retracts the joints of the evaporation source holder 60680.
The position of the evaporation source holder 606 can be freely moved within its movable range.
A distance sensor 60682 is provided on the substrate 606.
The optimum gap during deposition may be controlled by monitoring the gap between the arm 89. In that case, the arm may be a multi-joint arm that is displaceable in the vertical direction (Z direction).

The substrate stage 60686 and the substrate chuck 60687 form a pair and fix the substrate 60689. The substrate stage 60686 may be configured to incorporate a heater so that the substrate 60689 can be heated. The substrate 60689 is fixed to the substrate stage 60686 and is carried in and out by loosening the substrate chuck 60687. For deposition, a shadow mask 60690 having openings corresponding to the pattern to be deposited can be used as necessary. In that case, the shadow mask 60690 is arranged to cover the substrate 60689 and the evaporation sources 60681a to 60681c.
The shadow mask 60690 is fixed by a mask chuck 60688 so as to be in close contact with or spaced apart from the substrate 60689.
When alignment of 0690 is required, a camera is placed in the processing chamber, and the mask chuck 60688 is provided with a positioning means that moves slightly in the XY-θ directions to perform the alignment.

The evaporation source 60681 is provided with an evaporation material supplying means for continuously supplying an evaporation material to the evaporation source. The evaporation material supplying means includes material supply sources 60685a, 60685b, and 60685c arranged at positions apart from the evaporation source 60681, and a material supply pipe 6068 connecting the two.
Typically, the material supply sources 60685a, 60685b, and 60685c are provided corresponding to the evaporation source 60681. In the case of FIG. 97, the material supply source 60685a
and 606 evaporation source 81a correspond to the material supply source 60685b and the evaporation source 60681b.
The same applies to the material supply source 60685c and the evaporation source 60681c.

The evaporation material can be supplied by an air current transport method, an aerosol method, or the like. The air current transport method transports the evaporation material in fine powder on an air current, and transports it to the evaporation source 60681 using an inert gas or the like. The aerosol method transports a raw material liquid in which the evaporation material is dissolved or dispersed in a solvent, turns it into an aerosol using a sprayer, and performs evaporation while vaporizing the solvent in the aerosol. In either case, the evaporation source 60681 is provided with a heating means, and the transported evaporation material is evaporated to form a film on the substrate 60689. In the case of FIG. 97, the material supply pipe 60684
It is made of thin tubes that can be bent flexibly and have sufficient rigidity so that they do not deform even under reduced pressure.

When the airflow transport method or the aerosol method is applied, the film may be formed in the film forming process chamber at atmospheric pressure or lower, preferably at a reduced pressure of 133 Pa to 13,300 Pa. The film forming process chamber may be filled with an inert gas such as helium, argon, neon, krypton, xenon, or nitrogen, or the pressure may be adjusted while supplying the gas (while simultaneously evacuating the gas). In addition, a gas such as oxygen or nitrous oxide may be introduced into the film forming process chamber where an oxide film is formed to create an oxidizing atmosphere. In addition, a gas such as hydrogen may be introduced into the film forming process chamber where an organic material is evaporated to create a reducing atmosphere.

As another method for supplying the evaporation material, a screw may be provided in the material supply pipe 60684 to continuously push out the evaporation material toward the evaporation source.

This deposition apparatus can continuously form a film with good uniformity even on a large-screen display panel. In addition, since it is not necessary to replenish the deposition material every time the deposition source runs out of the deposition material, the throughput can be improved.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 12)
In this embodiment, a pixel circuit and a driving method of a display device in which this embodiment can be implemented will be described.

First, digital time gray scale driving applicable to this embodiment will be described. First, a driving method in which a signal writing period (address period) to a pixel and a light emission period (sustain period) are separated will be described with reference to Fig. 98 (A). Here, a case of 4-bit digital time gray scale will be described as an example.

A period for completely displaying an image of one display area is called one frame period. One frame period has multiple subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required to write signals to all rows of pixels, and the periods Tb1 to Tb4 indicate the time required to write signals to one row of pixels (or one pixel). The sustain periods Ts1 to Ts4 indicate the time during which the pixels are maintained in a lit or unlit state according to the video signals written to them, and the ratio of their lengths is Ts1:Ts2:Ts3:Ts4 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8:4:2:1. The gradation is expressed by which sustain period is lighted.

The operation will be described. First, in the address period Ta1, pixel selection signals are input to the scanning lines in order from the first row, and pixels are selected. Then, when a pixel is selected, a video signal is input to the pixel from the signal line. Then, when a video signal is written to a pixel, the pixel holds the signal until a signal is input again. The written video signal controls the lighting and non-lighting of each pixel in the sustain period Ts1. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and the video signals control the lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4. Then, in each subframe period, the pixels are not lit during the address period, and after the address period ends, the sustain period begins, and the pixels to which a signal for lighting is written are lit.

Here, with reference to FIG. 98B, a description will be given focusing on the i-th pixel row. First, in an address period Ta1, pixel selection signals are input to the scanning lines starting from the first row.
During period Tb1(i) of a1, the pixels in the i-th row are selected. When the pixels in the i-th row are selected, a video signal is input from the signal line to the pixels in the i-th row.
When a video signal is written to the pixels in the i-th row, the pixels in the i-th row hold the signal until a signal is input again. The written video signal controls whether the pixels in the i-th row are turned on or off during the sustain period Ts1. Similarly, during the address periods Ta2, Ta3, and Ts4,
At a4, a video signal is input to the pixels in the i-th row, and the video signal controls whether the pixels in the i-th row are turned on or off during the sustain periods Ts2, Ts3, and Ts4. In each subframe period, the pixels are not turned on during the address period, and after the address period ends, the sustain period begins, and the pixels to which a signal to turn on the pixels is written are turned on.

Although the case of expressing 4-bit gradation has been described here, the number of bits and the number of gradations are not limited to this. Also, the lighting order does not have to be Ts1, Ts2, Ts3, and Ts4, but may be random, or may be divided into a plurality of parts for light emission.
The lighting times Ts3, Ts4 do not need to be powers of two, and may be the same length or may be slightly shifted from a power of two.

Next, a driving method in which the signal writing period (address period) to the pixels and the light emission period (sustain period) are not separated will be described. In other words, the pixels in a row in which the video signal writing operation has been completed retain the signal until the next signal writing (or erasure) to the pixel. The period from the writing operation to the next signal writing to the pixel is called the data retention time. During this data retention time, the pixel is turned on or off according to the video signal written to the pixel. The same operation is performed up to the last row, and the address period ends. Then, the signal writing operation for the next sub-frame period is started in order from the row in which the data retention time has ended.

In this way, in the case of a driving method in which the pixel is turned on or off according to the video signal written to the pixel immediately after the signal writing operation is completed and the data holding time is reached, even if it is attempted to make the data holding time shorter than the address period, signals cannot be input to two rows at the same time, so the address periods must not overlap, and therefore the data holding time cannot be shortened, which results in difficulty in performing high gradation display.

Therefore, by providing an erase period, a data holding time shorter than the address period is set. A driving method in which an erase period is provided to set a data holding time shorter than the address period will be described with reference to FIG.

First, in an address period Ta1, pixel scanning signals are input to the scanning lines starting from the first row.
A pixel is selected. When the pixel is selected, a video signal is input from a signal line to the pixel. When a video signal is written to the pixel, the pixel holds the signal until a signal is input again. A sustain period Ts1 is generated by the written video signal.
The lighting or non-lighting of each pixel in the row is controlled. In the row where the writing operation of the video signal is completed, the pixel is turned on or off according to the video signal written immediately. The same operation is performed up to the last row, and the address period Ta1 ends. Then, the signal writing operation of the next subframe period is started in order from the row where the data holding time has ended. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and the lighting or non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 is controlled by the video signals. The end of the sustain period TS4 is set by the start of the erase operation. This is because when the signal written to the pixel in the erase time Te of each row is erased, the pixel is forced to be non-lighted regardless of the video signal written to the pixel in the address period until the signal is written to the next pixel. In other words, the data holding time ends from the pixel in the row where the erase time Te has started.

Here, with reference to FIG. 99(B), a description will be given focusing on the i-th row of pixels. In the i-th row of pixels, pixel scanning signals are input to the scanning lines in order from the first row during the address period Ta1, and the pixels are selected. Then, when the i-th row pixels are selected during period Tb1(i), a video signal is input to the i-th row pixels. Then, when a video signal is written to the i-th row pixels, the i-th row pixels retain that signal until a signal is input again. This written video signal controls whether the i-th row pixels are lit or not during the sustain period Ts1(i). In other words, when the operation of writing a video signal to the i-th row is completed,
The pixels in the i-th row are turned on or off according to the video signal that is immediately written. Similarly, a video signal is input to the pixels in the i-th row in the address periods Ta2, Ta3, and Ta4, and the pixels in the i-th row are controlled to be turned on or off in the sustain periods Ts2, Ts3, and Ts4 by the video signal. The end of the sustain period Ts4(i) is set by the start of the erase operation, because the pixels in the i-th row are forcibly turned off regardless of the video signal written to the pixels in the i-th row during the erase time Ts(i) of the i-th row. In other words, when the erase time Te(i) starts, the data retention time of the pixels in the i-th row ends.

Therefore, it is possible to provide a display device with a high gray scale and a high duty ratio (the ratio of the lighting period to one frame period) that is shorter than the address period without separating the address period and the sustain period. In addition, it is possible to reduce the instantaneous luminance, which makes it possible to improve the reliability of the display element.

Although the case of expressing 4-bit gradation has been described here, the number of bits and the number of gradations are not limited to this. Also, the lighting order does not have to be Ts1, Ts2, Ts3, and Ts4, but may be random, or may be divided into a plurality of parts.
The lighting times Ts3 and Ts4 do not have to be a power of two, and may be the same length, or may be slightly shifted from a power of two.

Here, the pixel configuration capable of performing the digital time gray scale driving described in Fig. 98(A) and Fig. 99(A) will be described with reference to Figs. 100(A), (B), (C), (D) and (E). Note that the display elements shown in Figs. 100(A), (B), (C), (D) and (E) are EL
Display media whose contrast changes due to electromagnetic effects, such as elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic materials), electron emission elements, liquid crystal elements, electronic ink, grating light valves (GLV), digital micromirror devices (DMD), carbon nanotubes, etc., can be applied.
For the pixels shown in (C), (D) and (E), a self-luminous element such as an EL element is suitable as the display element. Although Fig. 100 (A), (B), (C), (D) and (E) show only one pixel, a plurality of pixels are arranged in a matrix in the row and column directions in the pixel portion of the display device.

The pixel shown in Fig. 100A has a switching transistor 80301a, a driving transistor 80302a, and a capacitor 80304a. The switching transistor 80301a has a gate terminal connected to a scanning line 80312a, a first terminal (source terminal or drain terminal) connected to a signal line 80311a, and a second terminal (source terminal or drain terminal) connected to the gate terminal of the driving transistor 80302a. The second terminal of the switching transistor 80301a is connected to a power supply line 80302a via a capacitor 80304a.
80313a. Furthermore, the driving transistor 80302a has a first terminal connected to the power line 80313a and a second terminal connected to the first electrode of the display element 80320a. A low power supply potential is set to the second electrode 80321a of the display element 80320a. Note that the low power supply potential is a potential that satisfies the condition that the low power supply potential is smaller than the high power supply potential based on the high power supply potential set to the power line 80313a, and the low power supply potential may be set to, for example, GND or 0 V. The potential difference between the high power supply potential and the low power supply potential is set to the display element 80320.
a to cause a current to flow through the display element 80320a to cause the display element 80320a to emit light, the high power supply potential and the low power supply potential are set so that the potential difference between them is equal to or greater than the forward threshold voltage of the display element 80320a. Note that the capacitor element 80304a can be omitted by substituting the gate capacitance of the driving transistor 80302a. Regarding the gate capacitance of the driving transistor 80302a, a capacitance may be formed in a region where the source region, the drain region, the LDD region, or the like overlaps with the gate electrode, or a capacitance may be formed between the channel region and the gate electrode.

When a pixel is selected by the scanning line 80312a, that is, when the switching transistor 8
When the signal line 80301a is turned on, a video signal is input to the pixel from the signal line 80311a. Then, a charge equivalent to the voltage of the video signal is accumulated in the capacitor element 80304a.
The capacitor element 80304a holds the voltage. This voltage is supplied to the driving transistor 80302.
This is the voltage between the gate terminal and the first terminal of the driving transistor 80302a, and corresponds to the gate-source voltage Vgs of the driving transistor 80302a.

In general, the operating region of a transistor can be divided into a linear region and a saturation region. The boundary between them occurs when (Vgs-Vth)=Vds, where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. (Vgs-Vth)>Vds
In the case of , it is in the linear region, and the current value is determined by the magnitude of Vds and Vgs.
When Vgs-Vth) < Vds, the region is saturated. Ideally, even if Vds changes,
The current value remains almost unchanged. In other words, the current value is determined only by the magnitude of Vgs.

In the case of a voltage input voltage driving method, a video signal is input to the gate terminal of the driving transistor 80302a so that the driving transistor 80302a is in two states, that is, fully on or off. In other words, the driving transistor 80302a is operated in a linear region.

Therefore, when the driving transistor 80302a is turned on, the power supply potential VDD set in the power supply line 80313a is ideally applied to the display element 80320 as it is.
a is set to the first electrode.

In other words, ideally, the voltage applied to the display element 80320a is kept constant, and the voltage applied to the display element 8032
The brightness obtained from 0a is made constant. Then, a plurality of subframe periods are provided within one frame period, a video signal is written to a pixel in each subframe period, the lighting or non-lighting of the pixel is controlled in each subframe period, and the gradation is expressed by the sum of the lighting subframe periods.

Next, the pixel configuration of FIG. 100B will be described. The pixel shown in FIG. 100B includes a switching transistor 80301a, a driving transistor 80302a, and a rectifying element 80
The switching transistor 80301b has a gate terminal connected to the first scanning line 80312b and a display element 80320b.
A first terminal (source terminal or drain terminal) of the switching transistor 80302 is connected to a signal line 80311b, and a second terminal (source terminal or drain terminal) of the switching transistor 80302 is connected to a gate terminal of the driving transistor 80302b. Furthermore, the gate terminal of the driving transistor 80302 is connected to a second scanning line 80314b via a rectifying element 80306a.
The second terminal of the display element 80320b is connected to the power supply line 80313b via the capacitor element 80304b. The first terminal of the driving transistor 80302b is connected to the power supply line 80313b, and the second terminal of the driving transistor 80302b is connected to the first electrode of the display element 80320b.
A low power supply potential is set to the second electrode 80321b of the power supply line 80313b. Note that the low power supply potential is a potential that satisfies the condition that the low power supply potential is smaller than the high power supply potential with respect to the high power supply potential set to the power supply line 80313b, and the low power supply potential may be set to, for example, GND or 0 V.
The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80320b.
In order to pass a current through the display element 80320b to make the display element 80320b emit light, the potentials of the high power supply potential and the low power supply potential are set so that the potential difference between them is equal to or greater than the forward threshold voltage of the display element 80320b. Note that the capacitor element 80304b can be omitted by substituting the gate capacitance of the driving transistor 80302b. Regarding the gate capacitance of the driving transistor 80302b, a capacitance may be formed in a region where the source region, the drain region, the LDD region, or the like overlaps with the gate electrode, or a capacitance may be formed between the channel region and the gate electrode.

In this pixel configuration, a rectifying element 80306a and a second scanning line 8031 are added to the pixel of FIG.
Therefore, a switching transistor 80301b, a driving transistor 80302b, a capacitor element 80304b, a signal line 80311b, a first scanning line 80312b, and a power supply line 80313b are respectively
a, a driving transistor 80302a, a capacitor element 80304a, a signal line 80311a, a scanning line 80312a, and a power supply line 80313a. The writing operation and light emitting operation are similar, so that the description thereof will be omitted here.

An erase operation will now be described. During the erase operation, an H-level signal is input to the second scan line 80314b. Then, a current flows through the rectifying element 80306a, and the gate potential of the driving transistor 80302b held by the capacitor element 80304b can be set to a certain potential. In other words, the potential of the gate terminal of the driving transistor 80302b is set to a certain potential, and the driving transistor 80302b is turned on regardless of the video signal written to the pixel.
b can be forced off.

The L-level signal input to the second scanning line 80314b is set to a potential that prevents current from flowing through the rectifying element 80306a when a video signal that turns off the pixel is written in. The H-level signal input to the second scanning line 80314b is set to a potential that can set the gate terminal to a potential that turns off the driving transistor 80302b, regardless of the video signal written in the pixel.

Note that a diode-connected transistor can be used for the rectifying element 80306a. Furthermore, in addition to the diode-connected transistor, a PN junction or PIN junction diode, a Schottky diode, or a diode formed of a carbon nanotube may be used. FIG. 100C shows a case where a diode-connected N-channel transistor is used. The first terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal of the driving transistor 80302c. In addition,
The second terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal and also to the second scanning line 80314c. Then, when the second scanning line 80314c is at the L level, no current flows through the diode-connected transistor 80303c because the gate terminal and source terminal are connected.
When an H level signal is input to diode-connected transistor 80303c, the second terminal of diode-connected transistor 80303c becomes the drain terminal, so that a current flows through diode-connected transistor 80303c.
Therefore, the diode-connected transistor 80303c performs a rectifying function.

In addition, a switching transistor 80301c, a driving transistor 80302c, a capacitor element 80304c, a signal line 80311c, a first scanning line 80312c, a power supply line 8031
3c respectively represent the switching transistor 80301a, the driving transistor 80302a, the capacitor element 80304a, the signal line 80311a, and the scanning line 8031 in FIG.
2a corresponds to the power supply line 80313a. The second scanning line 80314c corresponds to the power supply line 80314b shown in FIG.
This corresponds to the second scan line 80312d in FIG.

In addition, the case where a diode-connected P-channel transistor is applied is shown in FIG. 100(D). The first terminal (source terminal or drain terminal) of the diode-connected transistor 80303d is connected to the second scan line 80313d.
The second terminal (source terminal or drain terminal) of the second scanning line 8031 is connected to the gate terminal of the driving transistor 80302d.
When the second scanning line 80313d is at the L level, no current flows through the diode-connected transistor 80303d because the gate terminal and source terminal are connected, but when an H-level signal is input to the second scanning line 80313d, the second terminal of the diode-connected transistor 80303d becomes the drain terminal, so that a current flows through the diode-connected transistor 80303d. Therefore, the diode-connected transistor 80303d exhibits a rectifying effect.

In addition, a switching transistor 80301d, a driving transistor 80302d, a capacitor element 80304d, a signal line 80311d, a first scanning line 80312d, a power supply line 8031
3d are the switching transistor 80301a, the driving transistor 80302a, the capacitor element 80304a, the signal line 80311a, and the scanning line 8031 in FIG.
2a corresponds to the power supply line 80313a. The second scanning line 80314d corresponds to the power supply line 80314a shown in FIG.
This corresponds to the second scan line 80312d in FIG.

Moreover, an erasing transistor may be provided to erase a signal written to the pixel.
The pixel shown in FIG. 100E is the pixel shown in FIG. 100A except that an erasing transistor 80303e
A switching transistor 80301e, a driving transistor 80302e, a capacitor element 80304e, a signal line 80312e, and a second scanning line 80312e are added.
311e, the first scanning line 80312e, and the power supply line 80313e are respectively shown in FIG.
These correspond to a switching transistor 80301a, a driving transistor 80302a, a capacitor element 80304a, a signal line 80311a, a scanning line 80312a, and a power supply line 80313a, and the writing operation and light emitting operation are similar, so that the description thereof will be omitted here.

The erase operation will be described. During the erase operation, an H-level signal is input to the second scanning line 80312e. Then, the erase transistor 80303e turns on, and the gate terminal and the first terminal of the drive transistor 80302e can be set to the same potential. In other words, the gate-source voltage of the drive transistor 80302e can be set to 0V. Note that it is desirable that the H-level potential of the second scanning line 80312e is higher than the potential of the power supply line 80313e by the threshold voltage Vth of the erase transistor 80303e or more. In this way, the drive transistor 80302e can be forcibly turned off.

Next, an example of a threshold voltage correction type pixel circuit and a driving method thereof that can be applied to this embodiment mode will be described with reference to FIG.

The pixel shown in FIG. 101A includes a driving transistor 80400 and a first switch 80401.
, a second switch 80402, a third switch 80403, a first capacitor element 80404,
The display element 80420 includes a second capacitor element 80405.
The gate terminal of the display element 80400 is connected to a signal line 80411 through a first capacitor element 80404 and a first switch 80401 in this order, the first terminal is connected to a power line 80412, and the second terminal is connected to a first electrode of the display element 80420 through a third switch 80403. Furthermore, the gate terminal of the driving transistor 80400 is connected to the power line 80412 through a second capacitor element 80405. Also, the gate terminal of the driving transistor 80400 is connected to a second terminal of the driving transistor 80400 through a second switch 80402. Also, a low power supply potential is set to the second electrode 80421 of the display element 80420. Note that the low power supply potential is a potential that satisfies the condition that the low power supply potential is less than the high power supply potential based on the high power supply potential set to the power line 80412, and the low power supply potential may be set to, for example, GND or 0 V. The potential difference between the high power supply potential and the low power supply potential is
to cause a current to flow through the display element 80420 to cause the display element 80420 to emit light.
The high power supply potential and the low power supply potential are set so that the potential difference between them is equal to or greater than the forward threshold voltage of the display element 80420. Note that the second capacitor element 80405 can be omitted by substituting the gate capacitance of the driving transistor 80400.
The gate capacitance of 400 may be formed in a region where the gate electrode overlaps with the source region, the drain region, the LDD region, or the like, or may be formed between the channel region and the gate electrode.
A first switch 80401, a second switch 80402, and a third switch 80403 are controlled to be turned on and off by a first scanning line 80413, a second scanning line 80414, and a third scanning line 80415, respectively.

The method of driving the pixel shown in FIG. 101A can be divided into an initialization period, a data writing period, a threshold acquisition period, and a light emission period.

In the initialization period, the second switch 80402 and the third switch 80403 are turned on.
The potential of the gate terminal of the driving transistor 80400 becomes lower than at least the potential of the power supply line 80412. At this time, the first switch 80401 may be on or off. The initialization period is not necessarily required.

During the threshold acquisition period, a pixel is selected by the first scanning line 80413. That is, the first switch 80401 is turned on, and a certain constant voltage is input from the signal line 80411. At this time, the second switch 80402 is turned on, and the driving transistor 80400 is diode-connected. In addition, the third switch 80403 is turned off. Therefore, the potential of the gate terminal of the driving transistor 80400 is a value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80412. The threshold voltage of the driving transistor 80400 is held in the first capacitor 80404. In addition, the second capacitor 80405
A potential difference between the potential of the gate terminal of the driving transistor 80400 and a constant voltage input from a signal line 80411 is held in the gate terminal 80402 .

In the data writing period, a video signal (voltage) is input from the signal line 80411. At this time, the first switch 80401 remains on, the second switch 80402 turns off, and the second switch 80402 remains off.
The gate terminal of the driving transistor 80400 is in a floating state. Therefore, the potential of the gate terminal of the driving transistor 80400 changes according to the potential difference between the constant voltage input to the signal line 80411 in the threshold acquisition period and the video signal input to the signal line 80411 in the data write period. For example, if the capacitance value of the first capacitor 80404 is smaller than the capacitance value of the second capacitor 80405, the potential of the gate terminal of the driving transistor 80400 in the data write period is approximately equal to the value obtained by adding the potential difference between the constant voltage input to the signal line 80411 in the threshold acquisition period and the video signal input to the signal line 80411 in the data write period to the value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80412. In other words, the potential of the gate terminal of the driving transistor 80400 is a potential obtained by correcting the threshold voltage of the driving transistor 80400.

During the light emission period, a current corresponding to the potential difference (Vgs) between the gate terminal of the driving transistor 80400 and the power supply line 80412 flows to the display element 80420. At this time, the first switch 80401 is turned off, the second switch 80402 remains off, and the third switch 80403 is turned on. Note that the current flowing to the display element 80420 is the same as that of the driving transistor 80400.
It is constant regardless of the 0400 threshold voltage.

Note that the pixel configuration shown in FIG. 101(A) is not limited to that shown in FIG.
A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in FIG. 01(A). In addition, for example, the second switch 80402 may be configured with a P-channel transistor or an N-channel transistor, the third switch 80403 may be configured with a transistor having a polarity different from that of the second switch 80402, and the second switch 80402 and the third switch 80403 may be controlled by the same scan line.

Next, an example of a current input type pixel circuit and a driving method thereof that can be applied to this embodiment will be described.
Description will be given with reference to Figure 101 (B).

The pixel shown in FIG. 101B includes a driving transistor 80430 and a first switch 8043.
The driving transistor 80430 has a gate terminal connected to a signal line 80441 via a second switch 80432 and a first switch 80431 in this order, a first terminal connected to a power line 80442, and a second terminal connected to a first electrode of the display element 80450 via a third switch 80433. Furthermore, the gate terminal of the driving transistor 80430 is connected to a power line 80442 via a capacitor 80434. Also, the gate terminal of the driving transistor 80430 is connected to a second terminal of the driving transistor 80430 via the second switch 80432. Also, the display element 804
A low power supply potential is set to the second electrode 80451 of the semiconductor device 50.
The potential satisfies the condition that the low power potential is smaller than the high power potential based on the high power potential set on the power line 80442, and the low power potential may be set to, for example, GND or 0 V. The potential difference between the high power potential and the low power potential is applied to the display element 80450, and the display element 8045
In order to make the display element 80450 emit light by passing a current through the high power supply potential 80434, the potential difference between the high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the display element 80450. Note that the capacitor 80434 can be omitted by substituting the gate capacitance of the driving transistor 80430. The gate capacitance of the driving transistor 80430 is as follows:
A capacitance may be formed in a region where the gate electrode overlaps with a source region, a drain region, an LDD region, or the like, or a capacitance may be formed between a channel region and a gate electrode.
The third switch 80433 is connected to the first scanning line 80443 and the second scanning line 80444.
0444 and the third scanning line 80445 control on/off.

The method of driving the pixel shown in FIG. 101B can be divided into a data writing period and a light emitting period.

In the data writing period, a pixel is selected by the first scanning line 80443. That is,
The first switch 80431 is turned on, and a current is input as a video signal from the signal line 80441. At this time, the second switch 80432 is turned on, and the third switch 80433 is turned off. Therefore, the potential of the gate terminal of the driving transistor 80430 becomes a potential corresponding to the video signal.
A voltage is maintained between the gate and source of the driving transistor 80430 such that the same current as the video signal flows.

Next, in the light emission period, the first switch 80431 and the second switch 80432 are turned off, and the third switch 80433 is turned on. Therefore, a current having the same value as that of the video signal flows through the display element 80450.

Note that the pixel configuration shown in FIG. 101B is not limited to that shown in FIG.
A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in FIG. 01(B). For example, the first switch 80431 may be configured with a P-channel transistor or an N-channel transistor, the second switch 80432 may be configured with a transistor having the same polarity as the first switch 80431, and the first switch 80431 and the second switch 80432 may be controlled by the same scan line.
2 may be disposed between the gate terminal of the driving transistor 80430 and the signal line 80441 .

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 13)
In this embodiment, a semiconductor device to which this embodiment can be applied is a thin film transistor (TF
A method for manufacturing a semiconductor device having a semiconductor device (T) as an element will be described with reference to the drawings.

102A and 102B are diagrams showing an example of a structure and a manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment can be applied. FIG. 102A is a diagram showing an example of a structure of a TFT that can be included in a semiconductor device to which this embodiment can be applied. FIG. 102B is a diagram showing an example of a structure of a TFT that can be included in a semiconductor device to which this embodiment can be applied.
1A to 1G are diagrams showing an example of a manufacturing process for a TFT that can be included in a semiconductor device to which this embodiment can be applied.

The structure and manufacturing process of a TFT that can be used in a semiconductor device to which this embodiment can be applied are not limited to those shown in FIG. 102, and various structures and manufacturing processes can be used.

First, with reference to FIG. 102A, an example of a TFT structure that can be included in a semiconductor device to which this embodiment can be applied will be described. FIG. 102A shows a TFT having a plurality of different structures.
102(A) shows a cross-sectional view of a FT having a plurality of different structures.
Although the TFTs are shown arranged side by side, this is an expression for explaining the structure of the TFT that can be possessed by a semiconductor device to which the invention can be applied, and the TFTs that can be possessed by a semiconductor device to which the invention can be applied do not actually need to be arranged side by side as in Figure 102 (A), and can be created separately as needed.

Next, features of each layer constituting a TFT that can be included in a semiconductor device to which this embodiment can be applied will be described.

The substrate 110111 may be a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, or a metal substrate including stainless steel. Other substrates include polyethylene terephthalate (PET), polyethylene naphthalate (P
It is also possible to use a substrate made of a flexible synthetic resin such as plastics typified by polyethersulfone (PES) or acrylic. By using a flexible substrate, it is possible to manufacture a semiconductor device that can be bent. In addition, since there is no significant limitation on the area and shape of the substrate as long as the substrate is flexible, the productivity can be significantly improved by using a rectangular substrate with one side of 1 meter or more as the substrate 110111. This advantage is a major advantage compared to the use of a circular silicon substrate.

The insulating film 110112 functions as a base film. It is provided to prevent alkali metals such as Na or alkaline earth metals from the substrate 110111 from adversely affecting the characteristics of the semiconductor element. The insulating film 110112 can be provided as a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y), or a laminate structure of these.
For example, when the insulating film 110112 has a two-layer structure, a silicon nitride oxide film may be provided as a first insulating film, and a silicon oxynitride film may be provided as a second insulating film.
When the insulating film 112 has a three-layer structure, a silicon oxynitride film may be provided as the first insulating film, a silicon nitride oxide film may be provided as the second insulating film, and a silicon oxynitride film may be provided as the third insulating film.

The semiconductor films 110113, 110114, and 110115 can be formed of an amorphous semiconductor or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor film may be used. The SAS is a semiconductor having an intermediate structure between an amorphous structure and a crystalline structure (including single crystal and polycrystal), and having a third state that is stable in terms of free energy, and includes a crystalline region having a short-range order and lattice distortion. In at least a part of the region in the film, a crystalline region of 0.5 to 20 nm can be observed, and when silicon is the main component, the Raman spectrum is shifted to the low wave number side from 520 cm ^-1 . In X-ray diffraction, diffraction peaks of (111) and (220) that are believed to be derived from the silicon crystal lattice are observed. Dangling bonds (
The SAS contains at least 1 atomic % or more of hydrogen or halogen as a dangling bond compensation. The SAS is formed by glow discharge decomposition (plasma CVD) of material gas. The material gas is _{SiH4 , Si2H6 , SiH2Cl2} , S
It is possible to use iHCl ₃ , SiCl ₄ , SiF ₄ , etc. Alternatively, GeF ₄
This material gas may be mixed with H ₂ , or H ₂ and one or more rare gas elements selected from He, Ar, Kr, and Ne. The dilution ratio is in the range of 2 to 1000 times. The pressure is in the range of approximately 0.1 Pa to 133 Pa, the power frequency is 1 MHz to 120 MHz,
The frequency is preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300° C. or less. The impurity elements in the film, such as oxygen, nitrogen, and carbon, are preferably 1×10 ²⁰ cm ⁻¹ or less in terms of impurity components. In particular, the oxygen concentration is preferably 5×10 ¹⁹ /cm ³ or less, and more preferably 1×10 ^1
9 / ^cm3 or less. Here, known methods (sputtering method, LPCVD method, plasma C
A material mainly composed of silicon (Si) (e.g. SixGe1-x, etc.) using a VD method, etc.
An amorphous semiconductor film is formed by a method such as a laser crystallization method, a thermal crystallization method using an RTA or an annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization.

The insulating film 110116 is made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (
The insulating film 100 can have a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide nitride (SiOxNy) (x>y) or silicon nitride oxide (SiNxOy) (x>y), or a laminated structure of these.

The gate electrode 110117 can be a single-layer conductive film, or a laminated structure of two or three layers of conductive films. A known conductive film can be used as the material of the gate electrode 110117. For example, a single film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), or silicon (Si), or a nitride film of the element (typically a tantalum nitride film, a tungsten nitride film, or a titanium nitride film), or an alloy film of the element (typically a Mo-W alloy or a Mo-Ta alloy), or a silicide film of the element (typically a tungsten silicide film or a titanium silicide film), or the like can be used. The single film, nitride film, alloy film, silicide film, or the like described above may be used as a single layer or may be used as a laminate.

The insulating film 110118 is formed by a known method (such as a sputtering method or a plasma CVD method) using a material selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y),
Silicon oxynitride (SiNxOy) (x>y) or other insulating films containing oxygen or nitrogen, or DLC (
The insulating layer 11 may have a single layer structure of a film containing carbon such as diamond-like carbon, or a laminate structure of these films.

The insulating film 110119 is made of siloxane resin, silicon oxide (SiOx), silicon nitride (S
iNx), silicon oxynitride (SiOxNy) (x>y), silicon nitride oxide (SiNxOy) (
Insulating films containing oxygen or nitrogen such as (x>y), DLC (diamond-like carbon) or other carbon-containing films, or epoxy, polyimide, polyamide, polyvinylphenol,
The insulating film 110119 may be formed in a single layer or a multilayer structure made of an organic material such as benzocyclobutene or acrylic. The siloxane resin corresponds to a resin containing Si-O-Si bonds. Siloxane has a skeletal structure formed by bonds between silicon (Si) and oxygen (O). An organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. In the semiconductor device of this embodiment, it is also possible to provide the insulating film 110119 directly so as to cover the gate electrode 110117 without providing the insulating film 110118.

The conductive film 110123 is made of Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, M
A single film of an element such as n, a nitride film of the element, an alloy film of a combination of the elements, or a silicide film of the element can be used. For example, as an alloy containing a plurality of the elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, etc. can be used. In addition, when a laminated structure is provided, a structure in which Al is sandwiched between Mo or Ti can be used. In this way, the resistance of Al to heat and chemical reactions can be improved.

Next, referring to the cross-sectional view of TFTs having a plurality of different structures shown in FIG.
The features of each structure will be explained below.

The semiconductor film 110101 is a single drain TFT, and can be manufactured by a simple method, which has the advantage of low manufacturing cost and high yield.
The semiconductor film 110113 is a channel region, and the semiconductor film 110115 is a semiconductor film having a different impurity concentration.
The semiconductor film 110115 is used as a source region and a drain region. In this way, the resistivity of the semiconductor film can be controlled by controlling the amount of impurities.
The electrical connection state with the gate electrode 110117 can be made closer to an ohmic connection. As a method for producing semiconductor films with different amounts of impurities, a method for doping the impurity into the semiconductor film using the gate electrode 110117 as a mask can be used.

The semiconductor film 110113, 110114, and 110115 have different impurity concentrations, and the semiconductor film 110113 is a channel region, the semiconductor film 110114 is a lightly doped drain (LDD) region, and the semiconductor film 110115 is a lightly doped drain (LDD) region.
are used as the source region and the drain region. In this way, by controlling the amount of impurities, the resistivity of the semiconductor film can be controlled. In addition, the electrical connection state between the semiconductor film and the conductive film 110123 can be made closer to ohmic connection. In addition, since the LDD region is provided,
A high electric field is unlikely to be applied inside the TFT, and deterioration of the element due to hot carriers can be suppressed.
A method of doping impurities into the semiconductor film using 0117 as a mask can be used.
In 110102, since the gate electrode 110117 has a taper angle of a certain degree or more, a gradient can be given to the concentration of the impurity that passes through the gate electrode 110117 and is doped into the semiconductor film, making it possible to easily form an LDD region.

110103 is a TFT in which the gate electrode 110117 is composed of at least two layers, and the lower gate electrode has a shape longer than the upper gate electrode. In this specification, the shapes of the upper gate electrode and the lower gate electrode are called hat-shaped. Gate electrode 110117
Since the shape of the gate electrode 11011 is hat-shaped, the LDD region can be formed without adding a photomask.
The structure overlapping with 7 is particularly called the GOLD structure (Gate Overlapped LDD).
In addition, the following method may be used to form the gate electrode 110117 in a hat shape.

First, when patterning the gate electrode 110117, the lower gate electrode and the upper gate electrode are etched by dry etching to give them a tapered shape on the side. Then, the upper gate electrode is processed by anisotropic etching so that the slope becomes nearly vertical. This forms a gate electrode with a hat-shaped cross section. Then, the gate electrode is etched twice.
A semiconductor film 1101 used as a channel region by doping an impurity element.
13, a semiconductor film 110114 to be used as an LDD region, and a semiconductor film 110115 to be used as a source electrode and a drain electrode are formed.

The LDD region overlapping the gate electrode 110117 is called the Lov region.
The LDD region that does not overlap with 0117 is called the Loff region.
The f region is highly effective in suppressing the off-current value, but is less effective in preventing the degradation of the on-current value due to hot carriers by relaxing the electric field near the drain. On the other hand, the Lov region relaxes the electric field near the drain, and is effective in preventing the degradation of the on-current value, but is less effective in suppressing the off-current value. Therefore, it is preferable to fabricate TFTs having a structure according to the characteristics required for each of various circuits. For example, when the semiconductor device of this embodiment is used as a display device, the pixel TFT
In the case of the peripheral circuit, it is preferable to use a TFT having a Loff region in order to suppress the off-current value, whereas in the case of the peripheral circuit, it is preferable to use a TFT having a Lov region in order to reduce the electric field near the drain and prevent the deterioration of the on-current value.

110104 is in contact with the side surface of the gate electrode 110117 and forms a sidewall 110121
By providing the sidewall 110121, the region overlapping with the sidewall 110121 can be made into an LDD region.

110105 is a semiconductor film doped with a mask to form an LDD (Lof
f) A TFT in which an LDD region is formed. By doing so, the LDD region can be formed reliably, and the off-current value of the TFT can be reduced.

110106 is a semiconductor film doped with a mask to form an LDD (Lov
In this way, the LDD region can be formed reliably, the electric field in the vicinity of the drain of the TFT can be relaxed, and the deterioration of the on-current value can be reduced.

Next, with reference to FIGS. 102B to 102G, an example of a manufacturing process for a TFT that can be included in a semiconductor device to which this embodiment can be applied will be described.
The structure and manufacturing process of a TFT that can be used in a semiconductor device to which this embodiment can be applied are not limited to those shown in FIG. 102, and various structures and manufacturing processes can be used.

In this embodiment, the surface of the substrate 110111, the surface of the insulating film 110112, the surface of the semiconductor film 110113, the surface of the semiconductor film 110114, the surface of the semiconductor film 110115, and the insulating film 110116 are formed on the surface of the substrate 110111.
By performing oxidation or nitridation using plasma treatment on the surface of 10116, the surface of the insulating film 110118, or the surface of the insulating film 110119, the semiconductor film or the insulating film can be oxidized or nitrided. In this way, by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, the surface of the semiconductor film or the insulating film can be modified, and C
Since a denser insulating film can be formed compared to insulating films formed by the VD method or sputtering method, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved.

First, the surface of the substrate 110111 is cleaned with hydrofluoric acid (HF), alkali, or pure water. The substrate 110111 may be a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, or a metal substrate including stainless steel. Other substrates include polyethylene terephthalate (PET), polyethylene naphthalate (
It is also possible to use a substrate made of plastics such as polyethersulfone (PEN) or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. Here, a case where a glass substrate is used as the substrate 110111 is shown.

Here, an oxide film or a nitride film may be formed on the surface of the substrate 110111 by performing a plasma treatment on the surface of the substrate 110111 to oxidize or nitride the surface of the substrate 110111 (FIG. 102(B)). An insulating film such as an oxide film or a nitride film formed by performing a plasma treatment on the surface is also referred to as a plasma-treated insulating film below. In FIG. 102(B), the insulating film 110131 is a plasma-treated insulating film. In general, when a semiconductor element such as a thin film transistor is provided on a substrate such as glass or plastic, impurity elements such as alkali metals or alkaline earth metals such as Na contained in the glass or plastic may mix with and contaminate the semiconductor element, thereby affecting the characteristics of the semiconductor element. However, by nitriding the surface of a substrate made of glass or plastic, it is possible to prevent impurity elements such as alkali metals or alkaline earth metals such as Na contained in the substrate from mixing with the semiconductor element.

In addition, when the surface is oxidized by plasma treatment, the surface is oxidized in an oxygen atmosphere (for example, oxygen (O ₂
) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe), or oxygen and hydrogen (H ₂ ) and a rare gas, or nitrous oxide and a rare gas). On the other hand, when nitriding the semiconductor film by plasma treatment, the plasma treatment is performed in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe), or nitrogen and hydrogen and a rare gas, or NH ₃ and a rare gas). For example, Ar can be used as the rare gas. Alternatively, a gas containing Ar and Kr may be used. Therefore, the plasma treatment insulating film contains the rare gas (containing at least one of He, Ne, Ar, Kr, and Xe) used in the plasma treatment. For example, when Ar is used, the plasma treatment insulating film contains Ar.

The plasma treatment is carried out in an atmosphere of the above gas with an electron density of 1×10 ¹¹ cm ⁻³
and the electron temperature of the plasma is 0.5 eV or more and 1.5 eV ^or less ^.
It is preferable to carry out the plasma treatment at the temperature below 1000 K. Since the plasma has a high electron density and the electron temperature in the vicinity of the object to be treated is low, damage to the object to be treated by the plasma can be prevented. In addition, since the plasma has a high electron density of 1×10 ¹¹ cm ⁻³ or more, the oxide or nitride film formed by oxidizing or nitriding the object to be irradiated using the plasma treatment has a high solubility in the atmosphere.
A dense film can be formed with excellent uniformity in thickness compared to films formed by the VD method, sputtering method, etc. Alternatively, since the plasma electron temperature is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature compared to conventional plasma treatments and thermal oxidation methods. For example, even if the plasma treatment is performed at a temperature 100 degrees or more lower than the strain point temperature of the glass substrate, oxidation or nitridation can be performed sufficiently. Note that a high frequency such as microwaves (2.45 GHz) can be used as the frequency for forming the plasma. Note that unless otherwise specified below, the plasma treatment is performed under the above conditions.

In FIG. 102B, the surface of the substrate 110111 is subjected to plasma treatment to form a plasma-treated insulating film.
This also includes the case where a plasma-treated insulating film is not formed on the surface of 11.

In addition, although the plasma processing insulating film formed by plasma processing the surface of the processing object is not shown in FIGS. 102C to 102G, in this embodiment, the substrate 1
10111, insulating film 110112, semiconductor film 110113, 110114, 110115
This also includes the case where a plasma-treated insulating film is formed by performing plasma treatment on the surface of insulating film 110116, insulating film 110118, or insulating film 110119.

Next, an insulating film 110112 is formed on the substrate 110111 by a known method (such as sputtering, LPCVD, or plasma CVD) (FIG. 102C). The insulating film 110112 can be made of silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y).

Here, a plasma treatment may be performed on the surface of the insulating film 110112 to oxidize or nitride the insulating film 110112, thereby forming a plasma-treated insulating film on the surface of the insulating film 110112. By oxidizing the surface of the insulating film 110112, the surface of the insulating film 110112 can be modified to obtain a dense film with few defects such as pinholes.
By oxidizing the surface of 112, a plasma-treated insulating film with a low content of N atoms can be formed, and when a semiconductor film is provided on the plasma-treated insulating film, the interface characteristics between the plasma-treated insulating film and the semiconductor film are improved. The plasma-treated insulating film contains a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe) used in the plasma treatment.
The plasma treatment can be carried out similarly under the conditions described above.

Next, island-shaped semiconductor films 110113 and 110114 are formed on the insulating film 110112 (
FIG. 102(D)). The island-shaped semiconductor films 110113 and 110114 are formed on the insulating film 110112.
Silicon (
The amorphous semiconductor film can be formed by forming an amorphous semiconductor film using a material (e.g., SixGe1-x, etc.) mainly composed of Si, crystallizing the amorphous semiconductor film, and selectively etching the semiconductor film. The amorphous semiconductor film can be crystallized by a known crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or an annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. Here, the end of the island-shaped semiconductor film is provided in a shape close to a right angle (θ=85 to 100°).
Alternatively, the semiconductor film 110114 that becomes the lightly doped drain region may be formed by doping impurities using a mask.

Here, the surfaces of the semiconductor films 110113 and 110114 are subjected to plasma treatment.
The surfaces of the semiconductor film 1101 and 110114 are oxidized or nitrided.
A plasma-treated insulating film may be formed on the surfaces of the semiconductor film 13, 110, 114.
When Si is used as the semiconductor films 110113 and 110114, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the plasma treatment insulating film. Alternatively, the semiconductor films 110113 and 110114 may be oxidized by plasma treatment, and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 110113 and 110114, and silicon nitride oxide (SiNxOy) (
When the semiconductor film is oxidized by plasma treatment, the plasma treatment is performed in an oxygen atmosphere (for example, an atmosphere of oxygen (O ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe), or an atmosphere of oxygen, hydrogen (H ₂ ), and a rare gas, or an atmosphere of dinitrogen monoxide and a rare gas). On the other hand, when the semiconductor film is nitrided by plasma treatment, the plasma treatment is performed in a nitrogen atmosphere (for example, an atmosphere of nitrogen (N ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe)).
The plasma treatment is performed under an atmosphere containing at least one of He, Ne, Ar, Kr, and Xe, or under an atmosphere of nitrogen, hydrogen, and a rare gas, or under an atmosphere of _NH3 and a rare gas. For example, Ar can be used as the rare gas. A mixed gas of Ar and Kr may also be used. Therefore, the plasma-treated insulating film contains the rare gas (containing at least one of He, Ne, Ar, Kr, and Xe) used in the plasma treatment. For example, when Ar is used, the plasma-treated insulating film contains A.
It contains r.

Next, an insulating film 110116 is formed (FIG. 102E). The insulating film 110116 is formed by depositing silicon oxide (SiO
The insulating film 110116 may have a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y), or a laminate structure of these. Note that when a plasma-treated insulating film is formed on the surfaces of the semiconductor films 110113 and 110114 by subjecting the surfaces of the semiconductor films 110113 and 110114 to plasma treatment, the plasma-treated insulating film can also be used as the insulating film 110116.

Here, a plasma treatment may be performed on the surface of the insulating film 110116 to oxidize or nitride the surface of the insulating film 110116, thereby forming a plasma-treated insulating film on the surface of the insulating film 110116. Note that the plasma-treated insulating film is formed by oxidizing or nitriding the surface of the insulating film 110116 using a rare gas (He, Ne,
, Ar, Kr, and Xe). The plasma treatment can be carried out under the above-mentioned conditions in the same manner.

Alternatively, the insulating film 110116 may be oxidized by once performing a plasma treatment in an oxygen atmosphere, and then nitrided by performing a plasma treatment again in a nitrogen atmosphere. In this manner, by performing a plasma treatment on the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116, the surface of the insulating film 110116 can be modified to form a dense film. The insulating film obtained by the plasma treatment is denser and has fewer defects such as pinholes compared to insulating films formed by a CVD method or a sputtering method, and therefore the characteristics of the thin film transistor can be improved.

Next, the gate electrode 110117 is formed (FIG. 102(F)).
can be formed by using known means (sputtering, LPCVD, plasma CVD, etc.).

In the case of 110101, after forming a gate electrode 110117, impurity doping can be performed to form a semiconductor film 110115 to be used as a source region and a drain region.

In 110102, by forming a gate electrode 110117 and then doping with impurities, it is possible to form 110114 to be used as an LDD region and a semiconductor film 110115 to be used as a semiconductor film source region and drain region.

In the case of 110103, by forming a gate electrode 110117 and then performing impurity doping, it is possible to form 110114 to be used as an LDD region and a semiconductor film 110115 to be used as a semiconductor film source region and drain region.

In the case of 110104, a sidewall 110121 is formed on the side of the gate electrode 110117.
After forming the 110114, impurity doping is performed to form the 110114 used as the LDD region.
Then, a semiconductor film 110115 to be used as a semiconductor film source region and drain region can be formed.

The sidewall 110121 is made of silicon oxide (SiOx) or silicon nitride (SiNx
) can be used as a method for forming the sidewalls 110121 on the sides of the gate electrode 110117. For example, after the gate electrode 110117 is formed, a silicon oxide (SiOx) or silicon nitride (SiNx) film is formed by a known method, and then the silicon oxide (SiOx) or silicon nitride (SiNx) film is etched by anisotropic etching. In this way, silicon oxide (
Since the silicon oxide (SiOx) or silicon nitride (SiNx) film can be left, the gate electrode 1101
A sidewall 110121 can be formed on the side of 17.

In the case of 110105, a mask 110122 is formed so as to cover the gate electrode 110117, and then impurity doping is performed to form a region 110122 to be used as an LDD (Loff) region.
0114 and a semiconductor film 110115 used as a semiconductor film source region and a drain region
can be formed.

In 110106, by forming a gate electrode 110117 and then performing impurity doping, it is possible to form 110114 to be used as an LDD (Lov) region and a semiconductor film 110115 to be used as a semiconductor film source region and drain region.

Next, an insulating film 110118 is formed (FIG. 102(G)). The insulating film 110118 is formed by depositing a silicon oxide (SiOx), a silicon nitride (
SiNx), silicon oxynitride (SiOxNy) (x>y), silicon nitride oxide (SiNxOy)
Insulating film containing oxygen or nitrogen such as (x>y) and DLC (Diamond-Like Carbon)
The carbon-containing film may have a single layer structure or a laminate structure thereof.

Here, a plasma treatment may be performed on the surface of the insulating film 110118 to oxidize or nitride the surface of the insulating film 110118, thereby forming a plasma-treated insulating film on the surface of the insulating film 110118. Note that the plasma-treated insulating film is formed by oxidizing or nitriding the surface of the insulating film 110118 using a rare gas (He, Ne,
, Ar, Kr, and Xe). The plasma treatment can be carried out under the above-mentioned conditions in the same manner.

Next, an insulating film 110119 is formed. The insulating film 110119 can be formed by known means (such as sputtering or plasma CVD) using an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y), or a film containing carbon, such as diamond-like carbon (DLC). Alternatively, epoxy, polyimide, polyamide, polyvinylphenol,
The insulating film may be a single layer structure of an organic material such as benzocyclobutene or acrylic, or a siloxane resin, or a laminated structure of these. The siloxane resin corresponds to a resin containing Si-O-Si bonds. The skeletal structure of siloxane is formed by bonds between silicon (Si) and oxygen (O). An organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. The plasma-treated insulating film contains a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe) used in the plasma treatment. For example, when Ar is used, Ar is contained in the plasma-treated insulating film.

When the insulating film 110119 is made of an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a siloxane resin, the insulating film 110119
The surface of the insulating film 110119 can be modified by oxidizing or nitriding the surface of the insulating film 110119 by plasma treatment. By modifying the surface, the strength of the insulating film 110119 is improved, and physical damage such as the occurrence of cracks during the formation of an opening and the loss of film during etching can be reduced. In addition, by modifying the surface of the insulating film 110119, adhesion to the conductive film 110123 is improved when the conductive film 110123 is formed on the insulating film 110119.
For example, when siloxane resin is used as the insulating film 110119 and nitrided using plasma treatment, the surface of the siloxane resin is nitrided to form a plasma-treated insulating film containing nitrogen or a rare gas, thereby improving the physical strength.

Next, in order to form a conductive film 110123 electrically connected to the semiconductor film 110115,
Contact holes are formed in the insulating films 110119, 110118, and 110116. The contact holes may have a tapered shape.
The coverage of the conductive film 110123 can be improved.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 14)
In this embodiment, a detailed configuration of a light emitting element that can be applied to a display device capable of implementing this embodiment will be described.

Light-emitting elements that utilize electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. In general, the former are called organic EL elements and the latter are called inorganic EL elements.

Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. The former have an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, while the latter have an electroluminescent layer made of a thin film of a luminescent material, but they are common in that they require electrons accelerated by a high electric field. The mechanisms of light emission that can be obtained include donor-acceptor recombination light emission that utilizes the donor level and acceptor level, and localized light emission that utilizes the inner-shell electron transition of metal ions. Generally, in dispersion-type inorganic EL, donor-
In the case of thin-film inorganic EL devices, the emission is of the acceptor recombination type, whereas in the case of thin-film inorganic EL devices, the emission is of the localized type.

The luminescent material that can be used in this embodiment is composed of a base material and an impurity element that serves as the luminescence center. By changing the impurity element to be contained, it is possible to obtain luminescence of various colors. As a method for producing the luminescent material, various methods such as a solid phase method or a liquid phase method (coprecipitation method) can be used. Alternatively, a spray pyrolysis method, a double decomposition method, a method using a pyrolysis reaction of a precursor, a reverse micelle method, a method combining these methods with high-temperature baking, a liquid phase method such as a freeze-drying method, etc. can also be used.

In the solid phase method, the base material and the impurity element or a compound containing the impurity element are weighed and mixed in a mortar.
This method involves heating and sintering in an electric furnace to induce a reaction and incorporate impurity elements into the base material. The sintering temperature is preferably 700 to 1500°C. If the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the base material will decompose. Although sintering may be performed in powder form, it is preferable to sinter in pellet form. Although sintering at a relatively high temperature is required, this is a simple method, which provides good productivity and is suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a host material or a compound containing the host material is reacted with an impurity element or a compound containing the impurity element in a solution, dried, and then fired. The particles of the luminescent material are uniformly distributed and have a small particle size, so the reaction can proceed even at a low firing temperature.

The host material used for the light emitting material may be a sulfide, an oxide, or a nitride.
Examples of sulfides that can be used include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), and barium sulfide (BaS). Examples of oxides that can be used include zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), and examples of nitrides that can be used include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), etc. can also be used, and ternary mixed crystals such as calcium gallium sulfide (CaGa ₂ S ₄ ), strontium gallium sulfide (SrGa ₂ S ₄ ), barium gallium sulfide (BaGa ₂ S ₄ ), etc. may also be used.

As the luminescence center of the localized luminescence, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium (Pr), etc. may be used. Note that halogen elements such as fluorine (F) and chlorine (Cl) may be added as charge compensation.

On the other hand, the first nucleon that forms a donor level serves as the luminescence center of donor-acceptor recombination luminescence.
A light-emitting material containing the first impurity element and a second impurity element forming an acceptor level can be used. The first impurity element can be, for example, fluorine (F), chlorine (Cl), aluminum (Al), or the like. The second impurity element can be, for example, copper (Cu),
Silver (Ag) or the like can be used.

When a light-emitting material of donor-acceptor recombination type light emission is synthesized by a solid phase method, a base material, a first impurity element or a compound containing the first impurity element, and a second impurity element or a compound containing the second impurity element are mixed.
The compounds containing the above impurity elements are weighed out and mixed in a mortar, and then heated and fired in an electric furnace. The above-mentioned base materials can be used as the base material, and the first impurity element or the compound containing the first impurity element can be, for example, fluorine (F), chlorine (Cl), aluminum sulfide (Al ₂ S ₃ ), etc., and the second impurity element or the compound containing the second impurity element can be, for example, copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), silver sulfide (Ag ₂ S), etc. The firing temperature is preferably 700 to 1500°C.
If the temperature is too low, the solid-phase reaction does not proceed, whereas if the temperature is too high, the base material decomposes. Although the firing may be performed in a powder state, it is preferable to perform the firing in a pellet state.

In addition, a compound composed of a first impurity element and a second impurity element may be used in combination as an impurity element when using a solid-phase reaction. In this case, the impurity element is easily diffused and the solid-phase reaction is easily promoted, so that a uniform luminescent material can be obtained. Furthermore, since no extra impurity element is added, a luminescent material with high purity can be obtained. As a compound composed of a first impurity element and a second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), etc. can be used.

The concentration of these impurity elements may be in the range of 0.01 to 10 atom % relative to the base material, and preferably in the range of 0.05 to 5 atom %.

In the case of a thin-film inorganic EL, the electroluminescent layer is a layer containing the above-mentioned luminescent material, and is formed by a resistance heating deposition method,
Vacuum deposition methods such as electron beam deposition (EB deposition) and physical vapor deposition methods such as sputtering (
Chemical vapor deposition (CV) methods such as PVD, metal organic CVD, and hydride transport reduced pressure CVD.
D) and atomic epitaxy (ALE).

103A to 103C show an example of a thin-film inorganic EL element that can be used as a light-emitting element. In FIG. 103A to 103C, the light-emitting element has a first electrode layer 120100
, an electroluminescent layer 120102 , and a second electrode layer 120103 .

The light-emitting elements shown in Fig. 103B and Fig. 103C have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element shown in Fig. 103A. The light-emitting element shown in Fig. 103B has an insulating layer 120104 between the first electrode layer 120100 and the electroluminescent layer 120102, and the light-emitting element shown in Fig. 103C has an insulating layer 120104 between the first electrode layer 120100 and the electroluminescent layer 120102.
102, an insulating layer 120105, a second electrode layer 120103 and an electroluminescent layer 12010
2 and an insulating layer 120106 between the electrode layers. In this way, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both of them.
The insulating layer may be a single layer or a laminate having multiple layers.

In FIG. 103B, an insulating layer 120104 is formed in contact with the first electrode layer 120100.
However, the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120103
An insulating layer 120104 may be provided in contact with the substrate 120104 .

In the case of a dispersion-type inorganic EL, a particulate light-emitting material is dispersed in a binder to form a film-like electroluminescent layer. The material is processed into particles. If the method for producing the light-emitting material does not provide particles of the desired size, the material may be processed into particles by crushing in a mortar or the like. The binder is,
The binder is a substance that fixes the granular light-emitting material in a dispersed state and maintains the shape of the electroluminescent layer. The light-emitting material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of a dispersion-type inorganic EL, the electroluminescent layer can be formed by a droplet discharge method capable of selectively forming an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coat method, a dipping method, a dispenser method, etc. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. In addition, in an electroluminescent layer containing a luminescent material and a binder, the ratio of the luminescent material is preferably 50 wt % or more and 80 wt % or less.

An example of a dispersion-type inorganic EL element that can be used as a light-emitting element is shown in Fig. 104 (A) to (C). The light-emitting element in Fig. 104 (A) has a laminated structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and contains a light-emitting material 120201 held by a binder in the electroluminescent layer 120202.

The binder that can be used in this embodiment can be an insulating material. As the insulating material, an organic material or an inorganic material can be used. Alternatively, a mixed material of an organic material and an inorganic material can be used. As the organic insulating material, a polymer having a relatively high dielectric constant, such as a cyanoethyl cellulose-based resin, or a resin such as polyethylene, polypropylene, a polystyrene-based resin, a silicone resin, an epoxy resin, or vinylidene fluoride can be used. Alternatively, aromatic polyamide, polybenzimidazole (polybenzimidazole), or the like can be used.
Heat-resistant polymers such as midazole, or siloxane resins may be used. The siloxane resin corresponds to a resin containing Si-O-Si bonds. Siloxane has a skeletal structure formed by bonds between silicon (Si) and oxygen (O). An organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Alternatively, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, a urethane resin, or an oxazole resin (polybenzoxazole) may be used. These resins may be formed by adding barium titanate (BaTiO ₃ ) or strontium titanate (SrTiO 3
The dielectric constant can also be adjusted by mixing an appropriate amount of fine particles having a high dielectric constant such as ethylenediaminetetraacetate.

The inorganic insulating material contained in the binder is silicon oxide (SiOx), silicon nitride (SiNx
), silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, aluminum oxide containing oxygen and nitrogen (Al ₂ O ₃ ), titanium oxide (TiO ₂ ).
, BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KN
_tantalum oxide ( _Ta2O5 ), _{barium tantalate} ( _BaTa2O6 ), lithium tantalate ( _{LiTaO3 )} , yttrium oxide (Y
_The dielectric constant _of the electroluminescent layer made of the luminescent material and _the binder can be controlled more precisely by adding an inorganic material having a high dielectric constant to the organic material, and the dielectric constant can be increased more precisely by adding an inorganic material having a high dielectric constant to the organic material.

In the manufacturing process, the light-emitting material is dispersed in a solution containing a binder. As a solvent for the binder-containing solution that can be used in this embodiment, a solvent that dissolves the binder material and can prepare a solution with a viscosity suitable for the method of forming an electroluminescent layer (various wet processes) and the desired film thickness may be appropriately selected. For example, an organic solvent or the like can be used as the solvent. When a siloxane resin is used as the binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also called PGMEA)
, 3-methoxy-3-methyl-1-butanol (also called MMB), or the like can be used as a solvent.

The light-emitting elements shown in Fig. 104(B) and Fig. 104(C) have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element shown in Fig. 104(A). The light-emitting element shown in Fig. 104(B) has an insulating layer 120204 between the first electrode layer 120200 and the electroluminescent layer 120202, and the light-emitting element shown in Fig. 104(C) has an insulating layer 120204 between the first electrode layer 120200 and the electroluminescent layer 120202.
202, an insulating layer 120205, a second electrode layer 120203 and an electroluminescent layer 12020
2 and an insulating layer 120206. In this manner, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both of them. The insulating layer may be a single layer or a laminate having multiple layers.

In FIG. 104B, an insulating layer 120204 is formed in contact with the first electrode layer 120200.
However, the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120203
An insulating layer 120204 may be provided in contact with the substrate 120204.

Materials that can be used for insulating layers such as insulating layer 120104 in FIG. 103 and insulating layer 120204 in FIG. 104 preferably have high insulation resistance and are dense films.
Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), barium titanate (BaTi
O ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., or a mixed film or a laminated film of two or more of these can be used. These insulating films can be formed by sputtering, vapor deposition, CVD, etc. Also, the insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but is preferably 10 to 10
00 nm range.

The light-emitting element described in this embodiment mode emits light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, and can be driven by either DC or AC.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 15)
In this embodiment, an example of a display device in which this embodiment can be implemented, particularly a case in which optical handling is performed, will be described.

The rear projection display device 130100 shown in Figures 105 (A) and (B) comprises a projector unit 130111, a mirror 130112, and a screen panel 130101.
In addition, the projector unit 130111 may be provided with a speaker 130102 and operation switches 130104.
110, and a mirror 13011 is disposed below the mirror 13011 to project light that projects an image based on a video signal.
The rear projection display device 130100 projects the image onto a screen panel 130101.
The device is configured to display images projected from the rear of the device.

106 shows a front projection display device 130200. The front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201. The projection optical system 130201 is configured to project an image onto a screen or the like disposed in front of the device.

The configuration of a projector unit 130111 that can be applied to the rear projection display device 130100 shown in Figure 105 and the front projection display device 130200 shown in Figure 106 is described below.

FIG. 107 shows an example of the configuration of a projector unit 130111. This projector unit 130111 includes a light source unit 130301 and a modulation unit 13030.
4. The light source unit 130301 includes a light source optical system 130303 including lenses, and a light source lamp 130302. The light source lamp 130302 is housed in a housing so as to prevent stray light from diffusing. As the light source lamp 130302, for example, a high-pressure mercury lamp or a xenon lamp capable of emitting a large amount of light is used. The light source optical system 130303 is configured by appropriately providing optical lenses, a film having a polarizing function, a film for adjusting phase difference, an IR film, etc. The light source unit 130301
The light emitted from the light source 130304 is arranged so as to be incident on the modulation unit 130304. The modulation unit 130304 includes a plurality of display panels 130308, a color filter, a dichroic mirror 130305, a total reflection mirror 130306, a prism 130309, and a projection optical system 130309.
0310. Light emitted from a light source unit 130301 is separated into a plurality of optical paths by a dichroic mirror 130305.

Each optical path is provided with a color filter that transmits light of a specific wavelength or wavelength band, and a display panel 130308. The display panel 130308 is a transmissive type, and modulates the transmitted light based on a video signal. The light of each color transmitted through the display panel 130308 is reflected by a prism 13.
The light is incident on the mirror 130309 and passes through the projection optical system 130310 to display an image on the screen. A Fresnel lens may be disposed between the mirror and the screen. The projection light projected by the projector unit 130111 and reflected by the mirror is converted by the Fresnel lens into approximately parallel light and projected onto the screen.

The projector unit 130111 shown in FIG. 108 includes a reflective display panel 130407.
, 130408, and 130409.

A projector unit 130111 shown in Fig. 108 includes a light source unit 130301 and a modulation unit 130400. The light source unit 130301 may have the same configuration as that shown in Fig. 107. The light from the light source unit 130301 is reflected by a dichroic mirror 13
0401, 130402, and a total reflection mirror 130403 divide the light into multiple optical paths,
The light beams are incident on the polarizing beam splitters 130404, 130405, and 130406. The polarizing beam splitters 130404, 130405, and 130406 are provided corresponding to the reflective display panels 130407, 130408, and 130409 corresponding to each color. The reflective display panels 130407, 130408, and 130409 modulate the reflected light based on a video signal. The light beams of each color reflected by the reflective display panels 130407, 130408, and 130409 are incident on the prism 130309 to be combined and projected through the projection optical system 130411.

Of the light emitted from light source unit 130301, dichroic mirror 130401 transmits only light in the red wavelength region and reflects light in the green and blue wavelength regions. Furthermore, dichroic mirror 130402 reflects only light in the green wavelength region. The light in the red wavelength region transmitted through dichroic mirror 130401 is reflected by total reflection mirror 130403 and enters polarizing beam splitter 130404. The light in the blue wavelength region enters polarizing beam splitter 130405 and the light in the green wavelength region is reflected by polarizing beam splitter 130406.
The polarizing beam splitters 130404, 130405, and 130406 are
The reflective display panels 130407, 130408, and 130409 have the function of separating incident light into P-polarized light and S-polarized light, and also have the function of transmitting only P-polarized light. The reflective display panels 130407, 130408, and 130409 polarize the incident light based on a video signal.

Only S-polarized light corresponding to each color is incident on the reflective display panels 130407, 130408, and 130409 corresponding to each color.
, 130409 may be a liquid crystal panel. In this case, the liquid crystal panel operates in an electric field controlled birefringence mode (ECB). Also, the liquid crystal molecules are aligned perpendicular to the substrate at a certain angle. Therefore, in the reflective display panels 130407, 130408, 130409, when the pixel is in the off state, the display molecules are aligned so as to reflect the incident light without changing its polarization state. Also, when the pixel is in the on state, the orientation state of the display molecules changes, and the polarization state of the incident light changes.

The projector unit 130111 shown in FIG. 108 can be applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG.

The projector unit shown in Fig. 109 shows a single-panel configuration. The projector unit 130111 shown in Fig. 109(A) includes a light source unit 130301, a display panel 1
The display panel 130507 includes a projection optical system 130511 and a retardation plate 130504. The projection optical system 130511 is composed of one or more lenses. The display panel 130507 may include a color filter.

FIG. 109B shows a projector unit 1 that operates in a field sequential manner.
109(B) shows the configuration of a field sequential type LCD panel 130301 and 130508. The field sequential type is a type in which light of each color, such as red, green, and blue, is incident on the display panel in a time-shifted manner in sequence, thereby performing color display without a color filter. In particular, when combined with a display panel that has a high response speed to changes in input signals, high-definition images can be displayed. In FIG. 109(B), a rotating color filter plate 130505 equipped with multiple color filters, such as red, green, and blue, is provided between the light source unit 130301 and the display panel 130508.

The projector unit 130111 shown in Fig. 109(C) shows a configuration of a color separation method using a macro lens as a color display method. This method is a method in which a microlens array 130506 is provided on the light input side of the display panel 130509, and color display is realized by illuminating each color of light from a different direction. The projector unit 130111 that employs this method has the characteristic that the light from the light source unit 130301 can be effectively used because there is little light loss due to color filters.
A projector unit 130111 shown in FIG. 9(C) includes a dichroic mirror 130501, a dichroic mirror 130502, and a dichroic mirror for red light 130503 so as to illuminate a display panel 130509 with light of each color from each direction.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 16)
In this embodiment, an example of an electronic device according to the present embodiment will be described.

110 shows a display panel module combining a display panel 900101 and a circuit board 900111. The display panel 900101 has a pixel portion 900102, a scanning line driver circuit 900103, and a signal line driver circuit 900104. For example, a control circuit 900112 and a signal division circuit 900113 are formed on the circuit board 900111. The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114. An FPC or the like can be used for the connection wiring.

The display panel 900101 may be formed by forming the pixel portion 900102 and some of the peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) integrally on a substrate using TFTs, forming some of the peripheral driver circuits (a driver circuit having a high operating frequency among a plurality of driver circuits) on an IC chip, and mounting the IC chip on the display panel 900101 by COG (chip on glass) or the like. In this way, the area of the circuit board 900111 can be reduced, and a small display device can be obtained. Alternatively, the IC chip can be mounted on a substrate using TAB (Tape Auto Binder).
The display panel 900101 may be mounted using a bonding board or a printed circuit board. This makes it possible to reduce the area of the display panel 900101, thereby making it possible to obtain a display device with a small frame size.

For example, in order to reduce power consumption, a pixel portion may be formed on a glass substrate using TFTs, all peripheral driving circuits may be formed on an IC chip, and the IC chip may be mounted on a display panel by COG or TAB.

A television receiver can be completed by using the display panel module shown in Fig. 110. Fig. 111 is a block diagram showing the main components of a television receiver. Tuner 9002
01 receives a video signal and an audio signal. The video signal is passed through a video signal amplifier circuit 900202 and
The signal output from the video signal amplifier circuit 900202 is processed by a video signal processing circuit 900203 that converts the signal into a color signal corresponding to each of the colors red, green, and blue, and a control circuit 900212 that converts the video signal into an input specification for a drive circuit.
12 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal division circuit 900213 may be provided on the signal line side to divide an input digital signal into m parts (m is a positive integer) and supply the divided signals.

Of the signals received by the tuner 900201, the audio signal is input to an audio signal amplifier circuit 900205.
The output of the signal is sent to a speaker 900207 via an audio signal processing circuit 900206. A control circuit 900208 receives control information for the receiving station (receiving frequency) and the volume from an input section 900208.
900209 and sends signals to the tuner 900201 and audio signal processing circuit 900206.

112A shows a television receiver incorporating a display panel module of a different form from that shown in FIG. 111. In FIG. 112A, a display screen 900302 housed in a housing 900301 is formed by a display panel module.
3. Operation switches 900304 etc. may be provided as appropriate.

Also, Fig. 112(B) shows a television receiver in which only the display can be carried wirelessly. A battery and a signal receiver are built into the housing 900312, and the battery drives the display unit 900313 and the speaker unit 900317. The battery can be repeatedly charged by a charger 900310. The charger 900310 can also transmit and receive video signals, and can transmit the video signals to the signal receiver of the display. The housing 900312 is controlled by an operation key 900316. Alternatively, as shown in Fig. 1
In the device shown in FIG. 12B, the operation keys 900316 are operated to operate the housing 9003.
Alternatively, the device may be a two-way audio-video communication device capable of transmitting a signal from the charger 900310 to the charger 900310 by operating the operation key 900316.
The remote control device may be a general-purpose remote control device that can control communication with other electronic devices by sending a signal from the remote control device 12 to the charger 900310 and allowing the other electronic devices to receive the signal that the charger 900310 can transmit. This embodiment mode can be applied to the display unit 900313.

113A shows a module in which a display panel 900401 and a printed wiring board 900402 are combined. The display panel 900401 includes a pixel portion 900403 having a plurality of pixels, a first scanning line driver circuit 900404, a second scanning line driver circuit 900405, and a second scanning line driver circuit 900406.
05 and a signal line driver circuit 900406 that supplies a video signal to a selected pixel.

The printed wiring board 900402 includes a controller 900407, a central processing unit (CPU
) 900408, memory 900409, power supply circuit 900410, audio processing circuit 90041
1 and a transmitting/receiving circuit 900412. The printed wiring board 900402 and the display panel 900401 are connected by a flexible wiring board (FPC) 900413. The printed wiring board (FPC) 900413 may be provided with a storage capacitor, a buffer circuit, etc., to prevent noise from being carried on the power supply voltage or signal, or to prevent the rise of the signal from becoming slow. In addition, the controller 900407, the audio processing circuit 900411, the memory 900409, the central processing unit (CPU) 900408, the power supply circuit 900410, etc. may be mounted on the display panel 900401 using a COG (chip on glass) method. The scale of the printed wiring board 900402 can be reduced by the COG method.

An interface (I/F) section 900414 provided on the printed wiring board 900402
Various control signals are input and output via the printed wiring board 900402. In addition, an antenna port 900415 for transmitting and receiving signals to and from an antenna is provided on the printed wiring board 900402.

Fig. 113(B) shows a block diagram of the module shown in Fig. 113(A). This module includes a VRAM 900416, a DRAM 900417, a flash memory 900418, etc. as the memory 900409. The VRAM 900416 stores image data to be displayed on the panel, the DRAM 900417 stores image data or audio data, and the flash memory stores various programs.

The power supply circuit 900410 supplies power to operate the display panel 900401, the controller 900407, the central processing unit (CPU) 900408, the audio processing circuit 900411, the memory 900409, and the transmission/reception circuit 900412. Depending on the specifications of the panel, the power supply circuit 900410 may also be provided with a current source.

The central processing unit (CPU) 900408 includes a control signal generating circuit 900420 and a decoder 90
The CPU 900408 includes a register 900421, a register 900422, an arithmetic circuit 900423, a RAM 900424, and an interface 900419 for a central processing unit (CPU) 900408. Various signals input to the central processing unit (CPU) 900408 via the interface 900419 are temporarily stored in the register 900422, and then input to the arithmetic circuit 900423 and the decoder 900421. The arithmetic circuit 900423 performs calculations based on the input signals and specifies where to send the various commands. Meanwhile, the signal input to the decoder 900421 is decoded and input to a control signal generation circuit 900420. The control signal generation circuit 900420 generates signals including various commands based on the input signals, and outputs the signals to the arithmetic circuit 900423.
423, specifically, the memory 900409, the transmission/reception circuit 90041
2. Send to audio processing circuit 900411, controller 900407, etc.

The memory 900409, the transmission/reception circuit 900412, the audio processing circuit 900411, and the controller 900407 operate according to the instructions they receive. The operations will be briefly described below.

The signal input from the input means 900425 is input to the interface (I/F) section 90041.
A central processing unit (CPU) 9004 mounted on a printed wiring board 900402 via a
08. The control signal generating circuit 900420 converts the image data stored in the VRAM 900416 into a predetermined format in accordance with a signal sent from an input means 900425 such as a pointing device or a keyboard, and sends it to the controller 900407.

The controller 900407 controls the central processing unit (CPU) 9004 according to the panel specifications.
08, a signal including image data is subjected to data processing, and a display panel 90040
The controller 900407 also controls the Hs
It generates a sync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L/R, and supplies them to the display panel 900401.

In the transmission/reception circuit 900412, signals transmitted and received as radio waves by the antenna 900428 are processed. Specifically, the circuit includes an isolator, a bandpass filter, a VCO (Volt
age Controlled Oscillator), LPF (Low Pass
The transmission/reception circuit 90 may include high-frequency circuits such as a filter, a coupler, and a balun.
Among the signals transmitted and received in the 0412, a signal including voice information is transmitted to the central processing unit (CPU
) 900408, the signal is sent to the audio processing circuit 900411 in accordance with an instruction from the audio processing circuit 900411.

A signal including voice information sent in accordance with an instruction from a central processing unit (CPU) 900408 is demodulated into a voice signal by a voice processing circuit 900411 and sent to a speaker 900427. A voice signal sent from a microphone 900426 is also demodulated into a voice signal by a voice processing circuit 900411.
1 and sent to the transmitting/receiving circuitry 900412 according to instructions from a central processing unit (CPU) 900408.

Controller 900407, central processing unit (CPU) 900408, power supply circuit 90041
0, an audio processing circuit 900411, and a memory 900409 can be implemented as a package according to this embodiment.

Of course, this embodiment is not limited to television receivers, but can be applied to a variety of uses, particularly as a large-area display medium, such as personal computer monitors, information display boards at railway stations and airports, and advertising display boards on the street.

Next, with reference to FIG. 114, we will explain an example of the configuration of a mobile phone according to this embodiment.

The display panel 900501 is detachably assembled in the housing 900530. The shape and dimensions of the housing 900530 can be changed as appropriate to match the size of the display panel 900501. The housing 900530 to which the display panel 900501 is fixed is fitted into a printed circuit board 900531 and assembled as a module.

The display panel 900501 is connected to a printed circuit board 900531 via an FPC 900513. The printed circuit board 900531 is provided with a speaker 900532, a microphone 900533, and a microphone 900534.
0533, a transmission/reception circuit 900534, a signal processing circuit 9 including a CPU and a controller, etc.
Such a module is combined with an input means 900536 and a battery 900537 and housed in a housing 900539.
The pixel portion is arranged so as to be visible through an opening window formed in the housing 900539.

The display panel 900501 may have a pixel portion and some of the peripheral driving circuits (a driving circuit having a lower operating frequency among multiple driving circuits) integrally formed on a substrate using TFTs, and some of the peripheral driving circuits (a driving circuit having a higher operating frequency among multiple driving circuits) formed on an IC chip, which is then mounted on the display panel 900501 using COG (chip on glass).
Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed circuit board. With such a configuration, the power consumption of the display device can be reduced, and the usage time of the mobile phone on a single charge can be extended. In addition, the cost of the mobile phone can be reduced.

The mobile phone shown in FIG. 115 is provided with operation switches 900604 and a microphone 90
A main body (A) 900601 including a display panel (A) 900608,
A main body (B) 900609 equipped with a display panel (B) 900609, a speaker 900606, etc.
The display panel (A) 90 is connected to the display panel (B) 90 by a hinge 900610 so as to be capable of opening and closing.
The display panel (B) 900608 and the display panel (B) 900609 are connected together with the circuit board 900607 to the main body (B) 900608.
The display panel (A) 900608 and the display panel (B) 900609 are housed in a housing 900603 of a display panel (A) 900602. The pixel portions of the display panel (A) 900608 and the display panel (B) 900609 are arranged so as to be visible through an opening window formed in the housing 900603.

The display panel (A) 900608 and the display panel (B) 900609 are the same as those of the mobile phone 90.
The number of pixels and other specifications can be set appropriately depending on the function of the display panel 0600. For example, the display panel (A) 900608 can be used as a main screen, and the display panel (B) 900609 can be used as a sub-screen.

The mobile phone according to this embodiment can be transformed into various forms depending on its functions and uses.
For example, an imaging element may be incorporated in the hinge 900610 to make a mobile phone with a camera. The above-mentioned effects can also be achieved by accommodating the operation switches 900604, the display panel (A) 900608, and the display panel (B) 900609 in a single housing. The same effects can also be achieved by applying the configuration of this embodiment to an information display terminal equipped with multiple display units.

The present embodiment can be applied to various electronic devices. Specifically, the present embodiment can be applied to display units of electronic devices. Examples of such electronic devices include video cameras, digital cameras,
Goggle-type displays, navigation systems, audio playback devices (car audio, audio components, etc.), computers, game machines, portable information terminals (mobile computers, mobile phones, portable game consoles, e-books, etc.), image playback devices equipped with recording media (specifically, devices that play back recording media such as Digital Versatile Discs (DVDs),
Examples of such a device include a display device capable of displaying the image.

Figure 116 (A) shows a display, which includes a housing 900711, a support stand 900712, a display portion 900713, etc.

FIG. 116B shows a camera, which includes a main body 900721, a display unit 900722, and an image receiving unit 900
723, operation keys 900724, external connection port 900725, shutter 900726
etc.

FIG. 116C shows a computer, which includes a main body 900731, a housing 900732, and a display unit 9
00733, a keyboard 900734, an external connection port 900735, a pointing device 900736, etc.

FIG. 116(D) shows a mobile computer, which includes a main body 900741 and a display unit 900742.
, switch 900743, operation keys 900744, infrared port 900745, etc.

FIG. 116(E) shows a portable image reproducing device (for example, a DVD reproducing device) equipped with a recording medium.
A main body 900751, a housing 900752, a display unit (A) 900753, a display unit (B
) 900754, recording medium (DVD, etc.) reading section 900755, operation keys 900756
, a speaker unit 900757, etc. The display unit (A) 900753 can mainly display image information, and the display unit (B) 900754 can mainly display text information.

FIG. 116(F) shows a goggle-type display, which includes a main body 900761 and a display unit 90076.
2. Includes earphones 900763 and a support part 900764.

116G shows a portable game machine, which includes a housing 900771, a display portion 900772, a speaker portion 900773, operation keys 900774, a storage medium insertion portion 900775, etc. A portable game machine in which the display device of this embodiment mode is used for the display portion 900772 can express vivid colors.

FIG. 116(H) shows a digital camera with a television receiving function, which includes a main body 900781, a display section 900782, operation keys 900783, a speaker 900784, and a shutter 90078.
5, an image receiving unit 900786, an antenna 900787, etc.

As shown in FIGS. 116A to 116E, the electronic devices according to this embodiment mode are characterized by having a display portion for displaying some information.

Next, we will explain application examples of the semiconductor device according to this embodiment.

FIG. 117 shows an example in which the semiconductor device according to this embodiment is integrated with a building. FIG. 117 shows a housing 900810, a display unit 900811, a remote control device 900812 which is an operation unit, and a
00812, speaker portion 900813, etc. The semiconductor device according to this embodiment mode is integrated with a building as a wall-mounted type, and can be installed without requiring a large installation space.

118 shows another example in which the semiconductor device according to this embodiment is provided in a building as an integral part of the building. A display panel 900901 is attached integrally to a unit bath 900902, and a person taking a bath can view the display panel 900901.
The device 0901 has the function of displaying information when operated by the bather and can be used as advertising or entertainment.

The semiconductor device according to this embodiment can be installed in various places, not just the side wall of the unit bath 900902 shown in Fig. 118. For example, it may be integrated with a part of a mirror surface or the bathtub itself. In this case, the shape of the display panel 900901 may be adapted to the shape of the mirror surface or the bathtub.

119 shows another example in which the semiconductor device according to this embodiment mode is integrated with a building. A display panel 901002 is attached while being curved to match the curved surface of a pillar 901001. Note that the pillar 901001 is described here as a utility pole.

The display panel 901002 shown in FIG. 119 is positioned higher than the human eye position.
By installing the display panel 901002 on a structure that stands repeatedly outdoors, such as a utility pole, it is possible to advertise to an unspecified number of viewers.
Since the display panel 901002 can easily display the same image and instantly switch images by external control, it is expected to be very effective in displaying information and advertising. Furthermore, by providing the display panel 901002 with a self-luminous display element, it can be said to be useful as a display medium with high visibility even at night. Furthermore, by installing the display panel 901002 on a utility pole,
It is easy to secure the power supply means 1002. Furthermore, in the event of an emergency such as a disaster, it can also be used as a means for quickly transmitting accurate information to disaster victims.

As the display panel 901002, for example, a display panel in which switching elements such as organic transistors are provided on a film-like substrate and images are displayed by driving the display elements can be used.

In this embodiment, a wall, a pillar, and a unit bath are used as examples of structures, but this embodiment is not limited to these, and the semiconductor device according to this embodiment can be installed in various structures.

Next, we will show an example in which the semiconductor device according to this embodiment is integrated with a moving object.

120 is a diagram showing an example in which the semiconductor device according to this embodiment mode is integrated with an automobile. A display panel 901102 is attached integrally to a body 901101 of the automobile, and can display on demand the operation of the automobile body and information input from inside and outside the automobile. In addition, the display panel may have a navigation function.

The semiconductor device according to this embodiment mode can be installed not only in the vehicle body 901 shown in FIG. 120 but also in various other places. For example, it may be integrated with a glass window, a door, a handle, a shift lever, a seat, a room mirror, etc. In this case, the display panel 901
The shape of 102 may be adapted to the shape of the object on which it is to be installed.

FIG. 121 is a diagram showing an example in which the semiconductor device according to this embodiment is integrated with a train car.

Fig. 121(a) is a diagram showing an example in which a display panel 901202 is provided on the glass of a door 901201 of a train car. Compared to conventional paper advertisements, this has the advantage that it does not require labor costs that would be required when switching advertisements. In addition, the display panel 901202 can instantly switch images displayed on the display unit in response to an external signal,
For example, it would be possible to switch images on the display panel depending on the time of day when the types of passengers getting on and off the train change, which would allow for more effective advertising.

FIG. 121(b) shows the glass of the train car door 901201 and the glass window 901203.
901202 and a ceiling 901204.
In this way, the semiconductor device according to the present embodiment can be easily installed in places where installation was previously difficult, and therefore effective advertising effects can be obtained. Furthermore, the semiconductor device according to the present embodiment can instantly switch images displayed on the display unit in response to an external signal, thereby reducing the cost and time required for switching advertisements and enabling more flexible advertising and information transmission.

The semiconductor device according to this embodiment mode can be installed in various places, not just the door 901201, the glass window 901203, and the ceiling 901204 shown in Fig. 121. For example, it may be integrated with a hanging strap, a seat, a handrail, a floor, etc. In this case, the shape of the display panel 901202 may be adapted to the shape of the object on which it is installed.

FIG. 122 is a diagram showing an example in which the semiconductor device according to this embodiment is integrated with a passenger airplane.

FIG. 122(a) shows a display panel 90130 mounted on a ceiling 901301 above the seats of a passenger airplane.
9 is a diagram showing the shape of the display panel 901302 when it is in use.
The display panel 901302 is attached to the ceiling 901301 via a hinge portion 901303, and passengers can view the display panel 901302 by expanding and contracting the hinge portion 901303. The display panel 901302 can display information when operated by passengers. It also has a function that can be used as advertising or entertainment. Also, as shown in FIG. 122(b), the hinge portion can be folded and stored in the ceiling 901301, which can ensure safety during takeoff and landing. In the event of an emergency, the display element of the display panel can be turned on to use it as a means of transmitting information and as an emergency exit light.

The semiconductor device according to this embodiment can be installed in various places, not just the ceiling 901301 shown in FIG. 122. For example, a seat, a seat table, an armrest,
It may be integrated with a window, etc. Also, a large display panel that can be viewed by many people at the same time may be installed on the wall of the aircraft. In this case, the shape of the display panel 901302 may be adapted to the shape of the object on which it is installed.

In this embodiment, the moving body is exemplified by a train car body, an automobile body, and an airplane body, but is not limited thereto.
The semiconductor device according to the present embodiment can be installed in various vehicles such as trains (including monorails, railways, etc.), ships, etc. Since the semiconductor device according to the present embodiment can instantly switch the display of a display panel in a moving body by an external signal, by installing the semiconductor device according to the present embodiment in a moving body, the moving body can be used for purposes such as an advertisement display board for an unspecified number of customers, an information display board in the event of a disaster, etc.

This embodiment can be freely combined with other embodiments.

It should be noted that the contents of each figure in this embodiment can be freely combined with the contents of other figures.

(Embodiment 17)
As described above, this specification includes at least the following inventions.

A liquid crystal display device having a pixel having a liquid crystal element and a driver circuit. The driver circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. At least a part of the driver circuit includes the following connections: a first electrode of the first transistor is electrically connected to a fourth wiring, and a second electrode of the first transistor is electrically connected to a third wiring. A first electrode of the second transistor is electrically connected to a sixth wiring, and a second electrode of the second transistor is electrically connected to a third wiring. A first electrode of the third transistor is electrically connected to a fourth wiring, and a second electrode of the second transistor is electrically connected to a third wiring.
a first electrode of the third transistor electrically connected to a fifth wiring, a second electrode of the third transistor electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor electrically connected to a seventh wiring; a first electrode of the fourth transistor electrically connected to a sixth wiring, a second electrode of the fourth transistor electrically connected to a gate electrode of the second transistor, and a gate electrode of the fourth transistor electrically connected to a gate electrode of the first transistor; a first electrode of the fifth transistor electrically connected to a seventh wiring, a second electrode of the fifth transistor electrically connected to a gate electrode of the first transistor, and a gate electrode of the fifth transistor electrically connected to the first wiring; a first electrode of the sixth transistor electrically connected to a sixth wiring, a second electrode of the sixth transistor electrically connected to a gate electrode of the first transistor, and a gate electrode of the sixth transistor electrically connected to a gate electrode of the second transistor. A first electrode of the seventh transistor is electrically connected to the sixth wiring, a second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the seventh transistor is electrically connected to the second wiring.

The liquid crystal display device having the pixel having the liquid crystal element and the driver circuit may include the following structure:
The W/L value of the first transistor is the largest among the W/L values of the fifth transistor.
A configuration including a driver circuit in which the channel length L of the third transistor is longer than the channel length L of the fourth transistor. A configuration including a capacitor element disposed between the second electrode of the first transistor and the gate electrode of the first transistor.
The first to seventh transistors include n-channel transistors, and the first to seventh transistors include transistors using amorphous silicon for a semiconductor layer.

A liquid crystal display device having a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit.
The first and second driving circuits at least partially include the following connection relationships.
The first driver circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. A first electrode of the first transistor is electrically connected to a fourth wiring, and a second electrode of the first transistor is electrically connected to a third wiring. A first electrode of the second transistor is electrically connected to a sixth wiring, and a second electrode of the ninth transistor is electrically connected to a third wiring. A first electrode of the third transistor is electrically connected to a fifth wiring, a second electrode of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to a seventh wiring. A first electrode of the fourth transistor is electrically connected to the sixth wiring, and a second electrode of the fourth transistor is electrically connected to a third wiring.
A second electrode of the first transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor. A first electrode of the fifth transistor is electrically connected to a seventh wiring, a second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the fifth transistor is electrically connected to the first wiring. A first electrode of the sixth transistor is electrically connected to a sixth wiring, a second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor. A first electrode of the seventh transistor is electrically connected to the sixth wiring, a second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the seventh transistor is electrically connected to the second wiring.
The second driver circuit has an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. A first electrode of the eighth transistor is electrically connected to the eleventh wiring, and a second electrode of the eighth transistor is electrically connected to the tenth wiring. A first electrode of the ninth transistor is electrically connected to the thirteenth wiring, and a second electrode of the ninth transistor is electrically connected to the tenth wiring. A first electrode of the tenth transistor is electrically connected to the twelfth wiring, a second electrode of the tenth transistor is electrically connected to a gate electrode of the ninth transistor, and a gate electrode of the tenth transistor is electrically connected to the fourteenth wiring. A first electrode of the eleventh transistor is electrically connected to the first wiring.
The first electrode of the eleventh transistor is electrically connected to the gate electrode of the ninth transistor, and the gate electrode of the eleventh transistor is electrically connected to the gate electrode of the eighth transistor.
A first electrode of the 12th transistor is electrically connected to the 13th wiring, a second electrode of the 12th transistor is electrically connected to the gate electrode of the eighth transistor, and the gate electrode of the 12th transistor is electrically connected to the 8th wiring. A first electrode of the 13th transistor is electrically connected to the 13th wiring, a second electrode of the 13th transistor is electrically connected to the gate electrode of the eighth transistor, and the gate electrode of the 13th transistor is electrically connected to the gate electrode of the 9th transistor. A first electrode of the 14th transistor is electrically connected to the 13th wiring, a second electrode of the 14th transistor is electrically connected to the gate electrode of the eighth transistor, and the gate electrode of the 14th transistor is electrically connected to the 9th wiring.

The liquid crystal display device having a pixel having the liquid crystal element and a driver circuit may include the following configurations: A configuration in which the fourth wiring and the eleventh wiring are electrically connected, the fifth wiring and the twelfth wiring are electrically connected, the sixth wiring and the thirteenth wiring are electrically connected, and the seventh wiring and the fourteenth wiring are electrically connected. A configuration in which the fourth wiring and the eleventh wiring are the same wiring, the fifth wiring and the twelfth wiring are the same wiring, the sixth wiring and the thirteenth wiring are the same wiring, and the seventh wiring and the fourteenth wiring are the same wiring. A configuration in which the third wiring and the tenth wiring are electrically connected. A configuration in which the third wiring and the tenth wiring are the same wiring. Among the values of the ratios W/L of the channel length L and the channel width W of the first to seventh transistors, the value of W/L of the first transistor is the largest, and among the values of the ratios W/L of the channel length L and the channel width W of the eighth to fourteenth transistors, the value of W/L of the eighth transistor is the largest.
The value of W/L of the fifth transistor is two to five times the value of W/L of the eighth transistor, and the value of W/L of the eighth transistor is two to five times the value of W/L of the twelfth transistor. The channel length L of the third transistor is longer than the channel length L of the fourth transistor, and the channel length L of the tenth transistor is two to five times the value of W/L of the eighth transistor.
A channel length L of the first transistor is longer than a channel length L of the eleventh transistor. A capacitor is disposed between a second electrode of the first transistor and a gate electrode of the first transistor, and a capacitor is disposed between a second electrode of the eighth transistor and a gate electrode of the eighth transistor. The first to fourteenth transistors are n-channel transistors. The first to fourteenth transistors use amorphous silicon as a semiconductor layer.

The liquid crystal display device shown in this embodiment mode is described in this specification, and therefore exerts the same effects as those of the other embodiments.

S1 Signal line Sj Signal line VDD Power supply potential VSS Power supply potential G1 Scanning line Gi Scanning line Gn Scanning line 11 Transistor 12 Transistor 13 Transistor 14 Transistor 15 Transistor 16 Transistor 17 Transistor 21 Signal line 22 Signal line 23 Wiring 24 Signal line 25 Power supply line 26 Power supply line 32 Silicon oxynitride film 41 Node 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 110 Wiring 107 Transistor 112 Wiring 108 Transistor 109 Transistor 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 129 Wiring 130 Wiring 131 Wiring 132 Wiring 133 Wiring 134 Wiring 141 Node 142 Node 221 Signal 222 Signal 223 Signal 225 Signal 226 Signal 232 Signal 241 Potential 242 Potential 401 Capacitor 402 Transistor 403 Resistor 501 Wiring 502 Wiring 503 Wiring 504 Wiring 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Wiring 701 Transistor 702 Transistor 711 Wiring 81a Evaporation source 1001 Flip-flop 1007 Wiring 1011 Wiring 1012 Wiring 1013 Wiring 1014 Wiring 1015 Wiring 1016 Wiring 1017 Wiring 1018 Wiring 1111 Signal 1112 Signal 1113 Signal 1117 Signal 1118 Signal 1211 Signal 1218 Signal 1301 Buffer 1602 Scanning line driver circuit 1801 Signal line driver circuit 1802 Scanning line driver circuit 1803 Pixel 1804 Pixel portion 1805 Insulating substrate 1808 Wiring 2108 Transistor 2132 Wiring 2301 Transistor 2302 Transistor 2303 Transistor 2304 Transistor 2305 Transistor 2306 Transistor 2307 Transistor 2321 Wiring 2322 Wiring 2323 Wiring 2324 Wiring 2325 Wiring 2326 Wiring 2327 Wiring 2328 Wiring 2329 Wiring 2330 Wiring 2331 Wiring 2341 Node 2342 Node 2421 Signal 2422 Signal 2423 Signal 2425 Signal 2426 Signal 2441 Potential 2442 Potential 2501 Conductive layer 2502 Conductive layer 2503 Conductive layer 2504 Conductive layer 2505 Conductive layer 2506 Conductive layer 2507 Conductive layer 2508 Conductive layer 2510 Conductive layer 2511 Conductive layer 2512 Conductive layer 2513 Conductive layer 2514 Conductive layer 2515 Conductive layer 2541 Wiring 2542 Wiring 2543 Wiring 2544 Wiring 2545 Wiring 2546 Wiring 2547 Wiring 2548 Wiring 2549 Wiring 2581 Semiconductor layer 2582 Semiconductor layer 2583 Semiconductor layer 2584 Semiconductor layer 2585 Semiconductor layer 2586 Semiconductor layer 2587 Semiconductor layer 2901 Flip-flop 2907 Wiring 2911 Wiring 2912 Wiring 2913 Wiring 2914 Wiring 2915 Wiring 2916 Wiring 2917 Wiring 2918 Wiring 2919 Wiring 3011 Signal 3018 Signal 3019 Signal 3101 Flip-flop 3111 Wiring 3120 Wiring 3121 Signal 3122 Signal 3123 Signal 3125 Signal 3126 Signal 3141 Potential 3142 Potential 3301 Flip-flop 3301 Wiring 3306 Wiring 3311 Wiring 3312 Wiring 3313 Wiring 3314 Wiring 3315 Wiring 3316 Wiring 3317 Wiring 3318 Wiring 3319 Wiring 3320 Wiring 3321 Wiring 3322 Wiring 3511 Signal 3512 Signal 3513 Signal 3514 Signal 3515 Signal 3519 Signal 3520 Signal 3521 Signal 3604 Board film 3611 Signal 3621 Signal 5601 Driver IC
5602 switch group 5611 wiring 5612 wiring 5613 wiring 5621 wiring 5721 signal 5821 signal 5911 wiring 5912 wiring 5913 wiring 6001 transistor 6002 transistor 6003 transistor 6004 transistor 6005 transistor 6006 transistor 6011 wiring 6012 wiring 6013 wiring 6014 wiring 6015 wiring 6016 wiring 6022 switch group 6101 transistor 6102 transistor 6111 wiring 6112 wiring 6201 transistor 6211 wiring 6401 transistor 6402 transistor 6411 wiring 6412 wiring 8000 buffer 8011 wiring 8012 wiring 802a scanning line driver circuit 802b scanning line driver circuit 8100 Buffer 8201 Transistor 8202 Transistor 8211 Wiring 8212 Wiring 8213 Wiring 8214 Wiring 8301 Transistor 8302 Transistor 8303 Transistor 8304 Transistor 8311 Wiring 8312 Wiring 8313 Wiring 8314 Wiring 8315 Wiring 8316 Wiring 8341 Node 8401 Transistor 8402 Transistor 8403 Transistor 8404 Transistor 8411 Wiring 8412 Wiring 8413 Wiring 8414 Wiring 8415 Wiring 8416 Wiring 8417 Wiring 8441 Node 8501 Transistor 8502 Transistor 8503 Transistor 8511 Wiring 8512 Wiring 8513 Wiring 8514 Wiring 8515 Wiring 8516 Wiring 8541 Node 8601 Transistor 8602 Transistor 8603 Transistor 8604 Transistor 8611 Wiring 8612 Wiring 8613 Wiring 8614 Wiring 8615 Wiring 8616 Wiring 8641 Node 10101 Substrate 10102 Insulating film 10103 Conductive layer 10104 Insulating film 10105 Semiconductor layer 10106 Semiconductor layer 10107 Conductive layer 10108 Insulating film 10109 Conductive layer 10110 Orientation film 10112 Orientation film 10113 Conductive layer 10114 Light-shielding film 10115 Color filter 10116 Substrate 10117 Spacer 10118 Liquid crystal molecule 10121 Scanning line 10122 Video signal line 10123 Capacitive line 10124 TFT
10125 Pixel electrode 10126 Pixel capacitance 10201 Substrate 10202 Insulating film 10203 Conductive layer 10204 Insulating film 10205 Semiconductor layer 10206 Semiconductor layer 10207 Conductive layer 10208 Insulating film 10209 Conductive layer 10210 Alignment film 10212 Alignment film 10213 Conductive layer 10214 Light-shielding film 10215 Color filter 10216 Substrate 10217 Spacer 10218 Liquid crystal molecule 10219 Alignment control protrusion 10221 Scanning line 10222 Video signal line 10223 Capacitor line 10224 TFT
10225 Pixel electrode 10226 Pixel capacitance 10301 Substrate 10302 Insulating film 10303 Conductive layer 10304 Insulating film 10305 Semiconductor layer 10306 Semiconductor layer 10307 Conductive layer 10308 Insulating film 10309 Conductive layer 10310 Orientation film 10312 Orientation film 10313 Conductive layer 10314 Light-shielding film 10315 Color filter 10316 Substrate 10317 Spacer 10318 Liquid crystal molecule 10319 Electrode cutout portion 10321 Scanning line 10322 Video signal line 10323 Capacitor line 10324 TFT
10325 pixel electrode 10326 pixel capacitance 10401 substrate 10402 insulating film 10403 conductive layer 10404 insulating film 10405 semiconductor layer 10406 semiconductor layer 10407 conductive layer 10408 insulating film 10409 conductive layer 10410 alignment film 10412 alignment film 10414 light shielding film 10415 color filter 10416 substrate 10417 spacer 10418 liquid crystal molecule 10421 scanning line 10422 video signal line 10423 common electrode 10424 TFT
10425 pixel electrode 10501 substrate 10502 insulating film 10503 conductive layer 10504 insulating film 10505 semiconductor layer 10506 semiconductor layer 10507 conductive layer 10508 insulating film 10509 conductive layer 10510 alignment film 10512 alignment film 10513 conductive layer 10514 light shielding film 10515 color filter 10516 substrate 10517 spacer 10518 liquid crystal molecule 10519 insulating film 10521 scanning line 10522 video signal line 10523 common electrode 10524 TFT
10525 Pixel electrode 10600 Liquid crystal layer 10601 Substrate 10602 Substrate 10603 Layer 10604 Layer 10605 Electrode 10606 Electrode 10607 Projection 10801 Electrode 10802 Electrode 10803 Electrode 10804 Electrode 10901 Insulating layer 2002a Scanning line driving circuit 2002b Scanning line driving circuit 20100 Substrate 20101 Pixel portion 20102 Pixel 20103 Scanning line input terminal 20104 Signal line input terminal 20105 Scanning line driving circuit 20106 Signal line driving circuit 20115 Substrate 20200 FPC
20201 Driver IC
20301 Transistor 20302 Liquid crystal element 20303 Capacitor element 20304 Wiring 20305 Wiring 20306 Capacitor line 20307 Counter electrode 20501 Insulating film 20502 Semiconductor layer 20503 Insulating layer 20504 Conductive layer 20505 Insulating layer 20506 Conductive film 20507 Insulating layer 20508 Conductive layer 20509 Insulating layer 20510 Liquid crystal layer 20511 Insulating film 20512 Conductive film 20513 Insulating film 20514 Insulating film 20515 Counter substrate 20516 Sealing material 20517 Anisotropic conductive layer 20518 FPC
20521 transistor 20525 driver circuit region 20526 pixel region 20530 IC chip 20531 spacer 20532 insulating film 20533 conductive film 20601 driver IC
21301 insulating film 21801 insulating film 22001 insulating film 2202a scanning line driver circuit 2202b scanning line driver circuit 22201 insulating film 22601 backlight unit 22602 diffusion plate 22603 light guide plate 22604 reflector 22605 lamp reflector 22606 light source 22607 liquid crystal panel 22608 layer 22609 layer 22610 slit 22701 video signal 22702 control circuit 22703 signal line driver circuit 22704 scanning line driver circuit 22705 pixel portion 22706 lighting means 22707 power supply 22708 driver circuit portion 22710 scanning line 22712 signal line 22731 shift register 22732 latch 22733 latch 22734 Level shifter 22735 Buffer 22741 Shift register 22742 Level shifter 22743 Buffer 22801 Cold cathode tube 22802 Light emitting diode 22803 Light emitting diode 22832 Lamp reflector 22852 Backlight unit 23000 Polarizing film 23001 Protective film 23002 Substrate film 23002 Substrate film 23003 PVA polarizing film 23004 Substrate film 23005 Adhesive layer 23006 Release film 23100 TFT substrate 23101 Counter substrate 23102 Sealing material 23103 Pixel portion 23104 Liquid crystal layer 23105 Colored layer 23106 Layer 23107 Layer 23109 Flexible wiring board 23110 Cold cathode tube 23111 Reflector 23112 Circuit board 23113 Diffuser 23199 Control unit 2901i Flip-flop 30101 Encoding circuit 30102 Frame memory 30103 Correction circuit 30104 DA conversion circuit 30112 Frame memory 30113 Correction circuit 30121 Input voltage 30122 Input voltage 30123 Output luminance 30124 Output luminance 30131 Input video signal 30132 Output video signal 30133 Output switching signal 30201 Transistor 30202 Auxiliary capacitance 30203 Display element 30204 Video signal line 30205 Scanning line 30206 Common line 30211 Transistor 30212 Auxiliary capacitance 30213 Display element 30214 Video signal line 30215 Scanning line 30216 Common line 30217 Common line 30301 Diffusion plate 30302 Cold cathode fluorescent lamp 30311 Diffusion plate 30312 Light source 30400 Frame period 30401 Image 30402 Intermediate image 30412 Intermediate image 30413 Intermediate image 5603a Switch 5603b Switch 5603c Switch 5703a Timing 5703b Timing 5703c Timing 5803a Timing 5803b Timing 5803c Timing 5903a Transistor 5903b Transistor 5903c Transistor 60105 TFT
60106 Wiring 60107 Wiring 60108 TFT
60111 Wiring 60112 Counter electrode 60113 Capacitor 60115 Pixel electrode 60116 Partition wall 60117 Organic conductive film 60118 Organic thin film 60119 Substrate 60200 Substrate 60201 Wiring 60202 Wiring 60203 Wiring 60204 Wiring 60205 TFT
60206 TFT
60207 TFT
60208 Pixel electrode 60211 Partition wall 60212 Organic conductive film 60213 Organic thin film 60214 Counter electrode 60300 Substrate 60301 Wiring 60302 Wiring 60303 Wiring 60304 Wiring 60305 TFT
60306 TFT
60307 TFT
60308 TFT
60309 Pixel electrode 60311 Wiring 60312 Wiring 60321 Partition wall 60322 Organic conductive film 60323 Organic thin film 60324 Counter electrode 60401 Anode 60402 Cathode 60403 Hole transport region 60404 Electron transport region 60405 Mixing region 60406 Region 60407 Region 60408 Region 60409 Region 60560 Transfer chamber 60561 Transfer chamber 60562 Load chamber 60563 Unload chamber 60564 Intermediate treatment chamber 60565 Sealing treatment chamber 60566 Transfer means 60567 Transfer means 60568 Heat treatment chamber 60569 Film formation treatment chamber 60570 Film formation treatment chamber 60571 Film formation chamber 60572 Plasma treatment chamber 60573 Film forming processing chamber 60574 Film forming processing chamber 60576 Film forming processing chamber 60680 Evaporation source holder 60681 Evaporation source 60682 Distance sensor 60683 Articulated arm 60684 Material supply pipe 60686 Substrate stage 60687 Substrate chuck 60688 Mask chuck 60689 Substrate 60690 Shadow mask 60691 Top plate 60692 Bottom plate 6301a Transistor 6301b Transistor 6302a Transistor 6302b Transistor 8001a Inverter 8001b Inverter 8001c Inverter 8002a Inverter 8002b Inverter 8002c Inverter 8003a Inverter 8003b Inverter 8003c Inverter 80302 Drive transistor 80400 Drive transistor 80401 Switch 80402 Switch 80403 Switch 80404 Capacitor 80405 Capacitor 80411 Signal line 80412 Power line 80413 First scanning line 80414 Second scanning line 80415 Third scanning line 80420 Display element 80421 Electrode 80430 Driving transistor 80431 Switch 80432 Switch 80433 Switch 80434 Capacitor 80441 Signal line 80442 Power line 80443 First scanning line 80444 Second scanning line 80445 Third scanning line 80450 Display element 80451 Electrode 80454 Scanning line 10606a Electrode 10801a Electrode 10801b Electrode 10801c Electrode 10801d Electrode 10802a Electrode 10802b Electrode 10802c Electrode 10802d Electrode 10803a Electrode 10803b Electrode 10803c Electrode 10803d Electrode 10804a Electrode 10804b Electrode 10804c Electrode 10804d Electrode 110111 Substrate 110112 Insulating film 110113 Semiconductor film 110114 Semiconductor film 110115 Semiconductor film 110116 Insulating film 110117 Gate electrode 110118 Insulating film 110119 Insulating film 110121 Sidewall 110122 Mask 110123 Conductive film 110131 Insulating film 120100 Electrode layer 120102 Electroluminescent layer 120103 Electrode layer 120104 Insulating layer 120105 Insulating layer 120106 Insulating layer 120200 Electrode layer 120201 Luminescent material 120202 Electroluminescent layer 120203 Electrode layer 120204 Insulating layer 120205 Insulating layer 120206 Insulating layer 130100 Rear projection display device 130101 Screen panel 130102 Speaker 130104 Operation switches 130110 Housing 130111 Projector unit 130112 Mirror 130200 Front projection display device 130201 Projection optical system 130301 Light source unit 130301 Light source unit 130302 Light source lamp 130303 Light source optical system 130304 Modulation unit 130305 Dichroic mirror 130306 Total reflection mirror 130308 Display panel 130309 Prism 130310 Projection optical system 130400 Modulation unit 130401 Dichroic mirror 130402 Dichroic mirror 130403 Total reflection mirror 130404 Polarizing beam splitter 130405 Polarizing beam splitter 130406 Polarizing beam splitter 130407 Reflective display panel 130411 Projection optical system 130501 Dichroic mirror 130502 Dichroic mirror 130503 Red light dichroic mirror 130504 Retardation plate 130505 Color filter plate 130506 Microlens array 130507 Display panel 130508 Display panel 130509 Display panel 130511 Projection optical system 20102a Pixel 20102b Pixel 20105a Scanning line driving circuit 20105b Scanning line driver circuit 20301a Transistor 20301b Transistor 20303a Capacitive element 20303b Capacitive element 20305a Wiring 20305b Wiring 203076 Wiring 20502a Semiconductor layer 20502b Semiconductor layer 20503a Insulating layer 20503b Insulating layer 20504a Conductive layer 20504b Conductive layer 20508a Conductive layer 20508b Conductive layer 20602a Driver IC
20602b Driver IC
23190a Red light source 23190b Green light source 23190c Blue light source 60577a Gate valve 60681a Evaporation source 60681b Evaporation source 60681c Evaporation source 60685a Material supply source 60685b Material supply source 60685c Material supply source 80301a Switching transistor 80301b Switching transistor 80301c Switching transistor 80301d Switching transistor 80301e Switching transistor 80302a Driving transistor 80302b Driving transistor 80302c Driving transistor 80302d Driving transistor 80302e Driving transistor 80303c Diode-connected transistor 80303d Diode-connected transistor 80303e Erasing transistor 80304a Capacitive element 80304b Capacitor 80304c Capacitor 80304d Capacitor 80304e Capacitor 80306a Rectifier 80311a Signal line 80311b Signal line 80311c Signal line 80311d Signal line 80311e Signal line 80312a First scanning line 80312b First scanning line 80312c First scanning line 80312d First scanning line 80312e First scanning line 80313a Power supply line 80313b Power supply line 80313c Power supply line 80313d Power supply line 80313e Power supply line 80314b Second scanning line 80314c Second scanning line 80314d Second scanning line 80320a Display element 80320b Display element 80321a Electrode 80321b Electrode 900101 Display panel 900102 Pixel portion 900103 Scanning line driver circuit 900104 Signal line driver circuit 900111 Circuit board 900112 Control circuit 900113 Signal division circuit 900114 Connection wiring 900201 Tuner 900202 Video signal amplifier circuit 900203 Video signal processing circuit 900205 Audio signal amplifier circuit 900206 Audio signal processing circuit 900207 Speaker 900208 Control circuit 900209 Input portion 900212 Control circuit 900213 Signal division circuit 900301 Housing 900302 Display screen 900303 Speaker 900304 Operation switch 900310 Charger 900312 Housing 900313 Display portion 900316 Operation keys 900317 Speaker section 900401 Display panel 900402 Printed wiring board 900403 Pixel section 900404 Scanning line driver circuit 900405 Scanning line driver circuit 900406 Signal line driver circuit 900407 Controller 900408 Central processing unit (CPU)
900409 Memory 900410 Power supply circuit 900411 Audio processing circuit 900412 Transmitting/receiving circuit 900413 Flexible printed circuit board (FPC)
900414 Interface (I/F) section 900415 Antenna port 900416 VRAM
900417 DRAM
900418 Flash memory 900419 Interface 900420 Control signal generating circuit 900421 Decoder 900422 Register 900423 Arithmetic circuit 900424 RAM
900425 Input means 900426 Microphone 900427 Speaker 900428 Antenna 900501 Display panel 900513 FPC
900530 Housing 900531 Printed circuit board 900532 Speaker 900533 Microphone 900534 Transmitting/receiving circuit 900535 Signal processing circuit 900536 Input means 900537 Battery 900539 Housing 900600 Mobile phone 900601 Main body (A)
900602 Body (B)
900603 Housing 900604 Operation switches 900605 Microphone 900606 Speaker 900607 Circuit board 900608 Display panel (A)
900609 Display panel (B)
900610 Hinge 900711 Housing 900712 Support base 900713 Display section 900721 Main body 900722 Display section 900723 Image receiving section 900724 Operation keys 900725 External connection port 900726 Shutter 900731 Main body 900732 Housing 900733 Display section 900734 Keyboard 900735 External connection port 900736 Pointing device 900741 Main body 900742 Display section 900743 Switch 900744 Operation keys 900745 Infrared port 900751 Main body 900752 Housing 900753 Display section (A)
900754 Display section (B)
900755 section 900756 operation keys 900757 speaker section 900761 main body 900762 display section 900763 earphones 900764 support section 900771 housing 900772 display section 900773 speaker section 900774 operation keys 900775 storage medium insertion section 900781 main body 900782 display section 900783 operation keys 900784 speaker 900785 shutter 900786 image receiving section 900787 antenna 900810 housing 900811 display section 900812 remote control device 900813 speaker section 900901 display panel 900902 unit bath 901001 columnar body 901002 display panel 901101 Car body 901102 Display panel 901201 Door 901202 Display panel 901203 Glass window 901204 Ceiling 901301 Ceiling 901302 Display panel 901303 Hinge section

Claims (3)

A gate driver is provided.
the gate driver includes first to seventh transistors;
one of the source and the drain of the first transistor is always electrically connected to a clock signal line;
the other of the source and the drain of the first transistor is always electrically connected to an output signal line;
one of the source and the drain of the second transistor is always electrically connected to a first power supply line;
the other of the source and the drain of the second transistor is always electrically connected to the output signal line;
one of a source and a drain of the third transistor is always electrically connected to a first signal line;
the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor;
one of the source and the drain of the fourth transistor is always electrically connected to the second power supply line;
the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the sixth transistor;
a gate of the fourth transistor is always electrically connected to a gate of the first transistor;
one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor;
the other of the source and the drain of the fifth transistor is always electrically connected to a first wiring;
the gate of the fifth transistor is always electrically connected to the second signal line;
one of the source and the drain of the sixth transistor is always electrically connected to the second power supply line;
the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor;
one of the source and the drain of the seventh transistor is always electrically connected to the second power supply line;
the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor;
the gate of the seventh transistor is always electrically connected to the third signal line;
W (W is a channel width)/L (L is a channel length) of the fourth transistor is larger than W/L of the third transistor,
the first transistor has a function of outputting a potential of the clock signal line to the output signal line through a channel formation region of the first transistor;
the third transistor has a function of controlling a timing at which a potential of the first signal line is supplied to a gate of the sixth transistor through a channel formation region of the third transistor;
the first signal line has a function of supplying an H signal potential and an L signal potential to the gate driver;
when the second power supply line is in a conductive state with the gate of the sixth transistor via at least a channel formation region of the fourth transistor, a potential at which the sixth transistor is turned off is input to the gate of the sixth transistor via at least a channel formation region of the fourth transistor,
When a potential of a second wiring is input to a gate of the second transistor, a potential of the gate of the second transistor is controlled in accordance with the potential of the second wiring ;
The signal of the first signal line is not input to the first wiring,
A signal on the first signal line is not input to the second wiring,
A semiconductor device in which a signal on the third signal line is not input to the second wiring . A gate driver is provided.
the gate driver includes first to seventh transistors;
one of the source and the drain of the first transistor is always electrically connected to a clock signal line;
the other of the source and the drain of the first transistor is always electrically connected to an output signal line;
one of the source and the drain of the second transistor is always electrically connected to a first power supply line;
the other of the source and the drain of the second transistor is always electrically connected to the output signal line;
one of a source and a drain of the third transistor is always electrically connected to a first signal line;
the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor;
one of the source and the drain of the fourth transistor is always electrically connected to the second power supply line;
the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the sixth transistor;
a gate of the fourth transistor is always electrically connected to a gate of the first transistor;
one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor;
the other of the source and the drain of the fifth transistor is always electrically connected to a first wiring;
the gate of the fifth transistor is always electrically connected to the second signal line;
one of the source and the drain of the sixth transistor is always electrically connected to the second power supply line;
the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor;
one of the source and the drain of the seventh transistor is always electrically connected to the second power supply line;
the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor;
the gate of the seventh transistor is always electrically connected to the third signal line;
W (W is a channel width)/L (L is a channel length) of the fourth transistor is larger than W/L of the third transistor,
the first transistor has a function of outputting a potential of the clock signal line to the output signal line through a channel formation region of the first transistor;
the third transistor has a function of controlling a timing at which a potential of the first signal line is supplied to a gate of the sixth transistor through a channel formation region of the third transistor;
the first signal line has a function of supplying an H signal potential and an L signal potential to the gate driver;
when the second power supply line is in a conductive state with the gate of the sixth transistor via at least a channel formation region of the fourth transistor, a potential at which the sixth transistor is turned off is input to the gate of the sixth transistor via at least a channel formation region of the fourth transistor,
When a potential of a second wiring is input to a gate of the second transistor, a potential of the gate of the second transistor is controlled in accordance with the potential of the second wiring;
The signal of the first signal line is not input to the first wiring,
A signal on the first signal line is not input to the second wiring,
The signal of the third signal line is not input to the second wiring,
a first conductive layer having a region functioning as one of a source electrode or a drain electrode of the fourth transistor has a region functioning as one of a source electrode or a drain electrode of the sixth transistor and a region functioning as one of a source electrode or a drain electrode of the seventh transistor;
a second conductive layer having a region functioning as the other of a source electrode or a drain electrode of the third transistor has a region functioning as the other of a source electrode or a drain electrode of the fourth transistor,
a third conductive layer having a region functioning as one of a source electrode and a drain electrode of the fifth transistor, the third conductive layer having a region functioning as the other of a source electrode and a drain electrode of the seventh transistor; A semiconductor device according to claim 1 or 2, and a pixel,
the pixel includes an eighth transistor;
One of the source and the drain of the eighth transistor is always electrically connected to the pixel electrode;
the other of the source and the drain of the eighth transistor is always electrically connected to a video signal line;
the gate of the eighth transistor is always electrically connected to the output signal line;
one of a source and a drain of the eighth transistor has a region sandwiched by the other of the source and the drain of the eighth transistor in a plan view;
The pixel electrode has a plurality of cutout portions.

Images