JP2023057172A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with reduced parasitic capacitance.

SOLUTION: A semiconductor device includes a first insulating layer on a substrate, a first metal oxide layer on the first insulating layer, an oxide semiconductor layer on the first metal oxide layer, a second metal oxide layer on the oxide semiconductor layer, a gate insulating layer on the second metal oxide layer, a second insulating layer on the second metal oxide layer, and a gate electrode layer on the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes a first region to a third region. The first region includes a region overlapping with the gate electrode layer. The second region includes a region overlapping with the gate insulating layer or the second insulating layer. The second region is a region between the first region and the third region. The second region and the third region include a region containing an element N (N is phosphorus, argon, or xenon).

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2023,JPO&INPIT

Description

The present invention relates to an article, method or method of manufacture. Alternatively, the invention relates to a process, machine, manufacture or composition of matter. In particular, the present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, power storage devices, imaging devices, driving methods thereof, or manufacturing methods thereof. In particular, one embodiment of the present invention relates to a semiconductor device or a manufacturing method thereof.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are modes of a semiconductor device. Also, a storage device,
A display device and an electronic device may include a semiconductor device.

A technique for forming a transistor using a semiconductor film formed over a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor.

JP 2006-165528 A

2. Description of the Related Art Miniaturization of transistors is indispensable for manufacturing semiconductor devices in which transistors are highly integrated. However, miniaturization of transistors poses a problem of an increase in parasitic capacitance of the transistors.

For example, in transistor operation, if parasitic capacitance exists in the vicinity of the channel (for example, between the source electrode and the drain electrode), it takes time to charge the parasitic capacitance. for that reason,
Responsiveness of the transistor and, in turn, the responsiveness of the semiconductor device are deteriorated.

In addition, as the miniaturization of transistors progresses, the difficulty in controlling the shape of transistors increases. Variation caused by the manufacturing process greatly affects transistor characteristics and reliability.

Therefore, one object of one embodiment of the present invention is to reduce parasitic capacitance of a transistor. Another object is to provide a semiconductor device that can operate at high speed. or,
An object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to reduce variation in characteristics of a transistor or a semiconductor device due to a manufacturing process. Another object is to provide a semiconductor device including an oxide semiconductor layer with few oxygen vacancies.
Another object is to provide a semiconductor device that can be formed through a simple process. Another object is to provide a semiconductor device having a structure in which interface state density in the vicinity of an oxide semiconductor layer can be reduced. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device or the like. Another object is to provide a method for manufacturing the above semiconductor device.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the descriptions of the specification, drawings, claims, etc. is.

(1)
One embodiment of the present invention includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, and It has a second metal oxide layer, a gate insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer, and the oxide semiconductor layer has first to third regions. the first region and the second region have a region overlapping with the gate electrode layer, the second region is a region between the first region and the third region, and the second region overlaps the first region; has a region of lower resistance than the second region, the third region has a region of lower resistance than the second region,
The semiconductor device is characterized in that the second region and the third region have regions containing an element N (N is phosphorus, argon, or xenon).

(2)
Another aspect of the present invention includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, and the first insulating layer. a second metal oxide layer on the oxide semiconductor layer; a first gate insulating layer on the second metal oxide layer; and a gate electrode layer on the first gate insulating layer; the oxide semiconductor layer and the first gate insulating layer have regions facing side surfaces of the first metal oxide layer and the oxide semiconductor layer, and the oxide semiconductor layer has first to third regions;
The first region and the second region have a region that overlaps the gate electrode layer, the second region is a region between the first region and the third region, and the second region is greater than the first region. The third region has a region with a lower resistance than the second region, and the second region and the third region contain element N (N is phosphorus, argon, xenon ).

(3)
Another aspect of the present invention is the semiconductor device according to (2), further comprising a second gate insulating layer between the first gate insulating layer and the gate electrode layer.

(4)
In another aspect of the present invention, in any one of (1) to (3), the second region has a region with a higher concentration of element N than the first region, and the third region comprises The semiconductor device is characterized by having a region in which the concentration of the element N is higher than that of the second region.

(5)
In another aspect of the present invention, in any one of (1) to (4), the concentration of the element N in the third region is 1×10 ¹⁸ atoms/cm ³ or more and 1×10 ²² atoms/cm ³ or less. A semiconductor device, comprising:

(6)
One embodiment of the present invention includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, and a second metal oxide layer, a gate insulating layer on the second metal oxide layer, a second insulating layer on the second metal oxide layer, and a gate electrode layer on the gate insulating layer; The insulating layer has a region in contact with the side surface of the gate electrode layer, the second insulating layer has a region in contact with the gate insulating layer, the oxide semiconductor layer has first to third regions, and the first The region has a region that overlaps with the gate electrode layer, the second region has a region that overlaps with the gate insulating layer or the second insulating layer, and the second region is a region between the first region and the third region. and
The semiconductor device is characterized in that the second region and the third region have regions containing an element N (N is phosphorus, argon, or xenon).

(7)
Another aspect of the present invention is that in (6), the second region has a region with lower resistance than the first region, and the third region has a region with lower resistance than the second region A semiconductor device comprising:

(8)
Another aspect of the present invention is characterized in that in (6) or (7), the angle formed by the tangent line between the bottom surface of the substrate and the side surface of the gate electrode layer is 60 degrees or more and 85 degrees or less. semiconductor device.

(9)
In another aspect of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, and a first A stack of the metal oxide layer and the first oxide semiconductor layer is etched in an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer, and a second oxidation is performed. a semiconductor layer and a third insulating layer on the first insulating layer;
forming a metal oxide layer, forming a second insulating layer on the third metal oxide layer, planarizing the second insulating layer to form a third insulating layer, and forming a second mask; to form a fourth insulating layer having a groove reaching the third metal oxide layer by etching a portion of the third insulating layer using a fifth insulating layer on the fourth insulating layer and the third metal oxide layer forming an insulating layer and forming a first insulating layer on the fifth insulating layer;
forming a conductive layer and planarizing the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed to form a gate electrode layer and a sixth insulating layer; masking the gate electrode layer; A gate insulating layer is formed by etching the fourth insulating layer and the sixth insulating layer using as a mask, and ions are added to the second oxide semiconductor layer using the gate electrode layer as a mask to form a source region. and forming a drain region.

(10)
In another aspect of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, and a first A stack of the metal oxide layer and the first oxide semiconductor layer is etched in an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer, and a second oxidation is performed. a semiconductor layer and a third insulating layer on the first insulating layer;
forming a metal oxide layer, forming a first gate insulating layer on the third metal oxide layer, forming a second insulating layer on the first gate insulating layer, and planarizing the second insulating layer to form a third insulating layer, and etching a portion of the third insulating layer using a second mask to form the first
forming a fourth insulating layer having a trench reaching the gate insulating layer, forming a first conductive layer on the fourth insulating layer and the first gate insulating layer, and exposing the fourth insulating layer with respect to the first conductive layer A gate electrode layer is formed by performing a planarization process until the gate electrode layer is flattened, and the fourth insulating layer is etched using the gate electrode layer as a mask to provide a region where the first gate insulating layer is exposed. is used as a mask to etch the first insulating layer to form a second gate insulating layer, and the second oxide semiconductor layer is ion-doped to form a source region and a drain region; A method for manufacturing a semiconductor device characterized by the following.

(11)
In another aspect of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, and a first A stack of the metal oxide layer and the first oxide semiconductor layer is etched in an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer, and a second oxidation is performed. a semiconductor layer and a third insulating layer on the first insulating layer;
forming a metal oxide layer, forming a first gate insulating layer on the third metal oxide layer, forming a second insulating layer on the first gate insulating layer, and planarizing the second insulating layer to form a third insulating layer, and etching a portion of the third insulating layer using a second mask to form the first
forming a fourth insulating layer having a trench reaching the gate insulating layer; forming a fifth insulating layer over the fourth insulating layer and the first gate insulating layer; forming a first conductive layer over the fifth insulating layer; , the first conductive layer, and the fifth insulating layer are planarized until the fourth insulating layer is exposed, thereby forming a gate electrode layer and a sixth insulating layer, and using the gate electrode layer as a mask, a first insulating layer is formed. Etching the fourth insulating layer and the sixth insulating layer to provide a region exposing the first gate insulating layer, and adding ions to the second oxide semiconductor layer to form a source region and a drain region. A method for manufacturing a semiconductor device characterized by:

(12)
Another embodiment of the present invention is the method for manufacturing a semiconductor device according to any one of (9) to (11), wherein phosphorus, argon, or xenon is used for ion addition.

(13)
Another aspect of the present invention is that in any one of (9) to (12), the dose of ions in the ion addition is 1×10 ¹⁴ ions/cm ² or more and 5×10 ¹⁶ ions/cm
² or less.

(14)
In another aspect of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, and a first A second metal oxide layer and a second oxide semiconductor layer are formed by etching the stack of the metal oxide layer and the first oxide semiconductor layer into an island shape using the first mask. A third metal oxide layer is formed over the oxide semiconductor layer and the first insulating layer, a second insulating layer is formed over the third metal oxide layer, and planarization treatment is performed on the second insulating layer. forming a third insulating layer, and etching a portion of the third insulating layer using a second mask to form a fourth insulating layer having a groove reaching the third metal oxide layer; forming a fifth insulating layer over the fourth insulating layer and the third metal oxide layer; forming a first conductive layer over the fifth insulating layer; forming a fourth insulating layer over the first conductive layer and the fifth insulating layer; A planarization process is performed until the insulating layer is exposed to form a gate electrode layer and a sixth insulating layer, and the gate electrode layer is used as a mask to etch the fourth insulating layer and the sixth insulating layer. A gate insulating layer having a region in contact with the side surface of the gate electrode layer and a seventh insulating layer having a region in contact with the gate insulating layer are formed, and ions are added to the second oxide semiconductor layer to form a source region and a drain. Forming a region is a method for manufacturing a semiconductor device.

(15)
Another embodiment of the present invention is the method for manufacturing a semiconductor device in (14), wherein phosphorus, argon, or xenon is used for ion addition.

(16)
Another aspect of the present invention is that in (14) or (15), the dose of ions in the ion addition is 1×10 ¹⁴ ions/cm ² or more and 5×10 ¹⁶ ions/cm ² or less. A method for manufacturing a semiconductor device characterized by the following.

(17)
Another embodiment of the present invention is the region in any one of (14) to (16), in which an angle formed by a tangent to the side surface of the gate electrode layer and the bottom surface of the substrate is 60 degrees or more and 85 degrees or less. to have
A method for manufacturing a semiconductor device characterized by

(18)
Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (8), a housing, and a speaker.

Therefore, by using one embodiment of the present invention, parasitic capacitance of a transistor can be reduced, and a semiconductor device capable of high-speed operation can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, variations in characteristics of transistors or semiconductor devices due to manufacturing processes can be reduced. Alternatively, a semiconductor device including an oxide semiconductor layer with few oxygen vacancies can be provided. Alternatively, a semiconductor device that can be formed through a simple process can be provided. Alternatively, a semiconductor device having a structure in which the interface state density in the vicinity of the oxide semiconductor layer can be reduced can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. Alternatively, a method for manufacturing the above semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract effects other than these from the descriptions of the specification, drawings, claims, etc. is.

1A and 1B are a top view and a cross-sectional view illustrating a transistor; 1A and 1B are a cross-sectional view of a transistor and a schematic diagram illustrating a band diagram; The figure explaining the ALD film-forming principle. Schematic diagram of an ALD apparatus. 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 3A to 3C are top views and cross-sectional views illustrating a method for manufacturing a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 1A and 1B are a top view and a cross-sectional view illustrating a transistor; 1A and 1B illustrate structural analysis by XRD of a CAAC-OS and a single-crystal oxide semiconductor, and a selected-area electron diffraction pattern of the CAAC-OS; A cross-sectional TEM image of CAAC-OS, a planar TEM image, and its image analysis image. A diagram showing an electron diffraction pattern of an nc-OS and a cross-sectional TEM image of the nc-OS. Cross-sectional TEM image of a-like OS. FIG. 4 is a diagram showing changes in the crystal part of an In--Ga--Zn oxide due to electron irradiation. 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device; 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device; The top view which shows an imaging device. FIG. 2 is a plan view showing pixels of an imaging device; Sectional drawing which shows an imaging device. Sectional drawing which shows an imaging device. 1A and 1B are a circuit diagram and timing charts for explaining a semiconductor device of one embodiment of the present invention; 3A and 3B are graphs and circuit diagrams for explaining a semiconductor device of one embodiment of the present invention; 1A and 1B are a circuit diagram and timing charts for explaining a semiconductor device of one embodiment of the present invention; 1A and 1B are a circuit diagram and timing charts for explaining a semiconductor device of one embodiment of the present invention; FIG. 4 is a diagram for explaining a configuration example of an RF tag; FIG. 3 is a diagram for explaining a configuration example of a CPU; A circuit diagram of a memory element. 3A and 3B illustrate a configuration example of a display device and a circuit diagram of a pixel; 1A and 1B are a top view and a cross-sectional view of a liquid crystal display device; 1A and 1B are a top view and a cross-sectional view of a display device; The figure explaining a display module. FIG. 4 is a perspective view showing a cross-sectional structure of a package using a lead frame interposer and a configuration of a module; 1A and 1B are diagrams for explaining an electronic device; 1A and 1B are diagrams for explaining an electronic device; 1A and 1B are diagrams for explaining an electronic device; 1A and 1B are diagrams for explaining an electronic device; Sectional drawing of a measurement sample. Sheet resistance measurement result of the measurement sample after ion implantation. Sheet resistance measurement result of the measurement sample after ion implantation. Sheet resistance measurement result of the measurement sample after ion implantation. FIG. 4 is a diagram for explaining measurement results of XRD spectra of samples; 4A and 4B are TEM images of samples and diagrams for explaining electron beam diffraction patterns; FIG. The figure explaining the EDX mapping of a sample.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals may be used for the same parts or parts having similar functions in different drawings, and repeated description thereof may be omitted. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

For example, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y function This specification and the like disclose the case where X and Y are directly connected and the case where X and Y are directly connected. Therefore, it is assumed that the connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.

Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

An example of the case where X and Y are directly connected is an element (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display element) that enables electrical connection between X and Y. element, light-emitting element, load, etc.) is not connected between X and Y, and an element that enables electrical connection between X and Y (e.g., switch, transistor, capacitive element, inductor , resistance element, diode, display element, light emitting element, load, etc.).

An example of the case where X and Y are electrically connected is an element that enables electrical connection between X and Y (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display elements, light emitting elements, loads, etc.) can be connected between X and Y. Note that the switch has a function of being controlled to be turned on and off. In other words, the switch has a function of controlling whether it is in a conducting state (on state) or a non-conducting state (off state) to allow current to flow. Alternatively, the switch has a function of selecting and switching a path through which current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (eg, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (booster circuit, step-down circuit, etc.), level shifter circuit that changes the potential level of a signal, etc.)
, voltage source, current source, switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc. ) can be connected between X and Y one or more times. As an example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected. do. Note that X and Y
are functionally connected, X and Y are directly connected, and X and Y
and are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, it means that X and Y are electrically connected (that is, if X and Y are electrically connected and when X and Y are functionally connected (that is, when X and Y are functionally connected with another circuit interposed between them) ) and the case where X and Y are directly connected (that is, the case where X and Y are connected without another element or another circuit between them). shall be disclosed in a document, etc. In other words, when it is explicitly stated that it is electrically connected, the same content as when it is explicitly stated that it is simply connected is disclosed in this specification, etc. It shall be

Note that, for example, the source (or the first terminal, etc.) of the transistor is electrically connected to X via (or not via) Z1, and the drain (or the second terminal, etc.) of the transistor is connected to Z
2 (or not), or the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and another part of Z1. One part is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to one part of Z2, and another part of Z2 is directly connected to Y. If so, it can be expressed as follows.

For example, "X and Y and source (or first terminal, etc.) and drain (or second
terminals, etc.) are electrically connected to each other in the following order: X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), Y It is ” can be expressed. Or, "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X is the source of the transistor ( or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. Or, "X is electrically connected to Y through the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X is the source (or first terminal, etc.) of the transistor; terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. Using the same expression method as these examples, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished by defining the order of connection in the circuit configuration. Alternatively, the technical scope can be determined.

Alternatively, as another expression method, for example, "the source of the transistor (or the first terminal, etc.)
is electrically connected to X via at least a first connection path, the first connection path does not have a second connection path, and the second connection path includes a transistor a path between a source (or a first terminal, etc.) of a transistor and a drain (or a second terminal, etc.) of a transistor via Z1; The drain (or second terminal, etc.) of the transistor is electrically connected to Y via at least a third connection path, the third connection path having the second connection path. First, the third connection path is a path via Z2. ” can be expressed. or "the source (or first terminal, etc.) of the transistor is electrically connected to X via Z1 by at least a first connection path, said first connection path being connected to a second connection path does not have
The second connection path has a connection path through a transistor, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y via Z2 by at least a third connection path. and the third connection path does not have the second connection path. ” can be expressed. or "the source (or first terminal, etc.) of a transistor is electrically connected to X, via Z1, by at least a first electrical path, said first electrical path being connected to a second having no electrical path, the second electrical path being an electrical path from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.); The drain (or second terminal, etc.) of the transistor is connected to at least a third
is electrically connected to Y through Z2 by an electrical path of, the third electrical path does not have a fourth electrical path, and the fourth electrical path is An electrical path from the drain (or second terminal, etc.) of a transistor to the source (or first terminal, etc.) of a transistor. ” can be expressed. Using the same expression method as these examples, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished by defining the connection path in the circuit configuration. , can determine the technical scope.

In addition, these expression methods are examples, and are not limited to these expression methods. where X
, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films,
layer, etc.).

Even if the circuit diagram shows independent components electrically connected to each other, if one component has the functions of multiple components There is also For example, when a part of the wiring also functions as an electrode, one conductive film has both the function of the wiring and the function of the electrode. Therefore, the term "electrically connected" in this specification includes cases where one conductive film functions as a plurality of constituent elements.

<Supplementary remarks regarding the description explaining the drawings>

In this specification, terms such as "above" and "below" are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. In addition, the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately rephrased according to the situation.

In addition, the terms "upper" and "lower" do not limit the positional relationship of the components to being directly above or directly below and in direct contact with each other. For example, for the expression "electrode B on insulating layer A",
It is not necessary for the electrode B to be formed directly on the insulating layer A, and other components between the insulating layer A and the electrode B are not excluded.

As used herein, the term “parallel” refers to a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, the case of −5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Also, in this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

In the drawings, sizes, layer thicknesses, and regions are shown as arbitrary sizes for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values shown in the drawings.

In addition, in the drawings, in the top view (also called a plan view or layout view) or a perspective view,
Some components may be omitted for clarity of the drawings.

Moreover, "the same" may have the same area or may have the same shape. In addition, it is assumed that the shape may not be exactly the same due to the manufacturing process, so even if the shape is substantially the same, it can be rephrased as the same.

<Supplementary notes on rephrasable descriptions>

In this specification and the like, when describing the connection relationship of a transistor, one of a source and a drain is referred to as “one of the source or the drain” (or the first electrode or the first terminal). The other is described as "the other of source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of a transistor can be appropriately changed to a source (drain) terminal, a source (drain) electrode, or the like, depending on the situation.

In addition, the terms “electrode” and “wiring” in this specification and the like do not functionally limit these constituent elements. For example, "electrode" may be used as part of "wiring",
The opposite is also true. Furthermore, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current flows through the drain, the channel region, and the source. is possible.

Here, since the source and the drain change depending on the structure of the transistor, operating conditions, or the like, it is difficult to define which is the source or the drain. Therefore, a portion functioning as a source and a portion functioning as a drain are not called a source or a drain,
One of the source and the drain may be referred to as the first electrode, and the other of the source and the drain may be referred to as the second electrode.

It should be noted that the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion of constituent elements, and are not numerically limited. do.

In addition, in this specification and the like, the substrate of the display panel is, for example, an FPC (Flexible Prix
circuit) or TCP (Tape Carrier Packa
ge), etc., or COG (Chip On Glass) on the substrate
A device in which an IC (integrated circuit) is directly mounted depending on the method is sometimes called a display device.

In addition, the terms "film" and "layer" can be interchanged depending on the case or situation. For example, it may be possible to change the term "conductive layer" to the term "conductive film." Or, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

<Supplementary notes on definitions of terms>
Definitions of terms used in this specification and the like will be described below.

In this specification, when the term "trench" or "groove" is used, it means a thin band-shaped depression.

<About connection>

In this specification, "A and B are connected" includes not only direct connection between A and B, but also electrical connection. Here, "A and B are electrically connected" means that when there is an object having some kind of electrical action between A and B, an electric signal can be exchanged between A and B. What to say.

It should be noted that the content (may be part of the content) described in one embodiment may be another content (may be part of the content) described in that embodiment, and/or one or more The contents described in another embodiment (or part of the contents) can be applied, combined, or replaced.

In addition, the content described in the embodiment means the content described using various drawings or the content described using sentences described in the specification in each embodiment.

It should be noted that the figure (or part of it) described in one embodiment may be another part of the figure,
By combining with other figures (may be part of) described in the embodiment and/or figures (may be part) described in one or more other embodiments, more Figures can be constructed.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

<Structure of Transistor 10>
1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 10 of one embodiment of the present invention. FIG. 1A is a top view, FIG. 1B is a cross section between the dashed-dotted line A1 and A2 shown in FIG. 1A, and FIG. 1C is a cross section between A3 and A4 shown in FIG. It is a diagram. In addition, Fig. 1
In (A), some elements are enlarged, reduced, or omitted for clarity of illustration. Also, the direction of the dashed line A1-A2 may be called the channel length direction, and the direction of the dashed line A3-A4 may be called the channel width direction.

The transistor 10 includes a substrate 100, an insulating layer 110, a metal oxide layer 121, an oxide semiconductor layer 122, a metal oxide layer 123, a low resistance region 125, a gate insulating layer 150, a gate electrode layer 160, It has an insulating layer 180 , a conductive layer 190 , and a conductive layer 195 .

An insulating layer 110 is provided on the substrate 100 .

A metal oxide layer 121 is provided on the insulating layer 110 .

The oxide semiconductor layer 122 is provided over the metal oxide layer 121 . Moreover, the oxide semiconductor layer 1
22 has a low resistance region 125 . The low-resistance region contains at least one of hydrogen, nitrogen, helium, neon, argon, krypton, xenon, boron, phosphorus, tungsten, and aluminum. The low resistance region 125 functions as a source or drain.

The metal oxide layer 123 is provided over the oxide semiconductor layer 122 .

A gate insulating layer 150 is provided on the metal oxide layer 123 .

A gate electrode layer 160 is provided on the gate insulating layer 150 . Note that the gate electrode layer 160
, the gate insulating layer 150, the metal oxide layer 123, and the oxide semiconductor layer 122 overlap with each other.

An insulating layer 180 is provided on the insulating layer 110 .

A conductive layer 190 is provided on the low resistance region 125 . The conductive layer 190 and the low resistance region 125 have regions that are electrically connected.

A conductive layer 195 is provided over the conductive layer 190 .

The low-resistance region 125 can also be partly provided under the gate electrode layer. Gate electrode layer 160
, the low resistance region 125 overlapping the gate electrode layer 160 and partly diffused with ions is the second region, and the low resistance region not overlapping the gate electrode layer 160 is the third region. , the second region has a region with a lower resistance than the first region, and the third region is
It can be said to have a region with a lower resistance than the second region. The resistance is obtained by measuring the resistance value (for example, sheet resistance measurement) and can be controlled by the impurity concentration. Further, in the third region, the concentration of the above element is 1×10 ¹⁸ atoms/cm ³ or more.
It has a region of ×10 ²² atoms/cm ³ or less.

<Regarding the metal oxide layer>
Note that the metal oxide layer (for example, the metal oxide layer 121 and the metal oxide layer 123) basically has an insulating property, and when the gate electric field or the drain electric field becomes strong, current flows near the interface with the semiconductor. A layer in which liquid can flow.

With the above structure, the parasitic capacitance between the gate and the source or between the gate and the drain can be reduced. As a result, the transistor 10 can operate at high speed, for example, the cutoff frequency characteristic of the transistor 10 is improved.

In addition, since the gate, source, and drain of the transistor 10 can be formed by self-alignment, alignment difficulty is reduced. Accordingly, a fine transistor can be easily manufactured.

As shown in the A3-A4 cross-sectional view of FIG. 1C, the transistor 10 has a gate electrode layer 160, a metal oxide layer 121, an oxide semiconductor layer 122, and a metal oxide layer 121 with a gate insulating layer 150 interposed therebetween in the channel width direction. It has a region facing the side surface of the oxide layer 123 . That is, when a voltage is applied to the gate electrode layer 160, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of a transistor in which the semiconductor is surrounded by the electric field of the gate electrode layer is called a surrounded channel
It is called an el (s-channel) structure.

Here, when the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are combined to form an oxide, a channel is formed in the entire oxide (bulk) in the transistor 10 in an on state. Therefore, the on current increases. On the other hand, in the off state, the channel region formed in the wide bandgap oxide semiconductor layer 122 acts as a potential barrier.
The off current can be further reduced.

<About channel length>
Note that the channel length of a transistor means, for example, in a top view of a transistor,
The source (source region or source electrode) and the drain (drain region or drain electrode). Note that the channel length does not always have the same value in all regions of one transistor. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the region where the channel is formed.

<About channel width>
The channel width refers to, for example, the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap. Note that the channel width does not always have the same value in all regions of one transistor. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this document:
The channel width is any one value, maximum value, minimum value or average value in the area where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width ) and may be different. for example,
In a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and the effect thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width if the shape of the semiconductor is not accurately known.

<About SCW>
Therefore, in this specification, in a top view of a transistor, an apparent channel width in a region where a semiconductor and a gate electrode overlap is referred to as a "surrounding channel width (SCW)."
ded Channel Width)”. In addition, in this specification, simply referring to the channel width may refer to the enclosing channel width or the apparent channel width. Alternatively, in this specification, simply referring to the channel width may refer to the effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosing channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. can.

Note that when the field-effect mobility of a transistor, the current value per channel width, and the like are calculated, they are sometimes calculated using the enclosed channel width. In that case, it may take a different value than when calculating using the effective channel width.

<Characteristics improvement in miniaturization>
Miniaturization of transistors is essential for high integration of semiconductor devices. On the other hand, it is known that miniaturization of transistors deteriorates the electrical characteristics of the transistors, and when the channel width is reduced, the on current decreases.

For example, in the transistor of one embodiment of the present invention illustrated in FIGS. It has a configuration in which the insulating layer does not contact. Therefore, carrier scattering at the interface between the channel formation region and the gate insulating layer can be suppressed, and the on-state current of the transistor can be increased.

Further, in the transistor of one embodiment of the present invention, the gate electrode layer 160 is formed so as to electrically surround the oxide semiconductor layer 122 serving as a channel in the channel width direction; A lateral gate electric field is applied in addition to the vertical gate electric field. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on current can be further increased.

Further, in the transistor of one embodiment of the present invention, formation of the metal oxide layer 123 over the metal oxide layer 121 and the oxide semiconductor layer 122 makes it difficult to form an interface state, and the oxide semiconductor layer 122 is positioned between the metal oxide layer 121 and the metal oxide layer 123, the entry of impurities from above and below can be suppressed. Therefore, it is possible to stabilize the threshold voltage and reduce the S value (sub-threshold value) in addition to the above-described improvement in the ON current of the transistor. Therefore, Icut (current when gate voltage VG is 0 V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, long-term reliability of the semiconductor device can be improved.

In the transistor of one embodiment of the present invention, the gate electrode layer 160 is formed so as to electrically surround the oxide semiconductor layer 122 serving as a channel in the channel width direction; A lateral gate electric field is applied in addition to the vertical gate electric field. That is, the gate electric field is applied to the entire oxide semiconductor layer 122, the influence of the drain electric field can be suppressed, and the short channel effect can be greatly suppressed. Therefore, even when miniaturized, good characteristics can be obtained.

In addition, the transistor of one embodiment of the present invention has high source-drain breakdown voltage characteristics and stable electric characteristics in various temperature environments because the oxide semiconductor layer 122 serving as a channel includes a wide bandgap material. be able to.

Note that although an example in which an oxide semiconductor layer or the like is used in a channel or the like is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, the channel and its vicinity, the source region, the drain region, etc. may be treated with silicon (including strained silicon), germanium, silicon germanium, silicon carbide,
It may be formed of materials including gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, and the like.

<Each configuration of the transistor>
Each structure of the transistor of this embodiment is described below.

<<Substrate 100>>
For the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Further, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, SOI (Silicon
(N On Insulator) substrates and the like can also be used, and those having semiconductor elements provided on these substrates may also be used. Substrate 100 is not limited to a mere support material,
It may be a substrate on which devices such as other transistors are formed. In this case, one or more of the gate, source, and drain of the transistor may be electrically connected to the other device.

Alternatively, a flexible substrate may be used as the substrate 100 . Note that as a method for providing a transistor over a flexible substrate, there is also a method in which a transistor is manufactured over a non-flexible substrate, separated, and transferred to the substrate 100 which is a flexible substrate. In that case, a peeling layer is preferably provided between the non-flexible substrate and the transistor. Note that as the substrate 100, a sheet, a film, a foil, or the like in which fibers are woven may be used. Also, the substrate 100 may have stretchability. Further, the substrate 100 may have the property of returning to its original shape when bending or pulling is stopped. Alternatively, it may have the property of not returning to its original shape. The thickness of the substrate 100 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. By thinning the substrate 100, the weight of the semiconductor device can be reduced. In addition, by making the substrate 100 thin, even when glass or the like is used, the substrate 100 may have stretchability, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact or the like applied to the semiconductor device on the substrate 100 due to dropping or the like can be mitigated. That is, a durable semiconductor device can be provided.

As the substrate 100 which is a flexible substrate, for example, metal, alloy, resin, glass, or fibers thereof can be used. The substrate 100, which is a flexible substrate, preferably has a lower coefficient of linear expansion because deformation due to the environment is suppressed. As the substrate 100, which is a flexible substrate,
For example, the coefficient of linear expansion is 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵
/K or less may be used. Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE), and the like. In particular, aramid is suitable for the substrate 100, which is a flexible substrate, because it has a low coefficient of linear expansion.

<<insulating layer 110>>
The insulating layer 110 includes silicon (Si), nitrogen (N), oxygen (O), fluorine (F), hydrogen (H
), aluminum (Al), gallium (Ga), germanium (Ge), yttrium (
Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf
) and tantalum (Ta).

The insulating layer 110 has a role of preventing impurities from diffusing from the substrate 100, and can also have a role of supplying oxygen to the oxide semiconductor layer 122 (the metal oxide layer 121 and the metal oxide layer 123). Therefore, the insulating layer 110 is preferably an insulating film containing oxygen, more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, a film having an oxygen release amount of 1.0×10 ¹⁹ atoms/cm ³ or more in terms of oxygen atoms by the TDS method is used. The surface temperature of the film during the TDS analysis was 100° C. or more and 700° C.
or less, or a range of 100° C. or higher and 500° C. or lower. Also, as described above, the substrate 10
If 0 is a substrate on which other devices are formed, the insulating layer 110 also functions as an interlayer insulating film. In that case, CMP (Chemical Mech
It is preferable to perform a planarization treatment by an anal polishing method or the like.

Further, when fluorine is contained in the insulating layer 110 , fluorine gasified from the insulating layer can stabilize oxygen vacancies in the oxide semiconductor layer 122 .

<<Metal Oxide Layer 121, Oxide Semiconductor Layer 122, Metal Oxide Layer 123>>
The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are made of In or Zn.
is an oxide semiconductor film containing In—Ga oxide, In—Zn oxide, In
-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y,
Sn, Zr, La, Ce, Mg, Hf, or Nd).

An oxide that can be used for the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 preferably contains at least indium (In) or zinc (Zn). Alternatively, it preferably contains both In and Zn. In addition, a stabilizer is preferably included together with the oxide semiconductor layer in order to reduce variations in electrical characteristics of the transistor including the oxide semiconductor layer.

Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr). Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (P
r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (
Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

The contents of indium, gallium, and the like in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 can be determined by time-of-flight secondary ion mass spectrometry (TOF-SIMS) or X-ray electron spectroscopy ( XPS) and ICP mass spectrometry (ICP-MS).

Since the oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, the off-state current of the transistor 10 can be reduced.

The thickness of the oxide semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 nm or less.
0 nm or less, more preferably 3 nm or more and 50 nm or less.

Note that the thickness of the oxide semiconductor layer 122 may be thinner, the same, or thicker than at least the metal oxide layer 121 . For example, when the oxide semiconductor layer 122 is thickened, on-state current of the transistor can be increased. In addition, the metal oxide layer 121 may have a thickness such that the effect of suppressing the generation of interface states in the oxide semiconductor layer 122 is not lost. For example, the thickness of the oxide semiconductor layer 122 can be more than 1 time, 2 times or more, 4 times or more, or 6 times or more the thickness of the metal oxide layer 121 . Further, in the case where it is not necessary to increase the on-state current of the transistor, the thickness of the metal oxide layer 121 may be greater than or equal to the thickness of the oxide semiconductor layer 122 . For example, insulating layer 1
10, or when oxygen is added to the insulating layer 180, the oxide semiconductor layer 1
22 can be reduced, and the electrical characteristics of the semiconductor device can be stabilized.

When the compositions of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are different, the interface is observed by a scanning transmission electron microscope (STEM).
can be observed using a mission Electron Microscope).

Further, the oxide semiconductor layer 122 preferably contains more indium than the metal oxide layers 121 and 123 . In the oxide semiconductor layer, s orbitals of heavy metals mainly contribute to carrier conduction. The mobility is higher than that of oxides in which In is equal to or less than M. Therefore, by using an oxide containing a large amount of indium for the oxide semiconductor layer 122, a transistor with high field-effect mobility can be realized.

Further, the oxide semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn
, Zr, La, Ce, Mg, Hf, or Nd), the atomic ratio of the metal elements in the target used for forming the oxide semiconductor layer 122 by a sputtering method is In:M
:Zn=x2:y2:z2, x2/(x2+y2+z2) is preferably 1/3 or more. The metal atomic ratio of the oxide semiconductor layer 122 also has the same composition. Further, x2/y2 is 1/3 or more and 6 or less, further 1 or more and 6 or less, and z2/y2 is
It is preferably ⅓ or more and 6 or less, more preferably 1 or more and 6 or less. As a result, CAAC-OS (C Axis Aligned Crystal) is used as the oxide semiconductor layer 122.
(Ine Oxide Semiconductor) film is easily formed. Typical examples of atomic number ratios of metal elements in the target are In:M:Zn=1:1:1, In:M:Z
n=1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2, 4:
2:3, 4:2:4.1, and so on.

Al, Ti, Ga, Y, Zr, Sn,
Having La, Ce, Mg, Hf, or Nd at a higher atomic ratio than In may have the following effects. (1) Increase the energy gap between the metal oxide layer 121 and the metal oxide layer 123 . (2) Reduce the electron affinity of the metal oxide layer 121 and the metal oxide layer 123 . (3) Shield impurities from the outside. (4) The insulating property is higher than that of the oxide semiconductor layer 122 . (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, H
Since f or Nd is a metal element having a strong bonding force with oxygen, Al, Ti, Ga, Y,
By having Zr, Sn, La, Ce, Mg, Hf, or Nd at a higher atomic ratio than In, oxygen vacancies are less likely to occur.

The metal oxide layer 121 and the metal oxide layer 123 are oxides containing one or more elements that form the oxide semiconductor layer 122 . Therefore, interfacial scattering is less likely to occur at the interfaces between the oxide semiconductor layer 122 and the metal oxide layers 121 and 123 . Therefore, since the movement of carriers is not hindered at the interface, the field effect mobility of the transistor 10 is increased.

The metal oxide layer 121 and the metal oxide layer 123 are typically made of In—Ga oxide, In—Z
n-oxide, In--Mg oxide, Ga--Zn oxide, Zn--Mg oxide, In--M--Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd)
and the energy level of the bottom of the conduction band is closer to the vacuum level than the oxide semiconductor layer 122, typically the energy level of the bottom of the conduction band of the metal oxide layer 121 and the metal oxide layer 123. , the difference from the energy level at the bottom of the conduction band of the oxide semiconductor layer 122 is 0.05 eV or more,
0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinities of the metal oxide layers 121 and 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05.
eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the electron affinity indicates the difference between the vacuum level and the energy level at the bottom of the conduction band.

In addition, the metal oxide layer 121 and the metal oxide layer 123 are In-M-Zn oxide (M is Al, T
i, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), the metal oxide layer 121 and the metal oxide layer The atomic ratio of M (Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd) contained in 123 is high, and the element represented by M is stronger than oxygen than indium. Since it bonds, it has a function of suppressing the occurrence of oxygen vacancies in the metal oxide layers 121 and 123 . That is, the metal oxide layer 121 and the metal oxide layer 123 are the oxide semiconductor layer 122
Oxygen vacancies are less likely to occur in the oxide semiconductor film. The metal atomic ratios of the metal oxide layer 121 and the metal oxide layer 123 also have the same composition.

Further, the metal oxide layer 121 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn,
Zr, La, Ce, Mg, Hf, or Nd), the atomic ratio of the metal elements in the target used for forming the metal oxide layer 121 is In:M:Zn=x1:y1:z
When 1, x1/y1<z1/y1, and z1/y1 is preferably 1/10 or more and 6 or less, more preferably 0.2 or more and 3 or less.

Further, since the metal oxide layer 121 and the metal oxide layer 123 have higher insulating properties than the oxide semiconductor layer 122, they can have a function similar to that of the gate insulating layer.

Also, the metal oxide layer 123 can be replaced with a metal oxide such as aluminum oxide, gallium oxide, hafnium oxide, silicon oxide, germanium oxide, or zirconia oxide, and the metal oxide layer 123 can be replaced with the metal oxide layer 123 . can also have

In addition, the metal oxide layer 123 may have a thickness such that the effect of suppressing the generation of interface states in the oxide semiconductor layer 122 is not lost. For example, the thickness may be equal to or less than that of the metal oxide layer 121 . If the metal oxide layer 123 is thick, the electric field generated by the gate electrode layer 160 might not easily reach the oxide semiconductor layer 122; therefore, the metal oxide layer 123 is preferably formed thin. For example, the metal oxide layer 123 may be thinner than the oxide semiconductor layer 122 . Note that the thickness of the metal oxide layer 123 is not limited to this, and the thickness of the gate insulating layer 150
It may be appropriately set according to the voltage for driving the transistor in consideration of the withstand voltage of the transistor.

For example, the thickness of the metal oxide layer 123 is 1 nm or more and 20 nm or less, or 3 nm or more and 10 nm or less.
nm or less is preferable.

In addition, the metal oxide layer 121 and the metal oxide layer 123 are In-M-Zn oxide (M is Al, T
i, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), the number of atoms of the metal element in the target used for forming the metal oxide layer 121 and the metal oxide layer 123 is When the ratio is In:M:Zn=x3:y3:z3, x3/y3<x2/y2, and z3/y3 is preferably 1/3 or more and 6 or less, more preferably 1 or more and 6 or less. . Note that by setting z3/y3 to be 1 or more and 6 or less, the metal oxide layer 121 and the metal oxide layer 123
As a result, the CAAC-OS film is easily formed. Typical examples of the atomic number ratios of the metal elements in the target are In:M:Zn=1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:
4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1:5:6,
1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6 and the like. Note that the atomic ratio is not limited to these, and an appropriate atomic ratio may be used according to the required semiconductor characteristics.

Further, the atomic ratios of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may each include a variation of plus or minus 40% in the above atomic ratio as an error.

For example, in the case of forming an oxide semiconductor film to be the oxide semiconductor layer 122, a target used for the deposition has an atomic ratio of metal elements of In:Ga:Zn=1:1:1. The atomic ratio of the metal elements in the oxide semiconductor film is In:Ga:Zn=1:1:0.6.
and the atomic number ratio of zinc may be the same or lower. Therefore, when an atomic number ratio is described, the vicinity of the atomic number ratio is included.

<About hydrogen concentration>
Hydrogen contained in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 reacts with oxygen bonded to the metal atom to become water, and the lattice from which oxygen is released (or the hydrogen from which oxygen is released). separated part) to form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, are generated in some cases. In addition, part of hydrogen may be combined with oxygen that is combined with a metal atom to generate an electron that is a carrier. Therefore, a transistor including an oxide semiconductor layer containing hydrogen is likely to have normally-on characteristics.

Therefore, it is preferable that oxygen vacancies and hydrogen be reduced as much as possible in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the interface between them. For example, secondary ion mass spectrometry (SIMS) is performed on the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their interfaces.
The hydrogen concentration obtained by mass spectrometry is 1×10 ¹⁶ at
oms/cm ³ or more and 2×10 ²⁰ atoms/cm ^{3 or} less, preferably 1×10 ¹⁶ at
oms/cm ³ or more and 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁶
atoms/cm ³ or more and 1×10 ¹⁹ atoms/cm ³ or less, more preferably 1×1
It is desirable to be 0 ¹⁶ atoms/cm ³ or more and 5×10 ¹⁸ atoms/cm ³ or less. As a result, the transistor 10 can have electrical characteristics with a positive threshold voltage (also referred to as normally-off characteristics).

<Concentration of carbon and silicon>
In addition, when silicon or carbon, which is one of Group 14 elements, is contained in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their interfaces, the metal oxide layer 121 is oxidized. Oxygen vacancies increase in the semiconductor layer 122 and the metal oxide layer 123, and an n-type region is formed. Therefore, the metal oxide layer 121 and the oxide semiconductor layer 122
, the metal oxide layer 123, and the silicon and carbon concentrations at their respective interfaces are desirably reduced. For example, the concentration of silicon or carbon obtained by SIMS in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the interface between them is 1×10 ¹⁶ atoms/cm ³ or more and 1×10 ¹⁹ atoms/cm 3 or more. /cm ³ or less, preferably 1×10 ¹⁶ atoms/cm ³ or more and 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁶ atoms/cm ³ or more and 2×10 ¹⁸ atoms/cm ³ or less. is desirable. As a result, the transistor 10 has electrical characteristics such that the threshold voltage is positive.

<Concentration of Alkali Metals and Alkaline Earth Metals>
Further, when an alkali metal and an alkaline earth metal are bonded to an oxide semiconductor, carriers might be generated, which might increase the off-state current of the transistor. Therefore, it is preferable to reduce the concentrations of alkali metals or alkaline earth metals in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their interfaces. For example, in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their interfaces, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms
s/cm ³ or less is desirable. Thus, the transistor 10 can have electrical characteristics with a positive threshold voltage.

<About nitrogen concentration>
Further, when nitrogen is contained in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the interface between them, electrons as carriers are generated, the carrier density increases,
An n-type region is formed. As a result, a transistor including an oxide semiconductor layer containing nitrogen tends to have normally-on characteristics. Therefore, nitrogen is preferably reduced as much as possible in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their interfaces. For example, the nitrogen concentration obtained by SIMS in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces is
1×10 ¹⁵ atoms/cm ³ or more and 5×10 ¹⁹ atoms/cm ³ or less, preferably 1×10 ¹⁵ atoms/cm ³ or more and 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁵ atoms/cm It is preferably ³ or more and 1×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁵ atoms/cm ³ or more and 5×10 ¹⁷ atoms/cm ³ or less. This allows the transistor 10 to have electrical characteristics such that the threshold voltage is positive.

However, this is not the case when the oxide semiconductor layer 122 contains excess zinc. Excess zinc might form oxygen vacancies in the oxide semiconductor layer 122 . Therefore, when the oxide semiconductor layer 122 contains excess zinc, oxygen vacancies caused by the excess zinc can be inactivated by including 0.001 to 3 atomic % of nitrogen in some cases. Therefore, the nitrogen eliminates the variation in characteristics of the transistor, so that the reliability can be improved.

<Regarding carrier density>
By reducing impurities in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, the carrier densities of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are reduced. be able to. Therefore, each of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 has a carrier density of 1×10 ¹⁵ /cm ³ or less, preferably 1×10 ¹³ /cm ³ or less, more preferably 1×10 13 /cm 3 or less. is less than 8×10 ¹¹ pieces/cm ³ ,
More preferably less than 1×10 ¹¹ pieces/cm ³ , most preferably less than 1×10 ¹⁰ pieces/cm ³ , and 1×10 ⁻⁹ pieces/cm ³ or more.

By using oxide semiconductor layers with a low impurity concentration and a low defect level density as the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, a transistor with even better electrical characteristics is manufactured. can do. Here, a low impurity concentration and a low defect level density (few oxygen vacancies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor layer has few carrier generation sources; thus, carrier density can be reduced in some cases. Therefore, a transistor whose channel region is formed in the oxide semiconductor layer tends to have electrical characteristics such that the threshold voltage is positive. Further, since a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor layer has a low defect level density, the trap level density may also be low. In addition, a transistor including a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor layer has significantly low off-state current.
When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V,
It is possible to obtain characteristics that the off current is below the measurement limit of the semiconductor parameter analyzer, that is, below 1×10 ⁻¹³ A. Therefore, a transistor in which a channel region is formed in the oxide semiconductor layer may be a highly reliable transistor with small variations in electrical characteristics.

Further, the off-state current of the transistor including the highly purified oxide semiconductor layer for the channel formation region as described above is extremely low. For example, the voltage between the source and drain is 0.1V, 5
V or about 10 V, the off current normalized by the channel width of the transistor can be reduced to several yA/μm to several zA/μm.

The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have non-single-crystal structures, for example. Non-single-crystalline structures include, for example, CAAC-OS, polycrystalline structures, microcrystalline structures, or amorphous structures, which are described below. Among non-single-crystal structures, the amorphous structure has the highest defect level density, and the CAAC-OS has the lowest defect level density.

The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have microcrystalline structures, for example. The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 having a microcrystalline structure contain microcrystals with a size of 1 nm or more and less than 10 nm, for example. Alternatively, an oxide film and an oxide semiconductor film with a microcrystalline structure are, for example, 1 nm or more in an amorphous phase.
It has a mixed phase structure with a crystal part of less than 0 nm.

The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may be amorphous structures, for example. The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 with an amorphous structure have, for example, disordered atomic arrangement and no crystalline component. or,
An oxide film and an oxide semiconductor film with an amorphous structure, for example, have a completely amorphous structure and do not have a crystal part.

Note that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are CA
It may be a mixed film having two or more structural regions of AC-OS, microcrystalline structure, and amorphous structure. As a mixed film, for example, an amorphous structure region, a microcrystalline structure region, and CAAC
-OS regions. Alternatively, as a mixed film, for example, there is a laminated structure of an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region.

Note that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have single crystal structures, for example.

An oxide film in which oxygen vacancies are less likely to occur than the oxide semiconductor layer 122 is used as the oxide semiconductor layer 122 .
, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, since the oxide semiconductor layer 122 is in contact with the metal oxide layer 121 and the metal oxide layer 123 each including one or more metal elements included in the oxide semiconductor layer 122, the metal oxide layer 12
1 and the oxide semiconductor layer 122 and the interface state density at the interface between the oxide semiconductor layer 122 and the metal oxide layer 123 are extremely low. For example, metal oxide layer 121, metal oxide layer 12
3. After oxygen is added to the gate insulating layer 150 , the insulating layer 110 , and the insulating layer 180 , heat treatment is performed so that the oxygen passes through the metal oxide layers 121 and 123 to the oxide semiconductor layer 122 . At this time, oxygen is less likely to be trapped in the interface state, and oxygen contained in the metal oxide layer 121 or the metal oxide layer 123 is efficiently transferred to the oxide semiconductor layer 1 .
22 can be moved. As a result, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. Further, since oxygen is added to the metal oxide layer 121 or the metal oxide layer 123, oxygen vacancies in the metal oxide layer 121 or the metal oxide layer 123 can be reduced. That is, at least the localized level density of the oxide semiconductor layer 122 can be reduced.

Further, when the oxide semiconductor layer 122 is in contact with an insulating film having different constituent elements (eg, a gate insulating layer containing a silicon oxide film), an interface level is formed, and the interface level forms a channel in some cases. . In such a case, a second transistor with a different threshold voltage appears, and the apparent threshold voltage of the transistor may fluctuate. However, the metal oxide layer 121 and the metal oxide layer 12 containing one or more metal elements constituting the oxide semiconductor layer 122
3 is in contact with the oxide semiconductor layer 122 , interface states are less likely to form at the interface between the metal oxide layer 121 and the oxide semiconductor layer 122 and at the interface between the metal oxide layer 123 and the oxide semiconductor layer 122 .

In addition, the metal oxide layer 121 and the metal oxide layer 123 suppress formation of a level due to impurities due to entry of constituent elements of the insulating layer 110 and the gate insulating layer 150 into the oxide semiconductor layer 122, respectively. It also functions as a barrier film for

For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150
Carbon that can be mixed therein may be mixed into the metal oxide layer 121 or the metal oxide layer 123 up to several nm from the interface. Impurities such as silicon and carbon are present in the oxide semiconductor layer 122 .
When it enters inside, an impurity level is formed, and the impurity level serves as a donor to generate electrons, which may make it n-type.

However, if the thickness of the metal oxide layer 121 and the metal oxide layer 123 is more than several nanometers, the mixed impurities such as silicon and carbon do not reach the oxide semiconductor layer 122.
The influence of impurity levels is reduced.

Therefore, by providing the metal oxide layer 121 and the metal oxide layer 123, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

Further, when the gate insulating layer 150 and the oxide semiconductor layer 122 are in contact with each other and a channel is formed at the interface, interface scattering occurs at the interface and the field-effect mobility of the transistor decreases. However, the metal oxide layer 12 containing one or more metal elements constituting the oxide semiconductor layer 122
1. Since the metal oxide layer 123 is provided in contact with the oxide semiconductor layer 122, carriers are less likely to scatter at the interface between the oxide semiconductor layer 122 and the metal oxide layers 121 and 123, which reduces the performance of the transistor. Field effect mobility can be increased.

In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122 and the amount of oxygen vacancies in the metal oxide layers 121 and 123 in contact with the oxide semiconductor layer 122 can be reduced. The localized level density of the oxide semiconductor layer 122 can be reduced. As a result,
The transistor 10 described in this embodiment can have a small change in threshold voltage and high reliability. Further, the transistor 10 described in this embodiment has excellent electrical characteristics.

Note that since an insulating film containing silicon is often used as a gate insulating layer of a transistor, a region serving as a channel of the oxide semiconductor layer is in contact with the gate insulating layer as in the transistor of one embodiment of the present invention for the above reason. It can be said that a structure that does not Further, in the case where a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, carrier scattering may occur at the interface, and the field-effect mobility of the transistor may be low. From this point of view as well, it is preferable to separate the region of the oxide semiconductor layer, which serves as a channel, from the gate insulating layer.

Therefore, with the stacked structure of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, a channel can be formed in the oxide semiconductor layer 122, and high field-effect mobility and stable electricity can be obtained. A transistor with characteristics can be formed.

Note that the number of oxide semiconductor layers is not necessarily three, and may be a single layer, two layers, four layers, or five layers.
It is good also as a structure more than a layer. In the case of a single layer, the oxide semiconductor layer 12 described in this embodiment is used.
A layer corresponding to 2 may be used.

<Band diagram>
Here, band diagrams of transistors of one embodiment of the present invention are described with reference to FIGS. The band diagram in FIG. 2B includes the insulating layer 110, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the gate insulating layer 15 for easy understanding.
For 0, the energy level (Ec) at the bottom of the conduction band and the energy level (Ev) at the top of the valence band are shown.

As shown in FIG. 2B, a metal oxide layer 121, an oxide semiconductor layer 122, and a metal oxide layer 1
At 23, the energy level of the conduction band bottom changes continuously. This is also understood from the fact that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 have the same elements, so that oxygen easily diffuses into each other. Therefore, the metal oxide layer 121,
Although the oxide semiconductor layer 122 and the metal oxide layer 123 are stacks of films with different compositions, they can be said to be continuous in terms of physical properties.

Oxide semiconductor films stacked with a common main component are not simply stacked layers, but a continuous junction (in particular, a U-shaped well in which the energy level at the bottom of the conduction band changes continuously between layers). (U Shape Well) structure) is formed. That is, the laminated structure is formed so that impurities that form defect levels such as trap centers and recombination centers do not exist at the interfaces of each layer. If impurities are mixed between the layers of the laminated multilayer film,
Continuity of the energy band is lost, and carriers disappear at the interface due to trapping or recombination.

Note that FIG. 2B shows the case where Ec of the metal oxide layer 121 and the metal oxide layer 123 are the same, but they may be different.

FIG. 2B shows that the oxide semiconductor layer 122 serves as a well and a channel is formed in the oxide semiconductor layer 122 in the transistor 10 . Note that a channel having a U-shaped well structure in which the energy at the bottom of the conduction band changes continuously with the oxide semiconductor layer 122 as the bottom can also be referred to as a buried channel.

Note that trap levels due to impurities and defects may be formed in the vicinity of interfaces between the metal oxide layers 121 and 123 and an insulating film such as a silicon oxide film. metal oxide layer 1
23 can keep the oxide semiconductor layer 122 away from the trap level. However, when the energy difference between Ec of the metal oxide layer 121 or the metal oxide layer 123 and Ec of the oxide semiconductor layer 122 is small, electrons in the oxide semiconductor layer 122 exceed the energy difference to reach the trap level. can reach When electrons that become negative charges are trapped in the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, in long-term storage tests of transistors, there is a concern that the traps may not be fixed, causing variations in characteristics.

Therefore, to reduce the threshold voltage variation of the transistor, the metal oxide layer 121,
Also, it is necessary to provide an energy difference between Ec of the metal oxide layer 123 and the oxide semiconductor layer 122 . The respective energy differences are preferably 0.1 eV or more, and 0.1 eV or more.
2 eV or more is more preferable.

Note that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 preferably contain crystal parts. In particular, by using crystals oriented along the c-axis, a transistor can have stable electrical characteristics.

Further, in the band diagram as shown in FIG. 2B, the metal oxide layer 123 is not provided, and an In—Ga oxide (for example, the atomic ratio is I) is interposed between the oxide semiconductor layer 122 and the gate insulating layer 150 .
In—Ga oxide (n:Ga=7:93) may be provided, or gallium oxide or the like may be provided. Alternatively, an In—Ga oxide may be provided between the metal oxide layer 123 and the gate insulating layer 150 while the metal oxide layer 123 is provided, or gallium oxide or the like may be provided.

For the oxide semiconductor layer 122, an oxide having higher electron affinity than the metal oxide layers 121 and 123 is used. For example, as the oxide semiconductor layer 122, the metal oxide layer 12
1 and the metal oxide layer 123 by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.2 eV to 0.4 eV. can.

Since the transistor described in this embodiment includes the metal oxide layer 121 and the metal oxide layer 123 which contain one or more metal elements for forming the oxide semiconductor layer 122, the metal oxide layer 121 and the metal oxide layer 123 are included. It becomes difficult to form an interface state at the interface with the oxide semiconductor layer 122 and at the interface between the metal oxide layer 123 and the oxide semiconductor layer 122 . Therefore, by providing the metal oxide layer 121 and the metal oxide layer 123, variations and fluctuations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

<<Gate insulating layer 150>>
Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al
), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge
), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd)
, hafnium (Hf), tantalum (Ta), titanium (Ti), and the like.
For example, aluminum oxide (AlO _x ), magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), silicon oxynitride (SiN _x O _y )
, silicon nitride (SiN _x ), gallium oxide (GaO _x ), germanium oxide (GeO _x
), yttrium oxide (YO _x ), zirconium oxide (ZrO _x ), lanthanum oxide (La
O _x ), neodymium oxide (NdO _x ), hafnium oxide (HfO _x ) and tantalum oxide (
TaO _x ). Alternatively, the gate insulating layer 150 may be a stack of the above materials. Note that the gate insulating layer 150 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as impurities.

In addition, an example of the stacked structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is
For example, it has oxygen, nitrogen, silicon, hafnium, and the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the film thickness of the gate insulating layer 150 can be increased as compared with the case where silicon oxide is used, so that leak current due to tunnel current can be reduced. That is, a transistor with low off-state current can be realized. Furthermore, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, hafnium oxide having a crystalline structure is preferably used for a transistor with low off-state current. Examples of crystal structures include monoclinic and cubic systems. However, one embodiment of the present invention is not limited to these.

By the way, a surface on which hafnium oxide having a crystal structure is formed may have an interface state caused by defects. The interface states may function as trap centers. for that reason,
When hafnium oxide is placed close to the channel region of a transistor, the interface states can degrade the electrical characteristics of the transistor. Therefore, in order to reduce the effect of the interface state, it may be preferable to separate the hafnium oxide from the channel region of the transistor by placing another film therebetween. This membrane has a buffer function. The film having a buffer function may be a film included in the gate insulating layer 150 or a film included in the oxide semiconductor film. That is, silicon oxide, silicon oxynitride, an oxide semiconductor layer, or the like can be used as the film having a buffer function. For the film having a buffer function, for example, a semiconductor or an insulator with a larger energy gap than the semiconductor serving as the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or an insulator whose electron affinity is lower than that of the semiconductor used as the channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or an insulator with ionization energy higher than that of the semiconductor used as the channel region is used.

On the other hand, in some cases, the threshold voltage of a transistor can be controlled by trapping charges in an interface state (trap center) on a formation surface of hafnium oxide having the crystal structure described above. In order for the charges to exist stably, for example, an insulator having a larger energy gap than hafnium oxide may be placed between the channel region and hafnium oxide. Alternatively, a semiconductor or insulator having an electron affinity lower than that of hafnium oxide may be provided. Alternatively, a semiconductor or an insulator with higher ionization energy than hafnium oxide may be provided for the film having a buffer function. By using such an insulator, the charge trapped in the interface level is less likely to be released, and the charge can be retained for a long period of time.

Examples of such insulators include silicon oxide and silicon oxynitride. Electrons may be transferred from the oxide semiconductor film to the gate electrode layer 160 in order to trap charges in the interface states in the gate insulating layer 150 . As a specific example, the potential of the gate electrode layer 160 is set at a high temperature (eg, 125° C. to 450° C., typically 150° C. to 300° C.), and the potential of the source electrode layer 130 and the drain electrode layer 140 is increased. is maintained for 1 second or more, typically 1 minute or more.

In a transistor in which a desired amount of electrons are trapped in the interface level of the gate insulating layer 150 or the like, the threshold voltage shifts to the positive side. By adjusting the voltage of the gate electrode layer 160 and the voltage application time, the amount of trapped electrons (the amount of change in the threshold voltage) can be controlled. Note that it does not have to be in the gate insulating layer 150 as long as the charge can be captured. A laminated film having a similar structure may be used for other insulating layers.

For example, when a conductive layer is provided under the transistor 10, the insulating layer 110 is the gate insulating layer 1
It can have a similar structure and function as 50.

<<Gate electrode layer 160>>
The gate electrode layer 160 includes, for example, aluminum (Al), titanium (Ti), chromium (C
r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (T
a), Tungsten (W), or Silicon (Si).
Further, the gate electrode layer 160 can be stacked. For example, the above materials alone,
Alternatively, they may be used in combination, or materials containing nitrogen such as nitrides of the above materials may be used in combination.

<<insulating layer 180>>
The insulating layer 180 includes, for example, magnesium oxide (MgO _x ) and silicon oxide (SiO _x ).
, silicon oxynitride (SiO _x N _y ), silicon oxynitride (SiN _x O _y ), silicon nitride (SiN _x ), gallium oxide (GaO x ), germanium oxide (GeO _{x )} , yttrium oxide (YO _x ), oxide zirconium ( _ZrOx ), lanthanum oxide ( _LaOx ), neodymium oxide ( _NdOx ), hafnium oxide ( _HfOx ) and tantalum oxide ( _TaOx ),
An insulating film containing one or more types of aluminum oxide (AlO _x ) can be used. Also, the insulating layer 180 may be a laminate of the above materials. Preferably, the insulating layer has more oxygen than the stoichiometric composition. Oxygen released from the insulating layer 180 can be diffused into the channel formation region of the oxide semiconductor layer 122 through the gate insulating layer 150; therefore, oxygen vacancies formed in the channel formation region can be filled with oxygen. can. Therefore, stable electrical characteristics of the transistor can be obtained.

<<Conductive layer 190>>
A material similar to that of the gate electrode layer 160 can be used for the conductive layer 190 .

<<Conductive layer 195>>
A material similar to that of the gate electrode layer 160 can be used for the conductive layer 195 .

<Method for manufacturing transistor>
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
It should be noted that description of portions that overlap with those described in the structure of the transistor will be omitted. Also, the A1-A2 direction shown in FIGS. 5 to 13 is sometimes referred to as the channel length direction shown in FIGS. 1A and 1B. Also, the A3-A4 direction shown in FIGS.
A) and FIG. 1C may be referred to as the channel width direction.

In this embodiment, each layer (insulating layer, oxide semiconductor layer, conductive layer, etc.) forming a transistor is formed by a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition).
deposition) method, vacuum deposition method, pulse laser deposition (PLD: Pulse La
It can be formed using a ser deposition method. Alternatively, it can be formed by a coating method or a printing method. As a film formation method, sputtering method, plasma CVD
method is typical, but a thermal CVD method may also be used. As an example of the thermal CVD method, metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition)
position) method and atomic layer deposition (ALD: Atomic Layer Deposit
ion) method may be used. Moreover, in the sputtering method, embedding properties can be improved by using a combination of the long-throw method and the collimate method.

<Thermal CVD method>
The thermal CVD method is a film forming method that does not use plasma, so it has the advantage of not generating defects due to plasma damage.

In the thermal CVD method, a raw material gas and an oxidizing agent are sent into a chamber at the same time, the inside of the chamber is set to atmospheric pressure or reduced pressure, and the gases are reacted in the vicinity of or on the substrate to form a film on the substrate. good too.

Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films. For film formation, trimethylindium, trimethylgallium, and dimethylzinc can be used. Note that the chemical formula of trimethylindium is In(CH ₃ ) ₃ . Also, the chemical formula of trimethylgallium is Ga(CH ₃ ) ₃ . Also, the chemical formula of dimethylzinc is Zn(CH ₃ ) ₂ . Moreover, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C ₂ H ₅ )) can be used instead of dimethylzinc. ₂ ) can also be used.

<ALD method>
A conventional film forming apparatus using the CVD method has a raw material gas (precursor) for reaction during film formation.
are simultaneously supplied to the chamber. A film forming apparatus using the ALD method is
Precursors for reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, each switching valve (also called a high-speed valve) is switched to sequentially supply two or more types of precursors to the chamber, and the first precursor is followed by an inert gas (argon, or nitrogen, etc.) is introduced, and a second precursor is introduced. Also, instead of introducing an inert gas, the second precursor can be introduced after the first precursor has been discharged by evacuation.

FIGS. 3A, 3B, 3C, and 3D show the film formation process of the ALD method. First precursor 6
01 adsorbs to the surface of the substrate (see FIG. 3(A)) and a first monolayer is deposited (see FIG. 3(B)
)reference). At this time, metal atoms and the like contained in the precursor can bond with hydroxyl groups present on the substrate surface. An alkyl group such as a methyl group or an ethyl group may be bonded to the metal atom. Reacting with the second precursor 602 introduced after evacuating the first precursor 601 (see FIG. 3(C)), the second monolayer is deposited on the first monolayer to form a thin film. (See FIG. 3(D)). For example, when an oxidizing agent is contained as the second precursor, a chemical reaction occurs between the metal atom present in the first precursor or the alkyl group bonded to the metal atom and the oxidizing agent, resulting in an oxide film. can be formed.

The ALD method is a film formation method based on surface chemical reactions, in which the precursor adsorbs to the surface of the film to be formed,
It is further formed by the action of the self-stopping mechanism. For example, a precursor such as trimethylaluminum reacts with a hydroxyl group (OH group) present on the film-forming surface. At this time, only a surface reaction due to heat occurs, so that the precursor comes into contact with the film-forming surface, and metal atoms and the like in the precursor can be adsorbed to the film-forming surface via thermal energy. In addition, the precursor has characteristics such as having a high vapor pressure, being thermally stable at the stage before film formation, not self-decomposing, and rapidly chemically adsorbing onto the substrate. In addition, since the precursor is introduced as a gas, if the alternately introduced precursor can have sufficient time to diffuse, it is possible to form a film with good coverage even in a region having unevenness with a high aspect ratio. can.

In addition, in the ALD method, a thin film having excellent step coverage can be formed by controlling the order of gas introduction and repeating the steps until a desired thickness is obtained. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible. In addition, by increasing the exhaust capacity, the film formation speed can be increased, and the impurity concentration in the film can be reduced.

In addition, the ALD method includes the ALD method using heat (thermal ALD method) and the ALD method using plasma (
plasma ALD method). In the thermal ALD method, the reaction of the precursor is performed using thermal energy, and in the plasma ALD method, the reaction of the precursor is performed in the state of radicals.

The ALD method can form an extremely thin film with high accuracy. The surface coverage is high and the film density is high even on an uneven surface.

<Plasma ALD method>
In addition, by forming a film by the plasma ALD method, it becomes possible to form the film at a lower temperature than the ALD method using heat (thermal ALD method). The plasma ALD method can form a film at a temperature of, for example, 100° C. or less without lowering the film forming speed. Moreover, in the plasma ALD method, since N ₂ can be radicalized by plasma, not only oxide but also nitride can be formed.

Also, in the plasma ALD method, the oxidizing power of the oxidizing agent can be enhanced. This allows ALD
When the film is formed by the method, the precursor remaining in the film or the organic component desorbed from the precursor can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced.
It can have a film with a low impurity concentration.

Further, when performing the plasma ALD method, when generating radical species, ICP (Indus
Plasma can also be generated in a state away from the substrate such as actively coupled plasma), and plasma damage to the substrate or the film on which the protective film is formed can be suppressed.

As described above, by using the plasma ALD method, the process temperature can be lowered and the surface coverage can be increased compared to other film formation methods, and the film can be formed. As a result, entry of water and hydrogen from the outside can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

<Description of ALD apparatus>
FIG. 4A shows an example of a film forming apparatus using the ALD method. A film forming apparatus using the ALD method includes a film forming chamber (chamber 1701), source supply units 1711a and 1711b, high-speed valves 1712a and 1712b as flow rate controllers, source inlets 1713a and 1713b, and source outlets. 1714 and an exhaust device 1715 . Raw material introduction ports 1713a and 1713b installed in the chamber 1701 are connected to raw material supply units 1711a and 1711a through supply pipes and valves.
11b, and the raw material discharge port 1714 is connected to an exhaust device 1715 via a discharge pipe, a valve, and a pressure regulator.

A substrate holder 1716 equipped with a heater is provided inside the chamber, and a substrate 1700 on which a film is to be formed is placed on the substrate holder.

In the raw material supply units 1711a and 1711b, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, heating means, or the like. Alternatively, the raw material supply units 1711a and 1711b may be configured to supply a gaseous raw material gas.

Moreover, although an example in which two raw material supply units 1711a and 1711b are provided is shown, the present invention is not particularly limited, and three or more may be provided. Further, the high-speed valves 1712a and 1712b can be precisely controlled by time, and are configured to supply either the raw material gas or the inert gas. The high-speed valves 1712a and 1712b are source gas flow controllers, and can also be said to be inert gas flow controllers.

In the deposition apparatus shown in FIG. 4A, after the substrate 1700 is loaded onto the substrate holder 1716 and the chamber 1701 is sealed, the substrate 1700 is heated by the heater of the substrate holder 1716.
is set to a desired temperature (for example, 100° C. or higher or 150° C. or higher), and the thin film is removed from the substrate by repeating the supply of the raw material gas, the evacuation by the evacuation device 1715, the supply of the inert gas, and the evacuation by the evacuation device 1715. form on the surface.

In the film formation apparatus shown in FIG. 4A, one kind of material selected from hafnium, aluminum, tantalum, zirconium, and the like is selected by appropriately selecting a material (eg, a volatile organometallic compound) prepared in the material supply units 1711a and 1711b. Oxides containing the above elements (including composite oxides)
can be deposited. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate is used. A film can be formed. By appropriately selecting raw materials (such as volatile organometallic compounds) prepared in the raw material supply units 1711a and 1711b, thin films such as metal layers such as a tungsten layer and a titanium layer, and nitride layers such as a titanium nitride layer can be formed. A film can also be formed.

For example, when a hafnium oxide layer is formed by a film forming apparatus using the ALD method, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Two types of gases are used: a raw material gas and ozone (O ₃ ) as an oxidizing agent. In this case, the first raw material gas supplied from the raw material supply unit 1711a is TDMAH, and the second raw material gas supplied from the raw material supply unit 1711b is TDMAH.
becomes ozone. The chemical formula of tetrakisdimethylamide hafnium is Hf
[N( _CH3 ) ₂ ] ₄ . Other materials include tetrakis(ethylmethylamido)hafnium. Note that nitrogen has a function of eliminating a charge trapping level. Therefore, when the source gas contains nitrogen, a film of hafnium oxide with a low charge trap level density can be formed.

For example, in the case of forming an aluminum oxide layer with a film forming apparatus using the ALD method, a raw material gas obtained by vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound and H ₂ O as an oxidizing agent are used. Use different types of gas. In this case, the first raw material gas supplied from the raw material supply unit 1711a is TMA, and the second raw material gas supplied from the raw material supply unit 1711b is H.
₂ O. The chemical formula of trimethylaluminum is Al(CH ₃ ) ₃ . again,
Other material liquids include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, when a silicon oxide film is formed by a film forming apparatus using the ALD method, hexachlorodisilane is adsorbed on the film formation surface, chlorine contained in the adsorbed substance is removed, and an oxidizing gas (O
₂ , dinitrogen monoxide) radicals are supplied to react with the adsorbate.

For example, when forming a tungsten film with a film forming apparatus using the ALD method, WF ₆
gas and B ₂ H ₆ gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF
₆ gas and _H2 gas are successively and repeatedly introduced to form a tungsten film. _SiH4 gas may be used instead of _B2H6 gas _.

For example, an oxide semiconductor film such as In-Ga-Zn-
When forming an O film, In(CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an In film.
—O layer is formed, and then Ga(CH ₃ ) ₃ gas and O ₃ gas are successively and repeatedly introduced to form Ga
An O layer is formed, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are sequentially and repeatedly introduced to form a Zn layer.
Form an O layer. Note that the order of these layers is not limited to this example. Further, these gases may be mixed to form a mixed compound layer such as an In--Ga--O layer, an In--Zn--O layer, or a Ga--Zn--O layer. Note that H ₂ obtained by bubbling with an inert gas such as Ar instead of O ₃ gas
Although O gas may be used, it is preferable to use O ₃ gas containing no H. Also, In(C
In(C ₂ H ₅ ) ₃ gas may be used instead of H ₃ ) ₃ gas. In addition, Ga( _CH3 )
Ga(C ₂ H ₅ ) ₃ gas may be used instead of ₃ gas. Alternatively, Zn(CH ₃ ) ₂ gas may be used.

《Multi-chamber manufacturing equipment》
FIG. 4B shows an example of a multi-chamber manufacturing apparatus having at least one deposition apparatus shown in FIG. 4A.

The manufacturing apparatus shown in FIG. 4B can continuously form laminated films without exposure to the atmosphere.
We are trying to prevent contamination of impurities and improve throughput.

The manufacturing apparatus shown in FIG. 4B includes a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703,
It has at least a chamber 1701 and an unload chamber 1706 which are film formation chambers. In addition, the chambers of the manufacturing equipment (including load chambers, processing chambers, transfer chambers, film formation chambers, unload chambers, etc.) should be filled with inert gas (nitrogen gas, etc.) with a controlled dew point to prevent moisture from adhering. is preferably filled, and desirably a reduced pressure is maintained.

Further, the chamber 1704 and the chamber 1705 may be a film forming apparatus using the same ALD method as the chamber 1701, a film forming apparatus using a plasma CVD method, or a film forming apparatus using a sputtering method. Alternatively, a film forming apparatus using the MOCVD method may be used.

For example, an example of depositing a laminated film using a deposition apparatus using plasma CVD as the chamber 1704 and a deposition apparatus using MOCVD as the chamber 1705 will be described below.

FIG. 4B shows an example in which the top view of the transfer chamber 1720 is hexagonal. good. In addition, although the top surface shape of the substrate is shown as a rectangle in FIG. 4B, it is not particularly limited. Further, although FIG. 4B shows an example of a single-wafer type, a batch-type film forming apparatus for forming films on a plurality of substrates may be used.

<Formation of insulating layer 110>
First, the insulating layer 110 is formed on the substrate 100 . The insulating layer 110 is formed by a plasma CVD method, a thermal CVD method (MOCVD method, ALD method), a sputtering method, or the like, using, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,
It can be formed using a metal oxide film such as hafnium oxide or tantalum oxide, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixed material thereof. Alternatively, a stack of any of the above materials may be used, and at least the upper layer of the stack that is in contact with the first metal oxide film that will later become the metal oxide layer 121 contains excess oxygen that can serve as an oxygen supply source for the oxide semiconductor layer 122 . It is preferably made of a material containing

Note that when the insulating layer 110 is formed using a material that does not contain hydrogen or has a hydrogen content of 1% or less, the occurrence of oxygen vacancies in the oxide semiconductor layer can be suppressed. operation can be stabilized.

For example, a silicon oxynitride film with a thickness of 100 nm can be used as the insulating layer 110 by a plasma CVD method.

Next, first heat treatment may be performed to desorb water, hydrogen, or the like from the insulating layer 110 . As a result, the concentrations of water, hydrogen, and the like in the insulating layer 110 can be reduced, and the heat treatment reduces the diffusion amount of water, hydrogen, and the like into the first metal oxide film that is formed later. can do.

<Formation of First Metal Oxide Film, Oxide Semiconductor Film to Become Oxide Semiconductor Layer 122>
Subsequently, over the insulating layer 110, a first metal oxide film to be the metal oxide layer 121 later and an oxide semiconductor film to be the oxide semiconductor layer 122 later are formed. The first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 can be formed by a sputtering method, an MOCVD method, a PLD method, or the like, and are more preferably formed by a sputtering method. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In addition, in the sputtering method, a facing target method (a facing electrode method, a vapor phase sputtering method, a VDSP (Vapor Depositio
Plasma damage during film formation can be reduced by forming the film by the n-sputtering method.

For example, when the oxide semiconductor film to be the oxide semiconductor layer 122 is formed by a sputtering method, each chamber in the sputtering apparatus is equipped with a cryopump to remove impurities such as water from the oxide semiconductor film as much as possible. high vacuum (up to about 5×10 ⁻⁷ Pa to 1×10 ⁻⁴ Pa) using an adsorption-type vacuum pump, and the substrate on which a film is to be formed is heated to 100° C. or higher, preferably 400° C. or higher. Heating is preferred. Alternatively, it is preferable to combine a turbomolecular pump and a cold trap to prevent backflow of gas containing carbon components, moisture, etc. from the exhaust system into the chamber. Alternatively, an exhaust system combining a turbomolecular pump and a cryopump may be used.

In order to obtain a highly purified intrinsic oxide semiconductor film, it is desirable not only to evacuate the chamber to a high vacuum, but also to highly purify the sputtering gas. An oxygen gas or an argon gas used as a sputtering gas is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, more preferably −100° C. or lower, so that the oxide semiconductor film is free from moisture or the like. can be prevented as much as possible.

As a sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate. In the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Note that in the case where the oxide semiconductor film to be the oxide semiconductor layer 122 is formed by, for example, a sputtering method, the substrate temperature is set to 150° C. to 750° C., preferably 150° C. to 750° C.
By forming an oxide semiconductor film at a temperature of 50° C. or lower, preferably 200° C. to 420° C. or lower, a CAAC-OS film can be formed.

A material for the first metal oxide film can be selected so that the electron affinity is lower than that of the oxide semiconductor film that serves as the oxide semiconductor layer 122 .

In the case where the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 are formed by a sputtering method, for example, the first metal oxide film can be formed by using a multi-chamber sputtering apparatus. Then, an oxide semiconductor film to be the oxide semiconductor layer 122 can be continuously formed without being exposed to the air. In that case, entry of unnecessary impurities into the interface between the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 can be suppressed, and the interface state density can be reduced. As a result, it is possible to stabilize the electrical characteristics of the transistor, especially the characteristics in the reliability test.

In addition, when the insulating layer 110 is damaged, the metal oxide layer 121 can keep the oxide semiconductor layer 122, which serves as a main conduction path, away from the damaged portion. In particular, the characteristics can be stabilized in reliability tests.

For example, as the first metal oxide film, In:
An insulating film formed to a thickness of 20 nm using Ga:Zn=1:3:4 (atomic ratio) can be used. In addition, the oxide semiconductor film was formed by a sputtering method, and In
:Ga:Zn=1:1:1 (atomic ratio), and an oxide semiconductor film having a thickness of 15 nm can be used.

Note that by performing second heat treatment after the oxide semiconductor film to be the first metal oxide film and the oxide semiconductor layer 122 is formed, oxidation to be the first metal oxide film and the oxide semiconductor layer 122 is performed. The amount of oxygen vacancies in the material semiconductor film can be reduced.

The temperature of the second heat treatment is 250° C. or higher and lower than the substrate strain point, preferably 300° C. or higher and 650° C.
°C or lower, more preferably 350 °C or higher and 550 °C or lower.

The second heat treatment is performed in an inert gas atmosphere containing a rare gas such as helium, neon, argon, xenon, or krypton, or nitrogen. Alternatively, after heating in an inert gas atmosphere, an oxygen atmosphere or dry air (with a dew point of −80° C. or less, preferably −100° C. or less, preferably −
It may be heated in an air atmosphere of 120° C. or less. Alternatively, it may be carried out under reduced pressure. In addition to the dry air, the inert gas and oxygen preferably do not contain hydrogen, water, etc. Typically, the dew point is -80°C or lower, preferably -100°C or lower. The treatment time is 3 minutes to 24 hours.

In the heat treatment, instead of the electric furnace, a device that heats the object by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, GRTA (Gas
Rapid Thermal Anneal) device, LRTA (Lamp Rapid
RTA (Rapid Thermal Anneal) equipment such as
neal) device can be used. An LRTA apparatus is an apparatus that heats an object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. The hot gas may be a noble gas such as argon or an inert gas such as nitrogen.

Note that the second heat treatment may be performed after etching for forming the metal oxide layer 121 and the oxide semiconductor layer 122, which is described later.

For example, after heat treatment is performed at 450° C. for 1 hour in a nitrogen atmosphere, heat treatment can be performed at 450° C. for 1 hour in an oxygen atmosphere.

Through the above steps, oxygen vacancies in the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 can be reduced, and impurities such as hydrogen and water can be reduced. Further, the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 can be formed in which the localized level density is reduced.

Note that an effect similar to that of heat treatment can be obtained by high-density plasma irradiation using oxygen as a material. The irradiation time is 1 minute or more and 3 hours or less, preferably 3 minutes or more and 2 hours or less, more preferably 5 minutes or more and 1 hour or less.

<Formation of first conductive film>
Next, a first conductive film used as a hard mask is formed over the oxide semiconductor layer 122 . The first conductive film is formed by a sputtering method, a chemical vapor deposition (CVD) method (organometallic chemical vapor deposition (
MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). ), a vapor deposition method, a pulsed laser deposition (PLD) method, or the like.

Materials of the first conductive film are copper (Cu), tungsten (W), molybdenum (Mo), gold (A
u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta),
Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (
Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S
It is preferable to use a single layer or a laminated layer of a conductive film containing a single substance or an alloy of materials such as r), or a compound containing these materials as a main component.

For example, a tungsten film with a thickness of 20 to 100 nm can be formed as the first conductive film by a sputtering method.

Although the first conductive film is formed as a hard mask in this embodiment mode, the present invention is not limited to this, and an insulating film may be formed.

<Formation of Metal Oxide Layer 121 and Oxide Semiconductor Layer 122>
Next, a resist mask is formed by a lithography process, and using the resist mask,
The first conductive film is selectively etched to form a conductive layer 130b. Subsequently, after removing the resist on the hard mask, the oxide semiconductor film to be the oxide semiconductor layer 122 and the first metal oxide film are selectively etched, respectively, and the oxide semiconductor layer 122 and the metal oxide layer 121 are etched. is formed in an island shape (see FIG. 5). Note that a dry etching method can be used as an etching method. Note that when the oxide semiconductor layer is etched using the conductive layer 130b as a hard mask, the edge roughness of the oxide semiconductor layer after etching can be reduced as compared with the resist mask.

<Formation of Metal Oxide Film 123a>
Next, a metal oxide film 123 a to be used as the metal oxide layer 123 is formed over the oxide semiconductor layer 122 and the insulating layer 110 . The metal oxide film 123a can be formed by a method similar to that of the oxide semiconductor film and the first metal oxide film, and the metal oxide film 123a has lower electron affinity than the oxide semiconductor film. material can be selected.

In addition, by forming the metal oxide film 123a by a long-throw sputtering method, the embedding property of the metal oxide film 123a in the trench 174 can be improved.

For example, as the metal oxide film 123a, In:Ga:Zn=1 is formed by a sputtering method.
A 5-nm-thick oxide semiconductor film can be formed using a target of :3:2 (atomic ratio).

<Formation of First Insulating Film>
Next, a first insulating film to be the insulating layer 175 later is formed over the metal oxide film 123a. first
can be formed by a method similar to that of the insulating layer 110 .

The first insulating film is formed by a plasma CVD method, a thermal CVD method (MOCVD method, ALD method), a sputtering method, or the like, such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxyfluoride, or gallium oxide. , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide, nitride insulating films such as silicon nitride, silicon nitride oxide, aluminum nitride and aluminum nitride oxide, or these can be formed using a mixed material of Moreover, the lamination|stacking of the said material may be sufficient.

<Planarization of first insulating film>
Next, planarization treatment is performed on the first insulating film to form an insulating layer 175b (see FIG. 6). The planarization treatment can be performed using a CMP (Chemical Mechanical Polishing) method, a dry etching method, a reflow method, or the like. Further, in the case of planarization using the CMP method, by introducing a film having a composition different from that of the first insulating film on the first insulating film, the film of the insulating layer 175b within the substrate surface after the CMP process is reduced. Thickness can be uniform.

<Formation of Grooves>
Next, a resist mask is formed over the planarized insulating layer 175b by a lithography process. Note that the lithography process may be performed after the organic film is applied on the insulating layer or after the resist mask is applied. The organic film can comprise propylene glycol monomethyl ether, ethyl lactate, and the like. The use of the organic film has effects such as an antireflection effect during exposure, an improvement in adhesion between the resist mask and the film, an improvement in resolution, and the like. The organic film can also be used in other processes.

In the case of forming a transistor with an extremely short channel length, a resist mask is processed using a method suitable for fine line processing such as electron beam exposure, immersion exposure, or EUV (EUV: Extreme Ultra-Violet) exposure. Etching may be performed using a resist mask. When forming a resist mask by electron beam exposure, if a positive resist is used as the resist mask, the exposure area can be minimized.
Throughput can be improved. Using such a method, a channel length of 10
A transistor with a thickness of 0 nm or less, 30 nm or less, or even 20 nm or less can be formed. Alternatively, fine processing may be performed by an exposure technique using X-rays or the like.

Using the resist mask, groove processing is performed on the insulating layer 175b by a dry etching method until the metal oxide film 123a is exposed. By the processing, the insulating layer 175
, grooves 174 are formed.

It should be noted that the shape of the groove portion 174 is preferably perpendicular to the substrate surface.

It should be noted that the processing method of the groove portion 174 is not limited to the above method. For example, not only a resist mask but also a hard mask may be used, or a halftone mask may be used in a lithography process to control the shape of the resist mask. Also, the shape of the mask may be controlled by a nanoimprint method or the like. The method can also be applied to other processes.

<Formation of Second Insulating Film 150a>
Next, a second insulating film 150 a to be the gate insulating layer 150 is formed over the metal oxide film 123 a and the insulating layer 175 . For example, aluminum oxide (A
_lOx ), magnesium oxide ( _MgOx ), _silicon oxide ( _{SiOx )} , _silicon oxynitride (SiOxNy), silicon oxynitride ( _SiNxOy ), silicon nitride ( _SiNx ),
Gallium oxide (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _x
), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x ), neodymium oxide (NdO
_x ), hafnium oxide (HfO _x ) and tantalum oxide (TaO _x ) can be used. Note that the second insulating film 150a may be a stack of the above materials. The second insulating film 150a can be formed using a sputtering method, a CVD method (plasma CVD method, MOCVD method, ALD method, etc.), an MBE method, or the like. In addition, the second insulating film 150a can be formed using a method similar to that for the insulating layer 110 as appropriate.

For example, as the second insulating film 150a, 10 nm of silicon oxynitride is deposited by plasma CVD.
m can be formed.

<Formation of Conductive Film 160a>
Next, a conductive film 160a to be the gate electrode layer 160 is formed over the second insulating film 150a.
(See FIG. 7). As the conductive film 160a, for example, aluminum (Al), titanium (Ti
), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag)
, tantalum (Ta), tungsten (W), or an alloy material containing these as main components can be used. The conductive film 160a is formed by a sputtering method or a CVD method (plasma CVD method,
MOCVD method, ALD method, etc.), MBE method, vapor deposition method, plating method, or the like. As the conductive film 160a, a conductive film containing nitrogen may be used, or a stack of the above conductive film and a conductive film containing nitrogen may be used.

For example, as the conductive film 160a, a stacked structure in which titanium nitride is formed with a thickness of 10 nm by ALD and tungsten is formed with a thickness of 150 nm by metal CVD can be used.

<Planarization treatment>
Next, planarization processing is performed. The planarization treatment can be performed using a CMP method, a dry etching method, or the like. The planarization process may be finished when the second insulating film 150a is exposed, or may be finished when the insulating layer 175 is exposed. As a result, the gate electrode layer 160,
A gate insulating layer 150 may be formed (see FIG. 8).

<Etch-back treatment of insulating layer 175>
Next, the insulating layer 175 is etched back by dry etching to expose the metal oxide film 123a. Further, a portion of the metal oxide film 123a that does not overlap with the gate electrode layer 160 is etched to form the metal oxide layer 123 (see FIG. 9).

Note that the method for forming the structure shown in FIG. 9 is not limited to the above.

For example, as shown in FIG.
, a structure including the gate electrode layer 160 may be employed. Alternatively, as shown in FIG. 11, the second insulating film 150a may be formed on the metal oxide film 123a.

<Ion addition treatment>
Next, addition treatment of ions 167 is performed on the oxide semiconductor layer 122 (see FIG. 12). Materials to be added are hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), boron (B), phosphorus (P), and tungsten (W).
, aluminum (Al), or the like can be used. Methods of adding include an ion doping method, an ion implantation method, a plasma immersion ion implantation method, a high-density plasma processing method, and the like.
Note that in miniaturization, it is preferable to use an ion implantation method because addition of impurities other than predetermined ions can be suppressed. Also, the ion doping method and the plasma immersion ion implantation method are excellent when processing a large area.

In the ion doping process, the ion acceleration voltage is desirably adjusted according to the ion species and the implantation depth. For example, it can be 1 kV or more and 100 kV or less, or 3 kV or more and 60 kV or less. In addition, the dose amount of ions is 1×10 ¹² ions/cm ² or more and 1×10 ^1
7 ions/cm ² or less, preferably 1×10 ¹⁴ ions/cm ² or more and 5×10 ¹⁶ i
Ons/cm ² or less is desirable.

By the ion addition treatment, oxygen vacancies are formed in the oxide semiconductor layer 122 and the low-resistance regions 125 are formed.
(see FIG. 13). Note that in some cases, ions are diffused into a region of the oxide semiconductor layer 122 that overlaps with the gate electrode layer, and the low-resistance region 125 is formed also in a portion of the oxide semiconductor layer 122 that overlaps with the gate electrode layer.

Further, by performing heat treatment after the ion addition treatment, damage to the film caused during the ion addition treatment can be repaired.

Next, a third insulating film that will later become the insulating layer 180 is formed. A method for forming the third insulating film can be the same as that for the insulating layer 110 . After forming the third insulating film, it is desirable to planarize it.

Next, dry etching is performed to form openings in the third insulating film.

Next, after forming a third conductive film to be the conductive layer 190 in the opening, planarization treatment is performed to form the conductive layer 190 .

Next, a fourth conductive film to be the conductive layer 195 is formed over the conductive layer 190 . A conductive layer 195 is formed by using a photolithography method, a nanoimprinting method, or the like on the fourth conductive film.

By using the above manufacturing method, the transistor 10 can be formed. By using the above manufacturing method, an extremely fine transistor with a channel length of 100 nm or less, 30 nm or less, or 20 nm or less can be stably manufactured.

Note that the transistor 10 may have a region where the gate insulating layer 150 is in contact with side surfaces of the gate electrode layer (see FIG. 14).

<Modification 1 of Transistor 10: Transistor 11>
A transistor 11 having a shape different from that of the transistor 10 illustrated in FIG. 1 is described with reference to FIG.

15A, 15B, and 15C are a top view and a cross-sectional view of the transistor 11. FIG. 15A is a top view of the transistor 11, and FIG. 15B is a
), and FIG. 15C is a cross-sectional view between B3-B4.

The transistor 11 has an insulating layer 170 and an insulating layer 172, which is the same as the transistor 10.
different from

<<insulating layer 170>>
The insulating layer 170 contains oxygen, nitrogen, fluorine, aluminum (Al), and magnesium (Mg).
, silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y),
Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf), Tantalum (Ta), Titanium (Ti), and the like. Aluminum oxide (AlO
_x ), magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (
_{SiOxNy )} , silicon nitride oxide ( _SiNxOy ), silicon nitride ( _SiNx ), gallium oxide ( _GaOx ), germanium oxide ( _{GeOx )} , yttrium oxide ( _YOx ),
Zirconium oxide (ZrO _x ), Lanthanum oxide (LaO _x ), Neodymium oxide (NdO _x )
, hafnium oxide (HfO _x ) and tantalum oxide (TaO _x ).

The insulating layer 170 preferably includes an aluminum oxide (AlO _x ) film. The aluminum oxide film can have a barrier effect of impermeability of both hydrogen, impurities such as moisture, and oxygen through the film. Therefore, in the aluminum oxide film, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 contain impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor during and after the manufacturing process of the transistor. To prevent contamination, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 1 of oxygen which is the main component material
23 and unnecessary release of oxygen from the insulating layer 110, and is suitable for use as a protective film.

Further, the insulating layer 170 is preferably a film having an oxygen supply capability. When the insulating layer 170 is formed, a mixed layer is formed at an interface with another oxide layer, and the mixed layer or the other oxide layer is filled with oxygen. can be diffused into the oxide semiconductor layer to compensate for oxygen vacancies in the oxide semiconductor layer, and the transistor characteristics (for example,
threshold voltage, reliability, etc.) can be improved.

Also, the insulating layer 170 may be a single layer or a laminated layer. Further, another insulating layer may be provided above or below the insulating layer. For example, an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide is used. be able to. Preferably, the insulating layer has more oxygen than the stoichiometric composition. Oxygen released from the insulating layer can be diffused into the channel formation region of the oxide semiconductor layer 122 through the gate insulating layer 150 or the insulating layer 110; can be supplemented. Therefore, stable electrical characteristics of the transistor can be obtained.

<<insulating layer 172>>
The insulating layer 172 includes oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), and yttrium (Y). , zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlO _x ), magnesium oxide (MgO _x ), silicon oxide (Si
O _x ), silicon oxynitride (SiO _x N _y ), silicon oxynitride (SiN _x O _y ), silicon nitride (SiN _x ), gallium oxide (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _{x )} ), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x )
, neodymium oxide (NdO _x ), hafnium oxide (HfO _x ) and tantalum oxide (TaO
_x ) can be used. Also, the insulating layer 172 may be a laminate of the above materials.

The insulating layer 172 preferably contains an aluminum oxide film. The aluminum oxide film is
It can have the effect of blocking both hydrogen, impurities such as moisture, and oxygen from permeating through the membrane. Therefore, in the aluminum oxide film, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 contain impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor during and after the manufacturing process of the transistor. As a protective film that has the effects of preventing contamination, preventing oxygen, which is the main component material, from being released from the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, and preventing oxygen from being released from the insulating layer 110. suitable for use.

In addition, the insulating layer 172 can function as a protective film. By providing the insulating layer 172, the gate insulating layer 150 can be protected from plasma damage.
Thereby, it is possible to suppress the provision of electron traps in the vicinity of the channel.

<Method for Manufacturing Transistor 11>
A method for manufacturing the transistor 11 will be described with reference to FIGS. Note that the description is used for the same part as the manufacturing method of the transistor 10 .

<Formation of insulating layer 172>
An insulating layer 172 is formed over the insulating layer 110, the oxide semiconductor layer 122, and the gate electrode layer 160 (see FIG. 16). Note that the oxide semiconductor layer 122 and the gate insulating layer 150 may be damaged by plasma when the insulating layer 172 is formed; therefore, the insulating layer 172 is preferably formed by MOCVD or ALD.

The thickness of the insulating layer 172 is 1 nm to 30 nm, preferably 3 nm to 10 nm.
The following are preferable.

Further, ion addition treatment may be performed on the oxide semiconductor layer 122 after the insulating layer 172 is formed (see FIG. 16). Accordingly, damage to the oxide semiconductor layer 122 during ion addition treatment can be reduced while forming a low-resistance region (see FIG. 17).

In addition, the insulating layer 172 may be processed by a lithography method, a nanoimprinting method, a dry etching method, or the like after film formation, or may be formed only by film formation.

<Formation of insulating layer 170>
Next, an insulating layer 170 is formed over the insulating layer 172 . The insulating layer 170 may be a single layer,
It may be laminated. The insulating layer 170 can be formed using a material, a method, and the like that are similar to those of the insulating layer 110 .

Further, the insulating layer 170 is preferably an aluminum oxide film formed by a sputtering method. When forming an aluminum oxide film by a sputtering method, it is desirable to use an oxygen gas as a gas for film formation. Moreover, it is desirable that the oxygen gas content is 1% to 100% by volume, preferably 4% to 100% by volume, and more preferably 10% to 100% by volume. When the oxygen content is 1% by volume or more, surplus oxygen can be supplied to the insulating layer or the adjacent insulating layer. Further, oxygen can be added to a layer in contact with the layer.

For example, the insulating layer 170 can be formed to a thickness of 20 nm to 40 nm by using aluminum oxide as a target and containing 50% by volume of oxygen gas as a sputtering gas.

Next, heat treatment is preferably performed. The heat treatment is typically performed at a temperature of 150° C. or higher and lower than the substrate strain point, preferably 250° C. or higher and 500° C. or lower, more preferably 300° C. or higher and 450° C. or higher.
°C or less. Due to the heat treatment, the oxygen 173 added to the insulating layer (eg, the insulating layer 110) diffuses and moves to the oxide semiconductor layer 122 to fill oxygen vacancies in the oxide semiconductor layer 122. (See FIG. 18).

In this embodiment mode, heat treatment can be performed at 400° C. for 1 hour in an oxygen atmosphere.

Note that the heat treatment may be performed as needed in other steps. By performing heat treatment, defects existing in the film can be repaired and the interface state density can be reduced.

<Addition of oxygen>
Note that the treatment for adding oxygen is not limited to the treatment through the insulating layer 170 . The treatment for adding oxygen may be performed on the insulating layer 110 and the insulating layer 175, or on the first metal oxide film,
It may be performed on the metal oxide film 123a or may be performed on other insulating layers. As oxygen to be added, one or more of oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, and the like are used. Methods for adding oxygen include an ion doping method, an ion implantation method, a plasma immersion ion implantation method, and the like.

Note that when an ion implantation method is used as a method of adding oxygen, oxygen atomic ions or oxygen molecular ions may be used. Using oxygen molecular ions can reduce damage to the film to which they are added. Oxygen molecule ions are separated on the surface of the film to which the oxygen is added, and are added as oxygen atomic ions. Since energy is used to separate the oxygen atoms from the oxygen molecules, the energy per oxygen atom ion when the oxygen molecule ions are added to the film to which the oxygen is added is It is lower than when added to a membrane with Therefore, damage to the film to which oxygen is added can be reduced.

In addition, by using oxygen molecular ions, the energy of each oxygen atomic ion implanted into the film to which oxygen is added is reduced, so the position at which the oxygen atomic ions are implanted is shallow. Therefore, in heat treatment performed later, oxygen atoms are likely to move, and the metal oxide layer 121,
More oxygen can be supplied to the oxide semiconductor layer 122 and the metal oxide layer 123 .

When oxygen molecular ions are implanted, the energy per oxygen atomic ion is lower than when oxygen atomic ions are implanted. Therefore, by implanting using oxygen molecule ions, it is possible to increase the acceleration voltage and increase the throughput. In addition, by implanting using oxygen molecular ions, compared to the case of using oxygen atomic ions,
It is possible to halve the dose. As a result, throughput can be increased.

When oxygen is added to the film to which oxygen is added, oxygen is added to the film to which oxygen is added using conditions such that the peak of the oxygen atom ion concentration profile is located in the film to which oxygen is added. addition is preferred. As a result, compared to the case of implanting oxygen atomic ions,
Acceleration voltage during implantation can be lowered, and damage to the film to which oxygen is added can be reduced. That is, the amount of defects in the film to which oxygen is added can be reduced, and variations in the electrical characteristics of the transistor can be suppressed. Furthermore, the amount of oxygen atoms added at the interface between the insulating layer 110 and the metal oxide layer 121 is less than 1×10 ²¹ atoms/cm ³ , less than 1×10 ²⁰ atoms/cm ³ , or less than 1×10 ¹⁹ atoms/cm
By adding oxygen to the film to which oxygen is added so that the density is less than ³ , the amount of oxygen added to the insulating layer 110 can be reduced. As a result, damage to the film to which oxygen is added can be reduced, and variations in electrical characteristics of the transistor can be suppressed.

Alternatively, oxygen may be added to the film to which oxygen is added by plasma treatment (plasma immersion ion implantation method) in which the film to which oxygen is added is exposed to plasma generated in an oxygen-containing atmosphere. The atmosphere containing oxygen includes an atmosphere containing an oxidizing gas such as oxygen, ozone, dinitrogen monoxide, or nitrogen dioxide. Note that by exposing the film to which oxygen is added to plasma generated with a bias applied to the substrate 100 side, the amount of oxygen added to the film to which oxygen is added can be increased, which is preferable. An example of an apparatus for performing such plasma processing is an ashing apparatus.

For example, oxygen molecule ions can be added to the insulating layer 110 by an ion implantation method with an acceleration voltage of 60 kV and a dose of 2×10 ¹⁶ /cm ² .

The above steps can also be applied to transistor 10 and other transistors.

As described above, the localized level density of the oxide semiconductor film is reduced, and a transistor having excellent electrical characteristics can be manufactured. In addition, a highly reliable transistor whose electric characteristics change little over time or due to stress tests can be manufactured.

<Modification 2 of Transistor 10: Transistor 12>
A transistor 12 having a shape different from that of the transistor 10 illustrated in FIG. 1 is described with reference to FIG.

19A, 19B, and 19C are a top view and a cross-sectional view of the transistor 12. FIG. 19A is a top view of the transistor 12, and FIG. 19B is a
), and FIG. 19C is a cross-sectional view between C3-C4.

In the transistor 12 , the metal oxide layer 123 is the oxide semiconductor layer 122 and the metal oxide layer 121 .
It differs from the transistor 10 in that it has a region in contact with the side edge of the transistor and that it has a conductive layer 165 . Note that in the transistor 12, the metal oxide film 123a can be used as the metal oxide layer 123 without being etched.

<<Conductive layer 165>>
The conductive layer 165 includes, for example, aluminum (Al), titanium (Ti), chromium (Cr),
Cobalt (Co), Nickel (Ni), Copper (Cu), Yttrium (Y), Zirconium (Zr), Molybdenum (Mo), Ruthenium (Ru), Silver (Ag), Tantalum (Ta),
It can have materials such as tungsten (W), or silicon. Also, the conductive layer 1
65 can be a laminate. In the case of lamination, it may be used in combination with a material containing nitrogen, such as a nitride of the above material.

The conductive layer 165 can have a function similar to that of the gate electrode layer 160 . Conductive layer 165
may be applied with the same potential as the gate electrode layer 160 or may be applied with a different potential.

Further, in the transistor 12 provided with the conductive layer 165 , the insulating layer 110 can have a structure and function similar to those of the gate insulating layer 150 .

With the above structure, damage to the oxide semiconductor layer during ion addition treatment can be suppressed (see FIGS. 20 and 21). In addition, the side edges of the oxide semiconductor layer 122 can be protected. As described above, the electrical characteristics of the transistor can be stabilized.

<Modification 3 of Transistor 10: Transistor 13>
A transistor 13 having a shape different from that of the transistor 10 illustrated in FIG. 1 is described with reference to FIG.

22A, 22B, and 22C are a top view and a cross-sectional view of the transistor 13. FIG. 22A is a top view of the transistor 13, and FIG. 22B is a
), and FIG. 22C is a cross-sectional view between D3-D4.

In the transistor 13, similarly to the transistor 12, the metal oxide layer 123 is the oxide semiconductor layer 1.
22. The transistor 10 is different from the transistor 10 in that it has a gate insulating layer 151 and a gate insulating layer 152 in addition to having regions in contact with the side ends of the metal oxide layer 121 in the channel length direction and the channel width direction. different.

<<Gate Insulating Layer 151, Gate Insulating Layer 152>>
The gate insulating layers 151 and 152 can have a material similar to that of the gate insulating layer 150 .

Note that the gate insulating layer 151 and the gate insulating layer 152 are preferably formed using different materials.

<Method for Manufacturing Transistor 13>
A method for manufacturing the transistor 13 is described with reference to FIGS. Note that the description is used for the same part as the manufacturing method of the transistor 10 .

<Formation of Gate Insulating Layer 151>
A gate insulating layer 151 is formed after the metal oxide layer 123 is formed. The gate insulating layer 151 is formed by sputtering, CVD (plasma CVD, MOCVD, ALD, etc.), MBE, etc.
It can be formed using a method, etc.

For example, as the gate insulating layer 151, aluminum oxide can be formed with a thickness of 5 nm by an ALD method.

<Formation of insulating film 152a>
Next, an insulating film 152a and a conductive film 160a are formed over the gate insulating layer 151 and the insulating layer 175 after the groove portion 174 is formed (see FIG. 23).

The insulating film 152a can be formed using a material and a method similar to those of the second insulating film 150a of the transistor 10 . For example, silicon oxide can be formed with a thickness of 5 nm by plasma CVD as the insulating film 152a.

Next, the insulating film 152a and the conductive film 160a are subjected to planarization treatment to form the gate electrode layer 160 and the insulating layer 152b (see FIG. 24).

The insulating layer 175 is then etched until the gate insulating layer 151 is exposed. Further, the insulating layer 152b is etched except for a portion overlapping with the gate electrode layer 160, whereby
A gate insulating layer 152 may be formed.

Next, addition processing of ions 167 is performed (see FIG. 25). The ion addition treatment is performed on the oxide semiconductor layer 122 through the gate insulating layer 151 and the metal oxide layer 123 to form the low-resistance region 125 (see FIG. 26).

By using the above method, for example, film reduction of the metal oxide layer 123 or the like during fabrication of a fine transistor can be reduced. In addition, damage caused during processing can be reduced. therefore,
Even in a fine transistor, the shape can be stabilized. In addition, the electrical characteristics and reliability of the transistor can be improved.

<Modification 4 of Transistor 10: Transistor 14>
A transistor 14 having a shape different from that of the transistor 10 shown in FIG. 1 is described with reference to FIG.

27A, 27B, and 27C are a top view and a cross-sectional view of the transistor 14. FIG. 27A is a top view of the transistor 14, and FIG. 27B is a
), and FIG. 27C is a cross-sectional view between E3-E4.

The shape of the metal oxide layer 123 of the transistor 14 is similar to that of the transistor 12, and the gate insulating layer 150 has a region in contact with the side surface of the gate electrode layer 160 and a region in contact with the side surface of the gate insulating layer 150. Transistor 10 in that insulating layer 176 is provided.
different from

Note that the angle (gradient) between the bottom surface of the substrate and the tangential line of the side surface of the gate electrode layer is 30 degrees or more and 90 degrees.
less than degrees, preferably 60 degrees or more and 85 degrees or less.

With the above structure, the size of the low resistance region 125 can be controlled. Thereby, the ON current can be improved. Moreover, the characteristics of the transistor can be stabilized.

<<insulating layer 176>>
The insulating layer 176 can be formed using a material similar to that of the insulating layer 175 .

<Method for Manufacturing Transistor 14>
A method for manufacturing the transistor 14 is described with reference to FIGS. Note that the description is used for the same part as that of the manufacturing method of another transistor.

The second insulating film 150a and the conductive film 160 are formed in the trench 174 provided on the metal oxide film 123a.
a (see FIG. 28).

In FIG. 28, the manufacturing process is the same as that in FIG. 7; is 6
It is desirable that the angle be 0 degrees or more and 85 degrees or less.

The gradient can also be obtained in the conductive film 160a facing the insulating layer 175 in the same manner.

Next, by performing planarization processing on the second insulating film 150a and the conductive film 160a,
A gate electrode layer 160 and a gate insulating layer 150 are formed (see FIG. 29).

Next, using the gate electrode layer 160 as a mask, the insulating layer 175 and the gate insulating layer 150 are etched by a dry etching method until the metal oxide film 123a is exposed, thereby forming the metal oxide layer 123 and the insulating layer 176. (see FIG. 30). The insulating layer 176 can function as sidewalls. By using the above steps, the sidewalls can be formed in a self-aligned manner, so that the steps can be simplified.

Next, ion 167 is added (see FIG. 31) to form a low resistance region (see FIG. 32).

Note that since the insulating layer 176 is provided, the size of the low-resistance region can be controlled even if ions are diffused in the lateral direction when heat treatment is performed, and the ions are included in a region to which ions are not added. It is possible. Therefore, the channel length is 100 nm or less, 60 nm or less, 30
Even if the thickness is 20 nm or less, the transistor can be stably operated.

Note that the transistor 14 may have a structure in which an insulating layer 170 is provided (see FIG. 33). Alternatively, the metal oxide layer 123 may be processed and provided (see FIG. 34). Alternatively, the second insulating film 150a to be the gate insulating layer 150 may be provided before the trench is formed (see FIG. 35).

Further, when the angle (gradient) formed by the tangent line between the bottom surface of the substrate and the side surface of the gate electrode layer 160 is large,
It may have a region without the insulating layer 176 (see FIG. 36).

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 2)
<Structure of oxide semiconductor>
The structure of an oxide semiconductor is described below.

Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned
crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor)
uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l
ike oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. As the crystalline oxide semiconductor, a single crystal oxide semiconductor, CAAC-
OS, polycrystalline oxide semiconductor, nc-OS, and the like.

Amorphous structures are generally isotropic with no inhomogeneous structures, metastable states with unfixed atomic arrangements, flexible bond angles, and short-range order but long-range order. It is said that it does not have

That is, a stable oxide semiconductor is completely amorphous.
) cannot be called an oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a perfect amorphous oxide semiconductor. On the other hand, a-li
The ke OS is not isotropic but has an unstable structure with voids.
In terms of being unstable, an a-like OS is physically similar to an amorphous oxide semiconductor.

<CAAC-OS>
First, the CAAC-OS will be explained.

A CAAC-OS is a type of oxide semiconductor including a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD) will be described. For example, when structural analysis is performed by the out-of-plane method on a CAAC-OS having InGaZnO ₄ crystals classified into the space group R-3m, the diffraction angle (2θ) is as shown in FIG. A peak appears near 31°. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has c-axis orientation, and the c-axis is the plane on which the CAAC-OS film is formed. It is also called a plane), or it can be confirmed that it is oriented in a direction substantially perpendicular to the top surface. 2θ is 31°
In addition to peaks in the vicinity, a peak may also appear near 2θ of 36°. The peak near 2θ of 36° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC
-OS preferably does not show this peak.

On the other hand, the in-pla method in which X-rays are incident on the CAAC-OS from a direction parallel to the formation surface
Structural analysis by the ne method reveals a peak near 2θ of 56°. This peak is I
It is assigned to the (110) plane of the crystal of _nGaZnO4 . Further, even if 2θ is fixed around 56° and the sample is rotated around the normal vector of the sample surface (φ axis) and analysis (φ scan) is performed, a clear image is obtained as shown in FIG. No peak appears. On the other hand, single crystal InGaZ
When φ scanning is performed with 2θ fixed around 56° for nO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. 37(C). Therefore, X
Structural analysis using RD confirms that the orientation of the a-axis and b-axis of CAAC-OS is irregular.

Next, CAAC-OS analyzed by electron diffraction will be described. For example, InGaZ
When an electron beam with a probe diameter of 300 nm is incident on the CAAC-OS having nO ₄ crystals in parallel with the surface on which the CAAC-OS is formed, a diffraction pattern (selected area electron diffraction) as shown in FIG. Also called a pattern.) may appear. In this diffraction pattern, In
A spot due to the (009) plane of the GaZnO ₄ crystal is included. Therefore, electron diffraction also shows that the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or upper surface. On the other hand, the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface is shown in FIG.
shown in A ring-shaped diffraction pattern is confirmed from FIG. Therefore, electron diffraction using an electron beam with a probe diameter of 300 nm also shows that the a-axis and b-axis of the pellet contained in CAAC-OS do not have orientation. The first ring in FIG. 37(E) is considered to be caused by the (010) and (100) planes of the InGaZnO ₄ crystal. Also, the second ring in FIG. 37(E) is considered to be caused by the (110) plane or the like.

In addition, a transmission electron microscope (TEM: Transmission Electron Mi
A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS bright-field image and a diffraction pattern using a croscope. On the other hand, even with a high-resolution TEM image, there are cases where the boundaries between pellets, that is, crystal grain boundaries (also called grain boundaries) cannot be clearly confirmed. Therefore, the CAAC
It can be said that -OS is less likely to cause a decrease in electron mobility due to grain boundaries.

FIG. 38(A) shows a high resolution T of the cross section of CAAC-OS observed from a direction substantially parallel to the sample surface.
EM images are shown. For observation of high-resolution TEM images, spherical aberration correction (Spherical Ab
Erration Corrector) function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image is
For example, it can be observed with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd., or the like.

From FIG. 38A, a pellet, which is a region in which metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellets can also be referred to as nanocrystals (nc). In addition, CAAC-OS can be replaced with CANC (C-Axis Aligned Nan
It can also be referred to as an oxide semiconductor having ocrystals. Pellets are CAAC
-It reflects the unevenness of the formation surface or upper surface of the OS, and is parallel to the formation surface or upper surface of the CAAC-OS.

38(B) and 38(C) show CAAC observed from a direction substantially perpendicular to the sample surface.
- Shows a Cs-corrected high-resolution TEM image of the plane of OS. FIGS. 38(D) and 38(E) are
38(B) and 38(C) are image-processed images. The image processing method will be described below. First, the fast Fourier transform (FFT: Fast
An FFT image is obtained by Fourier Transform) processing. Next, mask processing is performed to leave a range between 2.8 nm ⁻¹ and 5.0 nm ⁻¹ on the basis of the origin in the acquired FFT image. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT:
An image processed by Inverse Fast Fourier Transform processing is acquired. An image obtained in this way is called an FFT filtered image. The FFT-filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 38(D), broken lines indicate portions where the lattice arrangement is disturbed. The area enclosed by the dashed line is
One pellet. And the part shown by the broken line is a connection part of a pellet and a pellet. Since the dashed line indicates a hexagonal shape, it can be seen that the pellets have a hexagonal shape. Note that the shape of the pellet is not limited to a regular hexagon, and is often a non-regular hexagon.

In FIG. 38(E), a dotted line indicates a region between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement, and a dashed line indicates the orientation of the lattice arrangement. A clear grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting grid points around the grid point near the dotted line. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because CAAC-OS can tolerate strain due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. Conceivable.

As described above, CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, CA
AC-OS to CAA crystal (c-axis-aligned a-b-pl
It can also be referred to as an oxide semiconductor having an ane-anchored crystal.

CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be degraded by the contamination of impurities or the generation of defects, CAAC-OS can
It can also be said to be an oxide semiconductor with few oxygen vacancies.

Note that the impurities are elements other than the main component of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon that has a stronger bonding force with oxygen than a metal element that constitutes an oxide semiconductor deprives the oxide semiconductor of oxygen, thereby disturbing the atomic arrangement of the oxide semiconductor and lowering the crystallinity. be a factor. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have large atomic radii (or molecular radii), and thus disturb the atomic arrangement of the oxide semiconductor and deteriorate crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, or the like. For example, an impurity contained in an oxide semiconductor may act as a carrier trap or a carrier generation source. For example, oxygen vacancies in an oxide semiconductor may trap carriers or generate carriers by trapping hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ ,
More preferably, the carrier density is less than 1×10 ¹⁰ /cm ³ , and the oxide semiconductor can have a carrier density of 1×10 ⁻⁹ /cm ³ or more. Such an oxide semiconductor is called a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that the oxide semiconductor has stable characteristics.

<nc-OS>
Next, the nc-OS will be explained.

A case where the nc-OS is analyzed by XRD will be described. For example, when nc-OS is subjected to structural analysis by the out-of-plane method, no peak indicating orientation appears. That is, the crystal of nc-OS has no orientation.

Also, for example, an nc-OS having a crystal of InGaZnO ₄ is thinned to a thickness of 34 nm.
When an electron beam with a probe diameter of 50 nm is made incident parallel to the surface to be formed into the area of , as shown in FIG.
A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) is observed. FIG. 39B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample. A plurality of spots are observed in the ring-shaped region from FIG. 39(B). Therefore, the orderliness of the nc-OS is not confirmed when an electron beam with a probe diameter of 50 nm is incident, but the orderliness is confirmed when an electron beam with a probe diameter of 1 nm is incident.

Further, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm,
As shown in FIG. 39(C), an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal pattern may be observed. Therefore, it can be seen that the nc-OS has highly ordered regions, that is, crystals, in the thickness range of less than 10 nm. In addition, since the crystals are oriented in various directions, there are regions where regular electron diffraction patterns are not observed.

FIG. 39D shows a Cs-corrected high-resolution TEM image of the cross section of the nc-OS observed from a direction substantially parallel to the formation surface. In a high-resolution TEM image, the nc-OS has regions where crystal parts can be confirmed, such as the parts indicated by auxiliary lines, and regions where clear crystal parts cannot be confirmed. The crystal part included in the nc-OS has a size of 1 nm or more and 10 nm or less, and in particular, often has a size of 1 nm or more and 3 nm or less. In addition, the size of the crystal part is 1
An oxide semiconductor having a thickness of more than 0 nm and less than or equal to 100 nm is referred to as a microcrystalline oxide semiconductor (micro
It is sometimes called a crystalline oxide semiconductor). In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed. Note that the nanocrystals may share the same origin as the pellets in CAAC-OS. Therefore, the crystal part of the nc-OS may be called a pellet hereinafter.

Thus, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

In addition, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS is
It can also be referred to as an oxide semiconductor having random aligned nanocrystals (RANC) or an oxide semiconductor having non-aligned nanocrystals (NANC).

An nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. for that reason,
An nc-OS has a lower defect level density than an a-like OS and an amorphous oxide semiconductor. However, nc-OS shows no regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher defect level density than the CAAC-OS.

<a-like OS>
An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.

FIG. 40 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 40A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. Figure 40 (B
) is a high-resolution cross-sectional TEM image of an a-like OS after electron (e ⁻ ) irradiation of 4.3×10 ⁸ e ⁻ /nm ² . From FIGS. 40A and 40B, a-like OS
It can be seen that striped bright regions extending in the longitudinal direction are observed from the start of electron irradiation. Also, it can be seen that the shape of the bright region changes after electron irradiation. The bright regions are presumed to be void or low-density regions.

Due to the voids, the a-like OS is an unstable structure. Below, a-like
Structural changes due to electron irradiation are shown to show that OS has an unstable structure compared to CAAC-OS and nc-OS.

As samples, a-like OS, nc-OS and CAAC-OS are prepared. All samples are In--Ga--Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. A high-resolution cross-sectional TEM image shows that each sample has a crystal part.

It should be noted that the unit cell of the crystal of InGaZnO ₄ has three In—O layers, and the Ga—Zn—
It is known to have a structure in which a total of nine layers, including six O layers, are layered in the c-axis direction. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, which is found to be 0.29 nm from crystal structure analysis. Therefore, hereinafter, the portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less will be referred to as InGaZn.
It was regarded as the crystalline part of _O4 . The lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 41 shows an example of investigating the average size of crystal parts (22 to 30 points) of each sample. The length of the lattice fringes described above is the size of the crystal part. From FIG. 41, a-like
It can be seen that the crystal part of the OS increases in size according to the cumulative dose of electrons used for obtaining a TEM image. From FIG. 41, the crystal part (also referred to as the initial nucleus), which had a size of about 1.2 nm at the initial stage of observation by TEM, was reduced to a cumulative dose of 4.2×10 ⁸ e ⁻ of electrons (e ⁻ ).
It can be seen that the film grows to a size of about 1.9 nm at /nm ² . On the other hand, nc
-OS and CAAC-OS, the cumulative dose of electrons from the start of electron irradiation is 4.2×10 ⁸
It can be seen that there is no change in the crystal part size in the range up to e ⁻ /nm ² . From FIG. 41, regardless of the cumulative dose of electrons, the crystal part size of nc-OS and CAAC-OS is
It can be seen that they are about 1.3 nm and about 1.8 nm, respectively. For electron beam irradiation and TEM observation, Hitachi transmission electron microscope H-9000NAR was used. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7×10 ⁵ e ⁻ /(nm ² ·s), and a diameter of the irradiated region of 230 nm.

Thus, in the a-like OS, the growth of the crystal part may be observed by electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of crystal parts due to electron irradiation is observed. That is, compared to nc-OS and CAAC-OS, a-like OS has
It can be seen that the structure is unstable.

In addition, since it has voids, the a-like OS has a lower density structure than the nc-OS and CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Also, the density of nc-OS and CAAC
The density of -OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form a film of an oxide semiconductor whose density is less than 78% of that of a single crystal.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ³ . Further, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio],
Density of nc-OS and density of CAAC-OS are 5.9 g/cm ³ or more and 6.3 g/cm ³
is less than

If single crystals with the same composition do not exist, the density corresponding to a single crystal with a desired composition can be estimated by combining single crystals with different compositions at an arbitrary ratio. The density corresponding to the single crystal with the desired composition is, with respect to the ratio of combining the single crystals with different compositions,
It can be estimated using a weighted average. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and have various characteristics. Note that the oxide semiconductor is, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS,
A laminated film containing two or more of the CAAC-OS may be used.

<Configuration of CAC>
In the following, CAC (Cloud Aligned
Complementary) - The configuration of the OS will be explained.

CAC is, for example, one structure of a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following description, one or more metal elements are unevenly distributed in the oxide semiconductor, and the region containing the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2
A mixed state of nanometers or less in size or in the vicinity thereof is also referred to as a mosaic shape or a patch shape.

For example, CAC-IGZ in In-Ga-Zn oxide (hereinafter also referred to as IGZO)
O is indium oxide (hereinafter, InO _X1 (X1 is a real number greater than 0)).
, or indium zinc oxide (hereinafter In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z
2 is a real number greater than 0). ) and gallium oxide (hereafter GaO _X3 (X3 is 0
real number greater than ). ), or gallium zinc oxide (hereinafter Ga _X4 Zn _Y4 O
Let _Z4 (X4, Y4, and Z4 are real numbers greater than 0). ) and the like, the material is separated into a mosaic shape, and mosaic InO _X1 or In _X2 Zn _Y2 O _Z2
is uniformly distributed in the film (hereinafter also referred to as a cloud shape).

That is, CAC-IGZO has a region mainly composed of GaO _X3 and a region containing In _X2 Zn _Y2 O _Z
2 or a region containing InO _{2 X1} as a main component. In this specification, for example, the first region means that the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region. Assume that the concentration of In is higher than that of the region No. 2.

Note that IGZO is a common name, and may refer to one compound of In, Ga, Zn, and O. Representative examples include InGaO ₃ (ZnO) _m1 (m1 is a natural number), or In _(
1+x0) Ga _(1−x0) O ₃ (ZnO) _m0 (−1≦x0≦1, m0 is an arbitrary number).

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. note that,
A CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

CAC, on the other hand, relates to material composition. CAC is a material structure containing In, Ga, Zn, and O, in which a part of the nanoparticle-like region mainly composed of Ga and a part of In
A region observed in the form of nanoparticles containing as a main component refers to a configuration in which regions are randomly dispersed in a mosaic pattern. Therefore, in CAC, the crystal structure is a secondary factor.

Note that CAC does not include a laminated structure of two or more types of films with different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between a region containing GaO _X3 as a main component and a region containing In _{X2 ZnY2} O _Z2 or InO _X1 as a main component.

<Analysis of CAC-IGZO>
Next, measurement results of an oxide semiconductor deposited over a substrate using various measurement methods are described.

≪Structure of sample and preparation method≫
Nine samples according to one embodiment of the present invention are described below. Each sample is manufactured under different conditions of substrate temperature and oxygen gas flow rate when forming an oxide semiconductor film. Note that the sample has a structure including a substrate and an oxide semiconductor over the substrate.

A method for manufacturing each sample will be described.

First, a glass substrate is used as a substrate. Subsequently, a 100-nm-thick In--Ga--Zn oxide is formed as an oxide semiconductor over the glass substrate using a sputtering apparatus. The film formation conditions are that the pressure in the chamber is 0.6 Pa, and the target is an oxide target (
In:Ga:Zn=4:2:4.1 [atomic ratio]) is used. Also, AC power of 2500 W is supplied to the oxide target installed in the sputtering apparatus.

In addition, as a condition for forming an oxide film, the substrate temperature is set to a temperature that is not intentionally heated (hereinafter referred to as
R. T. Also called ), 130°C, or 170°C. Nine samples were prepared by setting the flow ratio of the oxygen gas to the mixed gas of Ar and oxygen (hereinafter also referred to as the oxygen gas flow ratio) to 10%, 30%, or 100%.

<<Analysis by X-ray diffraction>>
In this item, nine samples were subjected to X-ray diffraction (XRD: X-ray diffraction
n) Describe the results of the measurements. In addition, as an XRD device, D
8 ADVANCE was used. In addition, the condition is θ/2 by the Out-of-plane method
In the θ scan, the scanning range is 15 deg. to 50deg. , a step width of 0.02 de
g. , a scanning speed of 3.0 deg. / minutes.

FIG. 68 shows the result of XRD spectrum measurement using the out-of-plane method.
In FIG. 68, the upper part shows the measurement results of the sample with a substrate temperature condition of 170° C. during film formation, the middle part shows the measurement results of the sample with a substrate temperature condition of 130° C. during film formation, and the lower part shows the measurement results during film formation. The substrate temperature condition of R.I. T. shows the measurement results for the sample. In addition, the left column shows the measurement results for the sample with the oxygen gas flow ratio condition of 10%, and the middle column shows the oxygen gas flow ratio condition of 3%.
The measurement results for the 0% sample are shown, and the right column shows the measurement results for the sample with the oxygen gas flow ratio condition of 100%.

The XRD spectrum shown in FIG. 68 increases the peak intensity near 2θ=31° by increasing the substrate temperature during film formation or by increasing the ratio of the oxygen gas flow rate during film formation. The peak near 2θ = 31° is a crystalline IGZO compound (CAAC (c-axis aligned crystal
ine)-IGZO. ).

Further, in the XRD spectrum shown in FIG. 68, a clear peak did not appear as the substrate temperature during film formation was lower or as the oxygen gas flow rate ratio was smaller. Therefore, it can be seen that no orientation in the ab plane direction and the c-axis direction of the measurement region is observed in the sample with a low substrate temperature during film formation or a low oxygen gas flow rate ratio.

≪Analysis by electron microscope≫
In this item, the substrate temperature R.O.D. T. , and a sample prepared with an oxygen gas flow rate ratio of 10%, HAADF (High-Angle Annular Dark Field)-ST
EM (Scanning Transmission Electron Micros)
(hereinafter referred to as HAADF-S
An image acquired by a TEM is also called a TEM image. ).

The result of image analysis of a planar image (hereinafter also referred to as a planar TEM image) and a cross-sectional image (hereinafter also referred to as a cross-sectional TEM image) obtained by HAADF-STEM will be described.
The TEM image was observed using a spherical aberration correction function. The HAADF-STEM image was taken using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd., with an acceleration voltage of 200 kV and an electron beam with a beam diameter of about 0.1 nmφ.

FIG. 69A shows the substrate temperature R.D. during film formation. T. , and a planar TEM image of a sample produced with an oxygen gas flow ratio of 10%. FIG. 69B shows the substrate temperature R.D. during film formation. T. , and a cross-sectional TEM image of a sample produced with an oxygen gas flow ratio of 10%.

<<Analysis of Electron Diffraction Pattern>>
In this item, the substrate temperature R.O.D. T. , and an oxygen gas flow ratio of 10%, and an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) to obtain an electron beam diffraction pattern.

As shown in FIG. 69(A), the substrate temperature R.D. T. , and an electron beam diffraction pattern indicated by black point a1, black point a2, black point a3, black point a4, and black point a5 in the planar TEM images of the samples produced at an oxygen gas flow ratio of 10%. The observation of the electron beam diffraction pattern is performed while moving at a constant speed from the position of 0 seconds to the position of 35 seconds while irradiating the electron beam. The result of black point a1 is shown in FIG. 69(C), the result of black point a2 is shown in FIG. 69(D), and the result of black point a3 is shown in FIG.
E), the result of black point a4 is shown in FIG. 69(F), and the result of black point a5 is shown in FIG. 69(G).

From FIGS. 69(C), 69(D), 69(E), 69(F), and 69(G),
A circular (ring-like) area with high brightness can be observed. Also, a plurality of spots can be observed in a ring-shaped area.

Also, the substrate temperature R.D. during film formation shown in FIG. T. , and an electron beam diffraction pattern indicated by black points b1, black points b2, black points b3, black points b4, and black points b5 in the cross-sectional TEM images of the samples produced at an oxygen gas flow rate of 10%. The result of black point b1 is shown in FIG. 69(H), the result of black point b2 is shown in FIG. 69(I), the result of black point b3 is shown in FIG.
K), and the result of black point b5 are shown in FIG. 69(L).

From FIGS. 69(H), 69(I), 69(J), 69(K), and 69(L),
A ring-shaped area with high brightness can be observed. Also, a plurality of spots can be observed in a ring-shaped area.

Here, for example, when an electron beam _{with a probe diameter of 300 nm is incident parallel to the sample surface to a CAAC-OS having InGaZnO 4 crystals} , the (009
) surface, a diffraction pattern containing spots is seen. In other words, CAAC-OS has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or top surface. On the other hand, when an electron beam with a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface, a ring-shaped diffraction pattern is confirmed. That is, the CAAC-OS has the a-axis and b
It can be seen that the axis has no orientation.

In addition, an oxide semiconductor having microcrystals (nano crystalline oxide
semiconductor. Hereinafter, it will be referred to as nc-OS. ), a large probe diameter (
For example, when electron beam diffraction is performed using an electron beam of 50 nm or more), a diffraction pattern such as a halo pattern is observed. Also, when nanobeam electron diffraction using an electron beam with a small probe diameter (for example, less than 50 nm) is performed on the nc-OS, bright points (spots) are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS, a circular (ring-like) region with high brightness may be observed. Furthermore, a plurality of bright spots may be observed in the ring-shaped area.

Substrate temperature R.D. during film formation T. , and an oxygen gas flow ratio of 10%, the electron beam diffraction pattern has a ring-shaped region of high brightness and a plurality of bright spots in the ring region. Therefore,
Substrate temperature R.D. during film formation T. , and an oxygen gas flow ratio of 10%, the electron beam diffraction pattern is nc-OS, and does not have orientation in the planar direction and the cross-sectional direction.

From the above, an oxide semiconductor with a low substrate temperature during film formation or a low oxygen gas flow ratio is
It can be inferred that the oxide semiconductor film has properties that are clearly different from those of an oxide semiconductor film having an amorphous structure and those having a single crystal structure.

≪Elemental analysis≫
In this item, energy dispersive X-ray spectroscopy (EDX: Energy Dispersive
EDX mapping was acquired and evaluated using X-ray spectroscopy) to determine the substrate temperature R.E.M. T. , and the results of elemental analysis of the samples produced at an oxygen gas flow ratio of 10% will be described. For the EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used as an elemental analyzer. A Si drift detector is used to detect X-rays emitted from the sample.

In the EDX measurement, an electron beam is irradiated to each point in the region to be analyzed of the sample, and the energy and the number of occurrences of characteristic X-rays generated from the sample are measured to obtain an EDX spectrum corresponding to each point. In this embodiment, the peaks of the EDX spectrum at each point are defined as the electronic transition to the L shell of the In atom, the electronic transition to the K shell of the Ga atom, the electronic transition to the K shell of the Zn atom, and the K shell of the O atom. and calculate the ratio of each atom at each point. By performing this on the analysis target region of the sample, EDX mapping showing the distribution of the ratio of each atom can be obtained.

FIG. 70 shows the substrate temperature R.D. during film formation. T. , and an EDX mapping of a cross-section of a sample produced at an oxygen gas flow rate of 10%. FIG. 70(A) shows EDX mapping of Ga atoms (
The ratio of Ga atoms to all atoms is in the range of 1.18 to 18.64 [atomic %]. ). FIG. 70B is EDX mapping of In atoms (the ratio of In atoms to all atoms is in the range of 9.28 to 33.74 [atomic %]). Figure 70 (
C) EDX mapping of Zn atoms (ratio of Zn atoms to total atoms is 6.69-2
The range is 4.99 [atomic %]. ). 70(A) and 70(B)
), and FIG. 70(C) show the substrate temperature R.D. T. , and the cross section of the samples produced with the oxygen gas flow rate ratio of 10%. In addition, the EDX mapping is
In the range, the more elements measured, the brighter, and the fewer elements measured, the darker.
Brightness and darkness indicate the ratio of elements. Also, the magnification of the EDX mapping shown in FIG. 70 is 7.2 million times.

In the EDX mapping shown in FIGS. 70(A), 70(B), and 70(C), a distribution of relative light and dark can be seen in the image, and the substrate temperature R.D. T. , and an oxygen gas flow rate ratio of 10%
It can be confirmed that each atom has a distribution in the sample prepared in . Here, attention is paid to the range surrounded by solid lines and the range surrounded by broken lines shown in FIGS. 70(A), 70(B) and 70(C).

In FIG. 70A, the range surrounded by solid lines includes many relatively dark areas, and the range surrounded by dashed lines includes many relatively bright areas. Further, in FIG. 70B, the range surrounded by solid lines includes many relatively bright areas, and the range surrounded by broken lines includes many relatively dark areas.

That is, the area surrounded by the solid line is the area with relatively many In atoms, and the area surrounded by the broken line is the area with relatively few In atoms. Here, in FIG. 70(C), in the range surrounded by the solid line,
The right side is the relatively bright area and the left side is the relatively dark area. Therefore, the range surrounded by the solid line is a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component.

Also, the area surrounded by the solid line is the area with relatively few Ga atoms, and the area surrounded by the broken line is the area with relatively many Ga atoms. In FIG. 70(C), in the area enclosed by the dashed line, the upper left area is a relatively bright area, and the lower right area is a relatively dark area. Therefore, the range enclosed by the dashed line is a region where the main component is GaO _X3 or Ga _X4 Zn _Y4 O _Z4 .

70(A), 70(B), and 70(C), the distribution of In atoms is Ga
A region in which InO _X1 is the main component is relatively more uniformly distributed than atoms, and _InX2
They seem to be connected to each other through a region _{containing ZnY2OZ2} as a main component. In this way, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is formed to spread like a cloud.

In this way, the region mainly composed of GaO _X3 and In _X2 Zn _Y2 O _Z2 or InO
An In—Ga—Zn oxide having a structure in which regions containing _X1 as a main component are unevenly distributed and mixed can be referred to as CAC-IGZO.

Also, the crystal structure of CAC has an nc structure. The nc structure of CAC has several or more bright points (spots) in an electron beam diffraction image, in addition to the bright points (spots) caused by IGZO containing a single crystal, polycrystal, or CAAC structure. Alternatively, the crystal structure is defined as a ring-shaped region of high brightness appearing in addition to several or more bright points (spots).

70(A), 70(B), and 70(C), the size of the region whose main component is GaO _X3 and the region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 is observed at 0.5 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. In EDX mapping, the diameter of the region containing each metal element as a main component is preferably 1 nm or more and 2 nm or less.

As described above, CAC-IGZO has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of an IGZO compound. That is, CAC-IGZO is GaO
A region containing _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are phase-separated from each other, and the regions containing each element as a main component have a mosaic structure. . Therefore, when CAC-IGZO is used in a semiconductor device, the properties attributed to GaO _X3 and the like and the properties attributed to In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, resulting in a high on-current. (I _on ), and high field effect mobility (μ) can be achieved.

In addition, a semiconductor element using CAC-IGZO has high reliability. Therefore, the CAC-IGZ
O is most suitable for various semiconductor devices including displays.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 3)
In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to drawings.

<Cross-sectional structure>
FIG. 42A shows a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. 42(A), X
The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. Figure 42(A)
has a transistor 2200 using a first semiconductor material in its lower portion and a transistor 2100 using a second semiconductor material in its upper portion. In FIG. 42(A),
As the transistor 2100 using the second semiconductor material, an example in which the transistor described in any of the above embodiments is applied is shown. Note that the left side of the one-dot chain line is the cross section in the channel length direction of the transistor, and the right side is the cross section in the channel width direction.

Preferably, the first semiconductor material and the second semiconductor material are materials having different bandgap. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.). ), and the second semiconductor material can be an oxide semiconductor. A transistor using single crystal silicon or the like as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can have a small S value (subthreshold value) and a miniaturized transistor by using the transistor described as an example in the above embodiment. be. In addition, since the switching speed is high, high-speed operation is possible, and since the off current is low, the leakage current is small.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used depending on the circuit. In addition to using the transistor of one embodiment of the present invention using an oxide semiconductor, the specific structure of the semiconductor device, such as the material and structure, need not be limited to those shown here.

In the structure shown in FIG. 42A, the transistor 2100 is provided over the transistor 2200 with insulators 2201 and 2207 interposed therebetween. Moreover, the transistor 2200
A plurality of wirings 2202 is provided between the transistor 2100 and the transistor 2100 . Wirings and electrodes provided in upper and lower layers are electrically connected by a plurality of plugs 2203 embedded in various insulators. An insulator 2204 covering the transistor 2100 and a wiring 2205 over the insulator 2204 are provided.

By stacking two types of transistors in this way, the area occupied by the circuit can be reduced.
A plurality of circuits can be arranged with higher density.

Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer,
Hydrogen in the insulator provided near the semiconductor film of the transistor 2200 terminates dangling bonds of silicon and has the effect of improving the reliability of the transistor 2200 . on the other hand,
When an oxide semiconductor is used for the transistor 2100 provided in an upper layer, the transistor 21
Hydrogen in the insulator provided in the vicinity of the semiconductor film of 00 is one of the factors that generate carriers in the oxide semiconductor, which might reduce the reliability of the transistor 2100 . Therefore, in the case where the transistor 2100 using an oxide semiconductor is stacked over the transistor 2200 using a silicon-based semiconductor material, the insulator 2207 having a function of preventing diffusion of hydrogen is especially provided therebetween. Effective. insulator 220
7 improves the reliability of the transistor 2200 by confining hydrogen in the lower layer, and suppresses the diffusion of hydrogen from the lower layer to the upper layer, thereby improving the reliability of the transistor 2100 at the same time.

As the insulator 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

Further, a block film having a function of preventing diffusion of hydrogen is preferably formed over the transistor 2100 so as to cover the transistor 2100 including an oxide semiconductor film. As the block film, a material similar to that of the insulator 2207 can be used, and aluminum oxide is particularly preferably used. The aluminum oxide film has a high blocking effect of preventing both oxygen and impurities such as hydrogen and moisture from penetrating through the film. Therefore, by using the aluminum oxide film as the block film that covers the transistor 2100, oxygen is prevented from being released from the oxide semiconductor film included in the transistor 2100, and water and hydrogen are prevented from entering the oxide semiconductor film. can be prevented. Note that the block film may be used by stacking the insulator 2204 or may be provided below the insulator 2204 .

Note that the transistor 2200 can be not only a planar transistor but also various types of transistors. For example, a FIN (fin) type, a TRI-GATE (tri-gate) type transistor, or the like can be used. An example of a cross-sectional view in that case is
It is shown in FIG. An insulator 2212 is provided on the semiconductor substrate 2211 . The semiconductor substrate 2211 has a projection (also referred to as a fin) with a thin tip. An insulator may be provided on the projection. In addition, the tip of the protrusion may not be thin, and may be, for example, a substantially rectangular parallelepiped protrusion or a protrusion with a thick tip. A gate insulator 2214 is provided on the protrusion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. A semiconductor substrate 2211 has source and drain regions 2215 formed therein. Note that although an example in which the semiconductor substrate 2211 has a projection is shown here, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, by processing an SOI substrate,
A semiconductor region having a convex portion may be formed.

<Example of circuit configuration>
In the above structure, various circuits can be formed by connecting the electrodes of the transistor 2100 and the transistor 2200 as appropriate. An example of a circuit configuration that can be realized by using a semiconductor device of one embodiment of the present invention is described below.

<CMOS inverter circuit>
The circuit diagram shown in FIG. 42B is a so-called CMO in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
The configuration of the S inverter is shown.

<CMOS analog switch>
The circuit diagram in FIG. 42C shows a structure in which the sources and drains of the transistors 2100 and 2200 are connected. With such a configuration,
It can function as a so-called CMOS analog switch.

<Example of storage device>
FIG. 43 shows an example of a semiconductor device (storage device) that uses a transistor of one embodiment of the present invention, can hold memory contents even when power is not supplied, and has no limit on the number of times of writing.
shown in

A semiconductor device illustrated in FIG. 43A includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400 .
Note that the transistor described in the above embodiment can be used as the transistor 3300 .

FIG. 43B shows a cross-sectional view of the semiconductor device shown in FIG. 43A. Although the semiconductor device in the cross-sectional view shows a structure in which the transistor 3300 is provided with a back gate, a structure in which the back gate is not provided may be employed.

The transistor 3300 is a transistor whose channel is formed in a semiconductor including an oxide semiconductor. Since the transistor 3300 has a low off-state current, data can be retained for a long time by using the transistor 3300 . In other words, a semiconductor memory device that does not require a refresh operation or has an extremely low frequency of refresh operations can be provided, so that power consumption can be sufficiently reduced.

43A, a first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and a second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. In FIG. A third wiring 3003 is electrically connected to one of the source electrode and the drain electrode of the transistor 3300 , and a fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300 . A gate electrode of the transistor 3200 is electrically connected to the other of the source electrode and the drain electrode of the transistor 3300 and the first terminal of the capacitor 3400 , and the fifth wiring 3005 is connected to the second terminal of the capacitor 3400 . is electrically connected to

In the semiconductor device illustrated in FIG. 43A, by utilizing the feature that the potential of the gate electrode of the transistor 3200 can be held, data can be written, held, and read as follows.

Describe writing and retention of information. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor 3400 . That is, the gate electrode of the transistor 3200 has
A predetermined charge is applied (writing). Here, it is assumed that one of charges that give two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the charge applied to the gate electrode of the transistor 3200 is held (held).

Since the off-state current of the transistor 3300 is extremely low, charge in the gate electrode of the transistor 3200 is retained for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 while a predetermined potential (constant potential) is applied to the first wiring 3001, , the second wiring 3002 take different potentials. In general, if transistor 3200 is an n-channel type, transistor 3200
Apparent threshold voltage V _{th_H} when high level charge is applied to the gate electrode of
is lower than the apparent threshold V _{th_L} when the gate electrode of the transistor 3200 is supplied with low-level charge. Here, the apparent threshold voltage is
It refers to the potential of the fifth wiring 3005 necessary for turning on the transistor 3200 . Therefore, by setting the potential of the fifth wiring 3005 to the potential _V0 between _{Vth_H} and _{Vth_L} , the charge applied to the gate electrode of the transistor 3200 can be determined. For example, when high-level charge is applied in writing, the transistor 3200 is turned on when the potential of the fifth wiring 3005 becomes V ₀ (>V _{th — H} ). When low-level charge is applied, the transistor 3200 remains “off” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th — L} ). Therefore, by determining the potential of the second wiring 3002, the held information can be read.

Note that when memory cells are arranged in an array and used, it is necessary to be able to read only the information of a desired memory cell. For example, in a memory cell from which information is not read, the potential at which the transistor 3200 is turned off regardless of the state of the gate, that is, V _t
By applying a potential lower than _{h_H} to the fifth wiring 3005, only data in a desired memory cell can be read. Alternatively, in a memory cell from which data is not read, a potential at which the transistor 3200 is turned on regardless of the state of the gate, that is, a potential higher than _{Vth_L} is applied to the fifth wiring 3005 to obtain the desired memory. It is sufficient to have a configuration that allows only the information of the cell to be read.

The semiconductor device shown in FIG. 43C is similar to that shown in FIG. 43A in that the transistor 3200 is not provided.
). In this case as well, information can be written and held by operations similar to those described above.

Next, reading of information will be described. When the transistor 3300 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are brought into conduction, and electric charge is redistributed between the third wiring 3003 and the capacitor 3400 . As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is the potential of the first terminal of the capacitor 3400 (
Alternatively, it takes a different value depending on the charge accumulated in the capacitor 3400).

For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third
CB is the capacitance component of the wiring 3003, and VB0 is the potential of the third wiring 3003 before charge redistribution. Then, the potential of the third wiring 3003 after charge redistribution is (CB×
VB0+C*V)/(CB+C). Therefore, assuming that the potential of the first terminal of the capacitor 3400 has two states of V1 and V0 (V1>V0) as the state of the memory cell, the potential of the third wiring 3003 when the potential V1 is held. Potential (=(CB×VB0+C×V1)
/(CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=(C
B*VB0+C*V0)/(CB+C)).

By comparing the potential of the third wiring 3003 with a predetermined potential, information can be read.

In this case, a transistor made of the first semiconductor material is used in a driver circuit for driving a memory cell, and a transistor made of the second semiconductor material is stacked over the driver circuit as the transistor 3300. And it is sufficient.

In the semiconductor device described in this embodiment, memory data can be retained for an extremely long time by using a transistor including an oxide semiconductor for a channel formation region and having extremely low off-state current. In other words, the refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, memory contents can be retained for a long time even when power is not supplied (however, the potential is preferably fixed).

In addition, the semiconductor device described in this embodiment mode does not require a high voltage for writing data, and there is no problem of element deterioration. For example, there is no need to inject electrons into the floating gate or extract electrons from the floating gate, unlike conventional nonvolatile memories.
Problems such as deterioration of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limitation on the number of rewritable times, which is a problem in conventional nonvolatile memories, and reliability is dramatically improved. Furthermore, high-speed operation can be easily achieved because information is written depending on whether the transistor is on or off.

By using the semiconductor device described in this embodiment, a memory device with low power consumption and high capacity (eg, 1 terabit or more) can be manufactured.

In this specification and the like, active elements (transistors, diodes, etc.), passive elements (
A person skilled in the art may be able to configure one embodiment of the invention without specifying connection destinations of all terminals included in a capacitor, a resistor, and the like. In other words, it can be said that one aspect of the invention is clear without specifying the connection destination. If the content specifying the connection destination is described in this specification, etc., and if it is possible to determine that an aspect of the invention that does not specify the connection destination is described in this specification, etc. There is In particular, when a plurality of cases can be considered as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, by specifying the connection destination only for some terminals that have active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.),
It may be possible to constitute an aspect of the invention.

Note that in this specification and the like, a person skilled in the art may be able to specify the invention if at least the connection destination of a circuit is specified. Alternatively, if at least the function of a certain circuit is specified, a person skilled in the art may be able to specify the invention. That is, it can be said that one aspect of the invention is clear by specifying the function. In some cases, it may be possible to determine that one aspect of the invention whose function is specified is described in this specification and the like. Therefore, even if the function of a certain circuit is not specified, if the connection destination is specified, it is disclosed as one mode of the invention and can constitute one mode of the invention. Alternatively, if the function of a certain circuit is specified without specifying the connection destination, it is disclosed as one mode of the invention and can constitute one mode of the invention.

Note that, in this specification and the like, it is possible to configure one aspect of the invention by extracting a part of a diagram or text described in one embodiment. therefore,
When a figure or text describing a certain part is described, the content of the part of the figure or text is also disclosed as one aspect of the invention, and can constitute one aspect of the invention. Assume that there is Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductors, organic materials, inorganic materials, parts, devices, operation methods, manufacturing methods, etc. In the drawings or sentences in which one or more of are described, it is possible to take out a part thereof and constitute one aspect of the invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M<N) circuit elements (transistors, capacitors, etc.) etc.) to form one aspect of the invention. As another example, N
It is possible to configure one embodiment of the invention by extracting M layers (M is an integer and M<N) from a cross-sectional view having layers (N is an integer). As yet another example, N (
N is an integer) from the flow chart configured with M elements (M is an integer and M<N)
It is possible to construct one aspect of the invention by extracting the elements of.

<Imaging device>
An imaging device according to an aspect of the present invention will be described below.

FIG. 44A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 has a pixel section 210 , a peripheral circuit 260 for driving the pixel section 210 , a peripheral circuit 270 , a peripheral circuit 280 , and a peripheral circuit 290 . The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more).
The peripheral circuit 260 , the peripheral circuit 270 , the peripheral circuit 280 , and the peripheral circuit 290 each have a function of connecting to the plurality of pixels 211 and supplying signals for driving the plurality of pixels 211 . Note that in this specification and the like, all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like may be referred to as a "peripheral circuit" or a "drive circuit." For example, the peripheral circuit 260 can be said to be part of the peripheral circuit.

Also, the peripheral circuit has at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Further, the peripheral circuit may be formed over the substrate forming the pixel portion 210 . Also, the peripheral circuit may use a semiconductor device such as an IC chip for part or all of it. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted.

Further, as shown in FIG. 44B, in the pixel portion 210 included in the imaging device 200, the pixels 211 may be tilted. By arranging the pixels 211 at an angle, it is possible to shorten the pixel interval (pitch) in the row direction and the column direction. Thereby, the quality of imaging in the imaging device 200 can be further improved.

<Pixel configuration example 1>
A color image display is realized by configuring one pixel 211 of the imaging device 200 with a plurality of sub-pixels 212, and combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength band. You can get information for

FIG. 45A is a plan view showing an example of pixels 211 for acquiring a color image. A pixel 211 illustrated in FIG. 45A includes a sub-pixel 212 (hereinafter also referred to as a “sub-pixel 212R”) provided with a color filter that transmits light in the wavelength band of red (R) and wavelength of green (G). A sub-pixel 212 provided with a color filter that transmits light in the band (hereinafter also referred to as a “sub-pixel 212G”) and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band.
(hereinafter also referred to as “sub-pixel 212B”). A sub-pixel 212 can function as a photosensor.

The subpixels 212 (the subpixels 212R, 212G, and 212B) are connected to the wirings 23
1, electrically connected to the wirings 247 , 248 , 249 , and 250 . In addition, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are connected to independent wirings 25, respectively.
3 is connected. In this specification and the like, for example, the wiring 248 and the wiring 249 connected to the pixel 211 in the n-th row (n is an integer of 1 to p) are replaced with a wiring 248[n].
and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the m-th column (m is an integer equal to or greater than q and equal to or less than q) is described as a wiring 253[m]. Note that FIG.
), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the m-th column is designated as the wiring 2
53[m]R, the wiring 253[m]G that connects to the sub-pixel 212G, and the wiring 253[m]B that connects to the sub-pixel 212B. The sub-pixel 212 is electrically connected to the peripheral circuit through the wiring.

In addition, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 45B shows a sub-pixel 212 of a pixel 211 arranged in n rows (n is an integer of 1 or more and p or less and m columns (m is an integer of 1 or more and q or less)) and sub-pixels 212 adjacent to the pixels 211 . An example of connection of sub-pixels 212 included in a pixel 211 arranged in n+1 rows and m columns is shown. In FIG. 45(B), n
The sub-pixel 212R arranged in row m column and the sub-pixel 212R arranged in n+1 row m column are connected via the switch 201 . In addition, sub-pixels 212G arranged in n rows and m columns, and n
A sub-pixel 212G arranged at +1 row and m column is connected via a switch 202 . Also, the sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n+1 rows and m columns are connected via the switch 203 .

Note that the color filters used for the sub-pixels 212 are not limited to red (R), green (G), and blue (B), and transmit cyan (C), yellow (Y), and magenta (M) light, respectively. Color filters may also be used. A full-color image can be obtained by providing one pixel 211 with sub-pixels 212 that detect light in three different wavelength bands.

Alternatively, in addition to the sub-pixels 212 provided with color filters that transmit red (R), green (G), and blue (B) light, color filters that transmit yellow (Y) light are provided. Pixels 211 with sub-pixels 212 may be used. Alternatively, cyan (C), yellow (Y
) and sub-pixels 212 provided with color filters that transmit magenta (M) light, and sub-pixels 212 provided with color filters that transmit blue (B) light.
1 may be used. Sub-pixel 2 for detecting light of four different wavelength bands in one pixel 211
By providing 12, it is possible to further improve the color reproducibility of the acquired image.

Further, for example, in FIG. 45A, sub-pixels 212 that detect light in the red wavelength band, sub-pixels 212 that detect light in the green wavelength band, and sub-pixels 212 that detect light in the blue wavelength band
, the ratio of the number of pixels (or light receiving area ratio) may not be 1:1:1. For example, a Bayer array having a pixel number ratio (light-receiving area ratio) of red:green:blue=1:2:1 may be used. or,
The pixel number ratio (light-receiving area ratio) may be red:green:blue=1:6:1.

Note that one sub-pixel 212 may be provided in the pixel 211, but two or more sub-pixels are preferable. For example, by providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy can be increased and the reliability of the imaging device 200 can be increased.

IR (IR: Infrared) that absorbs or reflects visible light and transmits infrared light
By using a filter, the imaging device 200 that detects infrared light can be realized.

Moreover, by using an ND (Neutral Density) filter (dark filter), it is possible to prevent output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By using a combination of ND filters with different light reduction amounts, the dynamic range of the imaging device can be increased.

In addition to the filters described above, the pixels 211 may be provided with lenses. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described with reference to the cross-sectional view of FIG. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG.
4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2
A structure can be employed in which the light 256 is incident on the photoelectric conversion element 220 through 30 or the like.

However, part of the light 256 indicated by the arrow may be blocked by part of the wiring 257 as shown in the area surrounded by the dashed line. Therefore, as shown in FIG. 46B, the lens 255 and the filter 254 are arranged on the side of the photoelectric conversion element 220, and the photoelectric conversion element 220
A structure that efficiently receives the light 256 is preferable. By causing the light 256 to enter the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high detection sensitivity can be provided.

A photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used as the photoelectric conversion element 220 shown in FIG.

Alternatively, the photoelectric conversion element 220 may be formed using a substance that has a function of absorbing radiation and generating electric charge. Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium-zinc alloys, and the like are examples of substances that absorb radiation and generate charges.

For example, when selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light,
A photoelectric conversion element 2 having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays
20 can be realized.

Here, one pixel 211 of the imaging device 200 may have a sub-pixel 212 having a first filter in addition to the sub-pixel 212 shown in FIG.

<Example 2 of Pixel Configuration>
An example of forming a pixel using a transistor using silicon and a transistor using an oxide semiconductor is described below.

47(A) and 47(B) are cross-sectional views of elements constituting an imaging device.

The imaging device illustrated in FIG. 47A includes a transistor 351 using silicon provided over a silicon substrate 300 , a transistor 353 using an oxide semiconductor stacked over the transistor 351 , and a transistor 353 provided over the silicon substrate 300 . includes a photodiode 360 having an anode 361 and a cathode 362, which are separated from each other. Each transistor and photodiode 360 has electrical connections with various plugs 370 and wires 371 , 372 , 373 . Also, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363 .

The imaging device includes a layer 310 having a transistor 351 and a photodiode 360 provided over a silicon substrate 300 and a layer 310 provided in contact with the layer 310 and having a wiring 371 .
20, a layer 330 provided in contact with layer 320 and having transistor 353, and layer 330
and includes a layer 340 having wiring 372 and wiring 373 .

Note that in the example of the cross-sectional view of FIG. 47A, the transistor 3
The light-receiving surface of the photodiode 360 is provided on the surface opposite to the surface on which 51 is formed. With this structure, an optical path can be secured without being affected by various transistors, wiring, and the like. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 can be the same as the surface on which the transistor 351 is formed.

Note that in the case where a pixel is formed using a transistor using an oxide semiconductor, the layer 310 may be a layer including a transistor using an oxide semiconductor. Alternatively, the layer 310 may be omitted and a pixel may be formed using only a transistor including an oxide semiconductor.

In addition, in the cross-sectional view of FIG. 47A, the photodiode 360 provided in the layer 310 and the transistor provided in the layer 330 can be formed so as to overlap with each other. Then, the degree of integration of pixels can be increased. That is, the resolution of the imaging device can be enhanced.

In addition, in FIG. 47B, the imaging device can have a structure in which a photodiode 365 is arranged over a transistor on the layer 340 side. In FIG. 47B, for example, the layer 310 has
The layer 320 has a transistor 351 using silicon, the layer 320 has a wiring 371 , and the layer 330 has a wiring 371 .
The layer 340 includes a transistor 353 using an oxide semiconductor and an insulating layer 380 , and the layer 340 includes a photodiode 365 and is electrically connected to a wiring 373 and a wiring 374 through a plug 370 . .

With the element structure shown in FIG. 47B, the aperture ratio can be improved.

Alternatively, the photodiode 365 may be a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like. The photodiode 365 has a structure in which an n-type semiconductor 368, an i-type semiconductor 367, and a p-type semiconductor 366 are stacked in order. Amorphous silicon is preferably used for the i-type semiconductor 367 . For the p-type semiconductor 366 and the n-type semiconductor 368, amorphous silicon, microcrystalline silicon, or the like containing a dopant imparting conductivity type can be used. The photodiode 365 having a photoelectric conversion layer made of amorphous silicon has high sensitivity in the visible light wavelength region and can easily detect weak visible light.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 4)
In this embodiment, the transistor including the oxide semiconductor layer described in the above embodiment (
An example of a circuit configuration to which an OS transistor) can be applied will be described with reference to FIGS.

FIG. 48A shows a circuit diagram of an inverter that can be applied to memories, FPGAs, CPUs, and the like. The inverter 2800 outputs a signal obtained by inverting the logic of the signal applied to the input terminal IN to the output terminal OUT. The inverter 2800 has multiple OS transistors. The signal _SBG is a signal that can switch the electrical characteristics of the OS transistor.

FIG. 48B is a circuit diagram of an example of the inverter 2800. As shown in FIG. Inverter 2800 has OS transistor 2810 and OS transistor 2820 . Inverter 2
800 can be fabricated as an n-channel type and can have a so-called unipolar circuit configuration. Since the inverter can be manufactured with a unipolar circuit configuration, CMOS (Complement
Inverter (C
It can be manufactured at a lower cost than when manufacturing a MOS inverter).

Note that the inverter 2800 having an OS transistor is a C transistor composed of a Si transistor.
It can also be placed on a MOS circuit. Since the inverter 2800 can be overlapped with the CMOS circuit configuration, an increase in circuit area due to the addition of the inverter 2800 can be suppressed.

The OS transistors 2810 and 2820 each have a first gate functioning as a front gate, a second gate functioning as a back gate, a first terminal functioning as one of the source or the drain, and a first terminal functioning as the other of the source or the drain. It has two terminals.

A first gate of the OS transistor 2810 is connected to the second terminal. OS transistor 2
A second gate of 810 is connected to a wire carrying signal _SBG . OS transistor 281
A first terminal of 0 is connected to a wire that provides voltage VDD. A second terminal of the OS transistor 2810 is connected to the output terminal OUT.

A first gate of the OS transistor 2820 is connected to the input terminal IN. A second gate of the OS transistor 2820 is connected to the input terminal IN. A first terminal of the OS transistor 2820 is connected to the output terminal OUT. A second terminal of the OS transistor 2820 is connected to a wiring that supplies the voltage VSS.

FIG. 48C is a timing chart for explaining the operation of inverter 2800. In FIG. The timing chart in FIG. 48C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal _SBG , and the threshold voltage of the OS transistor 2810 .

By supplying the signal _SBG to the second gate of the OS transistor 2810, the threshold voltage of the OS transistor 2810 can be controlled.

The signal S _BG has a voltage V _{BG_A} for negatively shifting the threshold voltage and a voltage V _{BG_B} for positively shifting the threshold voltage. Applying the voltage V _{BG_A} to the second gate allows the OS transistor 2810 to be negatively shifted to the threshold voltage V _{TH_A} . By applying the voltage V _{BG_B} to the second gate, the OS transistor 2810 can be positively shifted to the threshold voltage V _{TH_B} .

In order to visualize the above description, FIG. 49A shows a graph of a Vg-Id curve, which is one of the electrical characteristics of a transistor.

The electrical characteristics of the OS transistor 2810 described above can be shifted to the curve represented by the dashed line 2840 in FIG. 49A by increasing the voltage of the second gate to _{VBG_A} . In addition, the electrical characteristics of the OS transistor 2810 described above can be shifted to a curve represented by a solid line 2841 in FIG. 49A by reducing the voltage of the second gate to the voltage _{VBG_B} . As shown in FIG. 49A, the OS transistor 28
10 can shift the threshold voltage positively or negatively by switching the signal S _BG between the voltage V _{BG_A} and the voltage V _{BG_B} .

By positively shifting the threshold voltage to the threshold voltage V _{TH_B} , the OS transistor 2810
can be in a state in which it is difficult for current to flow. FIG. 49B visualizes this state. As shown in FIG. 49B, the current _IB flowing through the OS transistor 2810 can be made extremely small. Therefore, when the signal applied to the input terminal IN is at a high level, OS
When the transistor 2820 is on (ON), the voltage of the output terminal OUT can drop sharply.

As shown in FIG. 49B, a state in which it is difficult for current to flow through the OS transistor 2810 can be achieved, so that the signal waveform 2831 of the output terminal in the timing chart shown in FIG. be able to. Wiring for applying voltage VDD and voltage V
Since it is possible to reduce the through current flowing between the SS and the wiring, it is possible to operate with low power consumption.

Further, by negatively shifting the threshold voltage to the threshold voltage _{VTH_A} , the OS transistor 2810 can be in a state where current easily flows. FIG. 49(C) visualizes this state. As shown in FIG. 49(C), the current _IA flowing at this time can be at least greater than the current _IB . Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 2820 is in the off state (OFF), the voltage of the output terminal OUT can be sharply increased.

As shown in FIG. 49C, current can easily flow through the OS transistor 2810, so that the signal waveform 2832 of the output terminal in the timing chart in FIG. be able to.

Note that the control of the threshold voltage of the OS transistor 2810 with the signal _SBG is preferably performed before the state of the OS transistor 2820 is switched, that is, before the times T1 and T2. For example, as illustrated in FIG. 48C, the threshold voltage of the OS transistor 2810 can be switched from the threshold voltage V _{TH_A} to the threshold voltage V _{TH_B} before time T1 at which the signal applied to the input terminal IN switches to high level. is preferred. Further, as shown in FIG. 48(C), before the time T2 at which the signal applied to the input terminal IN switches to low level,
It is preferable to switch the threshold voltage of the OS transistor 2810 from the threshold voltage V _{TH_B} to the threshold voltage V _{TH_A} .

Note that the timing chart in FIG. 48C shows a structure in which the signal _SBG is switched according to the signal applied to the input terminal IN, but another structure may be employed. For example, a voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 2810 which is in a floating state. FIG. 50 (A
).

In FIG. 50A, in addition to the circuit configuration shown in FIG. 48B, an OS transistor 2850
have A first terminal of OS transistor 2850 is connected to a second gate of OS transistor 2810 . A second terminal of the OS transistor 2850 is connected to a wiring that supplies the voltage V _{BG_B} (or the voltage V _{BG_A} ). A first gate of OS transistor 2850 is connected to a wiring that supplies signal _SF . The second gate of OS transistor 2850 is
It is connected to a wiring that gives voltage V _{BG_B} (or voltage V _{BG_A} ).

The operation of the circuit configuration in FIG. 50A will be described with reference to the timing chart in FIG. 50B.

A voltage for controlling the threshold voltage of the OS transistor 2810 is applied to the second gate of the OS transistor 2810 before time T3 when the signal applied to the input terminal IN switches to high level. The signal _SF is set to a high level to turn on the OS transistor 2850, and the voltage _{VBG_B} for controlling the threshold voltage is applied to the node _NBG .

After the node _NBG reaches the voltage _{VBG_B} , the OS transistor 2850 is turned off. Since the off-state current of the OS transistor 2850 is extremely low, the voltage V _{BG_B} that was once held at the node N _BG can be held by keeping it off. Therefore, the number of operations for applying the voltage _{VBG_B} to the second gate of the OS transistor 2850 is reduced, so that power consumption required for rewriting the voltage _{VBG_B} can be reduced.

Note that in the circuit configurations of FIGS. 48B and 50A, the voltage applied to the second gate of the OS transistor 2810 is externally controlled; however, another configuration may be employed. For example, a voltage for controlling the threshold voltage may be generated based on a signal applied to the input terminal IN and applied to the second gate of the OS transistor 2810 . FIG. 51A shows an example of a circuit configuration that can realize this configuration.

51A, a CMOS inverter 2860 is provided between the input terminal IN and the second gate of the OS transistor 2810 in the circuit configuration shown in FIG. 48B. The input terminal of CMOS inverter 2860 is connected to input terminal IN. CMOS inverter 286
The 0 output terminal is connected to the second gate of the OS transistor 2810 .

The operation of the circuit configuration of FIG. 51(A) will be described with reference to the timing chart of FIG. 51(B). In the timing chart of FIG. 51(B), the signal waveform of the input terminal IN, the output terminal O
Changes in the UT signal waveform, the output waveform IN_B of the CMOS inverter 2860, and the threshold voltage of the OS transistor 2810 are shown.

The output waveform IN_B, which is a signal obtained by inverting the logic of the signal supplied to the input terminal IN, can be a signal that controls the threshold voltage of the OS transistor 2810 . Therefore, FIG. 49 (A
) to (C), the threshold voltage of the OS transistor 2810 can be controlled. For example, at time T4 in FIG. 51B, the signal applied to the input terminal IN is at a high level and the OS transistor 2820 is turned on. At this time, the output waveform IN_B becomes low level. Therefore, the OS transistor 2810 can be in a state in which it is difficult for current to flow, and the voltage of the output terminal OUT can be sharply decreased.

At time T5 in FIG. 51B, the signal applied to the input terminal IN is at a low level and the OS transistor 2820 is turned off. At this time, the output waveform IN_B becomes high level. Therefore, the OS transistor 2810 can be in a state where current can easily flow, and the voltage of the output terminal OUT can be increased sharply.

As described above, in the structure of this embodiment, the voltage of the back gate in the inverter including the OS transistor is switched according to the logic of the signal of the input terminal IN. With such a structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor in accordance with the signal applied to the input terminal IN, the output terminal OU
The change in voltage on T can be steep. In addition, it is possible to reduce the through current between the wirings that supply the power supply voltage. Therefore, low power consumption can be achieved.

(Embodiment 5)
<RF tag>
In this embodiment mode, an RF transistor including the transistor or the memory device described in the above embodiment mode is used.
A tag will be described with reference to FIG.

The RF tag according to the present embodiment has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means such as wireless communication. Due to such features, RF tags can be used in individual authentication systems that identify articles by reading individual information on the articles. In addition, extremely high reliability is required for use in these applications.

A configuration of the RF tag will be described with reference to FIG. FIG. 52 is a block diagram showing a configuration example of an RF tag.

As shown in FIG. 52, the RF tag 800 has an antenna 8 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also called interrogator, reader/writer, etc.).
04. Further, the RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulator circuit 8
07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811.
Note that a material capable of sufficiently suppressing reverse current, such as an oxide semiconductor, may be used for the rectifying transistor included in the demodulation circuit 807 . As a result, it is possible to suppress the deterioration of the rectifying action caused by the reverse current and prevent the output of the demodulator from being saturated. That is, the output of the demodulation circuit can be made linear with respect to the input of the demodulation circuit. There are three major data transmission formats: the electromagnetic coupling method, in which a pair of coils are placed facing each other and communicate by mutual induction, the electromagnetic induction method, in which communication is performed by an induced electromagnetic field, and the radio wave method, in which communication is performed using radio waves. separated. The RF tag 800 shown in this embodiment can be used for any of these methods.

Next, the configuration of each circuit will be described. Antenna 804 is for transmitting/receiving radio signal 803 to/from antenna 802 connected to communication device 801 . Also, the rectifier circuit 8
05 rectifies, for example, half-wave double voltage rectification of an input AC signal generated by receiving a radio signal at the antenna 804, and smoothes the rectified signal with a capacitive element provided in the latter stage. is a circuit for generating an input potential at . A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805 . A limiter circuit is a circuit for controlling so that power exceeding a certain level is not input to a subsequent circuit when the amplitude of an input AC signal is large and the internally generated voltage is large.

A constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to generate the logic circuit 80
9 is a circuit for generating a reset signal.

The demodulation circuit 807 is a circuit for demodulating the input AC signal by detecting its envelope and generating a demodulation signal. A modulation circuit 808 is a circuit for performing modulation according to data output from the antenna 804 .

A logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is
A circuit that holds input information and has a row decoder, a column decoder, a storage area, and the like. A ROM 811 is a circuit for storing a unique number (ID) and the like, and for outputting according to processing.

It should be noted that each of the circuits described above can be omitted as appropriate, if necessary.

Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit 810 . The memory circuit of one embodiment of the present invention can hold information even when power is shut off; therefore, it can be suitably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention requires significantly less power (voltage) for data writing than conventional nonvolatile memories, so that there is no difference in the maximum communication distance between reading and writing data. is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to power shortage during data writing.

Further, since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be applied to the ROM 811 . In that case, it is preferable that the manufacturer separately prepares a command for writing data into the ROM 811 so that the user cannot freely rewrite the data. By shipping the product after the producer writes the unique number before shipping, it is possible to assign a unique number only to the good products to be shipped instead of assigning a unique number to all the manufactured RF tags. To facilitate customer management corresponding to products after shipment without discontinuity of unique numbers of products after shipment.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 6)
In this embodiment mode, a CPU including the storage device described in the previous embodiment mode will be described.

FIG. 53 is a block diagram showing a configuration of an example of a CPU using at least a part of the transistors described in the above embodiments.

<Circuit diagram of CPU>
The CPU shown in FIG. 53 has an ALU 1191 (ALU: Arithmet
ic logic unit, arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1
198, a rewritable ROM 1199, and a ROM interface 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190 . ROM1
199 and ROM interface 1189 may be provided on separate chips. of course,
The CPU shown in FIG. 53 is merely an example of a simplified configuration, and actual CPUs have a wide variety of configurations depending on their uses. For example, a configuration including a CPU or an arithmetic circuit shown in FIG. 53 may be used as one core, a plurality of such cores may be included, and the respective cores may operate in parallel. Also, the number of bits that the CPU can handle in the internal arithmetic circuit and data bus is
For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, and so on.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193 , decoded, and input to the ALU controller 1192 , interrupt controller 1194 , register controller 1197 and timing controller 1195 .

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on decoded instructions. Specifically, ALU controller 1192 generates signals for controlling the operation of ALU 1191 . Further, the interrupt controller 1194 judges and processes interrupt requests from external input/output devices and peripheral circuits based on their priority and mask status during program execution by the CPU. A register controller 1197 generates an address for the register 1196 and reads or writes the register 1196 according to the state of the CPU.

Also, the timing controller 1195 includes the ALU 1191 and the ALU controller 119
2. Generate signals that control the timing of the operation of instruction decoder 1193, interrupt controller 1194, and register controller 1197; For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the CPU shown in FIG. 53, the register 1196 is provided with memory cells. As the memory cell of the register 1196, the transistor described in Embodiment 1 can be used.

In the CPU shown in FIG. 53, a register controller 1197 selects a holding operation in register 1196 according to instructions from ALU 1191 . That is, register 11
In the memory cell of 96, it is selected whether data is held by a flip-flop or a capacitor. When data holding by the flip-flop is selected, power supply voltage is supplied to the memory cells in the register 1196 . When data retention in the capacitor is selected, data is rewritten in the capacitor, and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

<Memory circuit>
FIG. 54 is an example of a circuit diagram of a memory element that can be used as the register 1196. FIG.
The memory element 1200 includes a circuit 1201 in which stored data volatilizes when power is cut off, a circuit 1202 in which stored data does not volatilize when power is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitor element 1207, and a selection function. and a circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, a transistor 1210,
have Note that the memory element 1200 may further have other elements such as a diode, a resistor element, and an inductor, if necessary.

Here, the memory device described in the above embodiment can be used for the circuit 1202 .
When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 of the circuit 1202
9, a ground potential (0 V) or a potential for turning off the transistor 1209 is continuously input. For example, the first gate of the transistor 1209 is grounded through a load such as a resistor.

The switch 1203 is formed using a transistor 1213 having one conductivity type (eg, n-channel type), and the switch 1204 is formed using a transistor 1214 having a conductivity type opposite to the one conductivity type (eg, p-channel type). example. Here, the first terminal of switch 1203 corresponds to one of the source and drain of transistor 1213, and the second terminal of switch 1203 corresponds to one of the source and drain of transistor 1213.
corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 makes conduction or non-conduction between the first terminal and the second terminal (that is, ON state or OFF state of transistor 1213) is selected. A first terminal of switch 1204 corresponds to one of the source and drain of transistor 1214 , a second terminal of switch 1204 corresponds to the other of the source and drain of transistor 1214 , and switch 1204 is input to the gate of transistor 1214 . The control signal RD selects conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 1214).

One of the source and drain of the transistor 1209 is electrically connected to the first terminal of the capacitor 1208 and the gate of the transistor 1210 . Here, the connection part is node M
2. One of the source and drain of the transistor 1210 is electrically connected to a wiring capable of supplying a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and drain of the transistor 1213). on the other hand). A second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to a first terminal of switch 1204 (one of the source and drain of transistor 1214). A second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wiring capable of supplying power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (one of the source and the drain of the transistor 1214), the input terminal of the logic element 1206, and the capacitor 1207 is electrically connected to the first terminal. Here, the connection portion is assumed to be a node M1. A constant potential can be input to the second terminal of the capacitor 1207 . For example, low power supply potential (such as GND) or high power supply potential (
VDD, etc.) can be input. A second terminal of the capacitor 1207 is electrically connected to a wiring capable of supplying a low power supply potential (eg, a GND line). A constant potential can be input to the second terminal of the capacitor 1208 . for example,
A structure in which a low power supply potential (such as GND) or a high power supply potential (such as VDD) is input can be employed. A second terminal of the capacitor 1208 is electrically connected to a wiring capable of supplying a low power supply potential (eg, a GND line).

Note that the capacitors 1207 and 1208 can be omitted by positively using parasitic capacitance of transistors and wirings.

A control signal WE is input to the first gate (first gate electrode) of the transistor 1209 . Switches 1203 and 1204 are controlled by control signal RD, which is different from control signal WE.
selects a conducting state or a non-conducting state between the first terminal and the second terminal by , and when the first terminal and the second terminal of one switch are in a conducting state, the first terminal of the other switch A non-conducting state is established between the terminal and the second terminal.

Note that the transistor 1209 in FIG. 54 shows a structure having a second gate (second gate electrode: back gate). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal with a constant potential. As the constant potential, for example, a potential lower than the ground potential GND or the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and can further reduce the current when the gate voltage VG is 0V. Also, the control signal WE2 may be the same potential signal as the control signal WE. Note that a transistor without a second gate can be used as the transistor 1209 .

A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209 . FIG. 54 shows an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 . The signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) is
The logical value is inverted by the logic element 1206 to form an inverted signal, which is input to the circuit 1201 via the circuit 1220 .

FIG. 54 shows an example in which the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) is input to circuit 1201 via logic element 1206 and circuit 1220. is not limited to A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without having its logic value inverted. For example, in circuit 1201,
If there is a node that holds a signal with the inverted logic value of the signal input from the input terminal, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213)
can be input to the node.

In addition, in FIG. 54, transistors other than the transistor 1209 among the transistors included in the memory element 1200 are the layer or the substrate 119 formed of a semiconductor other than an oxide semiconductor.
A transistor in which a channel is formed at 0 can be used. For example, it can be a transistor in which a channel is formed in a silicon layer or a silicon substrate. Alternatively, all the transistors included in the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the channel of the remaining transistors is formed in a layer or substrate 1190 formed using a semiconductor other than an oxide semiconductor. It can also be a transistor that

A flip-flop circuit, for example, can be used for the circuit 1201 in FIG.
As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device of one embodiment of the present invention, data stored in the circuit 1201 is stored in the capacitor 120 provided in the circuit 1202 while power supply voltage is not supplied to the memory element 1200 .
8 can be held.

A transistor whose channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is significantly lower than that of a transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the memory element 120
The signal held in the capacitor 1208 is kept for a long time even while the power supply voltage is not supplied to 0. Thus, the memory element 1200 can retain memory contents (data) even while the supply of power supply voltage is stopped.

In addition, since the memory element is characterized by performing a precharge operation by providing the switches 1203 and 1204, the time until the circuit 1201 retains the original data after the supply of power supply voltage is restarted is shortened. be able to.

In addition, in the circuit 1202 , the signal held by the capacitor 1208 is input to the gate of the transistor 1210 . Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is changed to the state of the transistor 1210 (
on state or off state) and read out from the circuit 1202 . Therefore, even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates, the original signal can be read accurately.

By using such a memory element 1200 in a memory device such as a register of a processor or a cache memory, loss of data in the memory device due to stoppage of supply of power supply voltage can be prevented. In addition, after restarting the supply of the power supply voltage, the state before the power supply is stopped can be restored in a short period of time. Therefore, the entire processor or one or a plurality of logic circuits included in the processor can be powered off even for a short time, so that power consumption can be suppressed.

In this embodiment, an example in which the memory element 1200 is used for the CPU has been described.
200 is a DSP (Digital Signal Processor), custom L
LSI such as SI, PLD (Programmable Logic Device), R
It can also be applied to an F (Radio Frequency) tag.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 7)
In this embodiment, a structural example of a display device using a transistor of one embodiment of the present invention will be described.

<Display device circuit configuration example>
FIG. 55A is a top view of a display device of one embodiment of the present invention, and FIG. 55B can be used when a liquid crystal element is applied to a pixel of the display device of one embodiment of the present invention. 3 is a circuit diagram for explaining a pixel circuit; FIG. FIG. 55C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of a display device of one embodiment of the present invention.

A transistor provided in the pixel portion can be formed according to Embodiment Mode 1. FIG. again,
Since the transistor can easily be an n-channel transistor, part of a driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. Thus, by using the transistor described in any of the above embodiments for the pixel portion and the driver circuit, a highly reliable display device can be provided.

An example of a top view of an active matrix display device is shown in FIG. A pixel portion 701, a first scanning line driver circuit 702, and a second scanning line driver circuit 70 are formed on the substrate 700 of the display device.
3. It has a signal line driver circuit 704 . In the pixel portion 701, a plurality of signal lines are arranged extending from a signal line driver circuit 704, and a plurality of scanning lines are arranged in a first scanning line driver circuit 702 and a second scanning line driver circuit 702.
are arranged extending from the scanning line driving circuit 703 of . Pixels each having a display element are provided in a matrix in each intersection region between the scanning lines and the signal lines. Further, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or control IC) via a connecting portion such as an FPC (Flexible Printed Circuit).

In FIG. 55A, the first scanning line driver circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 are formed over the substrate 700 where the pixel portion 701 is formed. As a result, the number of parts such as a driving circuit provided outside is reduced, so that the cost can be reduced. Also, the substrate 7
00, the wiring must be extended, and the number of connections between the wirings increases. When a driver circuit is provided over the same substrate 700, the number of connections between wirings can be reduced, and reliability or yield can be improved. Note that any one of the first scanning line driver circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 is the substrate 70.
0 or provided outside the substrate 700 .

<Liquid crystal display device>
An example of the circuit configuration of a pixel is shown in FIG. Here, as an example, a pixel circuit that can be applied to a pixel of a VA liquid crystal display device is shown.

This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. As a result, the signals applied to the individual pixel electrode layers of the pixels designed in multi-domain can be independently controlled.

A scanning line 712 of the transistor 716 and a scanning line 713 of the transistor 717 are separated so that different gate signals can be applied. On the other hand, the signal line 714 is shared by the transistors 716 and 717 . The transistors described in Embodiment 1 can be used as appropriate for the transistors 716 and 717 . Thereby, a highly reliable liquid crystal display device can be provided.

The transistor 716 is electrically connected to the first pixel electrode layer, and the transistor 716 is electrically connected to the first pixel electrode layer.
A second pixel electrode layer is electrically connected to 17 . The first pixel electrode layer and the second pixel electrode layer are separated from each other. Note that the shapes of the first pixel electrode layer and the second pixel electrode layer are not particularly limited. For example, the first pixel electrode layer may be V-shaped.

A gate electrode of the transistor 716 is connected to the scanning line 712 and a gate electrode of the transistor 717 is connected to the scanning line 713 . By applying different gate signals to the scanning line 712 and the scanning line 713, the operation timing of the transistor 716 and the transistor 717 can be changed to control the orientation of the liquid crystal.

Alternatively, a storage capacitor may be formed by the capacitor wiring 710, a gate insulating layer functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

In a multi-domain design, one pixel has a first liquid crystal element 718 and a second liquid crystal element 719 . The first liquid crystal element 718 is composed of the first pixel electrode layer, the counter electrode layer, and the liquid crystal layer therebetween, and the second liquid crystal element 719 is composed of the second pixel electrode layer, the counter electrode layer, and the liquid crystal layer therebetween. consists of

Note that the pixel circuit shown in FIG. 55B is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel circuit shown in FIG.

FIGS. 56A and 56B are an example of a top view and a cross-sectional view of a liquid crystal display device. Note that in FIG. 56A, the display device 20, the display area 21, the peripheral circuit 22, and the FPC (
A representative configuration with a flexible printed circuit board 42 is shown. The display device shown in FIG. 56 uses a reflective liquid crystal.

Between broken lines AA', BB', CC' and DD of FIG. 56(A) in FIG. 56(B)
' shows a cross-sectional view between. AA' indicates the peripheral circuit portion, BB' indicates the display area, and C
Between -C' indicates the connecting part with the FPC.

The display device 20 using a liquid crystal element includes, in addition to the transistor 50 and the transistor 52 (the transistor 10 described in Embodiment 1), a conductive layer 165, a conductive layer 197, an insulating layer 420, a liquid crystal layer 490, a liquid crystal element 80, and a capacitor. Element 60, capacitive element 62, insulating layer 430, spacer 44
0, colored layer 460, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 4
73 , adhesive layer 474 , adhesive layer 475 , adhesive layer 476 , polarizing plate 103 , polarizing plate 403 , protective substrate 105 , protective substrate 402 , and anisotropic conductive layer 510 .

<Organic EL display device>
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display device using an organic EL element is shown.

In the organic EL element, electrons are emitted from one of a pair of electrodes by applying a voltage to the light emitting element.
Holes are injected from the other into the layer containing a light-emitting organic compound, and current flows. Recombination of electrons and holes causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

FIG. 55C is a diagram showing an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. In addition, digital time gray scale driving can be applied to the pixel circuit.

The configuration of an applicable pixel circuit and the operation of a pixel when digital time grayscale driving is applied will be described.

The pixel 720 has a switching transistor 721 , a driving transistor 722 , a light emitting element 724 and a capacitor 723 . The switching transistor 721 has a gate electrode layer connected to the scanning line 726, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 725, and a second electrode (the source electrode layer and the drain electrode layer). ) is connected to the gate electrode layer of the driving transistor 722 . driving transistor 7
22, the gate electrode layer is connected to the power supply line 727 via the capacitor 723, the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. there is A second electrode of the light emitting element 724 corresponds to the common electrode 728 . Common electrode 728 is electrically connected to a common potential line formed on the same substrate.

The transistors described in Embodiments 1 to 3 can be used as appropriate for the switching transistor 721 and the driving transistor 722 . This makes it possible to provide a highly reliable organic EL display device.

The potential of the second electrode (common electrode 728) of the light emitting element 724 is set to the low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727;
, 0 V or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the forward threshold voltage of the light emitting element 724 , and the potential difference between them is applied to the light emitting element 724 .
is applied to the light emitting element 724 to cause it to emit light. Note that the light emitting element 72
The forward voltage of 4 refers to the voltage at which the desired luminance is obtained, and includes at least the forward threshold voltage.

Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722 .

Next, signals input to the driving transistor 722 are described. In the case of the voltage input voltage driving method, a video signal is input to the driving transistor 722 so that the driving transistor 722 is sufficiently turned on or turned off. Note that a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722 in order to operate the driving transistor 722 in the linear region. Further, a voltage equal to or higher than the sum of the threshold voltage Vth of the driving transistor 722 and the power supply line voltage is applied to the signal line 725 .

When performing analog gradation driving, the light emitting element 72 is provided in the gate electrode layer of the driving transistor 722 .
4 plus the threshold voltage Vth of the driving transistor 722 is applied. Note that a video signal is input so that the driving transistor 722 operates in a saturation region, and current flows through the light emitting element 724 . In addition, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722 in order to operate the driving transistor 722 in the saturation region. By using an analog video signal, a current corresponding to the video signal can be supplied to the light emitting element 724 to perform analog gradation driving.

Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. For example, FIG.
A switch, a resistor element, a capacitor element, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit shown in (C).

When applying the transistors exemplified in the above embodiments to the circuit exemplified in FIG.
A source electrode (first electrode) is electrically connected to the low potential side, and a drain electrode (second electrode) is electrically connected to the high potential side. Further, the potentials exemplified above can be input, such as by controlling the potential of the first gate electrode by a control circuit or the like and applying a lower potential than the potential applied to the source electrode to the second gate electrode through wiring (not shown). configuration.

FIGS. 57A and 57B are an example of a top view and a cross-sectional view of a display device using a light-emitting element. It should be noted that FIG. 57A shows a typical configuration having a display device 24, a display area 21, a peripheral circuit 22, and an FPC (flexible printed circuit board) 42. FIG.

FIG. 57(B) shows cross-sectional views along broken lines AA', BB', and CC' in FIG. 57(A). AA' indicates the peripheral circuit portion, BB' indicates the display area, and CC' indicates the connecting portion with the FPC.

The display device 24 using a light-emitting element includes the transistor 50 and the transistor 52 (the transistor 10 described in Embodiment 1), the conductive layer 197, the conductive layer 410, and the optical adjustment layer 530.
, EL layer 450, conductive layer 415, light emitting element 70, capacitor 60, capacitor 62, insulating layer 4
30 , a spacer 440 , a colored layer 460 , an adhesive layer 470 , a partition 445 , a light shielding layer 418 , a substrate 400 and an anisotropic conductive layer 510 .

In this specification and the like, for example, a display device, a display device that is a device having a display device, a light-emitting device, and a light-emitting device that is a device having a light-emitting device use various forms or include various elements. can be done. Display elements, display devices, light-emitting elements or light-emitting devices include, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LED
etc.), transistors (transistors that emit light according to current), electron-emitting devices, liquid crystal devices, electronic inks, electrophoretic devices, grating light valves (GLV), plasma display panels (PDP), MEMS (micro-electro-mechanical devices), system),
Digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, electrowetting element, piezoelectric ceramic display, display element using carbon nanotubes, etc. have at least one of In addition to these, it may have a display medium in which contrast, brightness, reflectance, transmittance, etc. are changed by electrical or magnetic action. An example of a display device using an EL element is an EL display. Examples of display devices using electron-emitting devices include a field emission display (FED) or an SED flat panel display (SED: Surface-con
induction electron-emitter display) and the like. Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays,
transflective liquid crystal display, reflective liquid crystal display, direct view liquid crystal display, and projection liquid crystal display). An example of a display device using electronic ink or an electrophoretic element is electronic paper.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 8)
In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIGS.

<Display module>
A display module 6000 shown in FIG. It has a battery 6011 . Note that the backlight unit 6007, the battery 6011, the touch panel 6004, and the like may not be provided.

A semiconductor device of one embodiment of the present invention can be used, for example, in the display panel 6006 or an integrated circuit mounted over a printed circuit board.

The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the sizes of the touch panel 6004 and the display panel 6006 .

The touch panel 6004 is a resistive or capacitive touch panel.
006 can be used. In addition, it is also possible to provide a counter substrate (sealing substrate) of the display panel 6006 with a touch panel function. Or display panel 6
It is also possible to provide an optical sensor in each pixel of 006 to add an optical touch panel function. Alternatively, a touch sensor electrode can be provided in each pixel of the display panel 6006 to add a capacitive touch panel function.

The backlight unit 6007 has a light source 6008 . The light source 6008 may be provided at the end of the backlight unit 6007 and a light diffusion plate may be used.

The frame 6009 has a function of protecting the display panel 6006 as well as a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 . Also frame 600
9 may have a function as a heat sink.

A printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply or a separately provided battery 6011 may be used. Note that the battery 6011 can be omitted when a commercial power supply is used.

Further, the display module 6000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 9)
In this embodiment, usage examples of a semiconductor device according to one embodiment of the present invention will be described.

<Package using lead frame type interposer>
FIG. 59A shows a perspective view showing a cross-sectional structure of a package using a lead frame interposer. In the package shown in FIG. 59A, a chip 1751 corresponding to a semiconductor device according to one embodiment of the present invention is connected to terminals 1752 over an interposer 1750 by wire bonding. Terminal 1752 connects to chip 17 of interposer 1750
51 is placed on the surface on which it is mounted. The chip 1751 may be sealed with a mold resin 1753, but is sealed with a part of each terminal 1752 exposed.

FIG. 59B shows the configuration of a module of an electronic device (mobile phone) in which a package is mounted on a circuit board. The mobile phone module shown in FIG.
01, a package 1802 and a battery 1804 are mounted. A printed wiring board 1801 is mounted by an FPC 1803 on a panel 1800 provided with display elements.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 10)
In this embodiment, an electronic device and a lighting device of one embodiment of the present invention will be described with reference to drawings.

<Electronic equipment>
An electronic device or a lighting device can be manufactured using the semiconductor device of one embodiment of the present invention. Further, with the use of the semiconductor device of one embodiment of the present invention, highly reliable electronic devices and lighting devices can be manufactured. Further, by using the semiconductor device of one embodiment of the present invention, an electronic device or a lighting device with improved detection sensitivity of a touch sensor can be manufactured.

Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones and mobile phone devices). ), portable game machines, personal digital assistants, sound reproduction devices, and large game machines such as pachinko machines.

Further, when the electronic device or the lighting device of one embodiment of the present invention is flexible, it can be incorporated along the inner wall or outer wall of a house or building, or along the curved surface of the interior or exterior of an automobile.

Further, the electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

As secondary batteries, for example, lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using a gel electrolyte, lithium ion batteries, nickel hydrogen batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel-zinc batteries, silver-zinc batteries, and the like.

An electronic device of one embodiment of the present invention may have an antenna. An image, information, or the like can be displayed on the display portion by receiving a signal with the antenna. Also, if the electronic device has a secondary battery, the antenna may be used for contactless power transmission.

FIG. 60A shows a portable game machine including a housing 7101, a housing 7102, a display portion 7103,
It has a display portion 7104, a microphone 7105, a speaker 7106, operation keys 7107, a stylus 7108, and the like. A semiconductor device according to one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the housing 7101 . By using a normally-off CPU as the CPU, power consumption can be reduced, and the game can be enjoyed for a longer time than before. By using the semiconductor device according to one embodiment of the present invention for the display portion 7103 or the display portion 7104, a portable game machine with excellent usability and less deterioration in quality can be provided. Note that the portable game machine shown in FIG. 60A has two display portions 7103 and 7104, but the number of display portions in the portable game machine is not limited to this.

FIG. 60B shows a smartwatch including a housing 7302, a display portion 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. A semiconductor device according to one embodiment of the present invention can be used for a memory, a CPU, or the like included in the housing 7302 . Note that by using a reflective liquid crystal panel for the display used in FIG. 60B and a normally-off CPU for the CPU, power consumption can be reduced and the number of charging times in daily life can be reduced.

FIG. 60C shows a portable information terminal including a display portion 7502 incorporated in a housing 7501, operation buttons 7503, an external connection port 7504, a speaker 7505, and a microphone 7506.
, a display unit 7502, and the like. A semiconductor device according to one embodiment of the present invention includes a housing 7501
It can be used for mobile memory, CPU, etc. Note that the number of times of charging can be reduced by using a normally-off CPU. Also, the display unit 7502
is capable of producing very high definition, so even though it is small or medium-sized, it can display full high-definition, 4k
, or 8k, and a very clear image can be obtained.

FIG. 60D shows a video camera including a first housing 7701, a second housing 7702, and a display portion 77.
03, operation keys 7704, a lens 7705, a connection portion 7706, and the like. Operation key 770
4 and the lens 7705 are provided in the first housing 7701 and the display portion 7703 is provided in the second housing 7702 . The first housing 7701 and the second housing 7702 are connected by a connecting portion 7706, and the angle between the first housing 7701 and the second housing 7702 is
Connection 7706 allows modification. The image on the display unit 7703 is transferred to the connection unit 770
6 may be switched according to the angle between the first housing 7701 and the second housing 7702 . An imaging device of one embodiment of the present invention can be provided at the focal point of the lens 7705 . A semiconductor device according to one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the first housing 7701 .

FIG. 60E shows a digital signage, a display portion 7902 installed on a utility pole 7901.
It has The semiconductor device according to one embodiment of the present invention can be used for the display panel of the display portion 7902 and the built-in control circuit.

FIG. 61A shows a notebook personal computer including a housing 8121 and a display portion 8122.
, a keyboard 8123, a pointing device 8124, and the like. A semiconductor device according to one embodiment of the present invention can be applied to a CPU or a memory incorporated in the housing 8121 . Note that the display portion 8122 can have very high definition, so that it can display 8k even though it is small or medium-sized, and a very clear image can be obtained.

FIG. 61(B) shows the appearance of the automobile 9700. As shown in FIG. FIG. 61(C) shows the driver's seat of automobile 9700 . An automobile 9700 has a vehicle body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like. A semiconductor device of one embodiment of the present invention can be used for a display portion and a control integrated circuit of automobile 9700 . For example, the display portion 9710 shown in FIG.
The semiconductor device of one embodiment of the present invention can be provided in the display portion 9715 to the display portion 9715 .

A display portion 9710 and a display portion 9711 are display devices or input/output devices provided on the windshield of an automobile. A display device or an input/output device of one embodiment of the present invention is in a so-called see-through state, in which an electrode included in the display device or the input/output device is formed using a light-transmitting conductive material so that the opposite side can be seen through. display device or input/output device. A see-through display device or an input/output device does not obstruct the view when the automobile 9700 is driven. Therefore, the display device or the input/output device of one embodiment of the present invention can be installed on the windshield of the automobile 9700 . Note that in the case where a display device or an input/output device is provided with a transistor or the like for driving the display device or the input/output device, an organic transistor using an organic semiconductor material, a transistor using an oxide semiconductor, or the like can be used. A light-transmitting transistor is preferably used.

A display portion 9712 is a display device provided in a pillar portion. For example, by displaying an image from an imaging means provided on the vehicle body on the display portion 9712, the field of view blocked by the pillar can be complemented. A display unit 9713 is a display device provided in the dashboard portion. For example, by displaying an image from an imaging means provided on the vehicle body on the display portion 9713, the field of view blocked by the dashboard can be complemented. That is, by projecting an image from the imaging means provided outside the automobile, blind spots can be compensated for and safety can be enhanced. In addition, by projecting an image that supplements the invisible part, safety confirmation can be performed more naturally and without discomfort.

Further, FIG. 61(D) shows the interior of an automobile in which bench seats are used for the driver's seat and the front passenger's seat. The display unit 9721 is a display device or an input/output device provided on the door. For example, by displaying an image from an imaging unit provided in the vehicle body on the display portion 9721, the field of view blocked by the door can be complemented. A display unit 9722 is a display device provided on the steering wheel. The display unit 9723 is a display device provided in the center of the seating surface of the bench seat. Note that the display device can be installed on a seat surface, a backrest portion, or the like, and the display device can be used as a seat heater using the heat generated by the display device as a heat source.

Display 9714, display 9715, or display 9722 can provide navigation information, speedometer and tachometer, mileage, fuel level, gear status, air conditioning settings, and a variety of other information. In addition, the display items and layout displayed on the display unit can be appropriately changed according to the user's preference. The above information is displayed on the display unit 9
710 to the display portion 9713 , the display portion 9721 , and the display portion 9723 . Further, the display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as lighting devices. Further, the display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as a heating device.

Also, FIG. 62(A) shows the appearance of the camera 8000 . The camera 8000 includes a housing 8001
, a display portion 8002, an operation button 8003, a shutter button 8004, a coupling portion 8005, and the like. A lens 8006 can also be attached to the camera 8000 .

The connecting portion 8005 has an electrode, and can be connected to a finder 8100, which will be described later, as well as a strobe device or the like.

Here, the camera 8000 has a configuration in which the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.

An image can be captured by pressing the shutter button 8004 . Also, the display unit 80
02 has a function as a touch panel, and an image can be captured by touching the display portion 8002 .

A display device or an input/output device of one embodiment of the present invention can be applied to the display portion 8002 .

FIG. 62B shows an example in which a finder 8100 is attached to the camera 8000. FIG.

A viewfinder 8100 includes a housing 8101, a display portion 8102, buttons 8103, and the like.

The housing 8101 has a coupling portion that engages with a coupling portion 8005 of the camera 8000 so that the viewfinder 8100 can be attached to the camera 8000 . Further, the connecting portion has an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102 .

A button 8103 has a function as a power button. The button 8103 allows the display unit 8
The display of 102 can be switched on/off.

The semiconductor device of one embodiment of the present invention can be applied to the integrated circuit and the image sensor in the housing 8101 .

Note that in FIGS. 62A and 62B, the camera 8000 and the viewfinder 8100 are separate electronic devices and are detachable. A device, or a viewfinder with an input/output device, may be incorporated.

Also, FIG. 62(C) shows the appearance of the head mounted display 8200 .

The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 820
3. It has a display portion 8204, a cable 8205, and the like. A battery 8206 is built in the mounting portion 8201 .

Cable 8205 supplies power from battery 8206 to body 8203 . body 82
03 includes a wireless receiver or the like, and can display video information such as received image data on the display portion 8204 . In addition, by capturing the movement of the user's eyeballs and eyelids with a camera provided in the main body 8203 and calculating the coordinates of the user's viewpoint based on the information, the user's viewpoint can be used as an input means. can.

Also, the mounting portion 8201 may be provided with a plurality of electrodes at positions where the user touches.
The main body 8203 may have a function of recognizing the user's viewpoint by detecting the current flowing through the electrodes as the user's eyeballs move. It may also have a function of monitoring the user's pulse by detecting the current flowing through the electrode. Also, the mounting portion 8201
may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and may have a function of displaying the biological information of the user on the display unit 8204 . Alternatively, the movement of the user's head may be detected and the image displayed on the display portion 8204 may be changed according to the movement.

The semiconductor device of one embodiment of the present invention can be applied to an integrated circuit inside the main body 8203 .

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 11)
In this embodiment, usage examples of an RF tag using a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

<Usage example of RF tag>
RF tags are used in a wide range of applications. (B)
(see FIG. 63(C)), packaging containers (wrapping paper, bottles, etc., see FIG. 63(C)), recording media (DVDs, video tapes, etc., see FIG. 63(D)), personal items (bags, glasses, etc.), foods , plants, animals, the human body, clothes, daily necessities, medicines and medicines containing medicines, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), or other items 63(E) and 63(F)).

An RF tag 4000 according to an aspect of the present invention is fixed to an article by being attached to the surface or embedded. For example, if it is a book, it is embedded in paper, and if it is a package made of organic resin, it is embedded inside the organic resin and fixed to each article. Since the RF tag 4000 according to one embodiment of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after it is fixed to the article. In addition, by providing the RF tag 4000 according to one aspect of the present invention to bills, coins, securities, bearer bonds, certificates, or the like, an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one aspect of the present invention to packaging containers, recording media, personal effects, foods, clothes, daily necessities, electronic devices, or the like, the efficiency of systems such as inspection systems can be improved. can be planned. In addition, by attaching the RF tag according to one embodiment of the present invention to vehicles, security against theft or the like can be improved.

As described above, by using an RF tag using a semiconductor device according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced. It is possible to increase the communication distance. In addition, since information can be retained for an extremely long period of time even when power is shut off, it can be suitably used for applications in which writing and reading are infrequent.

Note that this embodiment can be combined with any of the other embodiments and examples described in this specification as appropriate.

Example 1 In this example, results of measurement of the resistance value of the oxide semiconductor layer 122 after ion addition treatment are described.

A structure shown in FIG. 64 was fabricated as a measurement sample. A measurement sample was produced by the method described in the first embodiment. Note that the method for manufacturing the samples is not limited to this method.

A Si wafer of about 700 μm was used as the substrate 100 .

As the insulating layer 110, a stack of a silicon oxide film and a silicon oxynitride film was formed.

As the silicon oxide film, a thermal oxide film of 100 nm was formed on a Si wafer by a hydrochloric acid oxidation method at 950.degree.

A silicon oxynitride film was formed to a thickness of 300 nm by plasma CVD. The film formation conditions are as follows: the gas flow rate for film formation is set to 2.3 sccm of silane and the dinitrogen monoxide is set to 800 sccm;
The power frequency was 27 MHz, the power during film formation was 50 W, the distance between the electrodes was 15 mm, and the substrate heating temperature was 400° C. during film formation.

Next, the oxide semiconductor layer 122 is formed by a sputtering method using In:G as a target.
An oxide semiconductor film was used which was formed to a thickness of 50 nm using an oxide of a:Zn=1:1:1 (atomic ratio). The film formation conditions are as follows: the pressure in the chamber during film formation is 0.7 Pa, the power during film formation is 0.5 kW using a DC power supply, and the gas flow rate for sputtering is 30% Ar gas.
sccm, oxygen gas 15 sccm, sample-target distance 60 mm,
The substrate heating temperature during film formation was set to 300.degree.

After the oxide semiconductor layer 122 was formed, heat treatment was performed at 450° C. for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 450° C. for 1 hour in an oxygen atmosphere.

The ion addition treatment was performed by an ion implantation method. Table 1 shows a summary of the ion implantation conditions that differ for each sample.

The resistance value of the sample was measured using a sheet resistance measuring machine, and the device was a VR manufactured by Hitachi Kokusai Denki.
-200 was used. 65, 66 and 67 show the sheet resistance measurement results.

From FIGS. 65, 66, and 67, for any ion species of phosphorus, argon, and xenon,
It was confirmed that the resistivity could be stably reduced in samples implanted with a dose amount of 3.0×10 ¹⁴ ions/cm ² or more.

10 Transistor 11 Transistor 12 Transistor 13 Transistor 14 Transistor 20 Display device 21 Display area 22 Peripheral circuit 24 Display device 50 Transistor 52 Transistor 60 Capacitive element 62 Capacitive element 70 Light emitting element 80 Liquid crystal element 100 Substrate 103 Polarizing plate 105 Protective substrate 110 Insulating layer 121 Metal oxide layer 122 Oxide semiconductor layer 123 Metal oxide layer 123a Metal oxide film 123b Metal oxide layer 125 Low resistance region 130 Source electrode layer 130b Conductive layer 140 Drain electrode layer 150 Gate insulating layer 150a Insulating film 150b Gate insulating layer 151 gate insulating layer 152 gate insulating layer 152a insulating film 152b insulating layer 160 gate electrode layer 160a conductive film 165 conductive layer 167 ion 170 insulating layer 172 insulating layer 173 oxygen 174 groove 175 insulating layer 175b insulating layer 176 insulating layer 180 insulating layer 190 conductive Layer 195 Conductive layer 197 Conductive layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel portion 211 Pixel 212 Subpixel 212B Subpixel 212G Subpixel 212R Subpixel 220 Photoelectric conversion element 230 Pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 Light 257 Wiring 260 Peripheral circuit 270 Peripheral circuit 280 Peripheral circuit 290 Peripheral circuit 300 Silicon substrate 310 Layer 320 Layer 330 Layer 340 Layer 351 Transistor 353 Transistor 360 Photodiode 361 Anode 362 Cathode 363 low-resistance region 365 photodiode 366 semiconductor 367 semiconductor 368 semiconductor 370 plug 371 wiring 372 wiring 373 wiring 374 wiring 380 insulating layer 400 substrate 402 protective substrate 403 polarizing plate 410 conductive layer 415 conductive layer 418 light shielding layer 420 insulating layer 430 insulating layer 440 Spacer 445 Partition 450 EL layer 460 Colored layer 470 Adhesive layer 473 Adhesive layer 474 Adhesive layer 475 Adhesive layer 476 Adhesive layer 480 Conductive layer 490 Liquid crystal layer 510 Anisotropic conductive layer 530 Optical adjustment layer 601 Precursor 602 Precursor 700 Substrate 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal line driver circuit 710 Capacitor wiring 712 Scanning line 713 Scanning line 714 Signal line 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Driving transistor 723 Capacitive element 724 Light emitting element 725 Signal line 726 Scanning line 727 Power supply line 728 Common electrode 800 RF tag 801 Communication device 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulator circuit 808 Modulator circuit 809 Logic circuit 810 Memory circuit 811 ROM
1189 ROM interface 1190 Substrate 1191 ALU
1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM
1200 memory element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitive element 1208 capacitive element 1209 transistor 1210 transistor 1213 transistor 1214 transistor 1220 circuit 1700 substrate 1701 chamber 1702 load chamber 1703 pretreatment chamber 1704 chamber 1705 chamber 1701a unload chamber Material supply part 1711b Material supply part 1712a High-speed valve 1712b High-speed valve 1713a Material introduction port 1713b Material introduction port 1714 Material discharge port 1715 Exhaust device 1716 Substrate holder 1720 Transfer chamber 1750 Interposer 1751 Chip 1752 Terminal 1753 Mold resin 1800 Panel 1801 Printed wiring board 1802 Package 1803 FPC
1804 Battery 2100 Transistor 2200 Transistor 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2207 Insulator 2211 Semiconductor substrate 2212 Insulator 2213 Gate electrode 2214 Gate insulator 2215 Source region and drain region 2800 Inverter 2810 OS transistor 2820 OS transistor 2831 Signal Waveform 2832 Signal waveform 2840 Broken line 2841 Solid line 2850 OS transistor 2860 CMOS inverter 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitive element 4000 RF tag 6000 Display module 6001 Upper cover 6002 Lower cover 6003 FPC
6004 Touch panel 6005 FPC
6006 display panel 6007 backlight unit 6008 light source 6009 frame 6010 printed circuit board 6011 battery 7101 housing 7102 housing 7103 display unit 7104 display unit 7105 microphone 7106 speaker 7107 operation keys 7108 stylus 7302 housing 7304 display unit 7311 operation buttons 7312 operation buttons 7313 Connection terminal 7321 Band 7322 Clasp 7501 Housing 7502 Display unit 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Housing 7702 Housing 7703 Display unit 7704 Operation keys 7705 Lens 7706 Connection unit 7901 Telephone pole 7902 Display unit 8000 Camera 8001 Housing Body 8002 Display unit 8003 Operation button 8004 Shutter button 8005 Joint unit 8006 Lens 8100 Viewfinder 8101 Housing 8102 Display unit 8103 Button 8121 Housing 8122 Display unit 8123 Keyboard 8124 Pointing device 8200 Head-mounted display 8201 Mounting unit 8202 Lens 8203 Main body 8204 Display unit 8205 Cable 8206 Battery 9700 Automobile 9701 Body 9702 Wheel 9703 Dashboard 9704 Light 9710 Display 9711 Display 9712 Display 9713 Display 9714 Display 9715 Display 9721 Display 9722 Display 9723 Display

Claims (2)

a first transistor having a first channel-forming region comprising silicon;
a second transistor including a second channel formation region having an oxide semiconductor;
A semiconductor device having a capacitive element,
a first insulating layer on the first channel forming region;
a first conductive layer having a region in contact with the top surface of the first insulating layer and having a region functioning as a gate electrode of the first transistor;
a second insulating layer on the first conductive layer;
a second conductive layer having a region in contact with the upper surface of the second insulating layer and having a region functioning as a first gate electrode of the second transistor;
a third insulating layer on the second conductive layer;
an oxide semiconductor layer located on the third insulating layer and having the second channel formation region;
a fourth insulating layer located on the oxide semiconductor layer;
a third conductive layer having a region in contact with the upper surface of the fourth insulating layer and having a region functioning as a second gate electrode of the second transistor;
a fifth insulating layer overlying the third conductive layer;
a fourth conductive layer having a region in contact with the top surface of the fifth insulating layer and constantly conducting to one of the source region and the drain region of the second transistor;
a fifth conductive layer located on the fifth insulating layer and having a region functioning as one electrode of the capacitive element;
a sixth insulating layer on the fifth conductive layer;
a sixth conductive layer located on the sixth insulating layer and having a region functioning as the other electrode of the capacitive element;
the fifth conductive layer is always conductive with the other of the source region and the drain region of the second transistor;
the fifth conductive layer is always conductive with the gate electrode of the first transistor;
The semiconductor device, wherein the sixth conductive layer has a region overlapping with the first channel forming region, a region overlapping with the second channel forming region, and a region overlapping with the fourth conductive layer. a first transistor having a first channel-forming region comprising silicon;
a second transistor including a second channel formation region having an oxide semiconductor;
A semiconductor device having a capacitive element,
a first insulating layer on the first channel forming region;
a first conductive layer having a region in contact with the top surface of the first insulating layer and having a region functioning as a gate electrode of the first transistor;
a second insulating layer on the first conductive layer;
a second conductive layer having a region in contact with the upper surface of the second insulating layer and having a region functioning as a first gate electrode of the second transistor;
a third insulating layer on the second conductive layer;
an oxide semiconductor layer located on the third insulating layer and having the second channel formation region;
a fourth insulating layer located on the oxide semiconductor layer;
a third conductive layer having a region in contact with the upper surface of the fourth insulating layer and having a region functioning as a second gate electrode of the second transistor;
a fifth insulating layer overlying the third conductive layer;
a fourth conductive layer having a region in contact with the top surface of the fifth insulating layer and constantly conducting to one of the source region and the drain region of the second transistor;
a fifth conductive layer located on the fifth insulating layer and having a region functioning as one electrode of the capacitive element;
a sixth insulating layer on the fifth conductive layer;
a sixth conductive layer located on the sixth insulating layer and having a region functioning as the other electrode of the capacitive element;
the fifth conductive layer is always conductive with the other of the source region and the drain region of the second transistor;
the fifth conductive layer is always conductive with the gate electrode of the first transistor;
the sixth conductive layer has a region overlapping with the first channel forming region, a region overlapping with the second channel forming region, and a region overlapping with the fourth conductive layer;
A semiconductor device, wherein a part of the lower surface of the third conductive layer is located below the lower surface of the oxide semiconductor layer in a cross-sectional view of the second transistor in the channel width direction.

Images