JP2018022713A - Semiconductor device, method of manufacturing the same, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with reduced parasitic capacitance.SOLUTION: A semiconductor device comprises: a first insulating layer on a substrate; a first metal oxide layer on the first insulating layer; an oxide semiconductor layer on the first metal oxide layer; a second metal oxide layer on the oxide semiconductor layer; a gate insulating layer on the second metal oxide layer; a second insulating layer on the second metal oxide layer; and a gate electrode layer on the gate insulating layer. The gate insulating layer has a region in contact with a lateral face of the gate electrode layer. The second insulating layer has a region in contact with the gate insulating layer. The oxide semiconductor layer has first to third regions. The first region has a region overlapping the gate electrode layer. The second region has a region overlapping the gate insulating layer or the second insulating layer. The second region is a region between the first region and the third region. The second region and the third region have a region containing an element N (N is phosphor, argon, or xenon).SELECTED DRAWING: Figure 1

Description

The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, the present invention relates to, for example, a semiconductor device, a display device, a light emitting device, a power storage device, an imaging device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a semiconductor device or a manufacturing method thereof.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, the memory device, the display device, and the electronic device may include a semiconductor device.

A technique for forming a transistor using a semiconductor film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor.

JP 2006-165528 A

Miniaturization of a transistor is indispensable for manufacturing a semiconductor device in which transistors are highly integrated. However, an increase in the parasitic capacitance of the transistor becomes a problem in miniaturization of the transistor.

For example, in the transistor operation, when a parasitic capacitance exists near the channel (for example, between the source electrode and the drain electrode), time required for charging the parasitic capacitance is required. Therefore, the responsiveness of the transistor, and consequently the responsiveness of the semiconductor device is degraded.

Further, as the miniaturization of the transistor advances, the shape controllability of the transistor becomes more difficult. Variation caused by the manufacturing process greatly affects transistor characteristics and further reliability.

Therefore, an object of one embodiment of the present invention is to reduce the parasitic capacitance of a transistor. Another object is to provide a semiconductor device capable of high-speed operation. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to reduce variation in characteristics of a transistor or a semiconductor device due to a manufacturing process. Another object is to provide a semiconductor device including an oxide semiconductor layer with few oxygen vacancies. Another object is to provide a semiconductor device which can be formed by a simple process. Another object is to provide a semiconductor device having a structure in which the interface state density in the vicinity of an oxide semiconductor layer can be reduced. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device or the like. Another object is to provide a method for manufacturing the semiconductor device.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

(1)
One embodiment of the present invention includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, and an oxide semiconductor layer A second metal oxide layer; a gate insulating layer over the second metal oxide layer; and a gate electrode layer over the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region have a region overlapping with the gate electrode layer, the second region is a region between the first region and the third region, and the second region is the first region. The third region has a region having a lower resistance than the second region, and the second region and the third region have an element N (N is phosphorus, argon, , Xenon), a semiconductor device characterized by having a region.

(2)
Another embodiment of the present invention includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, and a first insulating layer. A second metal oxide layer on the oxide semiconductor layer, a first gate insulating layer on the second metal oxide layer, and a gate electrode layer on the first gate insulating layer, and the second metal oxide layer The physical layer and the first gate insulating layer have regions facing the side surfaces of the first metal oxide layer and the oxide semiconductor layer. The oxide semiconductor layer has first to third regions. The first region and the second region have a region overlapping with the gate electrode layer, the second region is a region between the first region and the third region, and the second region is compared with the first region. The third region has a low resistance region as compared with the second region, and the second region and the third region include the element N (N is phosphorus, argon, Senone) to have a region having a semiconductor device according to claim.

(3)
Another embodiment of the present invention is a semiconductor device characterized in that, in (2), a second gate insulating layer is provided between the first gate insulating layer and the gate electrode layer.

(4)
According to another aspect of the present invention, in any one of (1) to (3), the second region has a region where the concentration of element N is higher than that of the first region, and the third region is It is a semiconductor device characterized by having a region where the concentration of element N is higher than that of the second region.

(5)
According to another embodiment of the present invention, in any one of (1) to (4), the concentration of the element N in the third region is 1 × 10 ¹⁸ atoms / cm ³ or more and 1 × 10 ²² atoms / cm ³ or less. A semiconductor device characterized by having a region.

(6)
One embodiment of the present invention includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, and an oxide semiconductor layer A gate having a second metal oxide layer, a gate insulating layer on the second metal oxide layer, a second insulating layer on the second metal oxide layer, and a gate electrode layer on the gate insulating layer; The insulating layer has a region in contact with the side surface of the gate electrode layer, the second insulating layer has a region in contact with the gate insulating layer, the oxide semiconductor layer has first to third regions, The region has a region overlapping with the gate electrode layer, the second region has a gate insulating layer or a region overlapping with the second insulating layer, and the second region is a region between the first region and the third region. The second region and the third region have a region containing the element N (N is phosphorus, argon, xenon). A conductor arrangement.

(7)
According to another aspect of the present invention, in (6), the second region has a region having a lower resistance than the first region, and the third region is a region having a lower resistance than the second region. It is a semiconductor device characterized by having.

(8)
Another embodiment of the present invention is characterized in that in (6) or (7), the angle formed by the tangent line between the bottom surface of the substrate and the side surface of the gate electrode layer has a region that is greater than or equal to 60 degrees and less than or equal to 85 degrees. Semiconductor device.

(9)
In another embodiment of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, The stack of the metal oxide layer and the first oxide semiconductor layer is etched into an island shape using the first mask to form the second metal oxide layer and the second oxide semiconductor layer, and the second oxidation Forming a third metal oxide layer on the physical semiconductor layer and the first insulating layer, forming a second insulating layer on the third metal oxide layer, and performing a planarization treatment on the second insulating layer; To form a fourth insulating layer having a groove reaching the third metal oxide layer by etching a part of the third insulating layer using a second mask. A fifth insulating layer is formed on the insulating layer and the third metal oxide layer, a first conductive layer is formed on the fifth insulating layer, and the first conductive layer is formed. The fifth insulating layer is planarized until the fourth insulating layer is exposed to form the gate electrode layer and the sixth insulating layer, and the fourth insulating layer and the sixth insulating layer are formed using the gate electrode layer as a mask. A gate insulating layer is formed by etching the insulating layer, and a source region and a drain region are formed by adding ions to the second oxide semiconductor layer using the gate electrode layer as a mask. This is a method for manufacturing a semiconductor device.

(10)
In another embodiment of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, The stack of the metal oxide layer and the first oxide semiconductor layer is etched into an island shape using the first mask to form the second metal oxide layer and the second oxide semiconductor layer, and the second oxidation Forming a third metal oxide layer on the physical semiconductor layer and the first insulating layer; forming a first gate insulating layer on the third metal oxide layer; and forming a second insulating layer on the first gate insulating layer Forming a third insulating layer by performing planarization treatment on the second insulating layer, and etching a part of the third insulating layer using the second mask to thereby form the first gate insulating layer; Forming a fourth insulating layer having a groove reaching the first conductive layer, and forming a first conductive layer on the fourth insulating layer and the first gate insulating layer By planarizing the first conductive layer until the fourth insulating layer is exposed, a gate electrode layer is formed, and the fourth insulating layer is etched using the gate electrode layer as a mask. A region exposing one gate insulating layer is provided, and the first insulating layer is etched using the gate electrode layer as a mask to form a second gate insulating layer, and ions are added to the second oxide semiconductor layer Thus, a method for manufacturing a semiconductor device is characterized in that a source region and a drain region are formed.

(11)
In another embodiment of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, The stack of the metal oxide layer and the first oxide semiconductor layer is etched into an island shape using the first mask to form the second metal oxide layer and the second oxide semiconductor layer, and the second oxidation Forming a third metal oxide layer on the physical semiconductor layer and the first insulating layer; forming a first gate insulating layer on the third metal oxide layer; and forming a second insulating layer on the first gate insulating layer Forming a third insulating layer by performing planarization treatment on the second insulating layer, and etching a part of the third insulating layer using the second mask to thereby form the first gate insulating layer; A fourth insulating layer having a groove reaching the first insulating layer is formed, and a fifth insulating layer is formed on the fourth insulating layer and the first gate insulating layer The first conductive layer is formed on the fifth insulating layer, and the first conductive layer and the fifth insulating layer are planarized until the fourth insulating layer is exposed, whereby the gate electrode layer and the sixth insulating layer are formed. Forming a layer and etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask, thereby providing a region exposing the first gate insulating layer; A method for manufacturing a semiconductor device is characterized in that a source region and a drain region are formed by adding ions.

(12)
Another embodiment of the present invention is a method for manufacturing a semiconductor device according to any one of (9) to (11), in which phosphorus, argon, or xenon is used for ion addition.

(13)
According to another aspect of the present invention, in any one of (9) to (12), in the ion addition, a dose amount of ions is 1 × 10 ¹⁴ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less. A method for manufacturing a semiconductor device.

(14)
In another embodiment of the present invention, a first insulating layer is formed over a substrate, a stack of a first metal oxide layer and a first oxide semiconductor layer is formed over the first insulating layer, The stack of the metal oxide layer and the first oxide semiconductor layer is etched into an island shape using the first mask, thereby forming the second metal oxide layer and the second oxide semiconductor layer. A third metal oxide layer is formed over the oxide semiconductor layer and the first insulating layer, a second insulating layer is formed over the third metal oxide layer, and planarization treatment is performed on the second insulating layer. By forming a third insulating layer and etching a part of the third insulating layer using a second mask, a fourth insulating layer having a groove reaching the third metal oxide layer is formed. Forming a fifth insulating layer on the fourth insulating layer and the third metal oxide layer; forming a first conductive layer on the fifth insulating layer; The gate electrode layer and the sixth insulating layer are formed by planarizing the layer and the fifth insulating layer until the fourth insulating layer is exposed, and the fourth insulating layer is formed using the gate electrode layer as a mask. By etching the layer and the sixth insulating layer, a gate insulating layer having a region in contact with the side surface of the gate electrode layer and a seventh insulating layer having a region in contact with the gate insulating layer are formed, and the second oxide semiconductor layer is formed. A method for manufacturing a semiconductor device is characterized in that a source region and a drain region are formed by ion addition.

(15)
Another embodiment of the present invention is a method for manufacturing a semiconductor device according to (14), wherein phosphorus, argon, or xenon is used for ion addition.

(16)
Another embodiment of the present invention is that in (14) or (15), in the ion addition, the ion dose is 1 × 10 ¹⁴ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less. This is a feature of a method for manufacturing a semiconductor device.

(17)
Another embodiment of the present invention is the region according to any one of (14) to (16), in which the angle formed between the tangent to the side surface of the gate electrode layer and the bottom surface of the substrate is greater than or equal to 60 degrees and less than or equal to 85 degrees. It is a manufacturing method of a semiconductor device characterized by having.

(18)
Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (8), a housing, and a speaker.

Thus, by using one embodiment of the present invention, a parasitic capacitance of a transistor can be reduced and a semiconductor device capable of high speed operation can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, variation in characteristics of a transistor or a semiconductor device due to a manufacturing process can be reduced. Alternatively, a semiconductor device including an oxide semiconductor layer with few oxygen vacancies can be provided. Alternatively, a semiconductor device that can be formed by a simple process can be provided. Alternatively, a semiconductor device having a structure in which the interface state density in the vicinity of an oxide semiconductor layer can be reduced can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. Alternatively, a method for manufacturing the semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a schematic diagram illustrating a cross-sectional view and a band diagram of a transistor. The figure explaining the ALD film-forming principle. ALD apparatus schematic diagram. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 8A and 8B are a top view and cross-sectional views illustrating a method for manufacturing a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 2A and 2B are a cross-sectional view and a circuit diagram of a semiconductor device. 2A and 2B are a cross-sectional view and a circuit diagram of a semiconductor device. The top view which shows an imaging device. The top view which shows the pixel of an imaging device. Sectional drawing which shows an imaging device. Sectional drawing which shows an imaging device. 6A and 6B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention. 10A and 10B are a graph and a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention. FIG. 6 illustrates a configuration example of an RF tag. The figure explaining the structural example of CPU. The circuit diagram of a memory element. 8A and 8B illustrate a structure example of a display device and a circuit diagram of a pixel. The top view and sectional drawing of a liquid crystal display device. The top view and sectional drawing of a display apparatus. The figure explaining a display module. The perspective view showing the cross-sectional structure of the package using a lead frame type interposer, and the structure of a module. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device. Sectional drawing of a measurement sample. The sheet resistance measurement result of the measurement sample after ion implantation. The sheet resistance measurement result of the measurement sample after ion implantation. The sheet resistance measurement result of the measurement sample after ion implantation. The figure explaining the measurement result of the XRD spectrum of a sample. The figure explaining the TEM image of a sample, and an electron beam diffraction pattern. The figure explaining the EDX mapping of a sample.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

For example, in this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected, and X and Y are functional. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.

Alternatively, as another expression method, for example, “a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path. The third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2. " Or, “the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least the first connection path, and the first connection path is the second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path. , Y, and the third connection path does not have the second connection path. Or “the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is The second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor; The drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path. The fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor. can do. Using the same expression method as those examples, by defining the connection path in the circuit configuration, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are distinguished. The technical scope can be determined.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

<Additional notes regarding the description explaining the drawings>

In this specification, the terms and phrases such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings.

In the drawings, some components may be omitted from the top view (also referred to as a plan view or a layout view) or a perspective view in order to clarify the drawing.

In addition, “same” may have the same area or the same shape. Moreover, since it is assumed that it does not become the completely same shape on the relationship of a manufacturing process, it can paraphrase that it is the same even if it is substantially the same.

<Additional notes on paraphrased descriptions>

In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done.

Here, since the source and the drain vary depending on the structure or operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, a portion that functions as a source and a portion that functions as a drain are not referred to as a source or a drain, but one of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. There is a case.

Note that the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion between components, and are not limited in number. To do.

Further, in this specification and the like, an IC (integrated circuit) is formed on a substrate of a display panel, for example, by attaching FPC (Flexible Printed Circuits) or TCP (Tape Carrier Package) or the like to the substrate by a COG (Chip On Glass) method. ) May be called a display device.

The terms “film” and “layer” can be interchanged with each other depending on circumstances or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

<Notes on the definition of words>
Below, the definition of the phrase in this specification etc. is demonstrated.

In this specification, when the term “trench” or “groove” is used, it refers to a thin strip-shaped recess.

<About connection>

In this specification, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

Note that the content described in one embodiment (may be a part of content) is different from the content described in the embodiment (may be a part of content) and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

Note that a drawing (or part thereof) described in one embodiment may be another part of the drawing, another drawing (or part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

<Structure of transistor 10>
1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 10 of one embodiment of the present invention. 1A is a top view, FIG. 1B is a cross-sectional view taken along alternate long and short dash line A1-A2 shown in FIG. 1A, and FIG. 1C is a cross-section taken along A3-A4 shown in FIG. FIG. Note that in FIG. 1A, some elements are enlarged, reduced, or omitted for clarity of illustration. The direction of the alternate long and short dash line A1-A2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line A3-A4 may be referred to as a channel width direction.

The transistor 10 includes a substrate 100, an insulating layer 110, a metal oxide layer 121, an oxide semiconductor layer 122, a metal oxide layer 123, a low resistance region 125, a gate insulating layer 150, a gate electrode layer 160, The insulating layer 180, the conductive layer 190, and the conductive layer 195 are included.

The insulating layer 110 is provided on the substrate 100.

The metal oxide layer 121 is provided over the insulating layer 110.

The oxide semiconductor layer 122 is provided over the metal oxide layer 121. The oxide semiconductor layer 122 includes a low resistance region 125. The low resistance region includes one or more of hydrogen, nitrogen, helium, neon, argon, krypton, xenon, boron, phosphorus, tungsten, and aluminum. The low resistance region 125 functions as a source or a drain.

The metal oxide layer 123 is provided over the oxide semiconductor layer 122.

The gate insulating layer 150 is provided over the metal oxide layer 123.

The gate electrode layer 160 is provided over the gate insulating layer 150. Note that the gate electrode layer 160, the gate insulating layer 150, the metal oxide layer 123, and the oxide semiconductor layer 122 are provided so as to overlap with each other.

The insulating layer 180 is provided over the insulating layer 110.

The conductive layer 190 is provided over the low resistance region 125. The conductive layer 190 and the low resistance region 125 have a region to be electrically connected.

The conductive layer 195 is provided over the conductive layer 190.

The low resistance region 125 can be partly provided below the gate electrode layer. The channel region that overlaps with the gate electrode layer 160 is the first region, the region that overlaps with the gate electrode layer 160, the low resistance region 125 in which ions are partially diffused is the second region, and the low resistance region that does not overlap with the gate electrode layer 160 is the first region. Assuming that there are three regions, it can be said that the second region has a region having a lower resistance than that of the first region, and the third region has a region having a lower resistance than that of the second region. The resistance is obtained by measuring a resistance value (for example, sheet resistance measurement), and can be controlled by the impurity concentration. In addition, the third region has a region where the concentration of the above-described element is 1 × 10 ¹⁸ atoms / cm ³ or more and 1 × 10 ²² atoms / cm ³ or less.

<About the metal oxide layer>
Note that the metal oxide layers (e.g., the metal oxide layer 121 and the metal oxide layer 123) basically have insulating properties, and current flows in the vicinity of the interface with the semiconductor when the gate electric field or the drain electric field becomes strong. A layer that can flow through.

With the above structure, the parasitic capacitance between the gate and the source or between the gate and the drain can be reduced. As a result, the transistor 10 can operate at high speed, such as improved cutoff frequency characteristics.

In addition, since the gate, the source, and the drain of the transistor 10 can be formed by self-alignment, the alignment difficulty is lowered. Thus, a fine transistor can be easily manufactured.

In the transistor 10, the gate electrode layer 160 includes a metal oxide layer 121, an oxide semiconductor layer 122, a metal through a gate insulating layer 150 in the channel width direction, as illustrated in the cross-sectional view of FIG. A region facing the side surface of the oxide layer 123 is provided. That is, when a voltage is applied to the gate electrode layer 160, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. A structure of a transistor in which a semiconductor is surrounded by an electric field of a gate electrode layer is referred to as a surrounded channel (s-channel) structure.

Here, in the case where the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are combined to form an oxide, a channel is formed in the whole oxide (bulk) in the transistor 10 in the on state. Therefore, the on-current increases. On the other hand, in the off state, the channel region formed in the oxide semiconductor layer 122 with a wide band gap serves as a potential barrier, so that the off-state current can be further reduced.

<About channel length>
Note that the channel length in a transistor means, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap or a channel is formed in a top view of the transistor. The distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

<About channel width>
The channel width refers to a length of a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, for example. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

<About SCW>
Therefore, in this specification, in the top view of a transistor, an apparent channel width in a region where a semiconductor and a gate electrode overlap with each other may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

<Improved characteristics in miniaturization>
Miniaturization of transistors is indispensable for high integration of semiconductor devices. On the other hand, it is known that the electrical characteristics of a transistor deteriorate due to miniaturization of the transistor, and when the channel width is reduced, the on-state current is reduced.

For example, in the transistor of one embodiment of the present invention illustrated in FIG. 1, as described above, the metal oxide layer 123 is formed so as to cover the oxide semiconductor layer 122 in which a channel is formed. The insulating layer is not in contact. Therefore, carrier scattering generated at the interface between the channel formation region and the gate insulating layer can be suppressed, and the on-state current of the transistor can be increased.

In the transistor of one embodiment of the present invention, the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel. In addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122. Therefore, the on-state current can be further increased.

In addition, in the transistor of one embodiment of the present invention, the metal oxide layer 123 is formed over the metal oxide layer 121 and the oxide semiconductor layer 122 so that an interface state is hardly formed, and the oxide semiconductor layer 122 By using a layer located between the metal oxide layer 121 and the metal oxide layer 123, mixing of impurities from above and below can be suppressed. Therefore, in addition to improving the on-state current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Therefore, Icut (current when the gate voltage VG is 0 V) can be reduced, and power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, long-term reliability of the semiconductor device can be improved.

In the transistor of one embodiment of the present invention, the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel. In addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, so that the influence of the drain electric field can be suppressed and the short channel effect can be significantly suppressed. Therefore, good characteristics can be obtained even when miniaturized.

In addition, since the transistor of one embodiment of the present invention includes a wide band gap material in the oxide semiconductor layer 122 serving as a channel, the transistor has high source-drain breakdown voltage characteristics and stable electric characteristics in various temperature environments. be able to.

Note that although an example in which an oxide semiconductor layer or the like is used for a channel or the like is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, the channel, the vicinity thereof, the source region, the drain region, etc., depending on the case or depending on the situation, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide , Gallium nitride, organic semiconductor, or the like.

<Each transistor configuration>
Each structure of the transistor in this embodiment is described below.

<< Substrate 100 >>
As the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. It is also possible to use a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon On Insulator) substrate, or the like, and a semiconductor element is formed on these substrates. You may use what was provided. The substrate 100 is not limited to a simple support material, and may be a substrate on which other devices such as transistors are formed. In this case, any one or more of a gate, a source, and a drain of the transistor may be electrically connected to the other device.

Further, a flexible substrate may be used as the substrate 100. Note that as a method for providing a transistor over a flexible substrate, there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled and transferred to the substrate 100 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 100. Further, the substrate 100 may have elasticity. Further, the substrate 100 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 100 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate 100 is thinned, the semiconductor device can be reduced in weight. Further, by reducing the thickness of the substrate 100, there are cases where the glass 100 or the like is stretchable or has a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 100 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 100 which is a flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. The substrate 100, which is a flexible substrate, is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower. As the substrate 100 that is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, since aramid has a low coefficient of linear expansion, it is suitable as the substrate 100 that is a flexible substrate.

<< Insulating layer 110 >>
The insulating layer 110 includes silicon (Si), nitrogen (N), oxygen (O), fluorine (F), hydrogen (H), aluminum (Al), gallium (Ga), germanium (Ge), yttrium (Y), An insulating film containing one or more of zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), and tantalum (Ta) can be used.

The insulating layer 110 has a role of preventing diffusion of impurities from the substrate 100 and can also serve to supply oxygen to the oxide semiconductor layer 122 (the metal oxide layer 121 and the metal oxide layer 123). Therefore, the insulating layer 110 is preferably an insulating film containing oxygen, and more preferably an insulating film containing oxygen larger than the stoichiometric composition. For example, a film having an oxygen release amount converted to oxygen atoms of 1.0 × 10 ¹⁹ atoms / cm ³ or more by the TDS method is used. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C. In addition, when the substrate 100 is a substrate on which another device is formed as described above, the insulating layer 110 also has a function as an interlayer insulating film. In that case, it is preferable to perform a planarization process by a CMP (Chemical Mechanical Polishing) method or the like so that the surface becomes flat.

In addition, when the insulating layer 110 includes fluorine, fluorine gasified from the insulating layer can stabilize oxygen vacancies in the oxide semiconductor layer 122.

<< Metal oxide layer 121, oxide semiconductor layer 122, metal oxide layer 123 >>
The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are oxide semiconductor films containing In or Zn, and are typically In—Ga oxide, In—Zn oxide, In— There are Mg oxide, Zn-Mg oxide, and In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd).

An oxide that can be used as the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 preferably contains at least indium (In) or zinc (Zn). Or it is preferable that both In and Zn are included. In addition, in order to reduce variation in electric characteristics of a transistor including the oxide semiconductor layer, a stabilizer is preferably included together with the transistor.

Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb). ), Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

Content of indium, gallium, or the like in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 is determined by time-of-flight secondary ion mass spectrometry (TOF-SIMS) or X-ray electron spectroscopy ( XPS) and ICP mass spectrometry (ICP-MS).

Since the oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, the off-state current of the transistor 10 can be reduced.

The thickness of the oxide semiconductor layer 122 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm.

Note that the oxide semiconductor layer 122 may be formed thinner, the same, or thicker than at least the metal oxide layer 121. For example, when the oxide semiconductor layer 122 is thick, the on-state current of the transistor can be increased. The metal oxide layer 121 may have a thickness that does not lose the effect of suppressing the generation of interface states of the oxide semiconductor layer 122. For example, the thickness of the oxide semiconductor layer 122 can be greater than 1 time, 2 times or more, 4 times or more, or 6 times or more with respect to the thickness of the metal oxide layer 121. In the case where it is not necessary to increase the on-state current of the transistor, the thickness of the metal oxide layer 121 may be greater than or equal to the thickness of the oxide semiconductor layer 122. For example, when oxygen is added to the insulating layer 110 or the insulating layer 180, the amount of oxygen vacancies in the oxide semiconductor layer 122 can be reduced by heat treatment, and the electrical characteristics of the semiconductor device can be stabilized. .

When the compositions of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are different, the interface can be observed using a scanning transmission electron microscope STEM (Scanning Transmission Electron Microscope). There is.

In addition, the oxide semiconductor layer 122 preferably has a higher indium content than the metal oxide layer 121 and the metal oxide layer 123. In the oxide semiconductor layer, s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the In content, more s orbitals overlap, so an oxide having a composition with more In than M is obtained. The mobility is higher than that of an oxide having a composition in which In is equal to or less than M. Therefore, by using an oxide containing a large amount of indium for the oxide semiconductor layer 122, a transistor with high field-effect mobility can be realized.

In the case where the oxide semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), an oxide semiconductor is formed by a sputtering method. In the target used for forming the layer 122, when the atomic ratio of metal elements is In: M: Zn = x2: y2: z2, x2 / (x2 + y2 + z2) is preferably 1/3 or more. The metal atomic ratio of the oxide semiconductor layer 122 has a similar composition. Moreover, x2 / y2 is 1/3 or more and 6 or less, more preferably 1 or more and 6 or less, and z2 / y2 is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. Accordingly, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film is easily formed as the oxide semiconductor layer 122. As typical examples of the atomic ratio of the target metal element, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, 2: 1: 1.5, 2: 1: 2.3, 2: 1: 3, 3: 1: 2, 4: 2: 3, 4: 2: 4.1, and the like.

By having Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf or Nd at a higher atomic ratio than In as the metal oxide layer 121 and the metal oxide layer 123, the following effects can be obtained. May have. (1) The energy gap between the metal oxide layer 121 and the metal oxide layer 123 is increased. (2) The electron affinity of the metal oxide layer 121 and the metal oxide layer 123 is reduced. (3) Shield impurities from the outside. (4) Compared with the oxide semiconductor layer 122, the insulating property is increased. (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd is a metal element having a strong binding force with oxygen, so Al, Ti, Ga, Y, Zr, By having Sn, La, Ce, Mg, Hf, or Nd at a higher atomic ratio than In, oxygen vacancies are less likely to occur.

The metal oxide layer 121 and the metal oxide layer 123 are oxides composed of one or more elements included in the oxide semiconductor layer 122. Therefore, interface scattering hardly occurs at the interface between the oxide semiconductor layer 122, the metal oxide layer 121, and the metal oxide layer 123. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor 10 is increased.

The metal oxide layer 121 and the metal oxide layer 123 typically include an In—Ga oxide, an In—Zn oxide, an In—Mg oxide, a Ga—Zn oxide, a Zn—Mg oxide, an In— M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd) and the energy level at the lower end of the conduction band is higher than that of the oxide semiconductor layer 122. Near the vacuum level, typically, the difference between the energy level at the bottom of the conduction band of the metal oxide layer 121 and the metal oxide layer 123 and the energy level at the bottom of the conduction band of the oxide semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the metal oxide layer 121 and the metal oxide layer 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0. 2 eV or more, 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. The electron affinity indicates the difference between the vacuum level and the energy level at the bottom of the conduction band.

In the case where the metal oxide layer 121 and the metal oxide layer 123 are In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), Compared with the oxide semiconductor layer 122 formed by a sputtering method, M (Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, M included in the metal oxide layer 121 and the metal oxide layer 123 is used. Since the atomic ratio of Hf or Nd) is high and the element represented by M is more strongly bonded to oxygen than indium, oxygen vacancies are prevented from occurring in the metal oxide layer 121 and the metal oxide layer 123. It has a function. That is, the metal oxide layer 121 and the metal oxide layer 123 are oxide semiconductor films in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 122. The metal atomic ratio of the metal oxide layer 121 and the metal oxide layer 123 also has the same composition.

In the case where the metal oxide layer 121 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), the metal oxide layer 121 is formed. In the target used for film formation, when the atomic ratio of metal elements is In: M: Zn = x1: y1: z1, x1 / y1 <z1 / y1, and z1 / y1 is 1/10 or more. It is preferably 6 or less, more preferably 0.2 or more and 3 or less.

Further, since the metal oxide layer 121 and the metal oxide layer 123 have higher insulating properties than the oxide semiconductor layer 122, they can have a function similar to that of the gate insulating layer.

Alternatively, the metal oxide layer 123 can be replaced with a metal oxide such as aluminum oxide, gallium oxide, hafnium oxide, silicon oxide, germanium oxide, or zirconia oxide, or the metal oxide layer 123 can be formed over the metal oxide layer 123. Can also be included.

The metal oxide layer 123 may have a thickness that does not lose the effect of suppressing the generation of interface states of the oxide semiconductor layer 122. For example, the thickness may be equal to or less than that of the metal oxide layer 121. If the metal oxide layer 123 is thick, an electric field generated by the gate electrode layer 160 may not easily reach the oxide semiconductor layer 122; therefore, the metal oxide layer 123 is preferably formed thin. For example, the metal oxide layer 123 may be thinner than the oxide semiconductor layer 122. Note that the thickness of the metal oxide layer 123 may be set as appropriate depending on the voltage for driving the transistor in consideration of the withstand voltage of the gate insulating layer 150.

For example, the thickness of the metal oxide layer 123 is preferably 1 nm to 20 nm, or 3 nm to 10 nm.

In the case where the metal oxide layer 121 and the metal oxide layer 123 are In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), In the target used for forming the metal oxide layer 121 and the metal oxide layer 123, when the atomic ratio of metal elements is In: M: Zn = x3: y3: z3, x3 / y3 <x2 / y2. Z3 / y3 is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that when z3 / y3 is greater than or equal to 1 and less than or equal to 6, a CAAC-OS film can be easily formed as the metal oxide layer 121 and the metal oxide layer 123. As typical examples of the atomic ratio of the target metal element, In: M: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, 1: 3: 8, 1: 4: 4, 1: 4: 5, 1: 4: 6, 1: 4: 7, 1: 4: 8, 1: 5: 5, 1: 5: 6, 1: 5: 7, 1: 5: 8, 1: 6: 8, 1: 6: 4, 1: 9: 6, etc. Note that the atomic ratio is not limited thereto, and an atomic ratio appropriate to the required semiconductor characteristics may be used.

In addition, the atomic ratios of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may each include a variation of plus or minus 40% of the above atomic ratio as an error.

For example, in the case where an oxide semiconductor film to be the oxide semiconductor layer 122 is formed, the atomic ratio of metal elements is formed using In: Ga: Zn = 1: 1: 1 in the target used for forming the film. When formed, the atomic ratio of metal elements in the oxide semiconductor film is approximately In: Ga: Zn = 1: 1: 0.6, and the atomic ratio of zinc may be the same or may be decreased. Therefore, when the atomic ratio is described, the vicinity of the atomic ratio is included.

<About hydrogen concentration>
Hydrogen contained in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 reacts with oxygen bonded to metal atoms to become water, and at the same time, a lattice from which oxygen is released (or oxygen is desorbed). Oxygen deficiency is formed in the separated part). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated. Therefore, a transistor including an oxide semiconductor layer containing hydrogen is likely to be normally on.

Therefore, it is preferable that hydrogen be reduced as much as possible along with oxygen vacancies in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the interfaces thereof. For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) at the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and each interface is 1 × 10 ^16. atoms / cm ^{3 to} 2 × 10 ²⁰ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁹ atoms / cm ³ , more preferably 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 × It is desirable that it is 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less. As a result, the transistor 10 can have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

<About carbon and silicon concentration>
Further, when silicon or carbon which is one of Group 14 elements is included in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces, the metal oxide layer 121, the oxide In the physical semiconductor layer 122 and the metal oxide layer 123, oxygen vacancies increase and an n-type region is formed. Therefore, it is desirable to reduce the silicon and carbon concentrations at the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces. For example, the concentration of silicon or carbon obtained by SIMS at the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces is 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms. / Cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ¹⁸ atoms / cm ³ or less. Is desirable. As a result, the transistor 10 has an electrical characteristic that the threshold voltage is positive.

<Concentration of alkali metal and alkaline earth metal>
Further, when alkali metal and alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase off-state current of the transistor. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal at the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their interfaces. For example, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is set to 1 × 10 ^{18 at} the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces. atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. Thereby, the transistor 10 can have an electrical characteristic that the threshold voltage is positive.

<About nitrogen concentration>
In addition, when nitrogen is contained in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces, electrons that are carriers are generated, the carrier density is increased, and the n-type region is increased. Will be formed. As a result, a transistor including an oxide semiconductor layer containing nitrogen is likely to be normally on. Therefore, nitrogen is preferably reduced as much as possible in the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces. For example, the nitrogen concentration obtained by SIMS at the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the respective interfaces is 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ^3. Or less, preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × It is preferable to set it to 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less. Thereby, the transistor 10 can have an electrical characteristic that the threshold voltage is positive.

Note that this is not the case when the oxide semiconductor layer 122 includes excess zinc. Excess zinc may form oxygen vacancies in the oxide semiconductor layer 122. Therefore, in the case where surplus zinc is contained, oxygen vacancies due to surplus zinc may be inactivated by including 0.001 to 3 atomic% of nitrogen in the oxide semiconductor layer 122 in some cases. Therefore, the characteristic variation of the transistor is eliminated by the nitrogen, and reliability can be improved.

<About carrier density>
By reducing impurities in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, the carrier density of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 is reduced. be able to. Therefore, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 have a carrier density of 1 × 10 ¹⁵ pieces / cm ³ or less, preferably 1 × 10 ¹³ pieces / cm ³ or less, and more preferably. Is less than 8 × 10 ¹¹ pieces / cm ³ , more preferably less than 1 × 10 ¹¹ pieces / cm ³ , most preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm ³ or more. To do.

By using an oxide semiconductor layer with a low impurity concentration and a low density of defect states as the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, a transistor having more excellent electrical characteristics is manufactured. can do. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor layer has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor layer tends to have electrical characteristics with a positive threshold voltage. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor layer has a low defect level density and thus may have a low trap level density. In addition, a transistor including an oxide semiconductor layer with high purity intrinsic or substantially high purity intrinsic has extremely low off-state current, and the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V. It is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less. Therefore, a transistor in which a channel region is formed in the oxide semiconductor layer may have a small change in electrical characteristics and be a highly reliable transistor.

Further, the off-state current of the transistor in which the oxide semiconductor layer purified as described above is used for a channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor is reduced to several yA / μm to several zA / μm. It becomes possible.

The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have a non-single crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS, a polycrystalline structure, a microcrystalline structure, or an amorphous structure which will be described later. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have a microcrystalline structure, for example. The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 having a microcrystalline structure include microcrystals having a size of greater than or equal to 1 nm and less than 10 nm, for example. Alternatively, the oxide film and the oxide semiconductor film having a microcrystalline structure have a mixed phase structure in which an amorphous phase has a crystal part of 1 nm to less than 10 nm, for example.

The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have an amorphous structure, for example. The amorphous metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 have, for example, disordered atomic arrangement and no crystal component. Alternatively, the oxide film and the oxide semiconductor film having an amorphous structure have a completely amorphous structure and have no crystal part, for example.

Note that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may be a mixed film including a region having two or more structures of a CAAC-OS, a microcrystalline structure, and an amorphous structure. Good. As the mixed film, for example, there is a single layer structure including an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region. Alternatively, the mixed film can be a stacked structure of an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region, for example.

Note that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have a single crystal structure, for example.

By providing oxide films in which oxygen vacancies are less likely to occur than the oxide semiconductor layer 122 in contact with the upper and lower portions of the oxide semiconductor layer 122, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, since the oxide semiconductor layer 122 is in contact with the metal oxide layer 121 including one or more of the metal elements included in the oxide semiconductor layer 122 and the metal oxide layer 123, the metal oxide layer 121 and the oxide semiconductor layer 122 are used. And the interface state density at the interface between the oxide semiconductor layer 122 and the metal oxide layer 123 are extremely low. For example, after oxygen is added to the metal oxide layer 121, the metal oxide layer 123, the gate insulating layer 150, the insulating layer 110, and the insulating layer 180, heat treatment is performed so that the oxygen is converted into the metal oxide layer 121 and the metal oxide layer. Although oxygen moves to the oxide semiconductor layer 122 through the physical layer 123, oxygen is hardly captured at the interface state at this time, and oxygen contained in the metal oxide layer 121 or the metal oxide layer 123 is efficiently absorbed. The oxide semiconductor layer 122 can be moved. As a result, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, since oxygen is also added to the metal oxide layer 121 or the metal oxide layer 123, oxygen vacancies in the metal oxide layer 121 and the metal oxide layer 123 can be reduced. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced.

In addition, when the oxide semiconductor layer 122 is in contact with an insulating film having a different constituent element (eg, a gate insulating layer including a silicon oxide film), an interface state is formed, and the interface state may form a channel. . In such a case, a second transistor having a different threshold voltage appears, and the apparent threshold voltage of the transistor may fluctuate. However, since the metal oxide layer 121 including one or more metal elements included in the oxide semiconductor layer 122 and the metal oxide layer 123 are in contact with the oxide semiconductor layer 122, the interface between the metal oxide layer 121 and the oxide semiconductor layer 122 is used. In addition, it is difficult to form an interface state at the interface between the metal oxide layer 123 and the oxide semiconductor layer 122.

In addition, the metal oxide layer 121 and the metal oxide layer 123 suppress the formation of levels due to impurities due to entry of constituent elements of the insulating layer 110 and the gate insulating layer 150 into the oxide semiconductor layer 122, respectively. It also functions as a barrier film.

For example, in the case where an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that can be mixed into the gate insulating layer 150 is oxidized by metal oxidation. The material layer 121 or the metal oxide layer 123 may be mixed from the interface to about several nm. When an impurity such as silicon or carbon enters the oxide semiconductor layer 122, an impurity level is formed, and the impurity level may serve as a donor to generate an n-type impurity.

However, if the thicknesses of the metal oxide layer 121 and the metal oxide layer 123 are larger than several nanometers, mixed impurities such as silicon and carbon do not reach the oxide semiconductor layer 122; The impact is reduced.

Thus, by providing the metal oxide layer 121 and the metal oxide layer 123, variation in electrical characteristics such as threshold voltage of the transistor can be reduced.

Further, in the case where a channel is formed at the interface between the gate insulating layer 150 and the oxide semiconductor layer 122, interface scattering occurs at the interface, and the field-effect mobility of the transistor is reduced. However, since the metal oxide layer 121 including one or more metal elements included in the oxide semiconductor layer 122 and the metal oxide layer 123 are provided in contact with the oxide semiconductor layer 122, the oxide semiconductor layer 122 and the metal oxide layer 121, carrier scattering hardly occurs at the interface with the metal oxide layer 123, and the field-effect mobility of the transistor can be increased.

In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122 and the amount of oxygen vacancies in the metal oxide layer 121 and the metal oxide layer 123 in contact with the oxide semiconductor layer 122 can be reduced. The localized state density of the oxide semiconductor layer 122 can be reduced. As a result, the transistor 10 described in this embodiment can have high reliability with little variation in threshold voltage. In addition, the transistor 10 described in this embodiment has excellent electrical characteristics.

Note that an insulating film containing silicon is often used as the gate insulating layer of the transistor; therefore, a region serving as a channel of the oxide semiconductor layer is in contact with the gate insulating layer as in the transistor of one embodiment of the present invention for the above reasons. It can be said that the structure which does not do is preferable. In addition, in the case where a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, carrier scattering occurs at the interface, and the field-effect mobility of the transistor may be reduced. From this point of view, it can be said that the region serving as a channel of the oxide semiconductor layer is preferably separated from the gate insulating layer.

Therefore, by using a stacked structure of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, a channel can be formed in the oxide semiconductor layer 122, and high field-effect mobility and stable electric power can be obtained. A transistor having characteristics can be formed.

Note that the oxide semiconductor layer is not necessarily provided in three layers, and may have a structure of a single layer, two layers, four layers, or five layers or more. In the case of a single layer, a layer corresponding to the oxide semiconductor layer 122 described in this embodiment may be used.

<Band diagram>
Here, a band diagram of a transistor of one embodiment of the present invention will be described with reference to FIGS. For ease of understanding, the band diagram illustrated in FIG. 2B illustrates the bottom of the conduction band of the insulating layer 110, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the gate insulating layer 150. The energy level (Ec) and the energy level (Ev) at the top of the valence band are shown.

As shown in FIG. 2B, in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, the energy level at the lower end of the conduction band changes continuously. This can also be understood from the fact that oxygen is easily diffused to each other because the elements constituting the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are common. Therefore, although the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are stacked bodies of films having different compositions, it can also be said that the physical properties are continuous.

Oxide semiconductor films stacked with the main component in common are not simply stacked layers, but a continuous junction (here, in particular, a U-shaped well in which the energy level at the bottom of the conduction band changes continuously between the layers). The (U Shape Well) structure is formed. That is, the stacked structure is formed so that there is no impurity that forms a defect level such as a trap center or a recombination center at the interface of each layer. If impurities are mixed between the laminated multilayer films, the continuity of the energy band is lost and carriers disappear at the interface by trapping or recombination.

Note that although Ec of the metal oxide layer 121 and the metal oxide layer 123 are similar to each other in FIG. 2B, they may be different from each other.

2B that the oxide semiconductor layer 122 serves as a well and a channel is formed in the oxide semiconductor layer 122 in the transistor 10. Note that a channel having a U-shaped well structure in which the energy at the lower end of the conduction band continuously changes with the oxide semiconductor layer 122 as a bottom can also be referred to as a buried channel.

Note that trap levels caused by impurities and defects can be formed in the vicinity of the interface between the metal oxide layer 121 and the metal oxide layer 123 and an insulating film such as a silicon oxide film. The presence of the metal oxide layer 123 can keep the oxide semiconductor layer 122 away from the trap level. Note that in the case where the energy difference between the Ec of the metal oxide layer 121 or the metal oxide layer 123 and the Ec of the oxide semiconductor layer 122 is small, the electrons in the oxide semiconductor layer 122 exceed the energy difference and are trapped. May reach. When electrons that become negative charges are trapped in the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, in the long-term storage test of the transistor, there is a concern that the trap is not fixed and the characteristics may be changed.

Therefore, in order to reduce variation in the threshold voltage of the transistor, it is necessary to provide an energy difference between the oxide semiconductor layer 122 and the Ec of the metal oxide layer 121 and the metal oxide layer 123. . Each energy difference is preferably 0.1 eV or more, and more preferably 0.2 eV or more.

Note that the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 preferably include a crystal part. In particular, stable electrical characteristics can be imparted to the transistor by using crystals oriented in the c-axis.

In the band diagram as illustrated in FIG. 2B, the metal oxide layer 123 is not provided, and an In—Ga oxide (eg, an atomic ratio of In is between the oxide semiconductor layer 122 and the gate insulating layer 150). : In = Ga oxide of Ga = 7: 93) or gallium oxide or the like may be provided. Further, an In—Ga oxide may be provided between the metal oxide layer 123 and the gate insulating layer 150 in a state where the metal oxide layer 123 is provided, or gallium oxide or the like may be provided.

As the oxide semiconductor layer 122, an oxide having an electron affinity higher than that of the metal oxide layer 121 and the metal oxide layer 123 is used. For example, the oxide semiconductor layer 122 has an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0. An oxide that is greater than or equal to 2 eV and less than or equal to 0.4 eV can be used.

The transistor described in this embodiment includes the metal oxide layer 121 and the metal oxide layer 123 which include one or more metal elements included in the oxide semiconductor layer 122; It is difficult to form interface states at the interface with the oxide semiconductor layer 122 and at the interface between the metal oxide layer 123 and the oxide semiconductor layer 122. Thus, by providing the metal oxide layer 121 and the metal oxide layer 123, variation or fluctuation in electrical characteristics such as threshold voltage of the transistor can be reduced.

<< Gate insulating layer 150 >>
The gate insulating layer 150 includes oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y ), Zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlO _x ), magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), silicon nitride oxide (SiN _x O _y ), silicon nitride (SiN _x ), Gallium oxide (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _x ), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x ), neodymium oxide (NdO _x ), hafnium oxide (HfO _x ) and oxide One or more types of tantalum (TaO _x ) can be included. The gate insulating layer 150 may be a stacked layer of the above materials. Note that the gate insulating layer 150 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity.

An example of a stacked structure of the gate insulating layer 150 is described. The gate insulating layer 150 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, the thickness of the gate insulating layer 150 can be increased as compared with the case where silicon oxide is used, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

By the way, a hafnium oxide surface having a crystal structure may have an interface state due to a defect. The interface state may function as a trap center. Therefore, when hafnium oxide is disposed in the vicinity of the channel region of the transistor, the electrical characteristics of the transistor may be deteriorated by the interface state. Therefore, in order to reduce the influence of the interface state, it may be preferable to separate the film from each other by disposing another film between the channel region of the transistor and hafnium oxide. This membrane has a buffer function. The film having a buffer function may be a film included in the gate insulating layer 150 or a film included in the oxide semiconductor film. That is, as the film having a buffer function, silicon oxide, silicon oxynitride, an oxide semiconductor layer, or the like can be used. For the film having a buffer function, for example, a semiconductor or an insulator having an energy gap larger than that of a semiconductor to be a channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or an insulator having an electron affinity lower than that of a semiconductor serving as a channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or an insulator having a higher ionization energy than a semiconductor serving as a channel region is used.

On the other hand, there is a case where the threshold voltage of the transistor can be controlled by trapping charges at the interface state (trap center) on the formation surface of hafnium oxide having the above-described crystal structure. In order to make this electric charge exist stably, for example, an insulator having an energy gap larger than that of hafnium oxide may be disposed between the channel region and hafnium oxide. Alternatively, a semiconductor or an insulator having an electron affinity smaller than that of hafnium oxide may be provided. Alternatively, a semiconductor or an insulator having higher ionization energy than hafnium oxide may be provided for the film having a buffer function. By using such an insulator, the charge trapped at the interface state is less likely to be released, and the charge can be held for a long time.

Examples of such an insulator include silicon oxide and silicon oxynitride. In order to capture charges at the interface state in the gate insulating layer 150, electrons may be moved from the oxide semiconductor film toward the gate electrode layer 160. As a specific example, the potential of the gate electrode layer 160 is changed to a source electrode layer 130 or a drain electrode layer 140 under a high temperature (eg, 125 ° C. to 450 ° C., typically 150 ° C. to 300 ° C.). It may be maintained for 1 second or longer, typically 1 minute or longer in a state higher than the potential of.

In this manner, the threshold voltage of the transistor in which a desired amount of electrons is captured at the interface state such as the gate insulating layer 150 is shifted to the positive side. By adjusting the voltage of the gate electrode layer 160 and the time during which the voltage is applied, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. Note that the charge may not be in the gate insulating layer 150 as long as charges can be trapped. A stacked film having a similar structure may be used for another insulating layer.

For example, in the case where a conductive layer is provided below the transistor 10, the insulating layer 110 can have a structure and a function similar to those of the gate insulating layer 150.

<< Gate electrode layer 160 >>
For the gate electrode layer 160, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum A material such as (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), or silicon (Si) can be used. The gate electrode layer 160 can be a stacked layer. For example, the above materials may be used alone or in combination, or a material containing nitrogen such as a nitride of the above material may be used in combination.

<Insulating layer 180>
Examples of the insulating layer 180 include magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), silicon nitride oxide (SiN _x O _y ), silicon nitride (SiN _x ), and oxide. Gallium (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _x ), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x ), neodymium oxide (NdO _x ), hafnium oxide (HfO _x ), and tantalum oxide An insulating film containing one or more of (TaO _x ) and aluminum oxide (AlO _x ) can be used. The insulating layer 180 may be a stacked layer of the above materials. The insulating layer preferably has more oxygen than the stoichiometric composition. Since oxygen released from the insulating layer 180 can be diffused into the channel formation region of the oxide semiconductor layer 122 through the gate insulating layer 150, oxygen can be compensated for oxygen vacancies formed in the channel formation region. it can. Therefore, stable electrical characteristics of the transistor can be obtained.

<< Conductive layer 190 >>
For the conductive layer 190, a material similar to that of the gate electrode layer 160 can be used.

<< Conductive layer 195 >>
For the conductive layer 195, a material similar to that of the gate electrode layer 160 can be used.

<Method for Manufacturing Transistor>
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. Note that portions overlapping with those described in the structure of the transistor are omitted. Further, the A1-A2 direction shown in FIGS. 5 to 13 may be referred to as the channel length direction shown in FIGS. 1 (A) and 1 (B). Further, the A3-A4 direction illustrated in FIGS. 5 to 13 may be referred to as a channel width direction illustrated in FIGS. 1A and 1C.

In this embodiment, each layer (an insulating layer, an oxide semiconductor layer, a conductive layer, or the like) included in the transistor is formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition ( It can be formed using a PLD (Pulse Laser Deposition) method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma CVD method are typical, but a thermal CVD method may also be used. As an example of the thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be used. In the sputtering method, the embedding property can be improved by using a combination of the long throw method and the collimation method.

<Thermal CVD method>
The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.

In the thermal CVD method, a source gas and an oxidant are simultaneously sent into a chamber, and the inside of the chamber is subjected to atmospheric pressure or reduced pressure. The film is formed by reacting in the vicinity of or on the substrate and depositing on the substrate. Also good.

In addition, a thermal CVD method such as an MOCVD method or an ALD method can form various films such as a metal film, a semiconductor film, and an inorganic insulating film described so far. For example, an In—Ga—Zn—O film can be formed. In the case of forming a film, trimethylindium, trimethylgallium, and dimethylzinc can be used. Note that the chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . Moreover, it is not limited to these combinations, Triethylgallium (chemical formula Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn (C ₂ H ₅ ) is used instead of dimethylzinc. ₂ ) can also be used.

<ALD method>
In a film forming apparatus using a conventional CVD method, at the time of film formation, one or more kinds of reaction source gases (precursors) are simultaneously supplied to a chamber. In a film formation apparatus using the ALD method, a precursor for reaction is sequentially introduced into a chamber, and film formation is performed by repeating the order of gas introduction. For example, each switching valve (also called a high-speed valve) is switched to supply two or more types of precursors to the chamber in order, and an inert gas (argon, or other) is provided after the first precursor so that a plurality of types of precursors are not mixed. Nitrogen etc.) are introduced, and the second precursor is introduced. Further, the second precursor can be introduced after the first precursor is discharged by evacuation instead of introducing the inert gas.

FIGS. 3A, 3B, 3C and 3D show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see FIG. 3A), and a first single layer is formed (see FIG. 3B). At this time, a metal atom or the like contained in the precursor can be bonded to a hydroxyl group present on the substrate surface. An alkyl group such as a methyl group or an ethyl group may be bonded to the metal atom. Reacting with the second precursor 602 introduced after exhausting the first precursor 601 (see FIG. 3C), the second single layer is laminated on the first single layer to form a thin film. (See FIG. 3D). For example, when an oxidizing agent is included as the second precursor, a chemical reaction occurs between a metal atom present in the first precursor or an alkyl group bonded to the metal atom and the oxidizing agent, and the oxide film Can be formed.

The ALD method is a film formation method based on a surface chemical reaction, and the precursor is adsorbed on the film formation surface and is formed further by a self-stop mechanism acting. For example, a precursor such as trimethylaluminum reacts with a hydroxyl group (OH group) present on the deposition surface. At this time, since only a surface reaction due to heat occurs, the precursor comes into contact with the film formation surface, and metal atoms or the like in the precursor can be adsorbed on the film formation surface through thermal energy. In addition, the precursor has a high vapor pressure, is thermally stable at the stage before film formation, does not self-decompose, and has a feature of fast chemical adsorption to the substrate. In addition, since the precursor is introduced as a gas, it is possible to form a film with good coverage even in a region having a high aspect ratio unevenness as long as the alternately introduced precursor has sufficient time for diffusion. it can.

Further, in the ALD method, a thin film having excellent step coverage can be formed by repeating a plurality of times until a desired thickness is achieved while controlling the order of gas introduction. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible. Further, by increasing the exhaust capacity, the film formation rate can be increased, and the impurity concentration in the film can be further reduced.

The ALD method includes an ALD method using heat (thermal ALD method) and an ALD method using plasma (plasma ALD method). In the thermal ALD method, a precursor reaction is performed using thermal energy, and in the plasma ALD method, the precursor reaction is performed in a radical state.

The ALD method can form a very thin film with high accuracy. The surface coverage is high and the film density is high even on the surface having irregularities.

<Plasma ALD method>
In addition, the film formation by the plasma ALD method enables the film formation at a lower temperature than the ALD method using heat (thermal ALD method). In the plasma ALD method, for example, a film can be formed at a temperature of 100 ° C. or lower without reducing the film formation rate. In the plasma ALD method, since N ₂ can be radicalized by plasma, not only an oxide but also a nitride can be formed.

Further, in the plasma ALD method, the oxidizing power of the oxidizing agent can be increased. Thereby, when the film is formed by the ALD method, the precursor remaining in the film or the organic component desorbed from the precursor can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, A film with a low impurity concentration can be provided.

In the case of performing plasma ALD, when generating radical species, plasma can be generated in a state of being separated from the substrate such as ICP (Inductively Coupled Plasma), and the substrate or the protective film is formed. Plasma damage to the film can be suppressed.

As described above, by using the plasma ALD method, the process temperature can be reduced and the surface coverage can be increased as compared with other film formation methods, so that the film can be formed. Thereby, the penetration | invasion of the water from the outside and hydrogen can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

<Description of ALD device>
FIG. 4A shows an example of a film formation apparatus using the ALD method. A film formation apparatus using the ALD method includes a film formation chamber (chamber 1701), raw material supply units 1711a and 1711b, high-speed valves 1712a and 1712b as flow controllers, raw material introduction ports 1713a and 1713b, and a raw material discharge port. 1714 and an exhaust device 1715. The raw material introduction ports 1713a and 1713b installed in the chamber 1701 are connected to the raw material supply units 1711a and 1711b via supply pipes and valves, respectively, and the raw material discharge port 1714 is connected via a discharge pipe, valves and pressure regulator. The exhaust device 1715 is connected.

There is a substrate holder 1716 provided with a heater inside the chamber, and a substrate 1700 to be deposited is placed on the substrate holder.

In the raw material supply units 1711a and 1711b, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer or a heating means. Alternatively, the raw material supply units 1711a and 1711b may be configured to supply a gaseous raw material gas.

Moreover, although the example which has provided the raw material supply parts 1711a and 1711b is shown, it is not specifically limited, You may provide three or more. The high-speed valves 1712a and 1712b can be precisely controlled with time, and are configured to supply either the source gas or the inert gas. The high-speed valves 1712a and 1712b are source gas flow controllers and can also be said to be inert gas flow controllers.

4A, after the substrate 1700 is carried onto the substrate holder 1716 and the chamber 1701 is hermetically sealed, the substrate 1700 is heated to a desired temperature (for example, 100 ° C. by heating the substrate holder 1716). The thin film is formed on the substrate surface by repeating the supply of the source gas, the exhaust by the exhaust device 1715, the supply of the inert gas, and the exhaust by the exhaust device 1715.

In the film formation apparatus shown in FIG. 4A, a material selected from hafnium, aluminum, tantalum, zirconium, or the like by appropriately selecting a raw material (such as a volatile organometallic compound) prepared in the raw material supply portions 1711a and 1711b. An insulating layer including an oxide containing the above elements (including a composite oxide) can be formed. Specifically, an insulating layer including hafnium oxide, an insulating layer including aluminum oxide, an insulating layer including hafnium silicate, or an insulating layer including aluminum silicate A film can be formed. In addition, by appropriately selecting raw materials (such as volatile organometallic compounds) prepared in the raw material supply units 1711a and 1711b, thin films such as metal layers such as tungsten layers and titanium layers and nitride layers such as titanium nitride layers can be formed. A film can also be formed.

For example, in the case where a hafnium oxide layer is formed by a film forming apparatus using the ALD method, a liquid containing a solvent and a hafnium precursor compound (hafnium amide such as hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Two kinds of gases, that is, a raw material gas and ozone (O ₃ ) as an oxidizing agent are used. In this case, the first source gas supplied from the source supply unit 1711a is TDMAH, and the second source gas supplied from the source supply unit 1711b is ozone. Note that the chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Other materials include tetrakis (ethylmethylamide) hafnium. Note that nitrogen has a function of eliminating a charge trap level. Therefore, when the source gas contains nitrogen, hafnium oxide having a low charge trapping level density can be formed.

For example, in the case where an aluminum oxide layer is formed by a film forming apparatus using the ALD method, a source gas obtained by vaporizing a liquid (TMA or the like) containing a solvent and an aluminum precursor compound, and H ₂ O 2 as an oxidizing agent are used. Use different types of gas. In this case, the first source gas supplied from the source supply unit 1711a is TMA, and the second source gas supplied from the source supply unit 1711b is H ₂ O. Note that the chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, in the case where a silicon oxide film is formed by a film formation apparatus using an ALD method, hexachlorodisilane is adsorbed on a film formation surface, chlorine contained in the adsorbed material is removed, and an oxidizing gas (O ₂ , one Dinitrogen oxide) radicals are supplied to react with the adsorbate.

For example, in the case where a tungsten film is formed by a film forming apparatus using the ALD method, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then WF ₆ gas and H _Two gases are successively introduced repeatedly to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using an ALD method, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced repeatedly. After forming an In—O layer, Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced repeatedly to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are sequentially introduced repeatedly. Thus, a ZnO layer is formed. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by mixing these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. In addition, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

《Multi-chamber manufacturing equipment》
FIG. 4B illustrates an example of a multi-chamber manufacturing apparatus including at least one film formation apparatus illustrated in FIG.

The manufacturing apparatus illustrated in FIG. 4B can continuously form a stacked film without exposure to the air, and prevents impurities from mixing and improves throughput.

The manufacturing apparatus illustrated in FIG. 4B includes at least a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, a chamber 1701 which is a film formation chamber, and an unload chamber 1706. Note that chambers (including load chambers, processing chambers, transfer chambers, film formation chambers, unload chambers, etc.) of manufacturing equipment are inert gases (nitrogen gas, etc.) with controlled dew points in order to prevent moisture from adhering. Is preferably filled, and desirably the reduced pressure is maintained.

The chamber 1704 and the chamber 1705 may be a film formation apparatus that uses the same ALD method as the chamber 1701, a film formation apparatus that uses a plasma CVD method, or a film formation apparatus that uses a sputtering method. Alternatively, a film forming apparatus using the MOCVD method may be used.

For example, an example of forming a stacked film using the film formation apparatus using the plasma CVD method as the chamber 1704 and the film formation apparatus using the MOCVD method as the chamber 1705 is described below.

In FIG. 4B, the top view of the transfer chamber 1720 shows an example of a hexagonal shape. However, depending on the number of layers of the laminated film, the manufacturing apparatus may be connected to more chambers as more polygons. Good. In FIG. 4B, the top surface shape of the substrate is shown as a rectangle, but it is not particularly limited. Although FIG. 4B illustrates a single-wafer type example, a batch-type film formation apparatus that forms a film on a plurality of substrates may be used.

<Formation of Insulating Layer 110>
First, the insulating layer 110 is formed over the substrate 100. The insulating layer 110 is formed by plasma CVD, thermal CVD (MOCVD, ALD), sputtering, or the like, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, Formed using metal oxide films such as zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, nitride insulating films such as silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide, or a mixed material thereof can do. Alternatively, a stack of the above materials may be used, and at least an upper layer of the stack in contact with the first metal oxide film to be the metal oxide layer 121 later may be an excess oxygen which can be a supply source of oxygen to the oxide semiconductor layer 122. It is preferable to form with the material containing.

Note that when the insulating layer 110 is formed, the use of a material that does not contain hydrogen or has a hydrogen content of 1% or less can suppress generation of oxygen vacancies in the oxide semiconductor layer, so that the transistor Can be stabilized.

For example, a silicon oxynitride film with a thickness of 100 nm can be used as the insulating layer 110 by a plasma CVD method.

Next, first heat treatment may be performed to desorb water, hydrogen, and the like contained in the insulating layer 110. As a result, the concentration of water, hydrogen, and the like contained in the insulating layer 110 can be reduced, and the amount of diffusion of water, hydrogen, and the like into the first metal oxide film to be formed later is reduced by heat treatment. can do.

<Formation of Oxide Semiconductor Film to be First Metal Oxide Film and Oxide Semiconductor Layer 122>
Next, a first metal oxide film that later becomes the metal oxide layer 121 and an oxide semiconductor film that later becomes the oxide semiconductor layer 122 are formed over the insulating layer 110. The first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 can be formed by a sputtering method, an MOCVD method, a PLD method, or the like, and more preferably formed by a sputtering method. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. Further, in the sputtering method, plasma damage at the time of film formation can be reduced by using a counter target method (also referred to as a counter electrode method, a gas phase sputtering method, or a VDSP (Vapor Deposition Sputtering) method).

For example, in the case where an oxide semiconductor film to be the oxide semiconductor layer 122 is formed by a sputtering method, each chamber in the sputtering apparatus is like a cryopump so as to remove water or the like that is an impurity for the oxide semiconductor film as much as possible. A high vacuum (up to about 5 × 10 ⁻⁷ Pa to 1 × 10 ⁻⁴ Pa) using a simple adsorption-type vacuum exhaust pump, and the substrate to be formed is 100 ° C. or higher, preferably 400 ° C. or higher. Preferably it can be heated. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that a gas containing a carbon component or moisture does not flow backward from the exhaust system into the chamber. Further, an exhaust system combining a turbo molecular pump and a cryopump may be used.

In order to obtain a high-purity intrinsic oxide semiconductor film, it is desirable not only to evacuate the chamber to a high vacuum but also to increase the purity of the sputtering gas. Oxygen gas or argon gas used as a sputtering gas has a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower. Can be prevented as much as possible.

As a sputtering gas, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are appropriately used. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the ratio of oxygen to the rare gas.

Note that when the oxide semiconductor film to be the oxide semiconductor layer 122 is formed, for example, when a sputtering method is used, the substrate temperature is 150 ° C. to 750 ° C., preferably 150 ° C. to 450 ° C., more preferably 200 ° C. A CAAC-OS film can be formed by forming an oxide semiconductor film at a temperature higher than or equal to 420 ° C. and lower than or equal to 420 ° C.

The material of the first metal oxide film can be selected so that the electron affinity is lower than that of the oxide semiconductor film to be the oxide semiconductor layer 122.

In the case where the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 are formed by, for example, a sputtering method, the first metal oxide film is formed by using a multi-chamber sputtering apparatus. The oxide semiconductor film to be the oxide semiconductor layer 122 can be continuously formed without being exposed to the air. In that case, excess impurities or the like can be prevented from entering the interface between the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122, and the interface state density can be reduced. As a result, the electrical characteristics of the transistor, in particular, the characteristics can be stabilized in the reliability test.

In addition, when the insulating layer 110 is damaged, the presence of the metal oxide layer 121 allows the oxide semiconductor layer 122 serving as a main conductive path to be away from the damaged portion, resulting in the electrical characteristics of the transistor, In particular, the characteristics can be stabilized in the reliability test.

For example, as the first metal oxide film, an insulating film formed with a thickness of 20 nm by sputtering using In: Ga: Zn = 1: 3: 4 (atomic ratio) as a target can be used. Alternatively, an oxide semiconductor film which is formed to a thickness of 15 nm by a sputtering method and using In: Ga: Zn = 1: 1: 1 (atomic ratio) as a target can be used as the oxide semiconductor film.

Note that after the oxide semiconductor film to be the first metal oxide film and the oxide semiconductor layer 122 is formed, the second heat treatment is performed, whereby the oxide to be the first metal oxide film and the oxide semiconductor layer 122 is obtained. The amount of oxygen vacancies in the physical semiconductor film can be reduced.

The temperature of the second heat treatment is 250 ° C. or higher and lower than the substrate strain point, preferably 300 ° C. or higher and 650 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower.

The second heat treatment is performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere or dry air (air having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower, preferably −120 ° C. or lower). Alternatively, it may be performed in a reduced pressure state. In addition to the dry air, it is preferable that hydrogen, water, and the like are not contained in the inert gas and oxygen. Typically, the dew point is preferably −80 ° C. or lower, preferably −100 ° C. or lower. The processing time is 3 minutes to 24 hours.

Note that in the heat treatment, an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used instead of an electric furnace. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, a rare gas such as argon or an inert gas such as nitrogen is used.

Note that the second heat treatment may be performed after etching for forming the metal oxide layer 121 and the oxide semiconductor layer 122, which will be described later.

For example, after heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere, heat treatment at 450 ° C. for 1 hour can be performed in an oxygen atmosphere.

Through the above steps, oxygen vacancies in the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 can be reduced, and impurities such as hydrogen and water can be reduced. In addition, the first metal oxide film with reduced localized state density and the oxide semiconductor film to be the oxide semiconductor layer 122 can be formed.

Note that the same effect as the heat treatment can be obtained by high-density plasma irradiation using oxygen as a material. The irradiation time is from 1 minute to 3 hours, preferably from 3 minutes to 2 hours, more preferably from 5 minutes to 1 hour.

<Formation of first conductive film>
Next, a first conductive film used as a hard mask is formed over the oxide semiconductor layer 122. The first conductive film is formed by sputtering, chemical vapor deposition (CVD) (metal organic chemical vapor deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD), or plasma chemical vapor deposition. (Including deposition (PECVD) method), vapor deposition method, pulsed laser deposition (PLD) method and the like.

The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc. It is preferable to form a single layer or a stacked layer of conductive films containing a simple substance made of a material, an alloy, or a compound containing these as a main component.

For example, a tungsten film with a thickness of 20 to 100 nm can be formed as the first conductive film by a sputtering method.

In this embodiment mode, the first conductive film is formed as a hard mask; however, the present invention is not limited to this, and an insulating film may be formed.

<Formation of Metal Oxide Layer 121 and Oxide Semiconductor Layer 122>
Next, a resist mask is formed by a lithography process, and the first conductive film is selectively etched using the resist mask to form the conductive layer 130b. Subsequently, after removing the resist on the hard mask, the oxide semiconductor film to be the oxide semiconductor layer 122 and the first metal oxide film are selectively etched, respectively, so that the oxide semiconductor layer 122 and the metal oxide layer 121 are etched. Are formed in an island shape (see FIG. 5). Note that a dry etching method can be used as an etching method. Note that when the oxide semiconductor layer is etched using the conductive layer 130b as a hard mask, the edge roughness of the oxide semiconductor layer after etching can be reduced as compared with the resist mask.

<Formation of Metal Oxide Film 123a>
Next, a metal oxide film 123 a used as the metal oxide layer 123 is formed over the oxide semiconductor layer 122 and the insulating layer 110. The metal oxide film 123a can be formed by a method similar to that of the oxide semiconductor film and the first metal oxide film, and the metal oxide film 123a has lower electron affinity than the oxide semiconductor film. The material can be selected.

In addition, the metal oxide film 123a is formed by a long-throw sputtering method, whereby the burying property of the metal oxide film 123a in the groove 174 can be improved.

For example, as the metal oxide film 123a, an oxide semiconductor film formed with a thickness of 5 nm by a sputtering method with a target of In: Ga: Zn = 1: 3: 2 (atomic ratio) can be used.

<Deposition of first insulating film>
Next, a first insulating film to be the insulating layer 175 later is formed over the metal oxide film 123a. The first insulating film can be formed by a method similar to that for the insulating layer 110.

The first insulating film is formed by, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxyfluoride, or gallium oxide by plasma CVD, thermal CVD (MOCVD, ALD), or sputtering. Metal oxide films such as germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide, nitride insulating films such as silicon nitride, silicon nitride oxide, aluminum nitride and aluminum nitride oxide, or these It is possible to form using a mixed material. Alternatively, a laminate of the above materials may be used.

<Planarization of the first insulating film>
Next, planarization treatment of the first insulating film is performed to form an insulating layer 175b (see FIG. 6). The planarization treatment can be performed using a CMP (Chemical Mechanical Polishing) method, a dry etching method, a reflow method, or the like. In the case where planarization is performed using the CMP method, a film having a composition different from that of the first insulating film is introduced over the first insulating film, whereby the film of the insulating layer 175b in the substrate surface after the CMP process is formed. The thickness can be made uniform.

<Formation of groove>
Next, a resist mask is formed over the planarized insulating layer 175b by a lithography process. Note that the lithography step may be performed after an organic film is applied over the insulating layer or after application over a resist mask. The organic film can include propylene glycol monomethyl ether, ethyl lactate, and the like. By using the organic film, in addition to the antireflection effect at the time of exposure, there are effects such as improvement in adhesion between the resist mask and the film and improvement in resolution. The organic film can be used for other processes.

Note that in the case of forming a transistor with a very short channel length, resist mask processing is performed using a method suitable for thin line processing such as electron beam exposure, immersion exposure, EUV (Extreme Ultra-Violet) exposure, and the like. Etching may be performed using a resist mask. Note that in the case where a resist mask is formed by electron beam exposure, if a positive resist is used as the resist mask, an exposure region can be minimized and throughput can be improved. By using such a method, a transistor with a channel length of 100 nm or less, 30 nm or less, and further 20 nm or less can be formed. Alternatively, fine processing may be performed by an exposure technique using X-rays or the like.

Using the resist mask, the insulating layer 175b is subjected to groove processing by a dry etching method until the metal oxide film 123a is exposed. Through the processing, the insulating layer 175 and the groove 174 are formed.

Note that the shape of the groove 174 is preferably perpendicular to the substrate surface.

In addition, the processing method of the groove part 174 is not limited to the said method. For example, not only the resist mask but also a hard mask may be used, and the shape of the resist mask may be controlled using a halftone mask in the lithography process. Further, the shape of the mask may be controlled by a nanoimprint method or the like. The method can also be applied to other steps.

<Formation of Second Insulating Film 150a>
Next, a second insulating film 150 a to be the gate insulating layer 150 is formed over the metal oxide film 123 a and the insulating layer 175. Examples of the second insulating film 150a include aluminum oxide (AlO _x ), magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), and silicon nitride oxide (SiN _x O _y). ), Silicon nitride (SiN _x ), gallium oxide (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _x ), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x ), neodymium oxide (NdO _x ) Hafnium oxide (HfO _x ), tantalum oxide (TaO _x ), or the like can be used. Note that the second insulating film 150a may be a stack of any of the above materials. The second insulating film 150a can be formed by sputtering, CVD (plasma CVD, MOCVD, ALD, or the like), MBE, or the like. The second insulating film 150a can be formed as appropriate using a method similar to that of the insulating layer 110.

For example, 10 nm of silicon oxynitride can be formed as the second insulating film 150a by a plasma CVD method.

<Formation of Conductive Film 160a>
Next, a conductive film 160a to be the gate electrode layer 160 is formed over the second insulating film 150a. (See FIG. 7). As the conductive film 160a, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum ( Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), or an alloy material containing these as a main component can be used. The conductive film 160a can be formed by a sputtering method, a CVD method (plasma CVD method, MOCVD method, ALD method, or the like), MBE method, vapor deposition method, plating method, or the like. As the conductive film 160a, a conductive film containing nitrogen may be used, or a stack of the conductive film and the conductive film containing nitrogen may be used.

For example, the conductive film 160a can have a stacked structure in which titanium nitride is formed to a thickness of 10 nm by an ALD method and tungsten is formed to a thickness of 150 nm by a metal CVD method.

<Planarization treatment>
Next, a flattening process is performed. The planarization treatment can be performed using a CMP method, a dry etching method, or the like. The planarization process may be terminated when the second insulating film 150a is exposed, or may be terminated when the insulating layer 175 is exposed. Thus, the gate electrode layer 160 and the gate insulating layer 150 can be formed (see FIG. 8).

<Etch back treatment of insulating layer 175>
Next, the insulating layer 175 is etched back by a dry etching method to expose the metal oxide film 123a. Further, the portion of the metal oxide film 123a that does not overlap with the gate electrode layer 160 is etched to form the metal oxide layer 123 (see FIG. 9).

Note that the method for forming the structure illustrated in FIG. 9 is not limited to the above.

For example, as illustrated in FIG. 10, the groove 174 may include a metal oxide layer 123 b, a gate insulating layer 150 b, and a gate electrode layer 160. Alternatively, as illustrated in FIG. 11, the second insulating film 150a may be formed over the metal oxide film 123a.

<Ion addition treatment>
Next, an addition treatment of ions 167 is performed on the oxide semiconductor layer 122 (see FIG. 12). Materials to be added are hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), boron (B), phosphorus (P), tungsten (W), Aluminum (Al) or the like can be used. Examples of the addition method include an ion doping method, an ion implantation method, a plasma immersion ion implantation method, and a high-density plasma treatment method. In miniaturization, it is preferable to use an ion implantation method because addition of impurities other than predetermined ions can be suppressed. In addition, the ion doping method and the plasma immersion ion implantation method are excellent when a large area is processed.

In the ion addition process, it is desirable to adjust the acceleration voltage of ions according to the ion species and the implantation depth. For example, it can be 1 kV or more and 100 kV or less, 3 kV or more and 60 kV or less. The dose amount of ions is 1 × 10 ¹² ions / cm ² or more and 1 × 10 ¹⁷ ions / cm ² or less, preferably 1 × 10 ¹⁴ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less. desirable.

By the ion addition treatment, oxygen vacancies are formed in the oxide semiconductor layer 122 and the low resistance region 125 can be provided (see FIG. 13). Note that in the oxide semiconductor layer 122, ions may be diffused also in a region overlapping with the gate electrode layer, and the low-resistance region 125 may be formed in a portion overlapping with the gate electrode layer.

In addition, by performing heat treatment after the ion addition treatment, damage to the film that occurs during the ion addition treatment can be repaired.

Next, a third insulating film to be the insulating layer 180 later is formed. A method for forming the third insulating film can be the same as that of the insulating layer 110. It is desirable to planarize after the third insulating film is formed.

Next, in order to provide an opening in the third insulating film, etching is performed by a dry etching method.

Next, after a third conductive film to be the conductive layer 190 is formed in the opening, planarization treatment is performed to form the conductive layer 190.

Next, a fourth conductive film to be the conductive layer 195 is formed over the conductive layer 190. The conductive layer 195 is formed by using a photolithography method, a nanoimprinting method, or the like for the fourth conductive film.

By using the above manufacturing method, the transistor 10 can be formed. By using the above manufacturing method, an extremely fine transistor having a channel length of 100 nm or less, 30 nm or less, and further 20 nm or less can be stably manufactured.

Note that the transistor 10 may include a region where the gate insulating layer 150 is in contact with the side surface of the gate electrode layer (see FIG. 14).

<Modification Example 1 of Transistor 10: Transistor 11>
A transistor 11 having a shape different from that of the transistor 10 illustrated in FIG. 1 will be described with reference to FIGS.

15A, 15B, and 15C are a top view and a cross-sectional view of the transistor 11, respectively. 15A is a top view of the transistor 11, FIG. 15B is a cross-sectional view taken along the alternate long and short dash line B1-B2 in FIG. 15A, and FIG. 15C is a cross-sectional view between B3-B4. .

The transistor 11 is different from the transistor 10 in that the transistor 11 includes an insulating layer 170 and an insulating layer 172.

<Insulating layer 170>
The insulating layer 170 includes oxygen, nitrogen, fluorine, aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), and lanthanum (La). ), Neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. Aluminum oxide (AlO _x ), magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), silicon nitride oxide (SiN _x O _y ), silicon nitride (SiN _x ), gallium oxide (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _x ), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x ), neodymium oxide (NdO _x ), hafnium oxide (HfO _x ), and tantalum oxide ( One or more TaO _x ) can be included.

The insulating layer 170 preferably includes an aluminum oxide (AlO _x ) film. The aluminum oxide film can have a blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture, and oxygen. Therefore, the aluminum oxide film includes a metal oxide layer 121, an oxide semiconductor layer 122, and a metal oxide layer 123 that are impurities such as hydrogen and moisture that cause variation in electric characteristics of the transistor during and after the manufacturing process of the transistor. Effects of preventing entry into oxygen, preventing release of oxygen as a main component material from the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, and preventing unnecessary release of oxygen from the insulating layer 110. Suitable for use as a protective film.

The insulating layer 170 is preferably a film having an oxygen supply capability. When the insulating layer 170 is formed, a mixed layer is formed at the interface with the other oxide layer, and oxygen is filled in the mixed layer or the other oxide layer, and oxygen is then converted into the oxide semiconductor layer by the subsequent heat treatment. Oxygen can be compensated for oxygen vacancies in the oxide semiconductor layer by diffusing into the oxide semiconductor layer, and transistor characteristics (eg, threshold voltage, reliability, and the like) can be improved.

The insulating layer 170 may be a single layer or a stacked layer. Further, another insulating layer may be provided on the upper side or the lower side of the insulating layer. For example, an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide is used. be able to. The insulating layer preferably has more oxygen than the stoichiometric composition. Since oxygen released from the insulating layer can be diffused into the channel formation region of the oxide semiconductor layer 122 through the gate insulating layer 150 or the insulating layer 110, oxygen is deficient in oxygen vacancies formed in the channel formation region. Can be compensated. Therefore, stable electrical characteristics of the transistor can be obtained.

<< Insulating layer 172 >>
The insulating layer 172 includes oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), and yttrium (Y). , Zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlO _x ), magnesium oxide (MgO _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), silicon nitride oxide (SiN _x O _y ), silicon nitride (SiN _x ), Gallium oxide (GaO _x ), germanium oxide (GeO _x ), yttrium oxide (YO _x ), zirconium oxide (ZrO _x ), lanthanum oxide (LaO _x ), neodymium oxide (NdO _x ), hafnium oxide (HfO _x ) and oxide An insulating film containing one or more types of tantalum (TaO _x ) can be used. The insulating layer 172 may be a stack of the above materials.

The insulating layer 172 preferably includes an aluminum oxide film. The aluminum oxide film can have a blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture, and oxygen. Therefore, the aluminum oxide film includes a metal oxide layer 121, an oxide semiconductor layer 122, and a metal oxide layer 123 that are impurities such as hydrogen and moisture that cause variation in electric characteristics of the transistor during and after the manufacturing process of the transistor. As a protective film having an effect of preventing entry into oxygen, preventing release of oxygen as a main component material from the metal oxide layer 121, oxide semiconductor layer 122, and metal oxide layer 123, and preventing release of oxygen from the insulating layer 110 Suitable for use.

The insulating layer 172 can function as a protective film. By providing the insulating layer 172, the gate insulating layer 150 can be protected from plasma damage. Thereby, it can suppress that an electron trap is provided in the channel vicinity.

<Method for Manufacturing Transistor 11>
A method for manufacturing the transistor 11 will be described with reference to FIGS. Note that the description is referred to for portions similar to those of the method for manufacturing the transistor 10.

<Formation of Insulating Layer 172>
An insulating layer 172 is formed over the insulating layer 110, the oxide semiconductor layer 122, and the gate electrode layer 160 (see FIG. 16). Note that formation of the insulating layer 172 may cause plasma damage to the oxide semiconductor layer 122 and the gate insulating layer 150; therefore, a film formed by MOCVD or ALD is preferably used.

The insulating layer 172 has a thickness of 1 nm to 30 nm, preferably 3 nm to 10 nm.

Alternatively, ion addition treatment may be performed on the oxide semiconductor layer 122 after the insulating layer 172 is formed (see FIG. 16). Accordingly, damage to the oxide semiconductor layer 122 during the ion addition treatment can be reduced while forming a low resistance region (see FIG. 17).

The insulating layer 172 may be provided by being processed using a lithography method, a nano-imprinting method, a dry etching method, or the like after film formation, or may be only formed.

<Formation of Insulating Layer 170>
Next, the insulating layer 170 is formed over the insulating layer 172. The insulating layer 170 may be a single layer or a stacked layer. The insulating layer 170 can be formed using a material, a method, or the like similar to that of the insulating layer 110.

The insulating layer 170 is preferably an aluminum oxide film formed by a sputtering method. When forming an aluminum oxide film by a sputtering method, it is desirable to have an oxygen gas as a gas used at the time of film formation. In addition, the oxygen gas is desirably contained in an amount of 1% to 100% by volume, preferably 4% to 100% by volume, and more preferably 10% to 100% by volume. By setting oxygen to 1% by volume or more, surplus oxygen can be supplied to the insulating layer or to the insulating layer in contact therewith. In addition, oxygen can be added to the layer in contact with the layer.

For example, the insulating layer 170 can be formed using aluminum oxide as a target and oxygen gas as a gas used at the time of sputtering in an amount of 50% by volume, and the thickness can be 20 nm to 40 nm.

Next, it is preferable to perform a heat treatment. The heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, preferably 250 ° C. or higher and 500 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower. Through the heat treatment, oxygen 173 added to the insulating layer (e.g., the insulating layer 110) diffuses and moves to the oxide semiconductor layer 122, so that oxygen vacancies in the oxide semiconductor layer 122 are filled with oxygen. (See FIG. 18).

In this embodiment, heat treatment can be performed at 400 ° C. for 1 hour in an oxygen atmosphere.

Note that the heat treatment may be performed as needed in other steps. By performing the heat treatment, defects present in the film can be repaired, and the interface state density can be reduced.

<Addition of oxygen>
Note that the treatment for adding oxygen is not limited to the treatment through the insulating layer 170. The treatment for adding oxygen may be performed on the insulating layer 110 and the insulating layer 175, may be performed on the first metal oxide film and the metal oxide film 123a, or may be performed on other insulating layers. Good. As oxygen to be added, one or more of oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, and the like are used. As a method for adding oxygen, there are an ion doping method, an ion implantation method, a plasma immersion ion implantation method, and the like.

Note that when an ion implantation method is used as a method for adding oxygen, an oxygen atom ion or an oxygen molecular ion may be used. When oxygen molecular ions are used, damage to the added film can be reduced. Oxygen molecular ions are separated at the surface of the film to which the oxygen is added and added as oxygen atom ions. Since energy is used to separate oxygen molecules from oxygen atoms, the energy per oxygen atom ion when oxygen molecule ions are added to the film to which oxygen is added is the oxygen atom ions added to the oxygen. It is low compared with the case where it is added to the film. For this reason, damage to the film to which the oxygen is added can be reduced.

In addition, since the energy of each oxygen atom ion implanted into the film to which the oxygen is added is reduced by using oxygen molecular ions, the position where the oxygen atom ions are implanted is shallow. Therefore, oxygen atoms easily move in the heat treatment later, so that more oxygen can be supplied to the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123.

Also, when oxygen molecular ions are implanted, the energy per oxygen atom ion is lower than when oxygen atom ions are implanted. Therefore, by using oxygen molecular ions for implantation, the acceleration voltage can be increased, and the throughput can be increased. In addition, by implanting using oxygen molecular ions, the dose can be halved compared to when oxygen atom ions are used. As a result, the throughput can be increased.

When oxygen is added to the film to which oxygen is added, oxygen is added to the film to which oxygen is added under such a condition that the peak of the concentration profile of oxygen atom ions is located in the film to which oxygen is added. It is preferable to add. As a result, compared with the case of implanting oxygen atom ions, the acceleration voltage at the time of implantation can be reduced, and damage to the film to which the oxygen is added can be reduced. That is, the amount of defects in the film to which oxygen is added can be reduced, and fluctuations in electrical characteristics of the transistor can be suppressed. Further, the amount of oxygen atoms added at the interface between the insulating layer 110 and the metal oxide layer 121 is less than 1 × 10 ²¹ atoms / cm ³ , or less than 1 × 10 ²⁰ atoms / cm ³ , or 1 × 10 ¹⁹ atoms / cm 3. By adding oxygen to the film to which oxygen is added so as to be less than ^3, the amount of oxygen added to the insulating layer 110 can be reduced. As a result, damage to the film to which oxygen is added can be reduced, and fluctuations in electrical characteristics of the transistor can be suppressed.

Alternatively, oxygen may be added to the film to which oxygen is added by a plasma treatment (plasma immersion ion implantation method) in which the film to which oxygen is added is exposed to plasma generated in an atmosphere having oxygen. As an atmosphere containing oxygen, there is an atmosphere containing an oxidizing gas such as oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide. Note that it is possible to increase the amount of oxygen added to the film to which oxygen is added by exposing the film to which oxygen is added to plasma generated with a bias applied to the substrate 100 side. An example of an apparatus that performs such plasma processing is an ashing apparatus.

For example, oxygen molecular ions having an acceleration voltage of 60 kV and a dose of 2 × 10 ¹⁶ / cm ² can be added to the insulating layer 110 by an ion implantation method.

The above steps can also be applied to the transistor 10 and other transistors.

Through the above, the localized state density of the oxide semiconductor film is reduced, and a transistor having excellent electric characteristics can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to aging and stress tests can be manufactured.

<Modification Example 2 of Transistor 10: Transistor 12>
A transistor 12 having a shape different from that of the transistor 10 illustrated in FIG. 1 will be described with reference to FIGS.

19A, 19B, and 19C are a top view and a cross-sectional view of the transistor 12, respectively. 19A is a top view of the transistor 12, FIG. 19B is a cross-sectional view taken along the alternate long and short dash line C1-C2 in FIG. 19A, and FIG. 19C is a cross-sectional view between C3-C4. .

The transistor 12 is different from the transistor 10 in that the metal oxide layer 123 has a region in contact with the side edges of the oxide semiconductor layer 122 and the metal oxide layer 121 and a conductive layer 165. Different. Note that in the transistor 12, the metal oxide film 123a can be used as the metal oxide layer 123 without being etched.

<< Conductive layer 165 >>
The conductive layer 165 includes, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum ( It can have materials such as Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), or silicon. The conductive layer 165 can be a stacked layer. In the case of stacking, for example, a material containing nitrogen such as a nitride of the above material may be used in combination.

The conductive layer 165 can have a function similar to that of the gate electrode layer 160. The conductive layer 165 may have a structure in which the same potential as that of the gate electrode layer 160 is applied or a structure in which a different potential can be applied.

In the transistor 12 provided with the conductive layer 165, the insulating layer 110 can have the same structure and function as the gate insulating layer 150.

With the above structure, damage to the oxide semiconductor layer during the ion addition treatment can be suppressed (see FIGS. 20 and 21). Further, the side end portion of the oxide semiconductor layer 122 can be protected. As described above, the electrical characteristics of the transistor can be stabilized.

<Modification Example 3 of Transistor 10: Transistor 13>
A transistor 13 having a shape different from that of the transistor 10 illustrated in FIG. 1 will be described with reference to FIGS.

22A, 22B, and 22C are a top view and a cross-sectional view of the transistor 13, respectively. 22A is a top view of the transistor 13, FIG. 22B is a cross-sectional view taken along the alternate long and short dash line D1-D2 in FIG. 22A, and FIG. 22C is a cross-sectional view between D3-D4. .

Similarly to the transistor 12, the transistor 13 includes a gate in addition to the region in which the metal oxide layer 123 is in contact with the oxide semiconductor layer 122, the side edges of the metal oxide layer 121 in the channel length direction and the channel width direction. The transistor 10 is different from the transistor 10 in that an insulating layer 151 and a gate insulating layer 152 are provided.

<< Gate Insulating Layer 151, Gate Insulating Layer 152 >>
The gate insulating layer 151 and the gate insulating layer 152 can have the same material as the gate insulating layer 150.

Note that the gate insulating layer 151 and the gate insulating layer 152 are preferably formed using different materials.

<Method for Manufacturing Transistor 13>
A method for manufacturing the transistor 13 will be described with reference to FIGS. Note that the description is referred to for portions similar to those of the method for manufacturing the transistor 10.

<Formation of Gate Insulating Layer 151>
A gate insulating layer 151 is formed after the metal oxide layer 123 is formed. The gate insulating layer 151 can be formed by a sputtering method, a CVD method (plasma CVD method, MOCVD method, ALD method, or the like), an MBE method, or the like.

For example, 5 nm of aluminum oxide can be formed as the gate insulating layer 151 by an ALD method.

<Formation of Insulating Film 152a>
Next, an insulating film 152a and a conductive film 160a are formed over the gate insulating layer 151 and the insulating layer 175 after the groove 174 is formed (see FIG. 23).

The insulating film 152a can be formed using a material and a method similar to those of the second insulating film 150a of the transistor 10. For example, 5 nm of silicon oxide can be formed as the insulating film 152a by a plasma CVD method.

Next, planarization treatment is performed on the insulating film 152a and the conductive film 160a, whereby the gate electrode layer 160 and the insulating layer 152b are formed (see FIG. 24).

Next, the insulating layer 175 is etched until the gate insulating layer 151 is exposed. Further, the gate insulating layer 152 can be formed by etching the insulating layer 152 b except for a portion overlapping with the gate electrode layer 160.

Next, ion 167 is added (see FIG. 25). Ion addition treatment is performed on the oxide semiconductor layer 122 through the gate insulating layer 151 and the metal oxide layer 123, so that the low-resistance region 125 is formed (see FIG. 26).

By using the above method, film loss of the metal oxide layer 123 or the like when a fine transistor is manufactured can be reduced, for example. In addition, damage caused during processing can be reduced. Therefore, the shape of a fine transistor can be stabilized. In addition, the electrical characteristics and reliability of the transistor can be improved.

<Modification Example 4 of Transistor 10: Transistor 14>
A transistor 14 having a shape different from that of the transistor 10 illustrated in FIG. 1 will be described with reference to FIGS.

27A, 27B, and 27C are a top view and a cross-sectional view of the transistor 14, respectively. 27A is a top view of the transistor 14, FIG. 27B is a cross-sectional view taken along the dashed-dotted line E1-E2 in FIG. 27A, and FIG. 27C is a cross-sectional view taken along the line E3-E4. .

The shape of the metal oxide layer 123 in the transistor 14 is the same as that of the transistor 12. The transistor 14 has a region where the gate insulating layer 150 is in contact with the side surface of the gate electrode layer 160 and a region in contact with the side surface of the gate insulating layer 150. It differs from the transistor 10 in that an insulating layer 176 is provided.

Note that an angle (gradient) formed by the bottom surface of the substrate and the tangent to the side surface of the gate electrode layer is 30 to 90 degrees, preferably 60 to 85 degrees.

With the above structure, the size of the low resistance region 125 can be controlled. Thereby, the on-current can be improved. In addition, the characteristics of the transistor can be stabilized.

<< Insulating layer 176 >>
The insulating layer 176 can be formed using a material similar to that of the insulating layer 175.

<Method for Manufacturing Transistor 14>
A method for manufacturing the transistor 14 is described with reference to FIGS. Note that the description is referred to for portions similar to those of another method for manufacturing a transistor.

A second insulating film 150a and a conductive film 160a are formed in the groove 174 provided over the metal oxide film 123a (see FIG. 28).

28, the manufacturing process is the same as that in FIG. 7, but the angle (gradient) formed by the tangent line between the bottom surface of the substrate and the side surface of the insulating layer 175 in providing the groove 174 is preferably 30 degrees or more and less than 90 degrees. Is preferably 60 degrees or more and 85 degrees or less.

The above gradient can be similarly obtained in the conductive film 160a facing the insulating layer 175.

Next, planarization treatment is performed on the second insulating film 150a and the conductive film 160a, so that the gate electrode layer 160 and the gate insulating layer 150 are formed (see FIG. 29).

Next, using the gate electrode layer 160 as a mask, the insulating layer 175 and the gate insulating layer 150 are etched by dry etching until the metal oxide film 123a is exposed, whereby the metal oxide layer 123 and the insulating layer 176 are formed. (See FIG. 30). The insulating layer 176 can function as a sidewall. By using the above process, the side wall can be formed in a self-aligned manner, so that the process can be simplified.

Next, by adding ions 167 (see FIG. 31), a low resistance region is formed (see FIG. 32).

Note that the insulating layer 176 can control the size of the low-resistance region even when, for example, ions are diffused in the lateral direction when heat treatment is performed and a region where ions are not added includes the ions. Is possible. Accordingly, the transistor can be stably operated even when the channel length is 100 nm or less, 60 nm or less, 30 nm or less, or 20 nm or less.

Note that the transistor 14 may be provided with an insulating layer 170 (see FIG. 33). Alternatively, the metal oxide layer 123 may be processed and provided (see FIG. 34). Alternatively, the second insulating film 150a to be the gate insulating layer 150 may be provided before forming the groove (see FIG. 35).

In the case where the angle (gradient) formed by the tangent line between the bottom surface of the substrate and the side surface of the gate electrode layer 160 is large, a region without the insulating layer 176 may be included (see FIG. 36).

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 2)
<Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, the CAAC-OS will be described.

A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS including an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed at around 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 37E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 37E, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 37E is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 37E is considered to be due to the (110) plane and the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

FIG. 38A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 38A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the CAAC-OS formation surface or top surface and is parallel to the CAAC-OS formation surface or top surface.

FIGS. 38B and 38C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. FIGS. 38D and 38E are images obtained by performing image processing on FIGS. 38B and 38C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is acquired by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 38D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 38E, the area between the lattice arrangements and the area with another lattice arrangement is indicated by a dotted line, and the direction of the lattice arrangement is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting the surrounding lattice points around the lattice points near the dotted line. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Thus, the CAAC-OS can also be referred to as an oxide semiconductor having CAA crystal (c-axis-aligned ab-plane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, less than 8 × ^{10 11} atoms / cm ^3, preferably 1 × ¹⁰ 11 / cm less than ^3, more preferably less than 1 × ^{10 10} atoms / cm ^3, 1 × ^{10 -9} / cm ³ or An oxide semiconductor having the above carrier density can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel with the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 39B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 39B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

FIG. 39D illustrates a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 40 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 40A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 40B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . 40A and 40B, it can be seen that the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 41 is an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 41, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons related to the acquisition of the TEM image and the like. From FIG. 41, the crystal part (also referred to as the initial nucleus), which was about 1.2 nm in the initial observation by TEM, has a cumulative electron (e ⁻ ) irradiation dose of 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 41 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

<Configuration of CAC>
Hereinafter, a configuration of a CAC (Cloud Aligned Complementary) -OS that can be used in one embodiment of the present invention will be described.

The CAC is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

For example, CAC-IGZO in an In—Ga—Zn oxide (hereinafter also referred to as IGZO) is indium oxide (hereinafter referred to as InO _X1 (X1 is a real number greater than 0)) or indium zinc oxide. objects _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real) than 0.), gallium oxide _{(hereinafter, GaO} X3 (X3 is a large real number) than 0. ), Or gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0)), etc. InO _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter also referred to as cloud shape).

That, CAC-IGZO has a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC relates to a material structure. CAC is a material structure containing In, Ga, Zn, and O, and is a region that is observed in a part of nanoparticles mainly composed of Ga, and a part of nanoparticles composed mainly of In. The observed region is a configuration in which the regions are randomly dispersed in a mosaic pattern. Therefore, in CAC, the crystal structure is a secondary element.

Note that CAC does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

<Analysis of CAC-IGZO>
Subsequently, the results of measurement of an oxide semiconductor film formed on a substrate using various measurement methods will be described.

<< Sample structure and production method >>
In the following, nine samples according to one embodiment of the present invention are described. Each sample is manufactured under different conditions for the substrate temperature and the oxygen gas flow rate when the oxide semiconductor film is formed. Note that the sample has a structure including a substrate and an oxide semiconductor over the substrate.

A method for manufacturing each sample will be described.

First, a glass substrate is used as the substrate. Subsequently, an In—Ga—Zn oxide with a thickness of 100 nm is formed as an oxide semiconductor over the glass substrate with a sputtering apparatus. The deposition conditions are such that the pressure in the chamber is 0.6 Pa and an oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) is used as the target. In addition, 2500 W AC power is supplied to the oxide target installed in the sputtering apparatus.

Note that as a condition for forming an oxide film, the substrate temperature was set to a temperature at which heating was not performed intentionally (hereinafter also referred to as RT), 130 ° C., or 170 ° C. In addition, nine samples are manufactured by setting the flow rate ratio of oxygen gas to the mixed gas of Ar and oxygen (hereinafter also referred to as oxygen gas flow rate ratio) to 10%, 30%, or 100%.

≪Analysis by X-ray diffraction≫
In this item, the results of X-ray diffraction (XRD) measurement on nine samples will be described. Note that Bruker D8 ADVANCE was used as the XRD apparatus. The condition is that the scanning range is 15 deg. In θ / 2θ scanning by the out-of-plane method. To 50 deg. , The step width is 0.02 deg. The scanning speed is 3.0 deg. / Min.

FIG. 68 shows the result of measuring the XRD spectrum using the out-of-plane method. In FIG. 68, the upper part shows the measurement result for the sample whose substrate temperature condition during film formation is 170 ° C., the middle part shows the measurement result for the sample whose substrate temperature condition during film formation is 130 ° C., and the lower part shows the measurement result during film formation. The substrate temperature condition of R.R. T.A. The measurement result in the sample is shown. The left column shows the measurement results for the sample with an oxygen gas flow ratio of 10%, the center column shows the measurement results for a sample with an oxygen gas flow ratio of 30%, and the right column shows the oxygen gas flow rate. The measurement result in the sample whose ratio condition is 100% is shown.

In the XRD spectrum shown in FIG. 68, the peak intensity in the vicinity of 2θ = 31 ° increases by increasing the substrate temperature during film formation or increasing the ratio of the oxygen gas flow rate ratio during film formation. Note that the peak near 2θ = 31 ° is a crystalline IGZO compound (also referred to as CAAC (c-axis aligned crystalline) -IGZO) oriented in the c-axis with respect to a surface to be formed or an upper surface substantially perpendicular to the surface. Is known to originate from

In the XRD spectrum shown in FIG. 68, a clear peak did not appear as the substrate temperature during film formation was lower or the oxygen gas flow rate ratio was smaller. Therefore, it can be seen that the sample having a low substrate temperature during film formation or a small oxygen gas flow ratio does not show orientation in the ab plane direction and c-axis direction of the measurement region.

≪Analysis with electron microscope≫
In this item, the substrate temperature R.D. T.A. Samples prepared at a gas flow rate ratio of 10% and HAADF (High-Angle Angular Dark Field) -STEM (Scanning Transmission Electron Microscope) will be described and explained below (hereinafter obtained by HAADF-STEM). The image is also called a TEM image.)

The results of image analysis of a planar image (hereinafter also referred to as a planar TEM image) acquired by HAADF-STEM and a sectional image (hereinafter also referred to as a sectional TEM image) will be described. The TEM image was observed using a spherical aberration correction function. The HAADF-STEM image was taken by irradiating an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 69A shows the substrate temperature R.P. T.A. , And a plane TEM image of a sample fabricated at an oxygen gas flow rate ratio of 10%. FIG. 69B shows the substrate temperature R.D. T.A. And a cross-sectional TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%.

≪Analysis of electron diffraction pattern≫
In this item, the substrate temperature R.D. T.A. The result of acquiring an electron beam diffraction pattern by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam) to a sample manufactured at an oxygen gas flow rate ratio of 10% will be described.

As shown in FIG. 69A, the substrate temperature R.D. T.A. , And an electron beam diffraction pattern indicated by black spots a1, black spots a2, black spots a3, black spots a4, and black spots a5 in a planar TEM image of a sample prepared at an oxygen gas flow rate ratio of 10%. The observation of the electron beam diffraction pattern is performed while moving at a constant speed from the 0 second position to the 35 second position while irradiating the electron beam. FIG. 69C shows the result of black point a1, FIG. 69D shows the result of black point a2, FIG. 69E shows the result of black point a3, FIG. 69F shows the result of black point a4, and FIG. It is shown in FIG.

From FIG. 69 (C), FIG. 69 (D), FIG. 69 (E), FIG. 69 (F), and FIG. 69 (G), it is possible to observe a region with high luminance like a circle (in a ring shape). A plurality of spots can be observed in the ring-shaped region.

In addition, as shown in FIG. T.A. In the cross-sectional TEM image of the sample manufactured at an oxygen gas flow rate ratio of 10%, the electron beam diffraction pattern indicated by black spot b1, black spot b2, black spot b3, black spot b4, and black spot b5 is observed. FIG. 69 (H) shows the result of black point b1, FIG. 69 (I) shows the result of black point b2, FIG. 69 (J) shows the result of black point b3, FIG. 69 (K) shows the result of black point b4, and FIG. As shown in FIG.

From FIG. 69 (H), FIG. 69 (I), FIG. 69 (J), FIG. 69 (K), and FIG. 69 (L), a region with high luminance can be observed in a ring shape. A plurality of spots can be observed in the ring-shaped region.

Here, for example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS having an InGaZnO ₄ crystal in parallel to the sample surface, spots resulting from the (009) plane of the InGaZnO ₄ crystal are included. A diffraction pattern is seen. That is, it can be seen that the CAAC-OS has c-axis orientation and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, when an electron beam with a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface, a ring-shaped diffraction pattern is confirmed. That is, in the CAAC-OS, the a-axis and the b-axis do not have orientation.

Further, when electron beam diffraction using an electron beam with a large probe diameter (for example, 50 nm or more) is performed on an oxide semiconductor having microcrystals (hereinafter referred to as nc-OS), a halo pattern is obtained. A simple diffraction pattern is observed. Further, when nanobeam electron diffraction is performed on the nc-OS using an electron beam with a small probe diameter (for example, less than 50 nm), bright spots (spots) are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed so as to draw a circle (in a ring shape). In addition, a plurality of bright spots may be observed in the ring-shaped region.

Substrate temperature R.D. T.A. The electron beam diffraction pattern of a sample manufactured at an oxygen gas flow rate ratio of 10% has a ring-like high luminance region and a plurality of bright spots in the ring region. Therefore, the substrate temperature R.D. T.A. And the sample manufactured at an oxygen gas flow rate ratio of 10% has an electron beam diffraction pattern of nc-OS and has no orientation in the plane direction and the cross-sectional direction.

As described above, an oxide semiconductor with a low substrate temperature or a low oxygen gas flow ratio during deposition has properties that are clearly different from those of an amorphous oxide semiconductor film and a single crystal oxide semiconductor film. Can be estimated.

≪Elemental analysis≫
In this item, by using energy dispersive X-ray spectroscopy (EDX) and obtaining and evaluating EDX mapping, the substrate temperature R.D. T.A. The results of elemental analysis of a sample prepared at an oxygen gas flow rate ratio of 10% will be described. For EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used as an element analyzer. A Si drift detector is used to detect X-rays emitted from the sample.

In the EDX measurement, each point in the analysis target region of the sample is irradiated with an electron beam, and the characteristic X-ray energy and the number of occurrences of the sample generated thereby are measured to obtain an EDX spectrum corresponding to each point. In this embodiment, the peak of the EDX spectrum at each point is represented by the electron transition from the In atom to the L shell, the electron transition from the Ga atom to the K shell, the electron transition from the Zn atom to the K shell, and the K shell from the O atom. And the ratio of each atom at each point is calculated. By performing this for the analysis target region of the sample, EDX mapping showing the distribution of the ratio of each atom can be obtained.

FIG. 70 shows the substrate temperature R.D. T.A. And EDX mapping in a cross section of a sample fabricated at an oxygen gas flow rate ratio of 10%. FIG. 70A is an EDX mapping of Ga atoms (the ratio of Ga atoms to all atoms is in the range of 1.18 to 18.64 [atomic%]). FIG. 70B is an EDX mapping of In atoms (the ratio of In atoms to all atoms is in the range of 9.28 to 33.74 [atomic%]). FIG. 70C is an EDX mapping of Zn atoms (the ratio of Zn atoms to all atoms is in the range of 6.69 to 24.99 [atomic%]). 70A, 70B, and 70C show the substrate temperature R.D. during film formation. T.A. In a cross section of a sample manufactured at an oxygen gas flow rate ratio of 10%, a region in the same range is shown. Note that the EDX mapping shows the ratio of elements in light and dark so that the more measurement elements in the range, the brighter the brightness, and the darker the measurement elements. The magnification of EDX mapping shown in FIG. 70 is 7.2 million times.

In the EDX mapping shown in FIGS. 70A, 70B, and 70C, a relative light / dark distribution is seen in the image, and the substrate temperature R.D. T.A. In the sample prepared at an oxygen gas flow rate ratio of 10%, it can be confirmed that each atom exists in a distributed manner. Here, attention is focused on a range surrounded by a solid line and a range surrounded by a broken line shown in FIGS. 70 (A), 70 (B), and 70 (C).

In FIG. 70A, a range surrounded by a solid line includes many relatively dark regions, and a range surrounded by a broken line includes many relatively bright regions. In FIG. 70B, the range surrounded by the solid line includes many relatively bright areas, and the range surrounded by the broken line includes many relatively dark areas.

That is, the range surrounded by the solid line is a region having a relatively large number of In atoms, and the range surrounded by a broken line is a region having a relatively small number of In atoms. Here, in FIG. 70C, in the range surrounded by the solid line, the right side is a relatively bright region and the left side is a relatively dark region. Therefore, the range surrounded by the solid line is a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 .

A range surrounded by a solid line is a region with relatively few Ga atoms, and a range surrounded by a broken line is a region with relatively many Ga atoms. In FIG. 70C, in the range surrounded by the broken line, the upper left region is a relatively bright region, and the lower right region is a relatively dark region. Therefore, the range surrounded by the broken line is a region whose main component is GaO _X3 , Ga _X4 Zn _Y4 O _Z4 , or the like.

Further, from FIGS. 70A, 70B, and 70C, the distribution of In atoms is relatively more uniform than Ga atoms, and InO _X1 is the main component. The regions appear to be connected to each other through a region mainly composed of In _X2 Zn _Y2 O _Z2 . As described above, the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 is formed so as to spread in a cloud shape.

As described above, an In—Ga—Zn oxide having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are unevenly distributed. Can be referred to as CAC-IGZO.

The crystal structure in CAC has an nc structure. The nc structure possessed by CAC has several bright spots (spots) in addition to bright spots (spots) caused by IGZO including single crystal, polycrystal, or CAAC structure in an electron diffraction image. Alternatively, in addition to several bright spots (spots), a crystal structure is defined as a region having a high brightness in a ring shape.

Further, FIG. 70 (A), FIG. 70 (B), and FIG. 70 from (C), area _{GaO X3} is the main component, and _In X2 _Zn Y2 _{O Z2} or _{InO X1} is the size of the area which is the main component, Are observed from 0.5 nm to 10 nm, or from 1 nm to 3 nm. Preferably, in EDX mapping, the diameter of a region in which each metal element is a main component is 1 nm or more and 2 nm or less.

As described above, CAC-IGZO has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has a property different from that of an IGZO compound. That, CAC-IGZO is a region such as _{GaO X3} is a region which is a main _component, In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is phase-separated from each other region and, in the main component, is mainly composed of the elements Has a mosaic structure. Therefore, when CAC-IGZO is used for a semiconductor element, a high on-current can be obtained because the properties caused by GaO _{X3 and the} like and the properties caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily. (I _on ) and high field effect mobility (μ) can be realized.

A semiconductor element using CAC-IGZO has high reliability. Therefore, CAC-IGZO is most suitable for various semiconductor devices including a display.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 3)
In this embodiment, an example of a circuit using the transistor of one embodiment of the present invention will be described with reference to drawings.

<Cross-section structure>
FIG. 42A is a cross-sectional view of the semiconductor device of one embodiment of the present invention. In FIG. 42A, the X1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device illustrated in FIG. 42A includes a transistor 2200 using a first semiconductor material in a lower portion and a transistor 2100 using a second semiconductor material in an upper portion. FIG. 42A illustrates an example in which the transistor illustrated in the above embodiment is applied as the transistor 2100 including the second semiconductor material. Note that the left side of the alternate long and short dash line is a cross section in the channel length direction of the transistor, and the right side is a cross section in the channel width direction.

The first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductor, etc. And the second semiconductor material can be an oxide semiconductor. A transistor using single crystal silicon or the like as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can have a small S value (subthreshold value) and can be a minute transistor by using the transistor illustrated in the above embodiment. is there. Further, since the switch speed is high, high speed operation is possible, and since the off current is low, the leakage current is small.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used depending on a circuit. In addition to the use of the transistor of one embodiment of the present invention using an oxide semiconductor, the specific structure of the semiconductor device, such as a material and a structure used, is not necessarily limited to that described here.

In the structure illustrated in FIG. 42A, the transistor 2100 is provided over the transistor 2200 with the insulator 2201 and the insulator 2207 provided therebetween. A plurality of wirings 2202 are provided between the transistors 2200 and 2100. In addition, wirings and electrodes provided in the upper layer and the lower layer are electrically connected by a plurality of plugs 2203 embedded in various insulators. An insulator 2204 that covers the transistor 2100 and a wiring 2205 over the insulator 2204 are provided.

Thus, by stacking two types of transistors, the area occupied by the circuit is reduced, and a plurality of circuits can be arranged at a higher density.

Here, in the case where a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulator provided in the vicinity of the semiconductor film of the transistor 2200 terminates dangling bonds of silicon, and the reliability of the transistor 2200 is increased. There is an effect to improve. On the other hand, in the case where an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulator provided in the vicinity of the semiconductor film of the transistor 2100 is one of the factors that generate carriers in the oxide semiconductor. In some cases, the reliability of the transistor 2100 may be reduced. Therefore, in the case where the transistor 2100 including an oxide semiconductor is stacked over the transistor 2200 including a silicon-based semiconductor material, it is particularly preferable to provide the insulator 2207 having a function of preventing hydrogen diffusion therebetween. It is effective. In addition to improving the reliability of the transistor 2200 by confining hydrogen in the lower layer with the insulator 2207, it is possible to simultaneously improve the reliability of the transistor 2100 by suppressing diffusion of hydrogen from the lower layer to the upper layer. it can.

As the insulator 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

In addition, a block film having a function of preventing hydrogen diffusion is preferably formed over the transistor 2100 so as to cover the transistor 2100 including the oxide semiconductor film. As the block film, a material similar to that of the insulator 2207 can be used, and aluminum oxide is particularly preferably used. The aluminum oxide film has a high blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the block film covering the transistor 2100, desorption of oxygen from the oxide semiconductor film included in the transistor 2100 is prevented, and mixing of water and hydrogen into the oxide semiconductor film is prevented. Can be prevented. Note that the block film may be used by stacking the insulators 2204 or may be provided below the insulators 2204.

Note that the transistor 2200 can be a transistor of various types as well as a planar transistor. For example, a transistor of FIN (fin) type, TRI-GATE (trigate) type, or the like can be used. An example of a cross-sectional view in that case is shown in FIG. An insulator 2212 is provided over the semiconductor substrate 2211. The semiconductor substrate 2211 has a convex portion (also referred to as a fin) with a thin tip. Note that an insulator may be provided on the convex portion. In addition, the convex part does not need to have a thin tip, for example, it may be a substantially rectangular parallelepiped convex part or a thick convex part. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. A source region and a drain region 2215 are formed in the semiconductor substrate 2211. Note that although the example in which the semiconductor substrate 2211 includes a convex portion is described here, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

<Circuit configuration example>
In the above structure, a variety of circuits can be formed by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. An example of a circuit configuration that can be realized by using the semiconductor device of one embodiment of the present invention will be described below.

<CMOS inverter circuit>
The circuit diagram shown in FIG. 42B shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

<CMOS analog switch>
A circuit diagram illustrated in FIG. 42C illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.

<Example of storage device>
FIG. 43 illustrates an example of a semiconductor device (memory device) that can store stored contents even in a state where power is not supplied and has no limit on the number of writing times, using the transistor which is one embodiment of the present invention.

A semiconductor device illustrated in FIG. 43A includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400. Note that as the transistor 3300, the transistor described in the above embodiment can be used.

FIG. 43B is a cross-sectional view of the semiconductor device illustrated in FIG. In the semiconductor device in the cross-sectional view, the transistor 3300 is provided with a back gate; however, the back gate may not be provided.

The transistor 3300 is a transistor in which a channel is formed in a semiconductor including an oxide semiconductor. Since the transistor 3300 has low off-state current, stored data can be held for a long time by using the transistor 3300. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

In FIG. 43A, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is electrically connected to one of a source electrode and a drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to a gate electrode of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the other of the source electrode and the drain electrode of the transistor 3300 and the first terminal of the capacitor 3400, and the fifth wiring 3005 is a second terminal of the capacitor 3400. And are electrically connected.

In the semiconductor device illustrated in FIG. 43A, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 3200 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, predetermined charge is supplied to the gate electrode of the transistor 3200 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, whereby the charge given to the gate electrode of the transistor 3200 is held (held).

Since the off-state current of the transistor 3300 is extremely small, the charge of the gate electrode of the transistor 3200 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the amount of charge held in the gate electrode of the transistor 3200 is increased. The second wiring 3002 has different potentials. In general, when the transistor 3200 is an n-channel transistor, the apparent threshold V _{th_H in the} case where a high-level charge is applied to the gate electrode of the transistor 3200 is a low-level charge applied to the gate electrode of the transistor 3200. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for turning on the transistor 3200. Therefore, the charge applied to the gate electrode of the transistor 3200 can be determined by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 3200 is turned on when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). In the case where a low-level charge is _supplied , the transistor 3200 remains in the “off state” even when the potential of the fifth wiring 3005 is V ₀ (<V _{th_L} ). Therefore, the stored information can be read by determining the potential of the second wiring 3002.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. For example, in a memory cell from which information is not read, a potential that turns off the transistor 3200 regardless of the state of the gate, that is, a potential smaller than V _{th_H} , is _applied to the fifth wiring 3005. It is sufficient that only the information is read. _{Alternatively} , in a memory cell from which information is not read, a potential that turns on the transistor 3200 regardless of the state of the gate, that is, a potential that is higher than V _{th_L} is _applied to the fifth wiring 3005. A configuration in which only cell information can be read out is sufficient.

The semiconductor device illustrated in FIG. 43C is different from FIG. 43A in that the transistor 3200 is not provided. In this case, information can be written and held by the same operation as described above.

Next, reading of information will be described. When the transistor 3300 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are brought into conduction, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on the potential of the first terminal of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed Is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. The potential (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + C × V0) / (CB + C)). I understand that

Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor material is applied is used for a driver circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied is stacked over the driver circuit as the transistor 3300. And it is sufficient.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating layer does not occur at all. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

By using the semiconductor device described in this embodiment, a memory device with low power consumption and high capacity (eg, 1 terabit or more) can be manufactured.

Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when a plurality of cases can be considered as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There are cases.

Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

Note that in this specification and the like, a part of the drawings or texts described in one embodiment can be extracted to constitute one embodiment of the present invention. Therefore, when a figure or a sentence describing a certain part is described, the content of the extracted part of the figure or the sentence is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It shall be possible. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, resistance elements, etc.), conductive layers, insulating layers, semiconductors, organic materials, inorganic materials, parts, devices, operating methods, manufacturing methods, etc. In the drawings or texts in which one or more are described, a part thereof can be taken out to constitute one embodiment of the present invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitors) Etc.) can be extracted to constitute one embodiment of the invention. As another example, M (M is an integer and M <N) layers are extracted from a cross-sectional view including N layers (N is an integer) to form one embodiment of the invention. It is possible to do. As another example, M elements (M is an integer and M <N) are extracted from a flowchart including N elements (N is an integer) to form one aspect of the invention. It is possible to do.

<Imaging device>
The imaging device according to one embodiment of the present invention is described below.

FIG. 44A is a plan view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211, respectively. Note that in this specification and the like, the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases. For example, the peripheral circuit 260 can be said to be part of the peripheral circuit.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. Further, the peripheral circuit may be formed on a substrate over which the pixel portion 210 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted from the peripheral circuit.

In addition, as illustrated in FIG. 44B, the pixel 211 may be tilted in the pixel portion 210 included in the imaging device 200. By arranging the pixels 211 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 200 can be further improved.

<Pixel Configuration Example 1>
A single pixel 211 included in the imaging apparatus 200 is configured by a plurality of sub-pixels 212, and a color image display is realized by combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength band. Information can be acquired.

FIG. 45A is a plan view illustrating an example of a pixel 211 for acquiring a color image. 45A includes a sub-pixel 212 (hereinafter also referred to as “sub-pixel 212R”) provided with a color filter that transmits light in the red (R) wavelength band, and a green (G) wavelength. Sub-pixel 212 (hereinafter also referred to as “sub-pixel 212G”) provided with a color filter that transmits light in the band and sub-pixel 212 (hereinafter referred to as “color filter” that transmits light in the blue (B) wavelength band. , Also referred to as “sub-pixel 212B”. The sub-pixel 212 can function as a photosensor.

The subpixel 212 (subpixel 212R, subpixel 212G, and subpixel 212B) is electrically connected to the wiring 231, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. Further, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 253. In this specification and the like, for example, the wiring 248 and the wiring 249 connected to the pixel 211 in the n-th row (n is an integer of 1 to p) are described as a wiring 248 [n] and a wiring 249 [n], respectively. To do. For example, the wiring 253 connected to the pixel 211 in the m-th column (m is an integer of 1 to q) is referred to as a wiring 253 [m]. 45A, the wiring 253 connected to the subpixel 212R included in the pixel 211 in the m-th column is the wiring 253 [m] R, the wiring 253 connected to the subpixel 212G is the wiring 253 [m] G, and A wiring 253 connected to the subpixel 212B is described as a wiring 253 [m] B. The subpixel 212 is electrically connected to a peripheral circuit through the wiring.

In addition, the imaging apparatus 200 has a configuration in which subpixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected via a switch. In FIG. 45B, the sub-pixel 212 included in the pixel 211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 211. A connection example of the sub-pixel 212 included in the pixel 211 arranged in n + 1 rows and m columns is shown. In FIG. 45B, a sub-pixel 212R arranged in n rows and m columns and a sub-pixel 212R arranged in n + 1 rows and m columns are connected through a switch 201. Further, the sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via a switch 202. Further, the sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are connected via a switch 203.

Note that the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively. A color filter may be used. A full color image can be acquired by providing the sub-pixel 212 that detects light of three different wavelength bands in one pixel 211.

Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 211 having a sub-pixel 212 may be used. Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, a color filter that transmits blue (B) light is provided. A pixel 211 having a sub-pixel 212 may be used. By providing the sub-pixel 212 that detects light of four different wavelength bands in one pixel 211, the color reproducibility of the acquired image can be further enhanced.

Also, for example, in FIG. 45A, the sub-pixel 212 that detects light in the red wavelength band, the sub-pixel 212 that detects light in the green wavelength band, and the sub-pixel 212 that detects light in the blue wavelength band. The pixel number ratio (or the light receiving area ratio) may not be 1: 1: 1. For example, a Bayer array in which the pixel number ratio (light receiving area ratio) is red: green: blue = 1: 2: 1 may be used. Alternatively, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

Note that the number of subpixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example, by providing two or more subpixels 212 that detect light in the same wavelength band, redundancy can be increased and the reliability of the imaging apparatus 200 can be increased.

In addition, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, the imaging device 200 that detects infrared light can be realized.

Further, by using an ND (ND: Neutral Density) filter (a neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.

In addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described with reference to the cross-sectional view of FIG. By providing the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 46A, the light 256 is transmitted to the photoelectric conversion element 220 through the lens 255, the filter 254 (filter 254R, the filter 254G, and the filter 254B) formed in the pixel 211, the pixel circuit 230, and the like. It can be set as the structure made to enter.

However, as illustrated in the region surrounded by the alternate long and short dash line, part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side as illustrated in FIG. 46B so that the photoelectric conversion element 220 efficiently receives the light 256 is preferable. By making the light 256 incident on the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high detection sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIG. 46, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

Alternatively, the photoelectric conversion element 220 may be formed using a substance having a function of generating charges by absorbing radiation. Examples of the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.

Here, one pixel 211 included in the imaging apparatus 200 may include a sub-pixel 212 including a first filter in addition to the sub-pixel 212 illustrated in FIG.

<Pixel Configuration Example 2>
Hereinafter, an example in which a pixel is formed using a transistor including silicon and a transistor including an oxide semiconductor will be described.

47A and 47B are cross-sectional views of elements included in the imaging device.

An imaging device illustrated in FIG. 47A is provided over a transistor 351 using silicon provided over a silicon substrate 300, a transistor 353 using an oxide semiconductor stacked over the transistor 351, and the silicon substrate 300. And a photodiode 360 having an anode 361 and a cathode 362. Each transistor and photodiode 360 has electrical connection with various plugs 370, wirings 371, wirings 372, and wirings 373. Further, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363.

The imaging device is provided in contact with the layer 310 including the transistor 351 and the photodiode 360 provided over the silicon substrate 300, the layer 320 including the wiring 371, and the layer 320 including the wiring 371. And a layer 340 which is provided in contact with the layer 330 and includes a wiring 372 and a wiring 373.

Note that in the example of the cross-sectional view in FIG. 47A, the silicon substrate 300 has a light-receiving surface of the photodiode 360 on a surface opposite to a surface where the transistor 351 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 may be the same as the surface on which the transistor 351 is formed.

Note that in the case where a pixel is formed using a transistor including an oxide semiconductor, the layer 310 may be a layer including a transistor including an oxide semiconductor. Alternatively, the layer 310 may be omitted, and the pixel may be formed using only a transistor including an oxide semiconductor.

In the cross-sectional view of FIG. 47A, the photodiode 360 provided in the layer 310 and the transistor provided in the layer 330 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.

In FIG. 47B, the imaging device can have a structure in which a photodiode 365 is provided over a transistor on the layer 340 side. 47B, for example, the layer 310 includes a transistor 351 using silicon, the layer 320 includes a wiring 371, the layer 330 includes a transistor 353 using an oxide semiconductor, and an insulating layer 380. The layer 340 includes a photodiode 365, and is electrically connected to the wiring 373 and the wiring 374 through the plug 370.

With the element structure illustrated in FIG. 47B, the aperture ratio can be improved.

As the photodiode 365, a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. The photodiode 365 has a structure in which an n-type semiconductor 368, an i-type semiconductor 367, and a p-type semiconductor 366 are sequentially stacked. Amorphous silicon is preferably used for the i-type semiconductor 367. For the p-type semiconductor 366 and the n-type semiconductor 368, amorphous silicon, microcrystalline silicon, or the like containing a dopant imparting each conductivity type can be used. The photodiode 365 using amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 4)
In this embodiment, an example of a circuit configuration to which the transistor including an oxide semiconductor layer (OS transistor) described in the above embodiment can be applied will be described with reference to FIGS.

FIG. 48A is a circuit diagram of an inverter that can be applied to a memory, an FPGA, a CPU, or the like. The inverter 2800 outputs a signal obtained by inverting the logic of the signal supplied to the input terminal IN to the output terminal OUT. The inverter 2800 includes a plurality of OS transistors. The signal _SBG is a signal that can switch the electrical characteristics of the OS transistor.

FIG. 48B is a circuit diagram illustrating an example of the inverter 2800. The inverter 2800 includes an OS transistor 2810 and an OS transistor 2820. The inverter 2800 can be manufactured in an n-channel type and can have a so-called unipolar circuit configuration. Since an inverter can be manufactured with a unipolar circuit configuration, it can be manufactured at a lower cost than a case where an inverter (CMOS inverter) is manufactured using a CMOS (Complementary Metal Oxide Semiconductor) circuit.

Note that the inverter 2800 including an OS transistor can be provided over a CMOS circuit including Si transistors. Since the inverter 2800 can be arranged so as to overlap with the CMOS circuit configuration, an increase in circuit area corresponding to the addition of the inverter 2800 can be suppressed.

The OS transistor 2810 and the OS transistor 2820 each include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of a source and a drain. It has 2 terminals.

A first gate of the OS transistor 2810 is connected to the second terminal. A second gate of the OS transistor 2810 is connected to a wiring that transmits the signal _SBG . A first terminal of the OS transistor 2810 is connected to a wiring that supplies the voltage VDD. A second terminal of the OS transistor 2810 is connected to the output terminal OUT.

A first gate of the OS transistor 2820 is connected to the input terminal IN. A second gate of the OS transistor 2820 is connected to the input terminal IN. A first terminal of the OS transistor 2820 is connected to the output terminal OUT. A second terminal of the OS transistor 2820 is connected to a wiring that supplies the voltage VSS.

FIG. 48C is a timing chart for explaining the operation of the inverter 2800. In the timing chart of FIG. 48 (C), the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, and indicates a change in the signal waveform, and the threshold voltage of the OS transistor 2810 of the signal _{S BG.}

The signal _SBG is supplied to the second gate of the OS transistor 2810, whereby the threshold voltage of the OS transistor 2810 can be controlled.

Signal _{S BG} has a voltage _{V BG_B} for voltage _{V BG_A} for causing negative shift of the threshold voltage, the threshold voltage is positive shift. By applying the voltage V _{BG_A} to the second gate, the OS transistor 2810 can be negatively shifted to the threshold voltage V _{TH_A} . _Further, by applying the voltage V _{BG_B} to the second gate, the OS transistor 2810 can be positively shifted to the threshold voltage V _{TH_B} .

In order to visualize the above description, FIG. 49A shows a graph of a Vg-Id curve which is one of the electrical characteristics of the transistor.

The above-described electrical characteristics of the OS transistor 2810 can be shifted to a curve represented by a broken line 2840 in FIG. _49A by increasing the voltage of the second gate like the voltage V _{BG_A} . Further, the above-described electrical characteristics of the OS transistor 2810 can be shifted to a curve represented by a solid line 2841 in FIG. _49A by reducing the voltage of the second gate as the voltage V _{BG_B} . As shown in FIG. 49 (A), OS transistor 2810, by switching the signal _{S BG} and so the voltage _{V BG_A} or voltage _{V BG_B,} can be shifted in the positive or negative shift of the threshold voltage.

By positively shifting the threshold voltage to the threshold voltage _{VTH_B} , the OS transistor 2810 can be in a state in which current does not easily flow. FIG. 49B visualizes this state. As shown in FIG. 49 (B), it can be extremely small current _{I B} flowing through the OS transistor 2810. Therefore, when the signal supplied to the input terminal IN is at a high level and the OS transistor 2820 is in an on state (ON), the voltage of the output terminal OUT can be sharply decreased.

As shown in FIG. 49B, since the current flowing through the OS transistor 2810 can hardly flow, the signal waveform 2831 at the output terminal in the timing chart shown in FIG. be able to. Since the through current flowing between the wiring for applying the voltage VDD and the wiring for supplying the voltage VSS can be reduced, an operation with low power consumption can be performed.

Further, the OS transistor 2810 can be in a state in which a current easily flows by negatively shifting the threshold voltage to the threshold voltage _{VTH_A} . FIG. 49C visualizes this state. As shown in FIG. 49 (C), it can be larger than at least the current I _B of the current I _A flowing at this time. Therefore, when the signal supplied to the input terminal IN is low and the OS transistor 2820 is off (OFF), the voltage of the output terminal OUT can be increased rapidly.

As illustrated in FIG. 49C, the current flowing through the OS transistor 2810 can easily flow, and thus the signal waveform 2832 at the output terminal in the timing chart illustrated in FIG. be able to.

The control of the threshold voltage of the OS transistor 2810 by signal _{S BG} previously the state of the OS transistor 2820 switches, i.e. it is preferably performed before time T1 and T2. For example, as illustrated in FIG. _48C , the threshold voltage of the OS transistor 2810 is switched from the threshold voltage V _{TH_A} to the threshold voltage V _{TH_B} before the time T1 when the signal applied to the input terminal IN switches to the high level. Is preferred. As shown in FIG. _48C , the threshold voltage of the OS transistor 2810 is switched from the threshold voltage V _{TH_B} to the threshold voltage V _{TH_A} before the time T2 when the signal applied to the input terminal IN switches to the low level. Is preferred.

Note that although the structure in which the signal _SBG is switched in accordance with the signal applied to the input terminal IN is illustrated in the timing chart in FIG. _48C , another structure may be employed. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 2810 in a floating state. An example of a circuit configuration that can realize this configuration is illustrated in FIG.

50A includes an OS transistor 2850 in addition to the circuit configuration illustrated in FIG. The first terminal of the OS transistor 2850 is connected to the second gate of the OS transistor 2810. The second terminal of the OS transistor 2850 is connected to a wiring for applying the voltage V _{BG_B} (or voltage V _{BG_A} ). The first gate of the OS transistor 2850 is connected to a wiring for providing signal _{S F.} A second gate of the OS transistor 2850 is connected to a wiring that _{supplies the} voltage V _{BG_B} (or voltage V _{BG_A} ).

The operation of the circuit configuration in FIG. 50A will be described with reference to a timing chart in FIG.

The voltage for controlling the threshold voltage of the OS transistor 2810 is applied to the second gate of the OS transistor 2810 before time T3 when the signal applied to the input terminal IN switches to a high level. The OS transistor 2850 is turned on the signal _{S F} to the high level, providing a voltage _{V BG_B} for controlling a threshold voltage in the node _{N BG.}

After the node N _BG becomes the voltage V _{BG_B} , the OS transistor 2850 is turned off. Since the off-state current of the OS transistor 2850 is extremely small, the voltage V _{BG_B} once held at the node N _BG can be held by continuing the off state. Therefore, the number of operations for applying the voltage V _{BG_B} to the second gate of the OS transistor 2850 is reduced, so that power consumption required for rewriting the voltage V _{BG_B} can be reduced.

Note that in the circuit structures in FIGS. 48B and 50A, the voltage supplied to the second gate of the OS transistor 2810 is given by control from the outside, but another structure may be used. For example, a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 2810. FIG. 51A illustrates an example of a circuit configuration that can realize this configuration.

In FIG. 51A, a CMOS inverter 2860 is provided between the input terminal IN and the second gate of the OS transistor 2810 in the circuit configuration shown in FIG. The input terminal of the CMOS inverter 2860 is connected to the input terminal IN. The output terminal of the CMOS inverter 2860 is connected to the second gate of the OS transistor 2810.

The operation of the circuit configuration in FIG. 51A will be described with reference to a timing chart in FIG. The timing chart in FIG. 51B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 2860, and the threshold voltage of the OS transistor 2810.

An output waveform IN_B that is a signal obtained by inverting the logic of a signal supplied to the input terminal IN can be a signal for controlling the threshold voltage of the OS transistor 2810. Therefore, as described in FIGS. 49A to 49C, the threshold voltage of the OS transistor 2810 can be controlled. For example, at time T4 in FIG. 51B, a signal supplied to the input terminal IN is high and the OS transistor 2820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 2810 can be in a state in which current does not easily flow, and the voltage at the output terminal OUT can be sharply decreased.

At time T5 in FIG. 51B, the signal supplied to the input terminal IN is low and the OS transistor 2820 is turned off. At this time, the output waveform IN_B is at a high level. Therefore, the OS transistor 2810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be increased sharply.

As described above, in the configuration of this embodiment, the voltage of the back gate in the inverter having the OS transistor is switched according to the logic of the signal at the input terminal IN. With this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor together with the signal applied to the input terminal IN, the voltage change at the output terminal OUT can be made steep. In addition, the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.

(Embodiment 5)
<RF tag>
In this embodiment, an RF tag including the transistor or the memory device described in the above embodiment will be described with reference to FIGS.

The RF tag in this embodiment has a storage circuit inside, stores necessary information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Because of these characteristics, the RF tag can be used in an individual authentication system that identifies an article by reading individual information about the article. Note that extremely high reliability is required for use in these applications.

The configuration of the RF tag will be described with reference to FIG. FIG. 52 is a block diagram illustrating a configuration example of an RF tag.

As shown in FIG. 52, the RF tag 800 includes an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator or a reader / writer). The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. Note that a material that can sufficiently suppress a reverse current, such as an oxide semiconductor, may be used for the transistor including the rectifying action included in the demodulation circuit 807. Thereby, the fall of the rectification action resulting from a reverse current can be suppressed, and it can prevent that the output of a demodulation circuit is saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. Note that there are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other to perform communication by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. Separated. The RF tag 800 described in this embodiment can be used for any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal by the antenna 804, for example, half-wave double voltage rectification, and the signal rectified by a capacitive element provided in the subsequent stage. It is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling not to input more than a certain amount of power to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.

The demodulation circuit 807 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation in accordance with data output from the antenna 804.

A logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a storage area, and the like. The ROM 811 is a circuit for storing a unique number (ID) or the like and outputting it according to processing.

Note that the above-described circuits can be appropriately disposed as necessary.

Here, the semiconductor device described in the above embodiment can be used for the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain information even when the power is turned off, the memory circuit can be preferably used for an RF tag. Further, the memory circuit of one embodiment of the present invention does not cause a difference in maximum communication distance between data reading and writing because power (voltage) necessary for data writing is significantly smaller than that of a conventional nonvolatile memory. It is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power during data writing.

The memory circuit of one embodiment of the present invention can also be applied to the ROM 811 because it can be used as a nonvolatile memory. In that case, it is preferable that the producer separately prepares a command for writing data in the ROM 811 so that the user cannot freely rewrite the command. By shipping the product after the producer writes the unique number before shipping, it is possible to assign a unique number only to the good products to be shipped, rather than assigning a unique number to all the produced RF tags, The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 6)
In this embodiment, a CPU including the storage device described in the above embodiment will be described.

FIG. 53 is a block diagram illustrating a configuration example of a CPU in which the transistor described in the above embodiment is used at least in part.

<Circuit diagram of CPU>
53 includes an ALU 1191 (ALU: arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. A rewritable ROM 1199 and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU in FIG. 53 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, a configuration including a CPU or an arithmetic circuit illustrated in FIG. 53 may be used as one core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

In the CPU illustrated in FIG. 53, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in Embodiment 1 can be used.

In the CPU shown in FIG. 53, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

<Memory circuit>
FIG. 54 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function. Circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.

Here, the memory device described in the above embodiment can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, the gate of the transistor 1209 in the circuit 1202 is continuously input with the ground potential (0 V) or the potential at which the transistor 1209 is turned off. For example, the first gate of the transistor 1209 is grounded through a load such as a resistor.

The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 1214).

One of a source and a drain of the transistor 1209 is electrically connected to the first terminal of the capacitor 1208 and the gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). A second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207 The first terminal is electrically connected. Here, the connection part is referred to as a node M1. The second terminal of the capacitor 1207 can have a structure in which a constant potential is input. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The second terminal of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The second terminal of the capacitor 1208 can be input with a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. A second terminal of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.

Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.

A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

Note that the transistor 1209 in FIG. 54 has a structure including a second gate (second gate electrode: back gate). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. As the certain potential, for example, a ground potential GND or a potential smaller than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the current when the gate voltage VG is 0V can be further reduced. The control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can be used.

A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 54 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .

Note that FIG. 54 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.

In FIG. 54, among the transistors used for the memory element 1200, a transistor other than the transistor 1209 can be a transistor in which a channel is formed in a layer formed of a semiconductor other than an oxide semiconductor or the substrate 1190. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.

For the circuit 1201 in FIG. 54, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device of one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.

In addition, a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.

Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.

In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 can be converted into the state of the transistor 1210 (on state or off state) and read from the circuit 1202. it can. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.

By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.

In this embodiment, the memory element 1200 is described as an example of using the CPU. However, the memory element 1200 is an LSI such as a DSP (Digital Signal Processor), a custom LSI, or a PLD (Programmable Logic Device), or an RF (Radio Frequency) tag. It can also be applied to.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 7)
In this embodiment, an example of a structure of a display device using the transistor of one embodiment of the present invention will be described.

<Display device circuit configuration example>
FIG. 55A is a top view of a display device of one embodiment of the present invention, and FIG. 55B can be used when a liquid crystal element is applied to a pixel of the display device of one embodiment of the present invention. It is a circuit diagram for demonstrating a pixel circuit. FIG. 55C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of the display device of one embodiment of the present invention.

The transistor provided in the pixel portion can be formed according to Embodiment 1. In addition, since the transistor can easily be an n-channel transistor, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in the above embodiment for the pixel portion and the driver circuit.

An example of a top view of the active matrix display device is shown in FIG. A pixel portion 701, a first scan line driver circuit 702, a second scan line driver circuit 703, and a signal line driver circuit 704 are provided over a substrate 700 of the display device. In the pixel portion 701, a plurality of signal lines are extended from the signal line driver circuit 704, and a plurality of scan lines are extended from the first scan line driver circuit 702 and the second scan line driver circuit 703. Has been placed. Note that pixels each having a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).

In FIG. 55A, the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 are formed over the same substrate 700 as the pixel portion 701. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when the drive circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings is increased. In the case where a driver circuit is provided over the same substrate 700, the number of connections between the wirings can be reduced, so that reliability or yield can be improved. Note that any of the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 may be mounted on the substrate 700 or provided outside the substrate 700. .

<Liquid crystal display device>
An example of a circuit configuration of the pixel is shown in FIG. Here, a pixel circuit that can be applied to a pixel of a VA liquid crystal display device is shown as an example.

This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be controlled independently.

The scan line 712 of the transistor 716 and the scan line 713 of the transistor 717 are separated so that different gate signals can be given. On the other hand, the signal line 714 is used in common by the transistor 716 and the transistor 717. As the transistor 716 and the transistor 717, the transistor described in Embodiment 1 can be used as appropriate. Thereby, a highly reliable liquid crystal display device can be provided.

In addition, a first pixel electrode layer is electrically connected to the transistor 716, and a second pixel electrode layer is electrically connected to the transistor 717. The first pixel electrode layer and the second pixel electrode layer are separated from each other. Note that there is no particular limitation on the shape of the first pixel electrode layer and the second pixel electrode layer. For example, the first pixel electrode layer may be V-shaped.

A gate electrode of the transistor 716 is connected to the scan line 712, and a gate electrode of the transistor 717 is connected to the scan line 713. By applying different gate signals to the scan line 712 and the scan line 713, the operation timings of the transistor 716 and the transistor 717 are made different so that the alignment of the liquid crystal can be controlled.

Further, a storage capacitor may be formed using the capacitor wiring 710, the gate insulating layer functioning as a dielectric, and the capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

In the multi-domain design, a first liquid crystal element 718 and a second liquid crystal element 719 are provided in one pixel. The first liquid crystal element 718 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 719 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Consists of.

Note that the pixel circuit illustrated in FIG. 55B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel circuit illustrated in FIG.

FIG. 56A and FIG. 56B are examples of a top view and a cross-sectional view of a liquid crystal display device. Note that FIG. 56A illustrates a typical structure including the display device 20, the display region 21, the peripheral circuit 22, and an FPC (flexible printed circuit board). The display device shown in FIG. 56 uses reflective liquid crystal.

56B is a cross-sectional view taken along broken lines A-A ′, B-B ′, C-C ′, and D-D ′ in FIG. 56A. A-A 'indicates a peripheral circuit portion, B-B' indicates a display area, and C-C 'indicates a connection portion with the FPC.

In addition to the transistor 50 and the transistor 52 (the transistor 10 described in Embodiment 1), the display device 20 including a liquid crystal element includes a conductive layer 165, a conductive layer 197, an insulating layer 420, a liquid crystal layer 490, a liquid crystal element 80, a capacitor Element 60, capacitive element 62, insulating layer 430, spacer 440, colored layer 460, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 473, adhesive layer 474, adhesive layer 475, adhesive layer 476, polarization A plate 103, a polarizing plate 403, a protective substrate 105, a protective substrate 402, and an anisotropic conductive layer 510 are included.

<Organic EL display device>
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display device using an organic EL element is shown.

In the organic EL element, by applying a voltage to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, by recombination of electrons and holes, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 55C illustrates an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. In addition, digital time grayscale driving can be applied to the pixel circuit.

An applicable pixel circuit configuration and pixel operation when digital time gray scale driving is applied will be described.

The pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitor 723. In the switching transistor 721, the gate electrode layer is connected to the scanning line 726, the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the signal line 725, and the second electrode (the source electrode layer and the drain electrode layer) Is connected to the gate electrode layer of the driving transistor 722. In the driving transistor 722, the gate electrode layer is connected to the power supply line 727 via the capacitor 723, the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. It is connected. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed over the same substrate.

The transistors described in Embodiments 1 to 3 can be used as appropriate as the switching transistor 721 and the driving transistor 722. Thereby, an organic EL display device with high reliability can be provided.

The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that the low power supply potential is lower than the high power supply potential supplied to the power supply line 727. For example, GND, 0V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the threshold voltage in the forward direction of the light emitting element 724, and by applying the potential difference to the light emitting element 724, a current is passed through the light emitting element 724 to emit light. Note that the forward voltage of the light-emitting element 724 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage.

Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722.

Next, a signal input to the driving transistor 722 will be described. In the case of the voltage input voltage driving method, a video signal that causes the driving transistor 722 to be sufficiently turned on or off is input to the driving transistor 722. Note that a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722 in order to operate the driving transistor 722 in a linear region. In addition, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

In the case of performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 724 is applied to the gate electrode layer of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in a saturation region, and a current is supplied to the light-emitting element 724. Further, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By making the video signal analog, current corresponding to the video signal can be passed through the light-emitting element 724 to perform analog gradation driving.

Note that the structure of the pixel circuit is not limited to the pixel structure illustrated in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

In the case where the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 55C, the source electrode (first electrode) is provided on the low potential side and the drain electrode (second electrode) is provided on the high potential side. It is configured to be electrically connected. Furthermore, the potential illustrated above can be input, for example, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is applied to the second gate electrode. What is necessary is just to make it a structure.

57A and 57B are examples of a top view and a cross-sectional view of a display device using a light-emitting element. Note that FIG. 57A illustrates a typical structure including the display device 24, the display region 21, the peripheral circuit 22, and an FPC (flexible printed circuit board).

FIG. 57B is a cross-sectional view taken along broken lines A-A ′, B-B ′, and C-C ′ in FIG. A-A 'indicates a peripheral circuit portion, B-B' indicates a display area, and C-C 'indicates a connection portion with the FPC.

In addition to the transistor 50 and the transistor 52 (the transistor 10 described in Embodiment 1), the display device 24 including a light-emitting element includes a conductive layer 197, a conductive layer 410, an optical adjustment layer 530, an EL layer 450, a conductive layer 415, The light-emitting element 70, the capacitor 60, the capacitor 62, the insulating layer 430, the spacer 440, the coloring layer 460, the adhesive layer 470, the partition 445, the light-blocking layer 418, the substrate 400, and the anisotropic conductive layer 510 are provided.

In this specification and the like, for example, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. A display element, a display device, a light emitting element, or a light emitting device includes, for example, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, Blue LEDs, etc.), transistors (transistors that emit light in response to current), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices, grating light valves (GLV), plasma display panels (PDP), MEMS (micro electro Mechanical system), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, electrowetting element, piezoelectric ceramic element Play has at least one such display device using a carbon nanotube. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, or the like is changed by an electric or magnetic action may be included. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 8)
In this embodiment, a display module to which the semiconductor device of one embodiment of the present invention is applied will be described with reference to FIGS.

<Display module>
A display module 6000 shown in FIG. 58 includes a touch panel 6004 connected to the FPC 6003, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, between the upper cover 6001 and the lower cover 6002. A battery 6011 is included. Note that the backlight unit 6007, the battery 6011, the touch panel 6004, and the like may not be provided.

The semiconductor device of one embodiment of the present invention can be used for, for example, the display panel 6006 or an integrated circuit mounted on a printed board.

The shapes and dimensions of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch panel 6004 and the display panel 6006.

As the touch panel 6004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 6006. Further, the counter substrate (sealing substrate) of the display panel 6006 can have a touch panel function. Alternatively, an optical sensor can be provided in each pixel of the display panel 6006 and an optical touch panel function can be added. Alternatively, a touch sensor electrode may be provided in each pixel of the display panel 6006 to add a capacitive touch panel function.

The backlight unit 6007 has a light source 6008. The light source 6008 may be provided at the end of the backlight unit 6007 and a light diffusing plate may be used.

The frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed board 6010 in addition to a protective function of the display panel 6006. The frame 6009 may function as a heat sink.

The printed board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power circuit, an external commercial power source or a battery 6011 provided separately may be used. Note that the battery 6011 can be omitted when a commercial power source is used.

Further, the display module 6000 may be additionally provided with a member such as a polarizing plate, a retardation plate, and a prism sheet.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 9)
In this embodiment, usage examples of a semiconductor device according to one embodiment of the present invention will be described.

<Package using lead frame type interposer>
FIG. 59A is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. In a package illustrated in FIG. 59A, a chip 1751 corresponding to a semiconductor device according to one embodiment of the present invention is connected to a terminal 1752 over an interposer 1750 by a wire bonding method. The terminal 1752 is disposed on the surface on which the chip 1751 of the interposer 1750 is mounted. The chip 1751 may be sealed with a mold resin 1753, but is sealed with a part of each terminal 1752 exposed.

FIG. 59B shows the structure of a module of an electronic device (mobile phone) in which a package is mounted on a circuit board. In the mobile phone module illustrated in FIG. 59B, a package 1802 and a battery 1804 are mounted on a printed wiring board 1801. In addition, a printed wiring board 1801 is mounted with an FPC 1803 on a panel 1800 provided with a display element.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 10)
In this embodiment, an electronic device and a lighting device of one embodiment of the present invention will be described with reference to drawings.

<Electronic equipment>
An electronic device or a lighting device can be manufactured using the semiconductor device of one embodiment of the present invention. A highly reliable electronic device or lighting device can be manufactured using the semiconductor device of one embodiment of the present invention. Further, an electronic device or a lighting device with improved detection sensitivity of a touch sensor can be manufactured using the semiconductor device of one embodiment of the present invention.

Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines.

In the case where the electronic device or the lighting device of one embodiment of the present invention has flexibility, the electronic device or the lighting device can be incorporated along an inner wall or an outer wall of a house or a building, or a curved surface of an interior or exterior of an automobile.

The electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using non-contact power transmission.

Secondary batteries include, for example, lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using a gel electrolyte, lithium ion batteries, nickel metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air batteries A secondary battery, a nickel zinc battery, a silver zinc battery, etc. are mentioned.

The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. Further, when the electronic device has a secondary battery, the antenna may be used for non-contact power transmission.

FIG. 60A illustrates a portable game machine including a housing 7101, a housing 7102, a display portion 7103, a display portion 7104, a microphone 7105, speakers 7106, operation keys 7107, a stylus 7108, and the like. The semiconductor device according to one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the housing 7101. By using a normally-off CPU as a CPU, power consumption can be reduced and games can be enjoyed for a longer time than before. With the use of the semiconductor device according to one embodiment of the present invention for the display portion 7103 or the display portion 7104, a portable game machine that has an excellent usability and is unlikely to deteriorate in quality can be provided. Note that although the portable game machine illustrated in FIG. 60A includes two display portions 7103 and 7104, the number of display portions included in the portable game device is not limited thereto.

FIG. 60B illustrates a smart watch, which includes a housing 7302, a display portion 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. The semiconductor device according to one embodiment of the present invention can be used for a memory, a CPU, or the like incorporated in the housing 7302. Note that a reflective liquid crystal panel is used for the display shown in FIG. 60B and a normally-off CPU is used for the CPU, so that power consumption can be reduced and the number of daily charging operations can be reduced.

FIG. 60C illustrates a portable information terminal which includes an operation button 7503, an external connection port 7504, a speaker 7505, a microphone 7506, a display portion 7502, and the like in addition to a display portion 7502 incorporated in a housing 7501. The semiconductor device according to one embodiment of the present invention can be used for a mobile memory, a CPU, or the like incorporated in the housing 7501. Note that the number of times of charging can be reduced by using a normally-off type CPU. In addition, since the display portion 7502 can have extremely high definition, the display portion 7502 can perform various displays such as full high-definition, 4k, or 8k while being small and medium, and can obtain a very clear image. it can.

FIG. 60D illustrates a video camera, which includes a first housing 7701, a second housing 7702, a display portion 7703, operation keys 7704, a lens 7705, a connection portion 7706, and the like. The operation key 7704 and the lens 7705 are provided in the first housing 7701, and the display portion 7703 is provided in the second housing 7702. The first housing 7701 and the second housing 7702 are connected by a connection portion 7706, and the angle between the first housing 7701 and the second housing 7702 can be changed by the connection portion 7706. is there. The video on the display portion 7703 may be switched in accordance with the angle between the first housing 7701 and the second housing 7702 in the connection portion 7706. The imaging device of one embodiment of the present invention can be provided at a position where the lens 7705 is focused. The semiconductor device according to one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the first housing 7701.

FIG. 60E illustrates digital signage, which includes a display portion 7902 installed on a utility pole 7901. The semiconductor device according to one embodiment of the present invention can be used for the display panel of the display portion 7902 and a built-in control circuit.

FIG. 61A illustrates a laptop personal computer, which includes a housing 8121, a display portion 8122, a keyboard 8123, a pointing device 8124, and the like. The semiconductor device according to one embodiment of the present invention can be applied to a CPU or a memory built in the housing 8121. Note that since the display portion 8122 can have very high definition, the display portion 8122 can display 8k while being small and medium-sized, and a very clear image can be obtained.

FIG. 61B shows the appearance of an automobile 9700. FIG. 61C illustrates a driver seat of a car 9700. The automobile 9700 includes a vehicle body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like. The semiconductor device of one embodiment of the present invention can be used for a display portion of the automobile 9700 and an integrated circuit for control. For example, the semiconductor device of one embodiment of the present invention can be provided in the display portion 9710 to the display portion 9715 illustrated in FIG.

The display portion 9710 and the display portion 9711 are display devices or input / output devices provided on a windshield of an automobile. A display device or an input / output device of one embodiment of the present invention is a so-called see-through state in which an electrode of the display device or the input / output device is made of a light-transmitting conductive material so that the opposite side can be seen through. Display devices or input / output devices. If the display device or the input / output device is in a see-through state, the view is not hindered even when the automobile 9700 is driven. Thus, the display device or the input / output device of one embodiment of the present invention can be provided on the windshield of the automobile 9700. Note that in the case where a transistor for driving the display device or the input / output device is provided in the display device or the input / output device, an organic transistor using an organic semiconductor material, a transistor using an oxide semiconductor, or the like, A transistor having a light-transmitting property may be used.

A display portion 9712 is a display device provided in the pillar portion. For example, the field of view blocked by the pillar can be complemented by displaying an image from the imaging means provided on the vehicle body on the display portion 9712. A display portion 9713 is a display device provided in the dashboard portion. For example, by displaying an image from an imaging unit provided on the vehicle body on the display portion 9713, the view blocked by the dashboard can be complemented. That is, by projecting an image from the imaging means provided outside the automobile, the blind spot can be compensated and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity.

FIG. 61D shows the interior of an automobile in which bench seats are used for the driver seat and the passenger seat. The display portion 9721 is a display device or an input / output device provided in the door portion. For example, the field of view blocked by the door can be complemented by displaying an image from an imaging unit provided on the vehicle body on the display portion 9721. The display portion 9722 is a display device provided on the handle. The display unit 9723 is a display device provided at the center of the seat surface of the bench seat. Note that the display device can be installed on a seating surface or a backrest portion, and the display device can be used as a seat heater using heat generated by the display device as a heat source.

The display portion 9714, the display portion 9715, or the display portion 9722 can provide various other information such as navigation information, a speedometer and a tachometer, a travel distance, an oil supply amount, a gear state, and an air conditioner setting. In addition, display items, layouts, and the like displayed on the display unit can be changed as appropriate according to the user's preference. Note that the above information can also be displayed on the display portion 9710 to the display portion 9713, the display portion 9721, and the display portion 9723. The display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as lighting devices. The display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as heating devices.

FIG. 62A shows the appearance of the camera 8000. FIG. A camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, a coupling portion 8005, and the like. A lens 8006 can be attached to the camera 8000.

The coupling portion 8005 includes electrodes, and can connect a strobe device or the like in addition to a finder 8100 described later.

Here, the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.

An image can be taken by pressing a shutter button 8004. In addition, the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.

The display device or the input / output device of one embodiment of the present invention can be applied to the display portion 8002.

FIG. 62B shows an example in which a viewfinder 8100 is attached to a camera 8000.

The viewfinder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 includes a coupling portion that engages with the coupling portion 8005 of the camera 8000, and the finder 8100 can be attached to the camera 8000. In addition, the coupling portion includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.

The button 8103 has a function as a power button. A button 8103 can be used to switch display on the display portion 8102 on and off.

The semiconductor device of one embodiment of the present invention can be applied to an integrated circuit or an image sensor in the housing 8101.

62A and 62B, the camera 8000 and the viewfinder 8100 are separate electronic devices and are configured to be detachable. However, a display of one embodiment of the present invention is displayed on the housing 8001 of the camera 8000. A finder provided with a device or an input / output device may be incorporated.

FIG. 62C shows the appearance of the head mounted display 8200.

The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. In addition, a battery 8206 is built in the mounting portion 8201.

A cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204. In addition, it is possible to use the user's viewpoint as an input unit by capturing the movement of the user's eyeball or eyelid with a camera provided in the main body 8203 and calculating the coordinates of the user's viewpoint based on the information. it can.

In addition, the mounting portion 8201 may be provided with a plurality of electrodes at a position where the user touches the user. The main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.

The semiconductor device of one embodiment of the present invention can be applied to the integrated circuit in the main body 8203.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 11)
In this embodiment, an example of using an RF tag using a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

<Usage example of RF tag>
Applications of RF tags are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 63A), vehicles (bicycles, FIG. 63, etc.) (See (B)), packaging containers (wrapping paper, bottles, etc., see FIG. 63 (C)), recording media (DVD, video tape, etc., see FIG. 63 (D)), personal items (bags, glasses, etc.) , Articles such as foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag (see FIGS. 63E and 63F) attached to each article.

The RF tag 4000 according to one embodiment of the present invention is fixed to an article by being attached to the surface or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the article itself even after being fixed to the article. In addition, by providing the RF tag 4000 according to one embodiment of the present invention to bills, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved. Can be planned. Even in the case of vehicles, the security against theft or the like can be improved by attaching the RF tag according to one embodiment of the present invention.

As described above, operating power including writing and reading of information can be reduced by using an RF tag including a semiconductor device according to one embodiment of the present invention for each application described in this embodiment. It is possible to increase the communication distance. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

In this example, the results of measuring the resistance value of the oxide semiconductor layer 122 after the ion addition treatment will be described.

A structure shown in FIG. 64 was produced as a measurement sample. The measurement sample was manufactured by the method described in Embodiment 1. Note that a sample manufacturing method is not limited to this method.

As the substrate 100, an Si wafer of about 700 μm was used.

As the insulating layer 110, a stack of a silicon oxide film and a silicon oxynitride film was formed.

As the silicon oxide film, a thermal oxidation film of 100 nm was formed on a Si wafer by a hydrochloric acid oxidation method at 950 ° C.

The silicon oxynitride film was formed to a thickness of 300 nm by a plasma CVD method. The film formation conditions are as follows: the gas flow rate for film formation is 2.3 sccm of silane, 800 sccm of dinitrogen monoxide, the pressure in the chamber during film formation is 40 Pa by the diaphragm type ballatron sensor and APC valve control, and the RF power supply frequency is 27 MHz. The power during film formation was 50 W, the distance between the electrodes was 15 mm, and the substrate heating temperature during film formation was 400 ° C.

Next, an oxide semiconductor film formed to a thickness of 50 nm using an oxide of In: Ga: Zn = 1: 1: 1 (atomic ratio) as a target by a sputtering method as the oxide semiconductor layer 122 is used. It was. The film formation conditions are as follows: the pressure in the chamber during film formation is 0.7 Pa, the power during film formation is 0.5 kW using a DC power source, the gas flow rate for sputtering is 30 sccm Ar gas, and 15 sccm oxygen gas, The distance between the sample and the target was 60 mm, and the substrate heating temperature during film formation was 300 ° C.

After the oxide semiconductor layer 122 was formed, heat treatment was performed at 450 ° C. for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 450 ° C. for 1 hour in an oxygen atmosphere.

The ion addition treatment was performed by an ion implantation method. A summary of the different ion implantation conditions for each sample is shown in Table 1.

The resistance value of the sample was measured using a sheet resistance measuring machine, and a VR-200 manufactured by Hitachi Kokusai Electric was used as the apparatus. 65, 66, and 67 show the sheet resistance measurement results.

65, 66, and 67, the resistivity can be stably reduced in a sample in which a dose amount of 3.0 × 10 ¹⁴ ions / cm ² or more is implanted for any ion species of phosphorus, argon, and xenon. It was confirmed that

10 transistor 11 transistor 12 transistor 13 transistor 14 transistor 20 display device 21 display region 22 peripheral circuit 24 display device 50 transistor 52 transistor 60 capacitor element 62 capacitor element 70 light emitting element 80 liquid crystal element 100 substrate 103 polarizing plate 105 protective substrate 110 insulating layer 121 Metal oxide layer 122 Oxide semiconductor layer 123 Metal oxide layer 123a Metal oxide film 123b Metal oxide layer 125 Low resistance region 130 Source electrode layer 130b Conductive layer 140 Drain electrode layer 150 Gate insulating layer 150a Insulating film 150b Gate insulating layer 151 Gate insulating layer 152 Gate insulating layer 152a Insulating film 152b Insulating layer 160 Gate electrode layer 160a Conductive film 165 Conductive layer 167 Ion 170 Insulating layer 172 Insulating layer 173 Oxygen 174 Groove part 1 75 Insulating layer 175b Insulating layer 176 Insulating layer 180 Insulating layer 190 Conductive layer 195 Conductive layer 197 Conductive layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel portion 211 Pixel 212 Subpixel 212B Subpixel 212G Subpixel 212R Subpixel 220 Photoelectric conversion Element 230 Pixel circuit 231 wiring 247 wiring 248 wiring 249 wiring 250 wiring 253 wiring 254 filter 254B filter 254G filter 254R filter 255 lens 256 light 257 wiring 260 peripheral circuit 270 peripheral circuit 280 peripheral circuit 290 peripheral circuit 300 silicon substrate 310 layer 320 layer 330 Layer 340 Layer 351 Transistor 353 Transistor 360 Photodiode 361 Anode 362 Cathode 363 Low resistance region 365 Photodiode 36 Semiconductor 367 Semiconductor 368 Semiconductor 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 380 Insulating layer 400 Substrate 402 Protective substrate 403 Polarizing plate 410 Conductive layer 415 Conductive layer 418 Light shielding layer 420 Insulating layer 430 Insulating layer 440 Spacer 445 Partition 450 EL layer 460 Coloring Layer 470 Adhesive layer 473 Adhesive layer 474 Adhesive layer 475 Adhesive layer 476 Adhesive layer 480 Conductive layer 490 Liquid crystal layer 510 Anisotropic conductive layer 530 Optical adjustment layer 601 Precursor 602 Precursor 700 Substrate 701 Pixel portion 702 Scan line drive circuit 703 Scan line drive Circuit 704 Signal line driver circuit 710 Capacitor wiring 712 Scan line 713 Scan line 714 Signal line 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Dynamic transistor 723 Capacitance element 724 Light emitting element 725 Signal line 726 Scan line 727 Power supply line 728 Common electrode 800 RF tag 801 Communication device 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulator circuit 809 Modulator circuit 809 Logic circuit 810 Memory circuit 811 ROM
1189 ROM interface 1190 board 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 memory element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitor element 1208 capacitor element 1209 transistor 1210 transistor 1213 transistor 1214 transistor 1220 circuit 1700 substrate 1701 chamber 1702 load chamber 1703 pretreatment chamber 1704 chamber 1705 chamber 1706 unload chamber 1711a Raw material supply unit 1711b Raw material supply unit 1712a High speed valve 1712b High speed valve 1713a Raw material introduction port 1713b Raw material introduction port 1714 Raw material discharge port 1715 Exhaust device 1716 Substrate holder 1720 Transfer chamber 1750 Interposer 1751 Chip 1752 Terminal 1753 Mold resin 1800 Panel 1801 Printed wiring board 1802 Package 1 803 FPC
1804 battery 2100 transistor 2200 transistor 2201 insulator 2202 wiring 2203 plug 2204 insulator 2205 wiring 2207 insulator 2211 semiconductor substrate 2212 insulator 2213 gate electrode 2214 gate insulator 2215 source region and drain region 2800 inverter 2810 OS transistor 2820 OS transistor 2831 signal Waveform 2832 Signal waveform 2840 Broken line 2841 Solid line 2850 OS transistor 2860 CMOS inverter 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitance element 4000 RF tag 6000 Display module 6001 Upper cover 6002 Lower cover 6003 FPC
6004 Touch panel 6005 FPC
6006 Display panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed circuit board 6011 Battery 7101 Case 7102 Case 7103 Display portion 7104 Display portion 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Case 7304 Display portion 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp 7501 Case 7502 Display unit 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Case 7702 Case 7703 Display unit 7704 Operation key 7705 Lens 7706 Connection unit 7901 Power pole 7902 Display unit 8000 Camera 8001 Case Body 8002 Display unit 8003 Operation button 8004 Shutter button 8005 Coupling unit 006 Lens 8100 Viewfinder 8101 Case 8102 Display unit 8103 Button 8121 Case 8122 Display unit 8123 Keyboard 8124 Pointing device 8200 Head mounted display 8201 Mounting unit 8202 Lens 8203 Body 8204 Display unit 8205 Cable 8206 Battery 9700 Car 9701 Car body 9702 Wheel 9703 Dashboard 9704 Light 9710 Display unit 9711 Display unit 9712 Display unit 9713 Display unit 9714 Display unit 9715 Display unit 9721 Display unit 9722 Display unit 9723 Display unit

Claims (18)

A first insulating layer on the substrate;
A first metal oxide layer on the first insulating layer;
An oxide semiconductor layer on the first metal oxide layer;
A second metal oxide layer on the oxide semiconductor layer;
A gate insulating layer on the second metal oxide layer;
A gate electrode layer on the gate insulating layer;
Have
The oxide semiconductor layer has a first region to a third region,
The first region and the second region have a region overlapping with the gate electrode layer,
The second region is a region between the first region and the third region,
The second region has a region having a lower resistance than the first region,
The third region has a region having a lower resistance than the second region,
The second region and the third region have a region containing an element N (N is phosphorus, argon, xenon);
A semiconductor device characterized by the above. A first insulating layer on the substrate;
A first metal oxide layer on the first insulating layer;
An oxide semiconductor layer on the first metal oxide layer;
The first insulating layer, a second metal oxide layer on the oxide semiconductor layer, and
A first gate insulating layer on the second metal oxide layer;
A gate electrode layer on the first gate insulating layer;
Have
The second metal oxide layer and the first gate insulating layer have regions facing the side surfaces of the first metal oxide layer and the oxide semiconductor layer,
The oxide semiconductor layer has a first region to a third region,
The first region and the second region have a region overlapping with the gate electrode layer,
The second region is a region between the first region and the third region,
The second region has a region having a lower resistance than the first region,
The third region has a region having a lower resistance than the second region,
The second region and the third region have a region containing an element N (N is phosphorus, argon, xenon);
A semiconductor device characterized by the above. In claim 2,
Having a second gate insulating layer between the first gate insulating layer and the gate electrode layer;
A semiconductor device characterized by the above. In any one of Claims 1 thru | or 3,
The second region has a region where the concentration of the element N is higher than that of the first region,
The third region has a region where the concentration of the element N is higher than that of the second region;
A semiconductor device characterized by the above. In any one of Claims 1 thru | or 4,
The third region has a region in which the concentration of the element N is 1 × 10 ¹⁸ atoms / cm ³ or more and 1 × 10 ²² atoms / cm ³ or less;
A semiconductor device characterized by the above. A first insulating layer on the substrate;
A first metal oxide layer on the first insulating layer;
An oxide semiconductor layer on the first metal oxide layer;
A second metal oxide layer on the oxide semiconductor layer;
A gate insulating layer on the second metal oxide layer;
A second insulating layer on the second metal oxide layer;
A gate electrode layer on the gate insulating layer;
Have
The gate insulating layer has a region in contact with a side surface of the gate electrode layer;
The second insulating layer has a region in contact with the gate insulating layer,
The oxide semiconductor layer has a first region to a third region,
The first region has a region overlapping the gate electrode layer,
The second region has a region overlapping with the gate insulating layer or the second insulating layer,
The second region is a region between the first region and the third region,
The second region and the third region have a region containing an element N (N is phosphorus, argon, xenon);
A semiconductor device characterized by the above. In claim 6,
The second region has a region having a lower resistance than the first region,
The third region has a region having a lower resistance than the second region;
A semiconductor device characterized by the above. In claim 6 or 7,
The angle formed by the tangent line between the bottom surface of the substrate and the side surface of the gate electrode layer has a region of 60 degrees to 85 degrees,
A semiconductor device characterized by the above. Forming a first insulating layer on the substrate;
Forming a stack of a first metal oxide layer and a first oxide semiconductor layer on the first insulating layer;
A stack of the first metal oxide layer and the first oxide semiconductor layer is etched into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer. ,
Forming a third metal oxide layer on the second oxide semiconductor layer and the first insulating layer;
Forming a second insulating layer on the third metal oxide layer;
By performing a planarization process on the second insulating layer, a third insulating layer is formed,
Forming a fourth insulating layer having a groove reaching the third metal oxide layer by etching a part of the third insulating layer using a second mask;
Forming a fifth insulating layer on the fourth insulating layer and the third metal oxide layer;
Forming a first conductive layer on the fifth insulating layer;
By performing a planarization process until the fourth insulating layer is exposed with respect to the first conductive layer and the fifth insulating layer, a gate electrode layer and a sixth insulating layer are formed,
Forming the gate insulating layer by etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask;
Forming a source region and a drain region by adding ions to the second oxide semiconductor layer using the gate electrode layer as a mask;
A method for manufacturing a semiconductor device. Forming a first insulating layer on the substrate;
Forming a stack of a first metal oxide layer and a first oxide semiconductor layer on the first insulating layer;
A stack of the first metal oxide layer and the first oxide semiconductor layer is etched into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer. ,
Forming a third metal oxide layer on the second oxide semiconductor layer and the first insulating layer;
Forming a first gate insulating layer on the third metal oxide layer;
Forming a second insulating layer on the first gate insulating layer;
By performing a planarization process on the second insulating layer, a third insulating layer is formed,
Etching a part of the third insulating layer using a second mask to form a fourth insulating layer having a groove reaching the first gate insulating layer;
Forming a first conductive layer on the fourth insulating layer and the first gate insulating layer;
By planarizing the first conductive layer until the fourth insulating layer is exposed, a gate electrode layer is formed,
Etching the fourth insulating layer using the gate electrode layer as a mask provides a region exposing the first gate insulating layer;
Forming a second gate insulating layer by etching the first gate insulating layer using the gate electrode layer as a mask;
Forming a source region and a drain region by adding ions to the second oxide semiconductor layer;
A method for manufacturing a semiconductor device. Forming a first insulating layer on the substrate;
Forming a stack of a first metal oxide layer and a first oxide semiconductor layer on the first insulating layer;
A stack of the first metal oxide layer and the first oxide semiconductor layer is etched into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer. ,
Forming a third metal oxide layer on the second oxide semiconductor layer and the first insulating layer;
Forming a first gate insulating layer on the third metal oxide layer;
Forming a second insulating layer on the first gate insulating layer;
By performing a planarization process on the second insulating layer, a third insulating layer is formed,
Etching a part of the third insulating layer using a second mask to form a fourth insulating layer having a groove reaching the first gate insulating layer;
Forming a fifth insulating layer on the fourth insulating layer and the first gate insulating layer;
Forming a first conductive layer on the fifth insulating layer;
By planarizing the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed, a gate electrode layer and a sixth insulating layer are formed,
Etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask provides a region exposing the first gate insulating layer,
Forming a source region and a drain region by adding ions to the second oxide semiconductor layer;
A method for manufacturing a semiconductor device. In any one of Claims 9 thru | or 11,
Using phosphorus, argon, or xenon in the ion addition;
A method for manufacturing a semiconductor device. In any one of claims 9 to 12,
In the ion addition,
The dose amount of ions is 1 × 10 ¹⁴ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less,
A method for manufacturing a semiconductor device. Forming a first insulating layer on the substrate;
A stack of a first metal oxide layer and a first oxide semiconductor layer is formed in an island shape over the first insulating layer,
The second metal oxide layer and the second oxide semiconductor layer are formed by etching the first metal oxide layer and the stack of the first oxide semiconductor layer into an island shape using a first mask. And
Forming a third metal oxide layer on the second oxide semiconductor layer and the first insulating layer;
Forming a second insulating layer on the third metal oxide layer;
By performing a planarization process on the second insulating layer, a third insulating layer is formed,
Etching a part of the third insulating layer using a second mask to form a fourth insulating layer having a groove reaching the third metal oxide layer;
Forming a fifth insulating layer on the fourth insulating layer and the third metal oxide layer;
Forming a first conductive layer on the fifth insulating layer;
A planarization process is performed on the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed, thereby forming a gate electrode layer and a sixth insulating layer,
Etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask has a gate insulating layer having a region in contact with a side surface of the gate electrode layer, and a region in contact with the gate insulating layer Forming a seventh insulating layer;
Forming a source region and a drain region by adding ions to the second oxide semiconductor layer;
A method for manufacturing a semiconductor device. In claim 14,
Using phosphorus, argon, or xenon in the ion addition;
A method for manufacturing a semiconductor device. In claim 14 or 15,
In the ion addition,
The dose amount of ions is 1 × 10 ¹⁴ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less,
A method for manufacturing a semiconductor device. In any one of claims 14 to 16,
An angle formed by a tangent to a side surface of the gate electrode layer and a bottom surface of the substrate has a region of 60 degrees to 85 degrees;
A method for manufacturing a semiconductor device. A semiconductor device according to any one of claims 1 to 8,
A housing, a speaker,
An electronic device comprising: