JP2023028520A - Method for manufacturing printed wiring board and method for manufacturing semiconductor package - Google Patents

Abstract

To provide a method for manufacturing a printed wiring board which is excellent in forming accuracy, can form a circuit pattern having high adhesion, and is excellent in working environment, and a method for manufacturing a semiconductor package using the printed wiring board obtained by the manufacturing method.SOLUTION: There are provided a method of manufacturing a printed wiring board including specific steps 1 to 6 in this order and a method of manufacturing of a semiconductor package using the printed wiring board obtained by the manufacturing method.SELECTED DRAWING: Figure 7

Description

The present embodiment relates to a printed wiring board manufacturing method and a semiconductor package manufacturing method.

2. Description of the Related Art In recent years, the development of the information society has been remarkable, and personal computers, mobile phones, and the like have been made smaller, lighter, and have higher performance and higher functionality. On the other hand, as industrial equipment, network-related equipment such as wireless base stations, optical communication devices, servers and routers, etc., regardless of size or size, are required to have improved functions. In addition, as the amount of information to be transmitted increases, the frequency of signals to be handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. For example, CPU (Central Processing Unit), DSP (Digital Signal Processing) and LSI (Large Scale Integration) such as various memories are increasing in speed and function, and as new high-density mounting technology, system-on-chip (SoC), system In-package (SiP) and the like are being actively developed. For this reason, semiconductor chip mounting substrates and motherboards are multi-layered build-up systems in which fine wiring with a small wiring width/space (L/S) is formed in order to respond to higher frequencies, higher wiring densities, and higher functionality. Wiring boards have come to be used.

In recent years, a semi-additive process (SAP: Semi-Additive Process, hereinafter also referred to as "SAP method") is generally considered useful for forming fine wiring. In the case of the semi-additive method, first, an electroless copper plating layer called a seed layer is provided on an insulating resin, and a dry film resist layer is provided on the copper plating layer. Then, a resist pattern is formed by a method of exposure through a photomask (photolithography) or a method of direct exposure with laser light. Next, after performing plasma treatment as necessary, a circuit pattern is formed by electrolytic copper plating in the part without the resist pattern, the resist pattern is removed, and finally the seed layer in the unnecessary part is etched and removed. (See Patent Document 1, for example).

JP 2017-208471 A

In the conventional SAP method, it was necessary to form a seed layer having a certain thickness of 0.5 μm or more, for example, in order to sufficiently exhibit its function as a seed layer. However, if the seed layer is thick, there is a problem that the amount of etching when removing the unnecessary seed layer increases, thereby increasing the degree of miniaturization of the circuit pattern. It is also conceivable to design the width of the circuit pattern to be thicker before etching by counting back the reduction of the circuit pattern, but in this case, it is necessary to reduce the width of the resist pattern. problem arises. This problem becomes more apparent as L/S becomes smaller. Furthermore, as the L/S becomes smaller, it becomes more difficult to completely remove the seed layer, and the residue of the seed layer impairs the insulation reliability.
On the other hand, simply reducing the thickness of the seed layer causes pinholes, voids, etc. in the seed layer, making it difficult to form a uniform seed layer.
In addition, an increase in the amount of etching when the seed layer is thickened and the generation of pinholes when the seed layer is thinned cause undercutting and peeling of the circuit pattern, resulting in deterioration of the adhesion of the circuit pattern. In particular, the seed layer by electroless copper plating formed by the conventional method is oxidized by palladium, which is a catalyst for electroless copper plating, which exists in the vicinity, so that the problem of undercut and peeling of the circuit pattern is further increased. becomes prominent.
Furthermore, after etching the seed layer to form a circuit pattern, CZ treatment is generally performed as a pretreatment for forming an insulating resin such as a solder resist or a build-up material on the circuit pattern. ing. The CZ treatment is, for example, roughening treatment by etching of about 1.0 to 1.5 μm. The treatment further promotes undercutting and peeling of circuit patterns.
In addition, in the conventional SAP method, highly toxic formalin, cyanide, etc. are used in the electroless copper plating solution used to form the seed layer. There is a demand for a method that does not use the compound of

Therefore, the present embodiment provides a method for manufacturing a printed wiring board which is excellent in formation accuracy, can form a circuit pattern having high adhesion, and is excellent in working environment, and a method for manufacturing a semiconductor package using the printed wiring board obtained by the manufacturing method. The task is to provide

The present inventors have made intensive studies to solve the above problems, and as a result, have found that the above problems can be solved by the present embodiment described below.
That is, the present embodiment relates to the following [1] to [6].
[1] A method for manufacturing a printed wiring board including the following steps 1 to 6 in this order.
Step 1: The surface of a substrate selected from a composite material containing a glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesion-assisting layer formed by forming an adhesion-assisting layer on the surface of the composite material ( S1) a step of providing an insulating material pattern and an insulating material pattern non-formation portion, which is a space corresponding to a gap between the insulating material patterns and exposes the surface (S1), on S1) Step 2: The insulating material pattern and a portion of the surface (S1) exposed in the insulating material pattern non-formed portion, by depositing a first catalyst on the surface (S2) to obtain a first catalyst adhesion treated surface step of forming (S3) Step 3: The first catalyst-adhering treated surface (S3) is brought into contact with an electroless nickel plating solution containing hypophosphite as a reducing agent, so as to contain at least nickel. Step of forming a second catalyst adhesion treated surface (S4) to which a second catalyst is adhered Step 4: Using hypophosphite as a reducing agent for the second catalyst adhesion treated surface (S4) A step of forming a seed layer on the second catalyst adhesion treated surface (S4) by contacting an electroless copper plating solution Step 5: Electrolytic copper plating is performed on the surface of the seed layer, and forming a copper layer; Step 6: removing the copper layer, the seed layer, the first catalyst and the second catalyst adhering to the upper surface of the insulating material pattern, thereby removing the insulating material pattern; The process [2] of obtaining the circuit pattern formed in the forming portion, and the method for producing a printed wiring board according to [1] above, further including the following step 7.
Step 7: Step of laminating an insulating resin material on the insulating material pattern and the circuit pattern [3] The printed wiring according to [1] or [2] above, wherein the electroless nickel plating solution has a pH of 7 to 10. Board manufacturing method.
[4] The method for producing a printed wiring board according to any one of [1] to [3] above, wherein the phosphorus content in the second catalyst is 6% by mass or less.
[5] The method for producing a printed wiring board according to any one of [1] to [4] above, wherein the seed layer has a thickness of 0.4 μm or less.
[6] A method for manufacturing a semiconductor package, comprising manufacturing a printed wiring board by the method for manufacturing a printed wiring board according to any one of [1] to [5] above, and mounting a semiconductor element on the printed wiring board.

According to the present embodiment, a method for manufacturing a printed wiring board which is excellent in forming accuracy, can form a circuit pattern having high adhesion, and is excellent in working environment, and a method for manufacturing a semiconductor package using the printed wiring board obtained by the manufacturing method are provided. can provide.

It is a cross-sectional schematic diagram which shows the process of the manufacturing method of this embodiment. It is a cross-sectional schematic diagram which shows the continuation process of the manufacturing method of this embodiment. It is a cross-sectional schematic diagram which shows the continuation process of the manufacturing method of this embodiment. It is a cross-sectional schematic diagram which shows the continuation process of the manufacturing method of this embodiment. It is a cross-sectional schematic diagram which shows the continuation process of the manufacturing method of this embodiment. It is a cross-sectional schematic diagram which shows the continuation process of the manufacturing method of this embodiment. It is a cross-sectional schematic diagram which shows the continuation process of the manufacturing method of this embodiment.

In this specification, a numerical range indicated using "to" indicates a range including the numerical values before and after "to" as the minimum and maximum values, respectively.
For example, the notation of a numerical range “X to Y” (X and Y are real numbers) means a numerical range that is greater than or equal to X and less than or equal to Y. And the description "X or more" in this specification means X and a numerical value exceeding X. In addition, the description “Y or less” in this specification means Y and a numerical value less than Y.
The lower and upper limits of any numerical range recited herein are optionally combined with the lower or upper limits of other numerical ranges, respectively.
In the numerical ranges described herein, the lower or upper limit of the numerical range may be replaced with the values shown in the examples.

Each component and material exemplified in this specification may be used alone or in combination of two or more unless otherwise specified.

The mechanism of action described in this specification is speculation, and does not limit the mechanism of the effect of this embodiment.

As used herein, the term "layer" includes a layer that is partially missing, and a layer that has vias or patterns formed thereon.

In this specification, "printed wiring board" is a concept including "multilayer printed wiring board".

Aspects in which the items described in this specification are arbitrarily combined are also included in this embodiment.

[Printed wiring board manufacturing method and printed wiring board]
The printed wiring board manufacturing method of the present embodiment is a printed wiring board manufacturing method including the following steps 1 to 6 in this order.
Step 1: The surface of a substrate selected from a composite material containing a glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesion-assisting layer formed by forming an adhesion-assisting layer on the surface of the composite material ( S1) a step of providing an insulating material pattern and an insulating material pattern non-formation portion, which is a space corresponding to a gap between the insulating material patterns and exposes the surface (S1), on S1) Step 2: The insulating material pattern and a portion of the surface (S1) exposed in the insulating material pattern non-formed portion, by depositing a first catalyst on the surface (S2) to obtain a first catalyst adhesion treated surface step of forming (S3) Step 3: The first catalyst-adhering treated surface (S3) is brought into contact with an electroless nickel plating solution containing hypophosphite as a reducing agent, so as to contain at least nickel. Step of forming a second catalyst adhesion treated surface (S4) to which a second catalyst is adhered Step 4: Using hypophosphite as a reducing agent for the second catalyst adhesion treated surface (S4) A step of forming a seed layer on the second catalyst adhesion treated surface (S4) by contacting an electroless copper plating solution Step 5: Electrolytic copper plating is performed on the surface of the seed layer, and forming a copper layer; Step 6: removing the copper layer, the seed layer, the first catalyst and the second catalyst adhering to the upper surface of the insulating material pattern, thereby removing the insulating material pattern; A step of obtaining a circuit pattern formed on the forming part

According to the printed wiring board manufacturing method of the present embodiment, the insulating material pattern used for forming the circuit pattern is used as the insulating layer without being removed. Therefore, according to the method for manufacturing a printed wiring board of the present embodiment, the removal of the resist pattern and the etching of the seed layer after removing the resist pattern are not required, and the side surface of the circuit pattern is reduced in size, the circuit pattern is undercut, and the like. problem does not occur. Therefore, the printed wiring board manufactured by the manufacturing method of this embodiment has excellent formation accuracy.

Further, in the printed wiring board manufacturing method of the present embodiment, the circuit pattern is formed by forming a composite material containing glass cloth and a cured product of a thermosetting resin, and forming an adhesion auxiliary layer on the surface of the composite material. on the surface (S1) of a substrate selected from: a composite material with an adhesion-assisting layer; Since the composite material containing the glass cloth and the cured product of the thermosetting resin has high rigidity, the printed wiring board manufactured by the manufacturing method of the present embodiment is less likely to warp.

In addition, according to the conventional method, when a circuit pattern is formed on the surface of a composite material containing a glass cloth having high rigidity and a cured product of a thermosetting resin, sufficient adhesion to the circuit pattern cannot be obtained. was there. The reason for this is considered to be that the composite material is designed for the purpose of increasing rigidity, and it was difficult to achieve compatibility with the material design for increasing the adhesion to the circuit pattern. On the other hand, in the method for manufacturing a printed wiring board of the present embodiment, before forming the seed layer, after attaching the first catalyst, contacting with an electroless nickel plating solution using hypophosphite as a reducing agent is performed. and depositing a second catalyst containing at least nickel. As a result, the throwing power of the seed layer is improved, and excellent adhesion can be obtained even when the substrate is a composite material having high rigidity.
In addition, in the circuit pattern formed by the conventional SAP method, the seed layer is formed from a palladium catalyst and copper, so the copper forming the wiring is more electrochemically base than the seed layer and is easily corroded. . On the other hand, in the circuit pattern of the printed wiring board of the present embodiment, the seed layer contains nickel, which is electrochemically less base than copper. , the copper forming the wiring becomes difficult to corrode, and a high HAST resistance can be obtained.

In addition, in the method for manufacturing a printed wiring board of the present embodiment, since an electroless copper plating solution using hypophosphite as a reducing agent is used to form the seed layer, it is necessary to use highly toxic formalin, cyanide, or the like. It is excellent in improving the working environment and safety.

Hereinafter, this embodiment will be described in detail with reference to the drawings for each step.
In the following description, the same or corresponding parts are denoted by the same reference numerals, and overlapping descriptions are omitted. In addition, unless otherwise specified, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to the illustrated ratios.

<Step 1: Formation of insulating material pattern>
In step 1, a substrate (hereinafter Insulating material patterns, and insulating material pattern non-formation portions corresponding to gaps between the insulating material patterns, where the surface (S1) is exposed, are formed on a surface (S1) of a surface (S1) of a substrate. is a step of providing .

As a method for forming the insulating material pattern on the surface (S1) of the substrate, a method of forming a photosensitive resin layer on the surface (S1) of the substrate and exposing and developing the photosensitive resin layer is preferable.

FIG. 1(a) shows a step of forming a photosensitive resin layer 2 on the surface S1 of the substrate 1. As shown in FIG.

The substrate 1 is a substrate selected from a composite material containing glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesion-assisting layer formed by forming an adhesion-assisting layer on the surface of the composite material. .
When the substrate 1 is a composite material with an adhesion-assisting layer, the photosensitive resin layer 2 is formed on the surface of the adhesion-assisting layer.

As the composite material used as the substrate 1, known materials used for printed wiring boards can be used. For example, a prepreg made by impregnating glass cloth with a resin composition containing a thermosetting resin is cured. It is preferable that the

As the thermosetting resin, for example, at least one selected from the group consisting of epoxy resins, phenol resins, urea resins, melamine resins, alkyd resins, cyanate compounds, bismaleimide compounds, bismaleimide compounds, monoamine compounds, and diamine compounds. reaction product, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) isocyanurate containing resins, resins synthesized from aromatic nitriles, trimerized aromatic dicyanamide resins, furan resins, ketone resins, xylene resins, thermosetting resins containing condensed polycyclic aromatics, benzocyclobutene resins, bisallyl nadimide resins, benzoxazine compounds and the like.
In addition to thermosetting resins, resin compositions include thermoplastic resins, curing agents, curing accelerators, inorganic fillers, organic fillers, flame retardants, thickeners, ultraviolet absorbers, adhesion imparting agents, coloring agents, It may contain an agent or the like.
Examples of the glass cloth include glass cloth using E glass, C glass, D glass, S glass, etc., glass cloth obtained by bonding short fibers with an organic binder, and a mixture of glass fiber and cellulose fiber. be done.

The adhesion assisting layer is a layer provided on the surface of the composite material for the purpose of improving the adhesion strength with the insulating material pattern and the circuit pattern, and is also called a primer layer.
The adhesion auxiliary layer is not particularly limited as long as it can achieve the purpose of improving adhesion strength, but is preferably formed from a resin composition containing a thermosetting resin.
Although the thickness of the adhesion-assisting layer is not particularly limited, it is preferably 0.5 to 20 μm, more preferably 0.7 to 15 μm, still more preferably 1 to 10 μm.

Although the thickness of the substrate 1 is not particularly limited, it is preferably 1 to 500 μm, more preferably 2 to 300 μm, even more preferably 3 to 100 μm, particularly preferably 5 to 5 μm, from the viewpoint of thinness and mechanical strength of the printed wiring board. 50 μm.

As the substrate 1, for example, products manufactured by Showa Denko Materials Co., Ltd. "GEA-700G (R)", "GEA-795G", "GEA-770G (R)", "GEA-770G (F)", "GEA-705G","GEA-705G(F)","GH-200","GH-100","GWA-900","GWA-910" and the like are commercially available.
Also, as the substrate 1 with an adhesion-assisting layer, products such as "PF-EL" and "PF-EL (SP)" manufactured by Showa Denko Materials Co., Ltd. are commercially available.

The photosensitive resin layer 2 is preferably made of a photosensitive resin composition.
The method of forming the photosensitive resin layer 2 using a photosensitive resin composition may be, for example, a method of applying a varnish-like photosensitive resin composition to the surface S1 of the substrate 1, or a film-like photosensitive resin composition. A method of attaching a resin composition (hereinafter also referred to as a “photosensitive resin film”) to the surface S1 of the substrate 1 may be used.

The photosensitive resin film is, for example, a film formed from a photosensitive resin composition on the surface of a support, and known photosensitive resin films for forming an insulating layer can be used. As such a photosensitive resin film, for example, "PV-F008" is commercially available as a photosensitive build-up film PV-F series manufactured by Showa Denko Materials.

The photosensitive resin layer 2 can be formed by arranging a photosensitive resin film on the surface S1 side of the substrate 1 and thermally laminating it using a laminator such as a roll laminator.

The thickness of the photosensitive resin layer 2 may be appropriately determined according to the thickness and shape of the circuit pattern to be formed, preferably 5 to 100 μm, more preferably 7 to 50 μm, and still more preferably 10 to 30 μm. .

In FIG. 1B, by exposing and developing a part of the photosensitive resin layer 2, the insulating material pattern 3 and the surface S1, which is a space corresponding to the gap between the insulating material patterns 3, are exposed. A step of providing an insulating material pattern non-formation portion 4 is illustrated.

The exposure conditions for the photosensitive resin layer 2 are not particularly limited, and may be appropriately determined according to the type of the photosensitive resin composition used for forming the photosensitive resin layer 2 and the like.
After the photosensitive resin layer is exposed, the unexposed area is removed by dissolving it in a dilute alkaline aqueous solution and developed. If necessary, the residue is removed by oxygen plasma ashing, heat treatment, etc., and desmear treatment are performed. Thus, an insulating material pattern 3 and an insulating material pattern non-formation portion 4 are formed.

<Step 2: Adhesion of first catalyst>
In step 2, a first catalyst is deposited on the surface (S2) composed of the surface of the insulating material pattern and the portion of the surface (S1) exposed in the insulating material pattern non-formed portion. , forming a first catalyst adhesion treatment surface (S3).

2(a) and 2(b) show a surface S2 composed of a surface Sα of the insulating material pattern 3 and a portion Sβ of the surface S1 exposed at the insulating material pattern non-formation portion 4, and a second surface S2 having a surface S2 formed thereon. The step of depositing one catalyst to form the first catalyst-deposited surface S3 is illustrated.
In addition, in FIG. 2(b), the first catalyst adhesion treated surface S3 is shown like a layer for convenience, but the first catalyst may not be formed in a layer, and usually the surface S2 Dotted above. When the first catalyst is scattered, the first catalyst adhesion treated surface S3 does not refer only to the portion where the first catalyst is adhered, but is subjected to the treatment for adhering the first catalyst. It means the entire surface, including the portion where the first catalyst is not adhered.

The first catalyst is a catalyst for promoting electroless nickel plating, which will be described later.
A palladium catalyst is preferably used as the first catalyst, but is not particularly limited as long as it is a catalyst for promoting electroless nickel plating, which will be described later. In the following description, an embodiment using a palladium catalyst as the first catalyst will be mainly described.

The first catalyst can be deposited on the surface S2, for example, by treating the surface S2 with an electroless plating catalyst (first catalyst). Specifically, the surface S2 is subjected to a cleaning process, a soft etching process, a neutralization process, a process using a catalyst for electroless plating (first catalyst), a reduction process, etc. in this order. It is preferable to attach the

The cleaning process can be carried out, for example, by using an alkaline cleaning solution at a temperature of preferably 40 to 70° C. for preferably 1 to 10 minutes, followed by washing with hot water and water.

In the soft etching process, for example, a treatment solution containing a sulfuric acid-hydrogen peroxide solution and a sodium persulfate solution is used, preferably at 15 to 30° C., preferably for 0.5 to 2 minutes. After that, it can be washed with water.

The neutralization treatment step can be carried out by, for example, using an aqueous solution of sulfuric acid or the like, preferably performing treatment at 20 to 30° C. for preferably 0.5 to 1 minute, and washing with water.

For example, a plating catalyst solution containing a palladium salt can be used in the treatment step using the electroless plating catalyst (first catalyst). In addition, as a pretreatment for applying the electroless plating catalyst, a pre-dip treatment solution is preferably used at 20 to 40 ° C., preferably for 0.5 to 2 minutes, and further using an alkaline palladium applying solution. , preferably at 30 to 50° C., preferably for 3 to 7 minutes, followed by washing with water.

The reduction treatment step can be carried out, for example, by using a palladium reduction treatment solution, preferably at 20 to 40° C., preferably for 3 to 7 minutes, followed by washing with water.

The amount of the first catalyst deposited in step 2 is preferably 0.5 to 50 mg/m ² , more preferably 1 to 30 mg/m ² from the viewpoint of moderately progressing the deposition of the second catalyst in step 3. , more preferably 5 to 20 mg/m ² .

<Step 3: Adhesion of second catalyst>
In step 3, an electroless nickel plating solution containing hypophosphite as a reducing agent is brought into contact with the first catalyst-adhering treated surface (S3) to adhere a second catalyst containing at least nickel. It is a step of forming a second catalyst-adhering treated surface (S4).

FIG. 3 shows a step of depositing the second catalyst on the first catalyst adhesion treated surface S3 to form the second catalyst adhesion treated surface S4.
In FIG. 3, for the sake of convenience, the second catalyst adhesion treated surface S4 is shown like a layer, but the second catalyst does not have to be formed in a layer. It is scattered on the processing surface S3. When the second catalyst is scattered, the second catalyst adhesion treated surface S4 does not refer only to the portion where the second catalyst is adhered, but the surface treated to adhere the second catalyst. It means the whole, and also includes a portion to which the second catalyst is not attached.

The second catalyst contains mainly nickel, but may contain phosphorus derived from the reducing agent. In that case, it can be said that this step is carrying out electroless nickel phosphorous plating. However, in this specification, the step of attaching the second catalyst may be referred to as "electroless nickel plating" for convenience.

From the viewpoint of facilitating etching, the phosphorus content in the second catalyst is preferably as low as possible, preferably 6% by mass or less, more preferably 4% by mass or less, and even more preferably 3% by mass or less. On the other hand, from the viewpoint of ease of production, the phosphorus content in the second catalyst may be 1% by mass or more.

The electroless nickel plating solution includes a nickel supply source such as nickel sulfate, a hypophosphite as a reducing agent, a pH adjuster such as sodium hydroxide, a complexing agent such as an organic acid salt, an organic acid, and an inorganic acid. accelerators such as sulfide; stabilizers; surfactants and the like.
The nickel concentration in the electroless nickel plating solution is, for example, 0.01-1.0 g/L.
Sodium hypophosphite is preferred as the hypophosphite that is the reducing agent. The hypophosphite concentration in the electroless nickel plating solution is, for example, 0.1-0.5 mol/L.
A citrate is preferable as the organic acid salt which is a complexing agent. The concentration of the complexing agent in the electroless nickel plating solution is, for example, 0.01-0.1 mol/L.
Boric acid is preferred as the organic acid that is a pH buffer. The concentration of the pH buffer in the electroless nickel plating solution is, for example, 0.1-1.0 mol/L.
A commercially available plating solution can also be used as the electroless nickel plating solution using hypophosphite as a reducing agent.

The temperature at which the first catalyst adhesion treated surface S3 is brought into contact with the electroless nickel plating solution is preferably 20 to 50.degree. C., more preferably 25 to 45.degree. C., still more preferably 30 to 40.degree. When the contact temperature is within the above range, the attached second catalyst has a low phosphorus content and can be easily removed by etching.
The time for which the first catalyst adhesion treated surface S3 is brought into contact with the electroless nickel plating solution may be, for example, 5 to 20 minutes, or may be 10 to 15 minutes.

The pH of the electroless nickel plating solution is preferably 7-10, more preferably 7.5-9.5, still more preferably 8-9. When the pH of the electroless nickel plating solution is within the above range, the adhered second catalyst has a low phosphorus content and can be easily removed by etching.

The adhesion amount of the second catalyst in step 3 is preferably 10 to 300 mg/m ² , more preferably 20 to 200 mg/m ² , still more preferably from the viewpoint of appropriately adjusting the thickness of the seed layer in step 4. is 50-150 mg/m ² .

<Step 4: Formation of seed layer>
In step 4, the second catalyst adhesion treated surface (S4) is brought into contact with an electroless copper plating solution using hypophosphite as a reducing agent, and the second catalyst adhesion treated surface (S4) is It is a step of forming a seed layer thereon.

FIG. 4 shows the step of forming the seed layer 5 on the second catalyst adhesion treated surface S4.

The electroless copper plating solution to be brought into contact with the second catalyst adhesion treated surface S4 includes a copper source such as copper sulfate, hypophosphite as a reducing agent, and a pH adjuster such as sodium hydroxide; complexing agents such as; pH buffers such as organic acids and inorganic acids; accelerators such as metal salts and sulfides; stabilizers;
The copper concentration in the electroless copper plating solution is, for example, 0.5-0.7 g/L.
Sodium hypophosphite is preferred as the hypophosphite that is the reducing agent.
The hypophosphite concentration in the electroless copper plating solution is, for example, 0.1-0.5 mol/L.
A citrate is preferable as the organic acid salt which is a complexing agent. The concentration of the complexing agent in the electroless copper plating solution is, for example, 0.01-0.1 mol/L.
Boric acid is preferred as the organic acid that is a pH buffer. The concentration of the pH buffer in the electroless copper plating solution is, for example, 0.1-1.0 mol/L.
Metal salts that are promoters include, for example, nickel sulfate.
A commercially available plating solution can also be used as the electroless copper plating solution using hypophosphite as a reducing agent.

The temperature at which the second catalyst adhesion treated surface S4 is brought into contact with the electroless copper plating solution may be, for example, 30 to 80.degree. C. or may be 60 to 70.degree.
The time for contacting the second catalyst adhesion treated surface S4 with the electroless copper plating solution may be, for example, 5 to 20 minutes, or may be 10 to 15 minutes.
The pH of the electroless copper plating solution is preferably 7-10, more preferably 7.5-9.5, still more preferably 8-9.

The thickness of the seed layer 5 is preferably 0.4 μm or less, more preferably 0.35 μm or less, and even more preferably 0.3 μm or less, from the viewpoint of forming a circuit pattern with excellent fine wiring properties and insulation reliability. . Moreover, the thickness of the seed layer 5 may be 0.1 μm or more, or may be 0.12 μm or more, from the viewpoint of sufficiently exhibiting the function as a seed layer.
In this specification, the thickness of the seed layer means that a cross section of the seed layer is formed by a focused ion beam (FIB), and the cross section is measured with a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees. Mean observed and measured seed layer thickness (n=10).

After the seed layer 5 is formed, washing with water or an organic solvent, drying by heating, or the like may be performed as necessary in order to remove excess plating solution.

<Step 5: Formation of copper layer>
Step 5 is a step of performing electrolytic copper plating on the surface of the seed layer to form a copper layer on the seed layer.

FIG. 5 shows a step of forming a copper layer 6 on the seed layer 5 by electrolytic copper plating.

As the electrolytic copper plating solution used for the electrolytic copper plating treatment, a commercially available electrolytic copper plating solution such as an electrolytic copper plating solution containing copper sulfate can be used.

<Step 6: Removal of seed layer and catalyst>
Step 6 is formed in the insulating material pattern non-forming portion by removing the copper layer, the seed layer, the first catalyst and the second catalyst adhering to the upper surface of the insulating material pattern. It is a step of obtaining a circuit pattern with a uniform shape.

In FIG. 6, the seed layer 5 and the copper layer 6 formed on the upper surface of the insulating material pattern 3 and the first catalyst and the second catalyst adhering to the upper surface of the insulating material pattern 3 are removed, and the circuit pattern 7 is formed. is shown.

The copper layer 6, the seed layer 5, the first catalyst and the second catalyst are preferably removed by chemical etching.
As the remover for removing the copper layer 6 and the seed layer 5, for example, acid etching such as sulfuric acid-hydrogen peroxide solution etching solution, nitric acid-hydrogen peroxide solution etching solution, ferric chloride-hydrochloric acid etching solution, etc. A liquid can be used.
As the removal liquid for removing the first catalyst and the second catalyst, for example, an acid etching liquid such as a nitric acid-hydrogen peroxide solution etching liquid, a ferric chloride-hydrochloric acid etching liquid, or the like can be used. Alternatively, a commercially available etchant can be used as long as it can remove the first catalyst and the second catalyst.
The seed layer 5, the first catalyst, and the second catalyst can be simultaneously removed using an acidic etchant such as a nitric acid-hydrogen peroxide solution etchant or a ferric chloride-hydrochloric acid etchant. .
The method for removing the copper layer 6, the seed layer 5, the first catalyst, and the second catalyst is not limited to the above method, and may be removed by mechanical polishing or CMP (Chemical Mechanical Planarization), for example.
Through the above steps, the circuit pattern 7 is formed in the portion which was the insulating material pattern non-formation portion 4 .

<Step 7: Multilayering step>
Preferably, the manufacturing method of the present embodiment further includes step 7 below.
Step 7: Laminating an insulating resin material on the insulating material pattern and circuit pattern

FIG. 7 shows a step of laminating an insulating resin material 8 on the circuit pattern 7 and the insulating material pattern 3 formed in steps 1-6.

The insulating resin material 8 may be the photosensitive resin composition used in forming the photosensitive resin layer 2 in step 1, or may be different.
Before laminating the insulating resin material 8, the circuit pattern 7 and the insulating material pattern 3 may be subjected to surface roughening treatment such as the above-described CZ treatment.

The printed wiring board manufacturing method of the present embodiment may be multilayered by repeating the above steps. Thereby, a multilayer printed wiring board can be manufactured.

[Semiconductor package manufacturing method]
The semiconductor package manufacturing method of the present embodiment is a method of manufacturing a semiconductor package in which a printed wiring board is manufactured by the printed wiring board manufacturing method of the present embodiment, and a semiconductor element is mounted on the printed wiring board.
The manufacturing method of the semiconductor package of this embodiment is, for example, a method of mounting a semiconductor element such as a semiconductor chip or a memory at a predetermined position on the printed wiring board of this embodiment, and sealing the semiconductor element with a sealing resin or the like. be.

Next, the present embodiment will be described in more detail by the following examples, but these examples are not intended to limit the present embodiment. Each step will be described below with reference to FIGS.

Example 1
(Step 1: Formation of insulating material pattern)
As the substrate 1, a composite substrate containing a glass cloth and a cured product of a thermosetting resin (manufactured by Showa Denko Materials Co., Ltd., trade name “GEA-770G(R)”, thickness 30 μm) was prepared.
As shown in FIG. 1(a), a photosensitive resin film for forming an insulating layer (manufactured by Showa Denko Materials Co., Ltd., trade name “PV-F008”, thickness 25 μm) is exposed on the surface S1 of the substrate 1. The flexible resin film was arranged so as to be the surface in contact with the composite material. Subsequently, lamination was performed by normal pressure lamination under the conditions of a roll pressure of 0.4 MPa, a processing temperature of 120° C., and a transport speed of 1.0 m/s to form a photosensitive resin layer 2 on the surface S1 of the substrate 1 .

Next, the formed photosensitive resin layer 2 is subjected to a pattern of L/S = 15 μm/15 μm under conditions of 55 mJ/cm ² using a direct exposure machine “DE-1UH” (manufactured by Via Mechanics Co., Ltd., product number). exposed with Subsequently, using a developing solution of sodium carbonate having a concentration of 1%, treatment was performed at a spray pressure of 0.17 MPa and 30° C. for 50 seconds, and development was performed by removing residues by oxygen plasma ashing treatment.
Then, the photosensitive resin layer after development was heated at 170° C. for 60 minutes. Then, as a desmear treatment, it was immersed in "Swelling Dip Securigant P" (manufactured by Atotech Japan Co., Ltd., trade name) at 70°C for 5 minutes, washed with hot water for 1 minute, and then washed with water for 3 minutes. Next, it was immersed in "Concentrate Compact CP" (manufactured by Atotech Japan Co., Ltd., trade name) at 70°C for 5 minutes, washed with hot water for 2 minutes, and then washed with water for 3 minutes. Subsequently, as a neutralization treatment step, after being immersed in "Reduction Solution Securigant P500" (manufactured by Atotech Japan Co., Ltd., trade name) at 40 ° C. for 5 minutes and then washed with water for 3 minutes, it is shown in FIG. Thus, the insulating material pattern 3 and the insulating material pattern non-formed portion 4 were formed on the surface S1 of the substrate 1. As shown in FIG.

(Step 2: Adhesion of first catalyst)
Next, as shown in FIGS. 2A and 2B, the surface composed of the surface Sα of the insulating material pattern 3 and the portion Sβ of the surface S1 exposed in the insulating material pattern non-formed portion 4 A first catalyst was deposited on S2 to form a first catalyst deposited surface S3. In addition, the process 2 was performed in the following procedures.
First, the substrate 1 on which the insulating material pattern 3 is formed is immersed in "Cleaner Securigant 902" (manufactured by Atotech Japan Co., Ltd., trade name) for 5 minutes at 60° C., followed by hot water washing for 1 minute. It was washed with water for 3 minutes.
Next, as a neutralization treatment step, it was immersed in a 5% sulfuric acid solution at 30° C. for 0.5 minutes and then washed with water for 1 minute. Subsequently, as a treatment step using an electroless plating catalyst, the sample was immersed in a mixed solution of 20 ml/L of "Predip Neogant B" (manufactured by Atotech Japan Co., Ltd., trade name) and 1 ml/L of 98% sulfuric acid at 30°C for 1 minute. Then, after immersion in a mixture of 40 ml/L of "Activator Neogant 834" (manufactured by Atotech Japan Co., Ltd., trade name), 5 g/L of boric acid aqueous solution, and 4 g/L of sodium hydroxide aqueous solution at 40° C. for 5 minutes, It was washed with water for 1 minute. After that, in the reduction treatment step, it was immersed in a mixture of 5 ml/L of "Reducer Neogant WA" (manufactured by Atotech Japan Co., Ltd., trade name) and 5 g/L of boric acid at 30°C for 5 minutes, and then washed with water for 0.5 minutes. .
The amount of the first catalyst deposited in step 2 was 10 mg/m ² .

(Step 3: Adhesion of second catalyst)
Next, as shown in FIG. 3, an electroless nickel plating solution using hypophosphite as a reducing agent is brought into contact with the first catalyst adhesion treated surface S3 to form a second nickel plating solution containing at least nickel. A second catalyst adhering treatment surface S4 was formed on which the catalyst was adhered. In addition, the process 3 was performed in the following procedures.
First, as an electroless nickel plating solution using sodium hypophosphite as a reducing agent, nickel sulfate hexahydrate 0.2 g / L, sodium hypophosphite monohydrate 30.0 g / L, citric acid An aqueous solution of trisodium 25 g/L and boric acid 30 g/L was prepared. The pH of the electroless nickel plating solution was adjusted to 9 with sodium hydroxide.
The substrate 1 to which the first catalyst is attached in step 2 is immersed in the electroless nickel plating solution at 35° C. for 10 minutes to attach the second catalyst to the substrate 1 to which the first catalyst is attached. rice field.
The amount of second catalyst deposited in step 3 was 100 mg/m ² .

(Step 4: Formation of seed layer)
Next, as shown in FIG. 4, an electroless copper plating solution containing hypophosphite as a reducing agent is brought into contact with the second catalyst adhesion treated surface S4 to obtain the second catalyst adhesion treated surface S4. A seed layer 5 was formed on S4. In addition, the process 4 was performed in the following procedures.
First, as an electroless copper plating solution using sodium hypophosphite as a reducing agent, copper sulfate pentahydrate 2.4 g / L, sodium hypophosphite monohydrate 30.0 g / L, citric acid An aqueous solution of trisodium 25 g/L and boric acid 30 g/L was prepared. The pH of the electroless copper plating solution was adjusted to 9 with sodium hydroxide.
The substrate 1 to which the second catalyst is attached in step 3 is immersed in the electroless copper plating solution prepared above at 65° C., electroless copper plating is performed, followed by washing with water and drying, followed by the second plating. A seed layer 5 (thickness: 0.30 μm) was formed on the catalyst adhesion-treated surface S4.

(Step 5: Formation of copper layer)
Next, as shown in FIG. 5, a copper layer 6 was formed on the seed layer 5 by electrolytic copper plating. In addition, the process 5 was performed in the following procedures.
The substrate 1 on which the seed layer 5 was formed in step 4 was immersed in a 5% sulfuric acid solution at 30° C. for 10 seconds. Next, electrolytic copper plating solution (copper sulfate pentahydrate 200 g/L, 98% sulfuric acid 50 g/L, chloride ion 40 mg/L, "Cu-Brite VF-IIA" (manufactured by JCU Co., Ltd., trade name) 20 ml/ L, "Cu-Brite VF-IIB" (manufactured by JCU Co., Ltd., trade name) 1 ml / L), electrolytic copper plating treatment was performed at 23 ° C. and 1.0 A / dm ² to form a copper layer 6 (thickness 10 μm).

(Step 6: Removal of seed layer and catalyst)
Next, as shown in FIG. 6, the seed layer 5 and the copper layer 6 formed on the upper surface of the insulating material pattern 3 and the first catalyst and the second catalyst adhering to the upper surface of the insulating material pattern 3 are removed. Then, a circuit pattern 7 was formed. In addition, the process 6 was performed in the following procedures.
Sulfuric acid-hydrogen peroxide solution etching solution (98% sulfuric acid 100 ml/L, DL-malic acid 100 g/L, hydrogen peroxide solution 30 ml/L, 1,2 , 3-benzotriazole (1 g/L)) at 30° C. and a spray pressure of 0.14 MPa to remove the copper layer 6 and the seed layer 5 .
Next, using a nitric acid-hydrogen peroxide solution etching solution (nitric acid 100 ml/L, DL-malic acid 100 g/L, hydrogen peroxide solution 10 ml/L, 1,2,3-benzotriazole 1 g/L), C. and a spray pressure of 0.14 MPa, the first catalyst and the second catalyst were removed. Thus, the circuit pattern 7 was formed in the insulating material pattern non-formation portion 4 .

Comparative example 1
A circuit pattern was formed in the same procedure as in Example 1, except that Step 3 was not performed.

[Evaluation of Peeling Strength of Copper Layer]
In Example 1, Steps 2 to 5 were performed without forming an insulating material pattern on the substrate 1, and a test piece 1 was obtained by forming a copper layer (20 μm thick) on the substrate 1.
In addition, in Comparative Example 1, Steps 2, 4 and 5 were carried out without forming an insulating material pattern on the substrate 1, and a copper layer (20 μm thick) was formed on the substrate 1. 2.
The copper layers of the test pieces 1 and 2 were etched into straight lines with a width of 5 mm, and the straight line-shaped copper foils were attached to Autograph AC-100C (manufactured by Shimadzu Corporation, product number). Next, the copper layer peeling strength was measured by peeling off the straight line-shaped copper layer in the direction of 90° at a peeling speed of 50 mm/min.
As a result, the copper layer peel strength of test piece 1 was 0.55 kN/m, and the copper layer peel strength of test piece 2 was 0.10 kN/m. Therefore, in the method for manufacturing a printed wiring board of the present embodiment, by performing the step of attaching the second catalyst, even when the substrate is a composite material containing glass cloth and a cured product of a thermosetting resin, , a high adhesion to the copper layer can be obtained.

1 substrate 2 photosensitive resin layer 3 insulating material pattern 4 insulating material pattern non-formed portion 5 seed layer 6 copper layer 7 circuit pattern 8 insulating resin material S1 surface Sα of substrate 1 surface Sβ of insulating material pattern 3 non-insulating material pattern formed portion Part S2 of surface S1 exposed at 4 Surface S3 composed of Sα and Sβ First catalyst adhesion treated surface S4 Second catalyst adhesion treated surface

Claims (6)

A method for manufacturing a printed wiring board including the following steps 1 to 6 in this order.
Step 1: The surface of a substrate selected from a composite material containing a glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesion-assisting layer formed by forming an adhesion-assisting layer on the surface of the composite material ( S1) a step of providing an insulating material pattern and an insulating material pattern non-formation portion, which is a space corresponding to a gap between the insulating material patterns and exposes the surface (S1), on S1) Step 2: The insulating material pattern and a portion of the surface (S1) exposed in the insulating material pattern non-formed portion, by depositing a first catalyst on the surface (S2) to obtain a first catalyst adhesion treated surface step of forming (S3) Step 3: The first catalyst-adhering treated surface (S3) is brought into contact with an electroless nickel plating solution containing hypophosphite as a reducing agent, so as to contain at least nickel. Step of forming a second catalyst adhesion treated surface (S4) to which a second catalyst is adhered Step 4: Using hypophosphite as a reducing agent for the second catalyst adhesion treated surface (S4) A step of forming a seed layer on the second catalyst adhesion treated surface (S4) by contacting an electroless copper plating solution Step 5: Electrolytic copper plating is performed on the surface of the seed layer, and forming a copper layer; Step 6: removing the copper layer, the seed layer, the first catalyst and the second catalyst adhering to the upper surface of the insulating material pattern, thereby removing the insulating material pattern; A step of obtaining a circuit pattern formed on the forming part 2. The method for manufacturing a printed wiring board according to claim 1, further comprising step 7 below.
Step 7: Laminating an insulating resin material on the insulating material pattern and circuit pattern 3. The method for producing a printed wiring board according to claim 1, wherein the electroless nickel plating solution has a pH of 7-10. The method for producing a printed wiring board according to any one of claims 1 to 3, wherein the phosphorus content in the second catalyst is 6% by mass or less. 5. The method for producing a printed wiring board according to claim 1, wherein the seed layer has a thickness of 0.4 μm or less. A method for manufacturing a semiconductor package, comprising: manufacturing a printed wiring board by the method for manufacturing a printed wiring board according to any one of claims 1 to 5; and mounting a semiconductor element on the printed wiring board.

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