JP2023009782A - Semiconductor light emitting element and method for manufacturing semiconductor emitting light element - Google Patents

Abstract

To provide a semiconductor light emitting element and a method for manufacturing a semiconductor light emitting element capable of increasing light out-coupling in the main or back surface direction even in a semiconductor light emitting element having a columnar semiconductor layer.SOLUTION: A semiconductor light emitting element (10) has a growth substrate (11), a plurality of columnar semiconductor layers (14-16) formed on the growth substrate (11), and an embedding layer (18) formed over the columnar semiconductor layers (14-16), and a side reflection portion (17) is formed on a side of the columnar semiconductor layers (14-16), which reflects at least part of light from the columnar semiconductor layers (14-16).SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device, and more particularly to a semiconductor light-emitting device having a structure in which a plurality of columnar semiconductor layers are embedded with a buried layer, and a method for manufacturing the semiconductor light-emitting device.

In recent years, crystal growth methods for nitride-based semiconductors have progressed rapidly, and blue and green light-emitting devices with high brightness using this material have been put to practical use. By combining conventional red light-emitting elements with these blue light-emitting elements and green light-emitting elements, all the three primary colors of light are obtained, and a full-color display device can be realized. That is, by mixing all the three primary colors of light, it becomes possible to obtain white light, which can be applied to illumination devices.

A semiconductor light-emitting device used as a light source for lighting is desirably capable of achieving high energy conversion efficiency and high light output in a high current density region, and is desirably stable in light distribution characteristics of emitted light. In order to solve these problems, in Patent Document 1, an n-type nanowire core, an active layer and a p-type layer are grown on a growth substrate, a tunnel junction layer is formed on the side surface of the p-type layer, and an n-type buried Embedded layer semiconductor light emitting devices have been proposed.

8A and 8B are schematic diagrams showing a conventionally proposed semiconductor light emitting device having a columnar semiconductor layer. FIG. 8A is a schematic cross-sectional view, and FIG. 8B is a schematic diagram showing the light extraction direction. It is a perspective view. As shown in FIG. 8A, the semiconductor light emitting device includes a growth substrate 1, an underlying layer 2, a mask 3, a nanowire layer 4, an active layer 5, a p-type layer 6, and a buried layer 7. , a cathode electrode 8n and an anode electrode 8p. Here, the nanowire layer 4, the active layer 5, and the p-type layer 6 are formed upright at a predetermined angle with respect to the main surface of the growth substrate 1, and constitute columnar semiconductor layers of a double heterostructure. .

In such a semiconductor light emitting device, when a voltage is applied between the anode electrode 8p and the cathode electrode 8n, holes are injected from the embedded layer 7 into the p-type layer 6, and electrons are injected from the underlying layer 2 into the nanowire layer 4. is injected, and light of a predetermined wavelength is emitted by radiative recombination in the active layer 5 . In such a semiconductor light emitting device, crystal defects and threading dislocations occurring in each semiconductor layer are less than those in which an active layer is formed on the entire surface of the growth substrate 1, and a high-quality crystal can be obtained. In addition, since the active layer has the m-plane, which is a non-polar plane along the side surface of the columnar semiconductor layer, as a facet, it is possible to improve the external quantum efficiency at a high current density.

JP 2020-077817 A

However, in such conventional technology, the active layer 5 is formed along the side surface of the columnar semiconductor layer, and the double heterostructure is also formed along the side surface. As shown in b), there is a stronger tendency to extract in the in-plane direction than in the main surface direction. Such extraction of light in the in-plane direction is not preferable for a surface emitting semiconductor light emitting device. In addition, the light emitted from each columnar semiconductor layer may be absorbed by other columnar semiconductor layers while traveling in the plane, making it difficult to improve the external quantum efficiency.

Therefore, the present invention has been devised in view of the above-described conventional problems, and is a semiconductor light-emitting device capable of increasing the amount of light extraction in the direction of the main surface or the direction of the back surface even in a semiconductor light-emitting device having a columnar semiconductor layer. It is an object of the present invention to provide a light-emitting device and a method for manufacturing a semiconductor light-emitting device.

In order to solve the above problems, a semiconductor light emitting device of the present invention includes a growth substrate, a plurality of columnar semiconductor layers formed on the growth substrate, and a buried layer formed covering the columnar semiconductor layers. A side reflecting portion is formed on a side surface of the columnar semiconductor layer to reflect at least part of the light from the columnar semiconductor layer.

In such a semiconductor light emitting device of the present invention, since the side reflecting portions are formed on the side surfaces of the columnar semiconductor layers, part of the light emitted by the columnar semiconductor layers is reflected in the direction perpendicular to the growth substrate. , it is possible to increase the amount of light extracted in the direction of the main surface.

Further, in one aspect of the present invention, the side reflection portion is a light reflection film formed in contact with the side surface of the columnar semiconductor layer.

In one aspect of the present invention, the light reflecting film is made of a metal material containing any one of Al, Au, Ag, and Cr as a main component.

In one aspect of the present invention, the light reflecting film is made of a semiconductor material having a bandgap larger than the wavelength of the light, and has an optical thickness larger than the wavelength of the light.

In one aspect of the present invention, the light reflecting film is a dielectric multilayer film containing any _one of _HfO2 , _TiO2 , _Ta2O5 , _{Al2O3 , SiO2} and _MgF2 .

In one aspect of the present invention, the embedded layer is made of a material having a refractive index different from that of the columnar semiconductor layer, and the side surface of the columnar semiconductor layer is an inclined side surface that is inclined with respect to the main surface of the growth substrate. and the side reflection portion is formed by an interface between the inclined side surface and the buried layer.

Further, in one aspect of the present invention, the light reflectance of the side reflection portion is in the range of 30 to 90%.

In one aspect of the present invention, a top reflecting portion that reflects the light toward the growth substrate is formed on the surface of the buried layer opposite to the growth substrate.

In order to solve the above-mentioned problems, the method for manufacturing a semiconductor light emitting device according to the present invention includes a columnar semiconductor growth step of forming a plurality of columnar semiconductor layers on a growth substrate, and forming a side reflector on a side surface of the columnar semiconductor layer. and a buried layer forming step of forming a buried layer covering the columnar semiconductor layer.

In the present invention, it is possible to provide a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device that can increase the amount of light extracted in the direction of the main surface or the direction of the back surface even in a semiconductor light-emitting device having a columnar semiconductor layer. can.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor light-emitting device 10 which concerns on 1st Embodiment, Fig.1 (a) is a schematic cross section, FIG.1(b) is a partial enlarged sectional view which shows an enlarged columnar semiconductor layer. 4 is a graph showing the relationship between the number of DBR layers and reflectance. 3(a) is a mask formation step, FIG. 3(b) is a nanowire growth step, and FIG. 3(c) is a growth of an active layer 15 and a p-type layer 16. FIG. FIG. 3(d) shows the step of forming the side reflection portion. 4(e) shows a buried layer forming process, FIG. 4(f) shows a mesa forming process, and FIG. 4(g) shows an electrode forming process. FIG. 5 is a schematic cross-sectional view showing a semiconductor light emitting device 10 according to a second embodiment; It is a figure which shows the semiconductor light-emitting device 30 which concerns on 3rd Embodiment, Fig.6 (a) is a schematic cross section, FIG.6(b) is a partial enlarged sectional view which shows an enlarged columnar semiconductor layer. 7(a) is a mask forming step, FIG. 7(b) is a nanowire growing step, and FIG. 7(c) is an active layer 35 and a A step of growing the p-type layer 36, and FIG. 3(d) show a step of forming the side reflection portion. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 8 is a schematic diagram showing a conventionally proposed semiconductor light-emitting device having a columnar semiconductor layer, FIG. 8A being a schematic cross-sectional view, and FIG. 8B being a schematic perspective view showing a light extraction direction; be.

(First embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. 1A and 1B are diagrams showing a semiconductor light emitting device 10 according to this embodiment, FIG. 1A being a schematic cross-sectional view, and FIG. 1B being a partially enlarged cross-sectional view showing an enlarged columnar semiconductor layer. be.

As shown in FIG. 1, a semiconductor light emitting device 10 includes a growth substrate 11, an underlying layer 12, a mask 13, a nanowire layer 14, an active layer 15, a p-type layer 16, a side reflector 17, and a buried layer. It includes an embedded layer 18, a cathode electrode 19n, and an anode electrode 19p. Here, the nanowire layer 14, the active layer 15, and the p-type layer 16 are selectively grown in a direction perpendicular to the growth substrate 11 to form a columnar shape, and constitute a columnar semiconductor layer in the present invention. As shown in FIG. 1(b), the columnar semiconductor layer has a side surface perpendicular to the main surface of the growth substrate 11, and the active layer 15 along the side surface is sandwiched between the nanowire layer 14 and the p-type layer 16. It constitutes a double heterostructure.

As shown in FIG. 1, part of the semiconductor light emitting device 10 has a buried layer 18 removed from the surface to the base layer 12 to form a mesa groove (mesa structure), and the surface of the base layer 12 is exposed. A cathode electrode 19n is formed. An anode electrode 19p is formed on the buried layer 18. As shown in FIG. Here, the mesa structure refers to a structure in which a groove is formed through a plurality of semiconductor layers so as to surround a predetermined region, so that the laminated structure cross section of each semiconductor layer is exposed from the side surface.

The growth substrate 11 is a substantially flat member made of a material capable of crystal growth of a semiconductor material. When the semiconductor light-emitting device 10 is made of a nitride-based semiconductor, it is preferable to use a GaN substrate as the growth substrate 11. For laser oscillation, a c-plane GaN substrate is used because the cavity plane can be easily formed by cleavage. may Alternatively, a heterosubstrate such as a c-plane sapphire substrate or a Si substrate made of a material different from the semiconductor material grown as the growth substrate 11 may be used.

The underlying layer 12 is a single crystal semiconductor layer formed on the growth substrate 11 . When the growth substrate 11 and the base layer 12 are made of different materials, it is preferable to grow a buffer layer on the surface of the growth substrate 11 and form the base layer 12 on the buffer layer. As the underlayer 12, for example, non-doped GaN is formed with a thickness of several μm, and a plurality of layers including an n-type semiconductor layer such as an n-type contact layer is formed thereon. The n-type contact layer is a semiconductor layer doped with an n-type impurity, such as Si-doped n-type Al _0.05 Ga _0.95 N. A mask 13 is formed on the main surface side of the underlying layer 12 . A part of the base layer 12 is exposed to form a cathode electrode 19n.

The buffer layer is a layer formed between the growth substrate 11 and the underlying layer 12 to alleviate the lattice mismatch between the two. When a c-plane sapphire substrate is used as the growth substrate 11, GaN is preferably used for the buffer layer, but AlN, AlGaN, or the like may be used. If the growth substrate 11 and the underlying layer 12 are made of the same material, the structure without the buffer layer may be adopted. When a single crystal substrate such as a GaN substrate is used as the growth substrate 11, the cathode electrode 19n may be formed on the surface of the growth substrate without providing the buffer layer and the underlying layer 12. FIG.

Mask 13 is a layer made of a dielectric material formed on the surface of underlying layer 12 . As a material for forming the mask 13, a material that is difficult to grow a semiconductor crystal from is selected from the mask 13. For example, SiO ₂ , SiN _x and Al ₂ O ₃ are suitable. A plurality of openings 13a, which will be described later, are formed in the mask 13, and a semiconductor layer can grow from the surface of the underlying layer 12 partially exposed through the openings 13a.

The columnar semiconductor layer is a semiconductor layer crystal-grown in the opening 13 a provided in the mask 13 , and the substantially columnar semiconductor layer is formed vertically with respect to the main surface of the growth substrate 11 . Such a columnar semiconductor layer can be obtained by setting appropriate growth conditions according to the semiconductor material to be formed, and performing selective growth in which a specific crystal plane orientation is grown. In the example shown in FIG. 1, since a plurality of openings 13a are formed two-dimensionally and periodically in the mask 13, the columnar semiconductor layers are also formed two-dimensionally and periodically on the growth substrate 11. .

The nanowire layer 14 is a columnar semiconductor layer selectively grown on the underlying layer 12 exposed from the opening 13a of the mask 13, and is made of GaN doped with n-type impurities, for example. When GaN is used as the nanowire layer 14, the nanowire layer 14 selectively grown on the growth substrate 11 has a substantially hexagonal prism shape with six m-planes formed as facets. In FIG. 1, it seems that the nanowire layer 14 is grown only in the region where the opening 13a is formed. An enlarged hexagonal prism is formed. For example, when the opening 13a is formed as a circle with a diameter of about 150 nm, it is possible to form a hexagonal columnar nanowire layer 14 with a height of about 1 to 2 μm and a hexagonal base that is inscribed in a circle with a diameter of about 240 nm. can. When the underlying layer 12 and the nanowire layer 14 are made of GaN, it is preferable to use an n-type semiconductor layer having an electron concentration of about 10 ¹⁸ atoms/cm ⁻³ , for example.

In this embodiment, an example using GaN as the nanowire layer 14 is shown. GaInN may be used as the nanowire layer 14 for this purpose. Similarly, when shortening the wavelength of the semiconductor light emitting device 10, it is possible to use AlGaN as the nanowire layer 14, or to change the well layer and the barrier layer of the active layer 15 to AlGaN having different compositions. be.

The active layer 15 is a semiconductor layer grown on the outer circumference of the nanowire layer 14. For example, the active layer 15 is a multiple quantum well active layer in which a GaInN quantum well layer with a thickness of 3 to 10 nm and a GaN barrier layer with a thickness of 5 to 20 nm are stacked five times. layer. Although a multiple quantum well active layer is mentioned here, a single quantum well structure or a bulk active layer may be used. Since the active layer 15 is formed on the side and top surfaces of the nanowire layer 14, the area of the active layer 15 can be secured. The higher the ratio of In taken into the active layer, the longer the emission wavelength of the semiconductor light emitting device 10. By setting the In composition ratio to 0.10 or more, the emission wavelength can be 480 nm or more. Further, by setting the In composition ratio to 0.12 or more, the emission wavelength can be set to 500 nm or more. In addition, since the side surfaces of the nanowire layer 14 are m-planes, the active layer 15 formed on the side surfaces is also a non-polar plane having m-planes, thereby improving droop characteristics.

The p-type layer 16 is a semiconductor layer grown on the outer periphery of the active layer 15, and is made of GaN doped with p-type impurities, for example. As shown in FIG. 1, p-type layer 16 is formed to cover the side and top surfaces of active layer 15 . As a result, the nanowire layer 14, the active layer 15, and the p-type layer 16 constitute a double heterostructure, and carriers can be well confined in the active layer 15 to improve the probability of radiative recombination. Although FIG. 1 shows an example in which the p-type layer 16 is composed of a single layer, it may have a multi-layered structure covering the side surface of the active layer 15 .

As shown in FIG. 1, the nanowire layer 14, the active layer 15 and the p-type layer 16 are erected with respect to the main surface of the growth substrate 11 and constitute the columnar semiconductor layers of the present invention. Also, the active layer 15 and the p-type layer 16 are formed along the side surfaces of the columnar semiconductor layers.

The side reflecting portion 17 is a film-like member that is formed in contact with the outer periphery of the side surface of the p-type layer 16 and reflects at least part of the light emitted from the active layer 15 . The material that forms the side reflection portion 17 is not limited, and for example, a metal material, a semiconductor material, or a dielectric material can be used. As will be described later in detail, the side reflection portion 17 preferably has a reflectance of 30 to 90%, more preferably 40 to 75%, with respect to light emitted from the active layer 15. more preferred.

When a metal material is used for the side reflection portion 17, it is preferable to use a material that well reflects the wavelength of light emitted from the active layer 15. For example, any one of Al, Au, Ag, and Cr is used as the main component. can be used. Alternatively, an alloy or laminated structure of these materials may be used. When a metal material is used for the side reflecting portion 17, the film thickness is preferably in the range of 10 to 80 nm. By adjusting the thickness of the metal film within the above range, the above reflectance for light emitted from the active layer 15 can be obtained.

When a semiconductor material is used for the side reflector 17, it is preferable to use a semiconductor material having a bandgap larger than the wavelength of light emitted by the active layer 15 in order to suppress absorption of light emitted by the active layer 15. . Examples include compound semiconductor materials such as GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. When a semiconductor material is used as the side reflecting portion 17 , the film thickness of the side reflecting portion 17 needs to have an optical thickness greater than the wavelength of the light emitted from the active layer 15 . By setting the optical film thickness to be larger than the wavelength of light, the interface between the p-type layer 16 and the side surface reflecting portion 17 and the interface between the side surface reflecting portion 17 and the buried layer 18 are affected by the difference in refractive index. This is because it utilizes reflection and refraction.

When a dielectric material is used for the side reflector 17, it is preferable to configure a distributed Bragg reflector (DBR) with a dielectric multilayer film in which a plurality of types of materials with different refractive indices are alternately laminated. One example is a combination of any of _dielectric materials such as _HfO2 , _TiO2 , _Ta2O5 , _{Al2O3 , SiO2} , _MgF2 . When the side reflector 17 is composed of a dielectric or semiconductor multilayer film to form a DBR, the reflectance can be controlled by configuring each layer with a quarter wavelength and adjusting the number of layers.

FIG. 2 is a graph showing the relationship between the number of DBR layers and reflectance. The graph shown in FIG. 2 shows the relationship between the number of DBR layers and the reflectance in a GaN/Al _0.27 Ga _0.73 N multilayer film at a wavelength of 440 nm. It can be seen that the reflectance can be controlled in the range of 60 to 80% by adjusting the number of pairs of high refractive index layers. The reflectance can be increased by increasing the number of layers more than shown in FIG. is preferably in the range of

The embedding layer 18 is a layer that fills between the plurality of side reflection portions 17 and the top surface of the columnar semiconductor layer. Examples of materials forming the embedded layer 18 include semiconductor materials such as GaN and transparent electrodes such as ITO (Indium Tin Oxide). An anode electrode 19p is formed on part of the surface of the embedded layer 18 . Although FIG. 1 shows an example in which the embedded layer 18 is composed of a single layer, it may have a multi-layered structure as long as it embeds from the surface of the underlying layer 12 to the upper surface of the columnar semiconductor layer. When the embedded layer 18 is made of a semiconductor material, a p-type semiconductor layer or an n-type semiconductor layer may be used to include functions such as a tunnel junction layer, a contact layer, and a current diffusion layer.

The mesa groove is a groove formed through each semiconductor layer from the buried layer 18 to the base layer 12, and divides the light emitting region of the semiconductor light emitting device 10 to form a mesa structure. An element isolation groove is further formed in the mesa groove to separate the semiconductor light emitting elements 10 individually.

The cathode electrode 19n is an electrode formed in the region where the base layer 12 is exposed in the mesa groove, and is composed of a laminated structure of a metal material and a pad electrode that make ohmic contact with the exposed semiconductor layer. The anode electrode 19p is an electrode formed on a portion of the buried layer 18, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the buried layer 18 and a pad electrode. Also, although not shown in FIG. 1, a known structure such as covering the surface of the semiconductor light emitting device 10 with a passivation film may be applied as necessary. Alternatively, a transparent electrode may be formed by extending the anode electrode 19p over the entire buried layer 18. FIG.

3A and 3B are schematic diagrams showing a method for manufacturing the semiconductor light emitting device 10, in which FIG. 3A is a mask forming step, FIG. 3B is a nanowire growing step, and FIG. The step of growing the layer 16, and FIG. 3(d) show the step of forming the side reflectors. 4A and 4B are schematic diagrams showing a method of manufacturing the semiconductor light emitting device 10. FIG. 4E shows a buried layer forming process, FIG. 4F shows a mesa forming process, and FIG. 4G shows an electrode forming process. showing.

First, as shown in FIG. 3A, a growth substrate 11 having an underlying layer 12 made of n-type GaN is prepared. In the mask forming step, a mask 13 made of SiO ₂ is deposited on the underlying layer 12 by a sputtering method to a thickness of about 30 nm, and an opening 13a having a diameter of about 150 nm is formed. A fine pattern forming method such as nanoimprinting lithography can be used to form the openings 13a. When a heterogeneous substrate such as sapphire is used as the growth substrate 11, a buffer layer, a base layer 12 and an n-type semiconductor layer are formed on the sapphire substrate, and the surface of the n-type semiconductor layer is used as the surface of the growth substrate 11. good too. The growth conditions for the buffer layer are, for example, TMA (TriMethylAluminium), TMG (TriMethylGallium) and ammonia are used as material gases, the growth temperature is 1100° C., the V/III ratio is 1000, hydrogen is used as carrier gas and the pressure is 10 hPa. The growth conditions for the underlying layer and the n-type semiconductor layer are, for example, a growth temperature of 1050° C., a V/III ratio of 1000, and a pressure of 500 hPa using hydrogen as a carrier gas.

Next, in the nanowire growth step shown in FIG. 3B, a nanowire layer 14 made of GaN is grown on the underlying layer 12 exposed from the opening 13a by selective growth by MOCVD. The growth conditions for the nanowire layer 14 are, for example, TMG and ammonia as material gases, a growth temperature of 1050° C., a V/III ratio of 10, and a pressure of 100 hPa with hydrogen as a carrier gas.

Next, in the step of growing the active layer 15 and the p-type layer 16 shown in FIG. 3C, the active layer 15 and the p-type layer 16 are grown on the side and top surfaces of the nanowire layer 14 using the MOCVD method. The active layer 15 may have, for example, a multiple quantum well structure in which GaInN quantum well layers with a thickness of 5 nm and GaN barrier layers with a thickness of 10 nm are stacked five times. The step of growing nanowires in FIG. 3B and the step of growing the active layer 15 and the p-type layer 16 in FIG. 3C correspond to the columnar semiconductor layer growing step in the present invention.

The growth conditions for the active layer 15 are, for example, a growth temperature of 800° C., a V/III ratio of 3000, a pressure of 1000 hPa with nitrogen as a carrier gas, and TMG, TMI (Trimethylindium) and ammonia as source gases. Examples of the p-type layer 16 include p-type GaN made of GaN doped with p-type impurities. The growth conditions for the p-type layer 16 are, for example, a growth temperature of 950° C., a V/III ratio of 4000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, Cp ₂ Mg (biscyclopentadienylmagnesium) and ammonia as source gases.

Next, in the side reflector forming step shown in FIG. Here, when the side reflection portion 17 is made of a semiconductor material, the side reflection portion 17 can be grown on the side surface of the p-type layer 16 in the same reaction chamber following the growth of the p-type layer 16 . When a metal material or a dielectric material is used for the side reflection portion 17, after the p-type layer 16 is grown, the side reflection portion 17 is formed on the side surface of the p-type layer 16 using a sputtering method or a vapor deposition method. can be done. At this time, by arranging the growth substrate 11 so as to be inclined with respect to the supply direction of the film material, it is possible to deposit the metal material or the dielectric material with an appropriate thickness on the side surface of the p-type layer 16 . In addition, by forming a film with the growth substrate 11 tilted in multiple directions, it is possible to form a film of a metal material or a dielectric material on the entire side surface of the p-type layer 16 . Moreover, it is preferable to remove the metal material and the dielectric material adhering to the top of the columnar semiconductor layer by dry etching or the like.

Next, in a buried layer forming step shown in FIG. 4E, a buried layer 18 is formed between the side reflection portions 17 formed in the plurality of columnar semiconductor layers and to cover the upper surface of the p-type layer 16. do. When the buried layer 18 is composed of a p-type semiconductor layer, the growth conditions for the buried layer 18 are, for example, a growth temperature of 950° C., a V/III ratio of 1000, hydrogen as a carrier gas, and a pressure of 300 hPa. TMG, Cp ₂ Mg and ammonia can be used as raw material gases. When forming the embedded layer 18 with a transparent electrode such as ITO, a known method such as a sputtering method can be used.

As described above, the buried layer 18 must be grown on the mask 13 provided between the columnar semiconductor layers, and there is a possibility that voids will be formed under the columnar semiconductor layers when the buried layer 18 is grown. be. Therefore, it is preferable to grow the buried layer 18 using TMG, silane, and ammonia as material gases at a low temperature and a low V/III ratio that promote lateral growth of the m-plane in the initial stage. An example of a low temperature and low V/III ratio is a V/III ratio of 100 or less at 800° C. or less and a pressure of 200 hPa using hydrogen as a carrier gas. After the top of the mask 13 is completely buried under the columnar semiconductor layer by the lateral growth of the buried layer 18, the growth should be performed at a high temperature and a high V/III ratio to promote the vertical growth of the c-plane. is preferred. An example of a high temperature and high V/III ratio is a V/III ratio of 2000 or more at 1000° C. or more and a pressure of 500 hPa using hydrogen as a carrier gas.

Next, in the mesa formation step shown in FIG. 4(f), portions from the embedded layer 18 to the base layer 12 are selectively removed by dry etching to expose the upper surface of the base layer 12 to form a mesa groove. . By forming the mesa groove, the area surrounded by the mesa groove is defined as the light emitting area of the semiconductor light emitting device 10 .

Next, in the electrode forming step shown in FIG. 4G, a cathode electrode 19n is formed on the surface of the underlying layer 12 exposed in the mesa groove, and an anode electrode 19p is formed on the buried layer 18. Next, as shown in FIG. Further, if necessary, annealing after electrode formation, formation of a passivation film, and element division are performed to obtain the semiconductor light emitting element 10 .

In the semiconductor light emitting device 10 of the present embodiment, when a voltage is applied between the cathode electrode 19n and the anode electrode 19p, current flows through the embedded layer 18, the p-type layer 16, the active layer 15, the nanowire layer 14, and the underlying layer 12 in this order. Light is generated by flow and radiative recombination in the active layer 15 . Light emitted from the active layer 15 reaches the side reflectors 17 and is partially reflected. 10 is taken out in the direction of the main surface.

As described above, the side reflecting portions 17 preferably have a reflectance of 30 to 90%, more preferably 40 to 75%, with respect to the light emitted from the active layer 15. . If the reflectance is too high, the light emitted from the active layer 15 is repeatedly reflected inside the columnar semiconductor layer and absorbed at a high rate, making it difficult to increase the amount of light extracted to the outside. On the other hand, if the reflectance is too low, the amount of light extracted from the side surfaces of the semiconductor light emitting device 10 increases, making it difficult to improve the light extraction efficiency in the main surface direction.

Part of the light emitted from the active layer 15 in one columnar semiconductor layer is reflected by the side reflectors 17 formed on the side surface of the columnar semiconductor layer and travels upward. It passes through the reflecting portion 17 . The light transmitted through the side reflecting portion 17 propagates through the embedded layer 18, reaches another side reflecting portion 17 provided in another columnar semiconductor layer, and is partly reflected upward. Therefore, by setting the reflectance of the side reflecting portions 17 within the above range, the light emitted by one active layer 15 is reflected upward by the plurality of side reflecting portions 17, and the light emitted from the main surface of the entire semiconductor light emitting device 10 is reflected upward. It is possible to improve the amount of light extracted in the direction.

In addition, since the side surfaces of the nanowire layer 14 are m-planes formed by selective growth, the active layer 15 and the p-type layer 16 formed on the outer periphery are also in contact with each other on the m-planes. Since the m-plane is a nonpolar plane and does not cause polarization, the luminous efficiency in the active layer 15 is high, and since all the side surfaces of the hexagonal prism are m-planes, the luminous efficiency of the semiconductor light-emitting device 10 can be improved. Furthermore, since the film thickness of the active layer can be increased, the volume of the active layer 15 can be increased to about 3 to 10 times that of the conventional semiconductor light emitting device, reducing the injection carrier density and improving the efficiency droop. can be significantly reduced.

As described above, in the semiconductor light emitting device and the method for manufacturing the semiconductor light emitting device of the present embodiment, the side reflector 17 is formed in contact with the side surface of the columnar semiconductor layer composed of the nanowire layer 14, the active layer 15, and the p-type layer 16. As a result, part of the light emitted from the active layer 15 is reflected, making it possible to increase the amount of light extracted in the direction of the main surface.

In addition, since the reflectance of the side reflecting portions 17 with respect to the light emitted from the active layer 15 is in the range of 30 to 90%, the light emitted from one active layer 15 is reflected by the plurality of side reflecting portions. By being reflected by 17, the amount of light extracted in the main surface direction in the entire semiconductor light emitting device 10 can be improved.

(Second embodiment)
Next, a second embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 5 is a schematic cross-sectional view showing the semiconductor light emitting device 10 according to this embodiment. This embodiment differs from the first embodiment in that the semiconductor light emitting device 10 is flip-chip mounted. As shown in FIG. 5, the semiconductor light emitting device 10 includes a growth substrate 11, an underlying layer 12, a mask 13, a nanowire layer 14, an active layer 15, a p-type layer 16, a side reflector 17, and a buried layer. It has a layer 18 , a cathode electrode 19 n , an anode electrode 19 p , a mounting portion 20 , a top reflector portion 21 and solder 22 .

The mounting portion 20 is a member for mounting the semiconductor light emitting element 10 by flip-chip connection, and wiring patterns and lands for supplying current to the semiconductor light emitting element 10 are formed on the upper surface. A specific configuration of the mounting portion 20 is not limited, and a known submount, printed wiring board, or the like can be used. The material forming the mounting portion 20 is not limited, either, and ceramics, insulators, glass epoxy resins, composite substrates of metal and insulating film, or the like can be used.

The top reflector 21 is a film-like member that is provided on the surface of the buried layer 18 opposite to the growth substrate 11 and reflects light toward the growth substrate 11 . It is a film-like member that reflects light emitted from the active layer 15 toward the growth substrate 11 . The top reflecting portion 21 may be formed on the buried layer 18 of the semiconductor light emitting device 10 as long as it is formed between the buried layer 18 and the mounting portion 20 , and is formed on the surface of the mounting portion 20 . may be Although the material forming the upper surface reflecting portion 21 is not limited, metal materials such as Al, Au, Ag, and Cr can be used.

The solder 22 is a member for electrically connecting the cathode electrode 19 n to the wiring pattern on the mounting portion 20 . Although not shown in FIG. 5, solder 22 is also provided between the anode electrode 19p and the mounting portion 20, and the two are electrically connected.

In this embodiment, part of the light emitted from the active layer 15 is reflected by the side reflectors 17 and extracted from the back surface of the growth substrate 11 . Also, part of the light is reflected by the side reflecting portion 17 , travels toward the mounting portion 20 , and reaches the top reflecting portion 21 . The light reaching the top reflecting portion 21 is totally reflected by the top reflecting portion 21 and extracted to the outside from the back surface of the growth substrate 11 . In addition, the light transmitted through the side reflecting portion 17 propagates through the embedded layer 18, reaches another side reflecting portion 17 provided in another columnar semiconductor layer, and is reflected. 11 is taken out from the back side.

As described above, in the semiconductor light emitting device 10 of the present embodiment, the side reflecting portions 17 are formed in contact with the side surfaces of the columnar semiconductor layers composed of the nanowire layer 14, the active layer 15, and the p-type layer 16, and the buried layers are formed. Since the top reflecting portion 21 is formed on 18, the amount of light extracted from the back surface of the growth substrate 11 can be increased.

(Third Embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. The description of the content that overlaps with the first embodiment is omitted. 6A and 6B are diagrams showing a semiconductor light emitting device 30 according to this embodiment, FIG. 6A being a schematic cross-sectional view, and FIG. 6B being a partially enlarged cross-sectional view showing an enlarged columnar semiconductor layer. be.

As shown in FIG. 6, a semiconductor light emitting device 30 of this embodiment includes a growth substrate 31, an underlying layer 32, a mask 33, a nanowire layer 34, an active layer 35, a p-type layer 36, and a buried layer 37. , a cathode electrode 38 n , an anode electrode 38 p , a mounting portion 20 , an upper surface reflecting portion 21 , and solder 22 . As shown in FIG. 6B, the side surface of the p-type layer 36 has an inclined side surface that is inclined with respect to the main surface of the growth substrate 31 .

First, as shown in FIG. 7A, a growth substrate 31 having an underlying layer 32 formed thereon is prepared, and a mask 33 having an opening 33a is formed in a mask forming step. Next, as shown in FIG. 7(b), a nanowire layer 34 is formed in a nanowire growth step. Next, an active layer 35 and a p-type layer 36 are formed as shown in FIG. 7(c). Here, specific examples of the mask formation process, the nanowire growth process, and the formation process of the active layer 35 and the p-type layer 36 are the same as in the first embodiment.

Next, as shown in FIG. 7D, the growth of the p-type layer 36 is continued under growth conditions such that the side surfaces of the p-type layer 36 are inclined with respect to the main surface of the growth substrate 31. , the side reflector forming step is carried out. At this time, the condition for making the side surface of the p-type layer 36 to be an inclined side surface includes a condition where the growth temperature is lowered or the V/III ratio is lowered than the growth condition where the m-plane grows as a facet. As an example, if the growth conditions for the vertical m-plane p-type layer 36 in FIG. For example, the ratio is 2000, the V/III ratio is 4000 at a growth temperature of 900°C, and the V/III ratio is 3000 at a growth temperature of 900°C.

Here, as shown in FIGS. 7(c) and 7(d), an example is shown in which the growth conditions of the p-type layer 36 are changed in two steps. Sides are not formed. Therefore, the side surface of the p-type layer 36 may be grown as the inclined side surface in one step using the growth conditions for forming the above-described inclined side surface after the formation of the active layer 35 .

After the step of forming the side surface reflecting portion shown in FIG. A top reflecting portion 21 is formed thereon, a mesa forming process and an electrode forming process are performed, and element division is performed to obtain a semiconductor light emitting element 30 .

In the present embodiment, the interface between the inclined side surface of the p-type layer 36 and the buried layer 37 constitutes a side reflection portion, which has a spire shape whose diameter becomes smaller in the direction away from the growth substrate 31 . The embedded layer 37 is made of a material having a different refractive index from that of the p-type layer 36 of the columnar semiconductor layer. Therefore, part of the light emitted by the active layer 35 is reflected by the refractive index difference at the interface (side reflecting portion) between the p-type layer 36 and the buried layer 37 and is taken out from the rear surface of the growth substrate 31 . Also, part of the light travels toward the mounting portion 20 and reaches the top reflecting portion 21 . The light reaching the top reflecting portion 21 is totally reflected by the top reflecting portion 21 and extracted from the back surface of the growth substrate 31 to the outside.

Further, the light transmitted from the p-type layer 36 to the buried layer 37 propagates through the buried layer 37 and reaches the interface between the buried layer 37 and another p-type layer 36 provided in another columnar semiconductor layer. As a result, the light is similarly extracted from the rear surface of the growth substrate 31 by being reflected or refracted.

7A and 7B are schematic diagrams showing a method for manufacturing the semiconductor light emitting device 30 according to the present embodiment. FIG. 7A is a mask forming step, FIG. 7B is a nanowire growing step, and FIG. FIG. 7(d) shows the step of growing the layer 35 and the p-type layer 36, and the step of forming the side reflectors. The present embodiment is different from the first embodiment in that the side surfaces of the p-type layer 36 are inclined instead of the step of forming the side reflecting portions shown in FIG. 3(d).

As described above, in the semiconductor light emitting device 30 of this embodiment, the p-type layer 36 and the buried layer 37 are made of materials having different refractive indices, and the side surface of the p-type layer 36 is inclined with respect to the main surface of the growth substrate 31. It has sloped sides. As a result, the interface between the p-type layer 36 and the buried layer 37 forms a side reflection portion, and the light emitted from the active layer 35 is extracted from the rear surface of the growth substrate 31 by reflection and refraction due to the refractive index difference. Therefore, it is possible to increase the amount of light extracted from the back surface of the growth substrate 31 .

The present invention is not limited to the above-described embodiments, but can be modified in various ways within the scope of the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. is also included in the technical scope of the present invention.

Reference Signs List 10, 30 Semiconductor light-emitting elements 11, 31 Growth substrates 12, 32 Base layers 13, 33 Masks 13a, 33a Openings 14, 34 Nanowire layers 15, 35 Active layers 16, 36 P-type layer 17 Side surface reflection portions 18, 37 Buried layers 19n, 38n Cathode electrodes 19p, 38p Anode electrode 20 Mounting portion 21 Top surface reflection portion 22 Solder

Claims (9)

a growth substrate;
a plurality of columnar semiconductor layers formed on the growth substrate;
a buried layer formed to cover the columnar semiconductor layer;
A semiconductor light-emitting device according to claim 1, wherein side surfaces of said columnar semiconductor layers are formed with side reflecting portions for reflecting at least part of light from said columnar semiconductor layers. The semiconductor light emitting device according to claim 1,
The semiconductor light emitting device, wherein the side reflection portion is a light reflection film formed in contact with the side surface of the columnar semiconductor layer. The semiconductor light emitting device according to claim 2,
A semiconductor light emitting device, wherein the light reflecting film is made of a metal material containing any one of Al, Au, Ag and Cr as a main component. The semiconductor light emitting device according to claim 2,
The semiconductor light emitting device, wherein the light reflecting film is made of a semiconductor material having a bandgap larger than the wavelength of the light, and has an optical thickness larger than the wavelength of the light. The semiconductor light emitting device according to claim 2,
A semiconductor light emitting device, wherein the light reflecting film is a dielectric multilayer film containing any _one of _HfO2 , _TiO2 , _Ta2O5 , _{Al2O3 , SiO2} and _MgF2 . The semiconductor light emitting device according to claim 1,
The embedded layer is made of a material having a different refractive index from that of the columnar semiconductor layer,
a side surface of the columnar semiconductor layer has an inclined side surface that is inclined with respect to the main surface of the growth substrate;
The semiconductor light emitting device, wherein the side reflecting portion is formed by an interface between the inclined side surface and the buried layer. The semiconductor light emitting device according to any one of claims 1 to 6,
The semiconductor light emitting device, wherein the light reflectance of the side reflecting portion is in the range of 30 to 90%. The semiconductor light emitting device according to any one of claims 1 to 7,
A semiconductor light-emitting device according to claim 1, wherein an upper reflecting portion for reflecting the light toward the growth substrate is formed on a surface of the buried layer opposite to the growth substrate. a columnar semiconductor growth step of forming a plurality of columnar semiconductor layers on a growth substrate;
a side reflector forming step of forming a side reflector on a side surface of the columnar semiconductor layer;
and a buried layer forming step of forming a buried layer covering the columnar semiconductor layer.

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