CN117616591A - Semiconductor light emitting element and method for manufacturing semiconductor light emitting element - Google Patents

Abstract

The present invention relates to a semiconductor light emitting element (10), which comprises: the semiconductor device comprises a growth substrate (11), a plurality of columnar semiconductor layers (14-16) formed on the growth substrate (11), and a buried layer (18) formed to cover the columnar semiconductor layers (14-16), wherein a side surface reflection part (17) for reflecting at least a part of light from the columnar semiconductor layers (14-16) is formed on the side surface of the columnar semiconductor layers (14-16).

Description

Semiconductor light emitting element and method for manufacturing semiconductor light emitting element

Technical Field

The present disclosure relates to a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element, and more particularly, to a semiconductor light emitting element having a structure in which a plurality of columnar semiconductor layers are buried by a buried layer, and a method for manufacturing the semiconductor light emitting element.

Background

In recent years, a crystal growth method of a nitride semiconductor has been rapidly progressed, and a blue or green light emitting element having high luminance using the material has been put to practical use. By combining a red light-emitting element, a blue light-emitting element, and a green light-emitting element, which are conventionally present, all three primary colors of light are aligned, and a full-color display device can be realized. That is, if all three primary colors of light are mixed, white light can be obtained, and the present invention can be applied to an illumination device.

In a semiconductor light emitting element used as a light source for illumination, it is desired that high energy conversion efficiency and high light output can be achieved in a high current density region, and that the light distribution characteristics of emitted light be stable. In order to solve these problems, patent document 1 proposes a semiconductor light emitting element in which an n-type nanowire core, an active layer, and a p-type layer are grown on a growth substrate, a tunnel junction layer is formed on the side surface of the p-type layer, and the tunnel junction layer is buried in an n-type buried layer.

Fig. 11A and 11B are schematic views showing a conventionally proposed semiconductor light emitting element including a columnar semiconductor layer, fig. 11A is a schematic cross-sectional view, and fig. 11B is a schematic perspective view showing a light extraction direction. As shown in fig. 11A, the semiconductor light-emitting element includes a growth substrate 1, a underlayer 2, a mask 3, a nanowire layer 4, an active layer 5, a p-type layer 6, a buried layer 7, a cathode electrode 8n, and an anode electrode 8p. The nanowire layer 4, the active layer 5, and the p-type layer 6 are formed to stand at a predetermined angle with respect to the main surface of the growth substrate 1, and constitute a columnar semiconductor layer having a double hetero structure.

In such a semiconductor light-emitting element, when a voltage is applied between the anode electrode 8p and the cathode electrode 8n, holes are injected from the buried layer 7 into the p-type layer 6, electrons are injected from the underlayer 2 into the nanowire layer 4, and light of a predetermined wavelength is emitted by recombination of light emission in the active layer 5. In such a semiconductor light-emitting element, crystal defects and threading dislocations generated in each semiconductor layer are reduced as compared with the case where an active layer is formed over the entire surface of the growth substrate 1, and high-quality crystals are obtained. In addition, since the active layer has the m-plane as a nonpolar plane along the side surface of the columnar semiconductor layer as a facet, improvement of external quantum efficiency at a high current density can be achieved.

Prior art literature

Patent literature

Patent document 1: japanese patent application laid-open No. 2020-077817

Disclosure of Invention

Problems to be solved by the invention

However, in such a conventional technique, since the active layer 5 is formed along the side surface of the columnar semiconductor layer and the double heterostructure is also formed along the side surface, the light emitted from the active layer 5 tends to be extracted in the in-plane direction more strongly than in the main surface direction as shown in fig. 11B. Such light extraction in the in-plane direction is not preferable in the surface light emitting semiconductor light emitting element. In addition, light emitted from each columnar semiconductor layer may be absorbed by other columnar semiconductor layers during in-plane traveling, and there is a problem in that external quantum efficiency is difficult to improve.

Accordingly, the present disclosure has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor light-emitting element and a method for manufacturing the semiconductor light-emitting element, which can increase the amount of light extracted in the main surface direction or the back surface direction even in the semiconductor light-emitting element having a columnar semiconductor layer.

Technical scheme for solving problems

In order to solve the above-described problems, the present disclosure provides a semiconductor light-emitting element comprising: growing a substrate; a plurality of columnar semiconductor layers formed on the growth substrate; and a buried layer formed so as to cover the columnar semiconductor layer, wherein a side surface reflection portion that reflects at least a part of light from the columnar semiconductor layer is formed on a side surface of the columnar semiconductor layer.

In the semiconductor light emitting element of the present disclosure, since the side surface reflection portion is formed on the side surface of the columnar semiconductor layer, a part of light emitted from the columnar semiconductor layer is reflected in a direction perpendicular to the growth substrate, and the light extraction amount in the main surface direction can be increased.

In addition, in an aspect of the present disclosure, the side surface reflection portion is a light reflection film formed in contact with a side surface of the columnar semiconductor layer.

In addition, in an aspect of the present disclosure, the light reflection film is composed of a metal material having any one of Al, au, ag, cr as a main component.

In addition, in an aspect of the present disclosure, the light reflection film is composed of a semiconductor material having a band gap larger than a wavelength of the light, and an optical thickness larger than the wavelength of the light.

In addition, in one aspect of the disclosure, the light reflecting film is a film comprising HfO ₂ 、TiO ₂ 、Ta ₂ O ₅ 、Al ₂ O ₃ 、SiO ₂ 、MgF ₂ Any one of the dielectric multilayer films.

In addition, in an aspect of the present disclosure, the buried layer is made of a material having a refractive index different from that of the columnar semiconductor layer, a side surface of the columnar semiconductor layer has an inclined side surface inclined with respect to a main surface of the growth substrate, and the side surface reflecting portion is made of an interface between the inclined side surface and the buried layer.

In addition, in an aspect of the present disclosure, the reflectance of the light of the side reflection part is in a range of 30 to 90%.

In addition, in one aspect of the present disclosure, an upper surface reflection portion that reflects the light toward the growth substrate is formed on a surface of the buried layer opposite to the growth substrate.

In order to solve the above-described problems, the present disclosure provides a method for manufacturing a semiconductor light-emitting element, comprising: a columnar semiconductor growth step of forming a plurality of columnar semiconductor layers on a growth substrate, a side surface reflection portion formation step of forming a side surface reflection portion on a side surface of the columnar semiconductor layers, and a buried layer formation step of forming a buried layer so as to cover the columnar semiconductor layers.

In order to solve the above-described problems, the present disclosure provides a semiconductor light-emitting element comprising: growing a substrate; a plurality of columnar semiconductor layers formed on the growth substrate; a buried layer covering the columnar semiconductor layer, the columnar semiconductor layer including: a nanowire layer, an active layer at the periphery of the nanowire layer, and a p-type layer at the periphery of the active layer, the side surface of the active layer being inclined with respect to the main surface of the growth substrate.

In the semiconductor light emitting element of the present disclosure, since the side surface of the active layer is inclined with respect to the main surface of the growth substrate, light emitted from the active layer is extracted obliquely upward of the growth substrate, and the amount of extraction of light in the main surface direction can be increased.

In addition, in an aspect of the present disclosure, the nanowire layer has a side surface inclined with respect to the main surface, that is, an inclined side surface portion.

In addition, in an aspect of the present disclosure, a mask having an opening is provided on the growth substrate, the nanowire layer is selectively grown from the opening provided to the mask, and the inclined side portion is formed in a region partially covering the mask.

In addition, in an aspect of the present disclosure, the nanowire layer, the active layer, and the p-type layer are composed of a nitride semiconductor.

In order to solve the above-described problems, the present disclosure provides a method for manufacturing a semiconductor light-emitting element, comprising: a columnar semiconductor growth step of forming a plurality of columnar semiconductor layers on a growth substrate, and a buried layer formation step of forming a buried layer by covering the columnar semiconductor layers, the columnar semiconductor layer growth step including: a nanowire layer growth step of forming a nanowire layer having an inclined side surface portion which is an inclined side surface with respect to a main surface of the growth substrate, an active layer growth step of forming an active layer on an outer periphery of the inclined side surface portion, and a p-type layer growth step of forming a p-type layer on an outer periphery of the active layer.

In addition, in one aspect of the present disclosure, the nanowire layer growth process includes: a nanowire core growth step of forming a nanowire core having a side surface perpendicular to the main surface of the growth substrate, and an inclined side surface portion growth step of forming an inclined side surface portion on the outer periphery of the nanowire core.

In addition, in one aspect of the present disclosure, the inclined side surface portion growth step reduces the V/III ratio of the raw material compared to the nanowire core growth step.

In addition, in one aspect of the present disclosure, the inclined side portion growing step reduces a growth temperature compared to the nanowire core growing step.

[ Effect of the invention ]

In the present disclosure, a semiconductor light-emitting element and a method for manufacturing the semiconductor light-emitting element can be provided, in which the light extraction amount in the main surface direction or the back surface direction can be increased even in the semiconductor light-emitting element having a columnar semiconductor layer.

Drawings

Fig. 1A is a schematic cross-sectional view of a semiconductor light-emitting element 10 of the first embodiment.

Fig. 1B is a partially enlarged cross-sectional view showing an enlarged pillar-shaped semiconductor layer of the semiconductor light-emitting element 10.

Fig. 2 is a graph showing the relationship between the number of layers and the reflectivity of the DBR.

Fig. 3A is a schematic diagram showing a mask forming step of the method for manufacturing the semiconductor light emitting element 10.

Fig. 3B is a schematic diagram showing a nanowire growth step in the method for manufacturing the semiconductor light-emitting element 10.

Fig. 3C is a schematic diagram showing a growth process of the active layer 15 and the p-type layer 16 in the method of manufacturing the semiconductor light emitting element 10.

Fig. 3D is a schematic diagram showing a side reflection portion forming process of the method for manufacturing the semiconductor light emitting element 10.

Fig. 4E is a schematic diagram showing a buried layer forming process in the method for manufacturing the semiconductor light emitting element 10.

Fig. 4F is a schematic diagram showing a mesa formation step in the method of manufacturing the semiconductor light emitting element 10.

Fig. 4G is a schematic diagram showing an electrode forming process of the method for manufacturing the semiconductor light emitting element 10.

Fig. 5 is a schematic cross-sectional view showing a semiconductor light-emitting element 10 according to a second embodiment.

Fig. 6A is a schematic cross-sectional view showing a semiconductor light-emitting element 30 according to the third embodiment.

Fig. 6B is a partially enlarged cross-sectional view showing an enlarged view of a columnar semiconductor layer of the semiconductor light-emitting element 30 of the third embodiment.

Fig. 7A is a schematic diagram showing a mask forming step of the method for manufacturing the semiconductor light emitting element 30 according to the third embodiment.

Fig. 7B is a schematic diagram showing a nanowire growth step in the method for manufacturing the semiconductor light emitting element 30.

Fig. 7C is a schematic diagram showing a growth process of the active layer 35 and the p-type layer 36 in the method for manufacturing the semiconductor light-emitting element 30.

Fig. 7D is a schematic diagram showing a side reflection portion forming step of the method for manufacturing the semiconductor light emitting element 30.

Fig. 8A is a schematic cross-sectional view showing a semiconductor light-emitting element 110 of the fourth embodiment.

Fig. 8B is a partially enlarged cross-sectional view showing the columnar semiconductor layer of the semiconductor light-emitting element 110 in an enlarged manner.

Fig. 9A is a schematic diagram showing a mask forming step of the method for manufacturing the semiconductor light emitting element 110.

Fig. 9B is a schematic diagram showing a nanowire core growth step in the nanowire layer growth step of the manufacturing method of the semiconductor light emitting element 110.

Fig. 9C is a schematic diagram showing an inclined side surface portion growth step in the nanowire layer growth step in the manufacturing method of the semiconductor light emitting element 110.

Fig. 9D is a schematic diagram showing a growth process of the active layer 115 and the p-type layer 116 in the method of manufacturing the semiconductor light emitting element 110.

Fig. 10E is a schematic diagram showing a buried layer forming process in the method for manufacturing the semiconductor light emitting element 110.

Fig. 10F is a schematic diagram showing a mesa formation step in the method of manufacturing the semiconductor light emitting element 110.

Fig. 10G is a schematic diagram showing an electrode forming process of the method for manufacturing the semiconductor light emitting element 110.

Fig. 11A is a schematic cross-sectional view showing a semiconductor light-emitting element including a conventionally proposed columnar semiconductor layer.

Fig. 11B is a schematic perspective view showing a light extraction direction of a semiconductor light emitting element including a conventionally proposed columnar semiconductor layer.

Detailed Description

(first embodiment)

Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The same or equivalent constituent elements, components, and processes shown in the drawings are denoted by the same reference numerals, and repetitive description thereof will be omitted as appropriate. Fig. 1A is a schematic cross-sectional view showing a semiconductor light-emitting element 10 according to the present embodiment, and fig. 1B is a partially enlarged cross-sectional view showing a columnar semiconductor layer of the semiconductor light-emitting element 10 in an enlarged manner.

As shown in fig. 1A, the semiconductor light-emitting element 10 includes a growth substrate 11, a underlayer 12, a mask 13, a nanowire layer 14, an active layer 15, a p-type layer 16, a side surface reflection portion 17, a buried layer 18, a cathode electrode 19n, and an anode electrode 19p. Here, the nanowire layer 14, the active layer 15, and the p-type layer 16 are selectively grown in a pillar shape in a direction perpendicular to the growth substrate 11, constituting a pillar-shaped semiconductor layer in the present disclosure. As shown in fig. 1B, the columnar semiconductor layer has a side surface perpendicular to the main surface of the growth substrate 11, and the active layer 15 along the side surface constitutes a double heterostructure sandwiched by the nanowire layer 14 and the p-type layer 16.

As shown in fig. 1A, a part of the semiconductor light emitting element 10 is formed by removing the buried layer 18 from the surface to the base layer 12 to form a mesa groove (mesa structure), and the surface of the base layer 12 is exposed to form a cathode electrode 19n. An anode electrode 19p is formed on the buried layer 18. The mesa structure is a structure in which a groove penetrating a plurality of semiconductor layers is formed so as to surround a predetermined region, whereby a cross section of a stacked structure of the semiconductor layers is exposed from a side surface.

The growth substrate 11 is a substantially flat plate-like member made of a material capable of growing a semiconductor material crystal. In the case where the semiconductor light-emitting element 10 is made of a nitride semiconductor, a GaN substrate is preferably used as the growth substrate 11, and a c-plane GaN substrate in which a resonator plane is easily formed by cleavage can be used for laser oscillation. Further, a substrate using a different type such as a c-plane sapphire substrate or a Si substrate, which is made of a material different from the semiconductor material grown as the growth substrate 11, may be used.

The underlayer 12 is a single crystal semiconductor layer formed on the growth substrate 11. When the growth substrate 11 and the underlayer 12 are made of different materials, it is preferable to grow a buffer layer on the surface of the growth substrate 11 and form the underlayer 12 on the buffer layer. The underlayer 12 is formed of, for example, a plurality of layers in which undoped GaN is formed to a thickness of several μm and an n-type semiconductor layer such as an n-type contact layer is provided thereon. The n-type contact layer is a semiconductor layer doped with n-type impurities, and examples thereof include Si-doped n-type Al _0.05 Ga _0.95 N. A mask 13 is formed on the main surface side of the base layer 12. A part of the underlayer 12 is exposed to form a cathode electrode 19n.

The buffer layer is formed between the growth substrate 11 and the underlayer 12, and is a layer for relaxing lattice mismatch between the two layers. In the case of using a c-plane sapphire substrate as the growth substrate 11, gaN is preferably used as the buffer layer, but AlN, alGaN, or the like may be used. In the case where the growth substrate 11 and the underlayer 12 are made of the same material, the buffer layer may not be provided. In the case of using a single crystal substrate such as a GaN substrate as the growth substrate 11, the cathode electrode 19n may be formed on the surface of the growth substrate without providing the buffer layer and the underlayer 12.

Mask for maskReference numeral 13 denotes a layer made of a dielectric material formed on the surface of the base layer 12. As a material constituting the mask 13, a material which is difficult to grow crystals of the semiconductor from the mask 13 is selected, for example, siO is preferable ₂ 、SiNx、Al ₂ O ₃ Etc. A plurality of openings 13a, which will be described later, are formed in the mask 13, and a semiconductor layer can be grown from the surface of the base layer 12 partially exposed from the openings 13 a.

The columnar semiconductor layer is a semiconductor layer grown by crystallization on the opening 13a provided in the mask 13, and is formed by standing a substantially columnar semiconductor layer perpendicular to the main surface of the growth substrate 11. Such a columnar semiconductor layer is obtained by setting appropriate growth conditions according to the semiconductor material to be formed, and performing selective growth for specific crystal plane orientation growth. In the example shown in fig. 1A and 1B, since the plurality of openings 13a are formed periodically in two dimensions on the mask 13, the columnar semiconductor layer is also formed periodically in two dimensions on the growth substrate 11.

The nanowire layer 14 is a columnar semiconductor layer selectively grown on the underlayer 12 exposed from the opening 13A (see fig. 3A) of the mask 13, and is made of GaN doped with an n-type impurity, for example. When GaN is used as the nanowire layer 14, the nanowire layer 14 selectively grown on the growth substrate 11 is formed into a substantially hexagonal prism shape having six m-faces formed into facets. In fig. 1A and 1B, the nanowire layer 14 appears to grow only in the region where the opening 13a is formed, but in reality, since the lateral growth also progresses the crystal growth on the mask 13, a hexagonal prism is formed that expands around the opening 13 a. For example, when the opening 13a is formed as a circle having a diameter of about 150nm, a hexagonal prism-shaped nanowire layer 14 having a height of about 1 to 2 μm with a hexagonal shape inscribed in the circle having a diameter of about 240nm as a bottom surface can be formed. When the underlayer 12 and nanowire layer 14 are made of GaN, for example, the electron concentration is preferably 10 ¹⁸ atoms/cm ^－3 Left and right n-type semiconductor layers.

In the present embodiment, gaN is used as the nanowire layer 14, but GaInN may be used as the nanowire layer 14 In order to reduce misfit dislocation due to lattice mismatch when the In component of the active layer 15 is increased In order to lengthen the emission wavelength. Similarly, when the wavelength of the semiconductor light-emitting element 10 is shortened, alGaN may be used as the nanowire layer 14, or the well layer and the barrier layer of the active layer 15 may be changed to AlGaN having different compositions.

The active layer 15 is a semiconductor layer grown on the outer periphery of the nanowire layer 14, and examples thereof include a multi-quantum well active layer in which a GaInN quantum well layer having a thickness of 3 to 10nm and a GaN barrier layer having a thickness of 5 to 20nm are stacked for 5 cycles. The multiple quantum well active layer is exemplified here, but may have a single quantum well structure or may be a bulk active layer. Since the active layer 15 is formed on the side surface and the upper surface of the nanowire layer 14, the area of the active layer 15 can be ensured. The higher the ratio of In to be taken into the active layer, the longer the emission wavelength of the semiconductor light-emitting element 10, and the emission wavelength can be made 480nm or more by making the In composition ratio 0.10 or more. In addition, by setting the In component ratio to 0.12 or more, the emission wavelength can be set to 500nm or more. Since the side surface of the nanowire layer 14 is formed of an m-plane, the active layer 15 formed on the side surface is also a nonpolar plane having an m-plane, and thus the drop characteristic can be improved.

The p-type layer 16 is a semiconductor layer grown on the outer periphery of the active layer 15, and is made of GaN doped with p-type impurities, for example. As shown in fig. 1A and 1B, the p-type layer 16 is formed so as to cover the side surfaces and the upper surface of the active layer 15. Thus, the double heterostructure constituted by the nanowire layer 14, the active layer 15, and the p-type layer 16 can satisfactorily enclose carriers in the active layer 15, and the probability of recombination of light emission can be improved. Fig. 1A and 1B show examples in which p-type layer 16 is formed of a single layer, but a multilayer layer structure may be used to cover the side surface of active layer 15.

As shown in fig. 1A and 1B, the nanowire layer 14, the active layer 15, and the p-type layer 16 are provided upright with respect to the main surface of the growth substrate 11, and constitute a columnar semiconductor layer in the present disclosure. The active layer 15 and the p-type layer 16 are formed along the side surfaces of the columnar semiconductor layer.

The side surface reflection portion 17 is a film-like member (light reflection film) formed in contact with the side surface outer periphery of the p-type layer 16 and reflecting at least a part of the light emitted from the active layer 15. The material constituting the side reflection portion 17 is not limited, and for example, a metal material, a semiconductor material, or a dielectric material may be used. As described in detail later, the side surface reflection portion 17 preferably has a reflectance in the range of 30 to 90% and more preferably has a reflectance in the range of 40 to 75% with respect to the light emitted from the active layer 15.

When a metal material is used for the side surface reflecting portion 17, a material that favorably reflects the wavelength of light emitted from the active layer 15 is preferably used, and for example, a metal material containing any one of Al, au, ag, cr as a main component can be used. In addition, an alloy or a laminated structure of these materials may also be used. When a metal material is used for the side surface reflecting portion 17, the film thickness is preferably in the range of 10 to 80 nm. By adjusting the thickness of the metal film within the above range, the above-described reflectance with respect to the light emitted from the active layer 15 can be obtained.

In the case of using a semiconductor material as the side surface reflecting portion 17, in order to suppress absorption of light emitted from the active layer 15, it is preferable to use a semiconductor material having a band gap larger than the wavelength of light emitted from the active layer 15. As an example, a compound semiconductor material such as GaN, alN, inN, alGaN, inGaN, alInGaN is given. In the case of using a semiconductor material as the side reflection portion 17, the film thickness of the side reflection portion 17 must have an optical film thickness larger than the wavelength of light emitted from the active layer 15. This is because, by making the optical film thickness larger than the wavelength of light, reflection and refraction of light due to a refractive index difference at the interface between the p-type layer 16 and the side surface reflection portion 17 and the interface between the side surface reflection portion 17 and the buried layer 18 are utilized.

When a dielectric material is used for the side reflection portion 17, it is preferable that the distributed bragg reflector (DBR: distributed Bragg Reflector) be constituted by a dielectric multilayer film in which a plurality of materials having different refractive indices are alternately laminated. As an example, hfO is mentioned ₂ 、TiO ₂ 、Ta ₂ O ₅ 、Al ₂ O ₃ 、SiO ₂ 、MgF ₂ And a material formed by any combination of dielectric materials. In the case where the side reflection portion 17 is formed of a dielectric or semiconductor multilayer film and the DBR is formedIn this case, the reflectance can be controlled by forming each layer with 1/4 wavelength and adjusting the number of layers to be stacked.

Fig. 2 is a graph showing the relationship between the number of layers and the reflectivity of the DBR. In the graph shown in FIG. 2, the GaN/Al is GaN/Al with the wavelength of 440nm _0.27 Ga _0.73 The N multilayer film shows the relationship between the number of layers of the DBR and the reflectance, and it is known that the reflectance can be controlled in the range of 60 to 80% by adjusting the number of layers (the logarithm of the low refractive index layer and the high refractive index layer). The reflectance can be improved by further increasing the number of layers as compared with that shown in fig. 2, but when the number of layers is too large, the man-hours for forming the side surface reflecting portion 17 increases, and therefore the number of layers is preferably in the range of 2 to 12 pairs.

The buried layer 18 is a layer that fills the space between the side reflection portions 17 and the upper surface of the columnar semiconductor layer. As a material constituting the buried layer 18, a semiconductor material such as GaN or a transparent electrode such as ITO (Indium Tin Oxide) is used. An anode electrode 19p is formed on a part of the surface of the buried layer 18. Although fig. 1A and 1B show an example in which the embedded layer 18 is formed of a single layer, the embedded layer may be a multilayer structure as long as the embedded layer is embedded in the upper surface of the columnar semiconductor layer from the surface of the underlayer 12. In the case where the buried layer 18 is made of a semiconductor material, a p-type semiconductor layer or an n-type semiconductor layer may be used, and functions such as a tunnel junction layer, a contact layer, and a current diffusion layer may be included.

The mesa groove is a groove formed through each semiconductor layer from the buried layer 18 to the underlayer 12, and is formed to divide the light emitting region of the semiconductor light emitting element 10 into a mesa structure. An element separation groove is also formed in the mesa groove to separate the semiconductor light emitting elements 10 individually.

The cathode electrode 19n is an electrode formed in the region where the underlayer 12 is exposed in the mesa groove, and is formed of a laminated structure of a metal material in ohmic contact with the exposed semiconductor layer and a pad electrode. The anode electrode 19p is an electrode formed on a part of the buried layer 18, and is formed of a laminated structure of a metal material in ohmic contact with the outermost surface of the buried layer 18 and a pad electrode. Although not shown in fig. 1A and 1B, a known structure such as a passivation film covering the surface of the semiconductor light emitting element 10 may be applied as necessary. In addition, a transparent electrode in which the anode electrode 19p is extended may be formed on the entire buried layer 18.

Fig. 3A to 3D are schematic views showing a method of manufacturing the semiconductor light emitting element 10, fig. 3A shows a mask forming step, fig. 3B shows a nanowire growth step, fig. 3C shows a growth step of the active layer 15 and the p-type layer 16, and fig. 3D shows a side reflection portion forming step. Fig. 4E to 4G are schematic views showing a method of manufacturing the semiconductor light emitting element 10, in which fig. 4E shows a buried layer forming step, fig. 4F shows a mesa forming step, and fig. 4G shows an electrode forming step.

First, as shown in fig. 3A, a growth substrate 11 having a base layer 12 made of n-type GaN formed thereon is prepared. In the mask forming step, siO of about 30nm is deposited on the underlayer 12 by sputtering ₂ The mask 13 is formed with an opening 13a having a diameter of about 150 nm. The opening 13a can be formed by a fine pattern forming method such as nanoimprint lithography. In the case of using a different type of substrate such as sapphire as the growth substrate 11, a buffer layer, a base layer 12, and an n-type semiconductor layer may be formed on the sapphire substrate, and the surface of the n-type semiconductor layer may be used for the surface of the growth substrate 11. As the growth conditions of the buffer layer, TMA (trimethylaluminum), TMG (trimethylgalium), and ammonia were used as raw material gases, the growth temperature was 1100 ℃, the V/III ratio was 1000, and hydrogen was used as a carrier gas, and the pressure was 10hPa. The growth conditions for the underlayer and the n-type semiconductor layer are, for example, 1050℃for growth temperature, 1000 for V/III ratio, and 500hPa for hydrogen as carrier gas.

Next, in the nanowire growth step shown in fig. 3B, a nanowire layer 14 made of GaN is grown on the underlayer 12 exposed from the opening 13a by selective growth by the MOCVD method. As the growth conditions of the nanowire layer 14, for example, TMG and ammonia are used as raw material gases, the growth temperature is 1050 ℃, the V/III ratio is 10, hydrogen is used as carrier gas, and the pressure is 100hPa.

Next, in the growth process of the active layer 15 and the p-type layer 16 shown in fig. 3C, the active layer 15 and the p-type layer 16 are grown on the side surfaces and the upper surface of the nanowire layer 14 by the MOCVD method. The active layer 15 is, for example, a multi-quantum well structure in which a GaInN quantum well layer having a thickness of 5nm and a GaN barrier layer having a thickness of 10nm are stacked for 5 cycles. The nanowire growth process of fig. 3B and the growth process of the active layer 15 and the p-type layer 16 of fig. 3C correspond to the pillar-shaped semiconductor layer growth process of the present disclosure.

As the growth conditions of the active layer 15, for example, a growth temperature of 800 ℃, a V/III ratio of 3000, nitrogen as a carrier gas, and a pressure of 1000hPa, TMG, TMI (TriMethylIndium) and ammonia are used as raw material gases. The p-type layer 16 is, for example, p-type GaN made of GaN doped with p-type impurities. As the conditions for growing the p-type layer 16, TMG and Cp were used, for example, at a growth temperature of 950℃and a V/III ratio of 4000, hydrogen as a carrier gas and a pressure of 300hPa ₂ Mg (biscycrentadienyl magnesium, magnesium dicyclopentadiene) and ammonia as raw material gases.

Next, in the side reflection portion forming step shown in fig. 3D, the side reflection portion 17 is formed along the side surface of the p-type layer 16. Here, in the case where the side surface reflecting portion 17 is made of a semiconductor material, the side surface reflecting portion 17 can be grown on the side surface of the p-type layer 16 in the same reaction chamber after the growth of the p-type layer 16. In the case of using a metal material or a dielectric material as the side surface reflecting portion 17, after the p-type layer 16 is grown, the side surface reflecting portion 17 can be formed on the side surface of the p-type layer 16 by using a sputtering method or a vapor deposition method. In this case, by disposing the growth substrate 11 obliquely with respect to the film material supply direction, a metal material or a dielectric material can be formed at an appropriate film thickness on the side surface of the p-type layer 16. Further, by forming a film in a plurality of directions by tilting the growth substrate 11, a metal material or a dielectric material can be formed on the entire side surface of the p-type layer 16. In addition, the metal material or the dielectric material attached to the top of the columnar semiconductor layer is preferably removed by dry etching or the like.

Next, in the buried layer forming step shown in fig. 4E, the buried layer 18 is formed so as to cover the upper surfaces of the p-type layer 16 and between the side reflection portions 17 formed in the plurality of columnar semiconductor layers. In the case of forming the buried layer 18 from a p-type semiconductor layerIn the case where the growth conditions of the buried layer 18 are, for example, 950 ℃, the V/III ratio is 1000, hydrogen is used as a carrier gas, the pressure is 300hPa, and TMG and Cp can be used ₂ Mg and ammonia were used as raw material gases. In the case of forming the embedded layer 18 from a transparent electrode such as ITO, a known method such as sputtering can be used.

As described above, the buried layer 18 needs to be grown on the mask 13 provided between the columnar semiconductor layers, and when the buried layer 18 is grown, voids may be generated in the lower portion of the columnar semiconductor layers. Therefore, in the growth of the buried layer 18, TMG, silane, and ammonia are preferably used as the source gases, and the growth is performed at a low temperature and a low V/III ratio in an initial stage to promote the growth of the m-plane which is the lateral growth. As an example of the low temperature and low V/III ratio, a V/III ratio of 100 or less at 800℃or less, hydrogen as a carrier gas, and a pressure of 200hPa can be given. Preferably, after the mask 13 is buried without a gap in the lower portion of the columnar semiconductor layer by lateral growth of the buried layer 18, the growth is performed at a high temperature and a high V/III ratio that promotes the growth of the c-plane as the longitudinal growth. As an example of the high temperature and high V/III ratio, there may be mentioned a V/III ratio of 1000℃or higher and 2000 or higher, hydrogen as a carrier gas, and a pressure of 500hPa.

Next, in the mesa formation step shown in fig. 4F, a portion from the buried layer 18 to the base layer 12 is selectively removed by dry etching, and the upper surface of the base layer 12 is exposed to form a mesa groove. By forming the mesa groove, the region surrounded by the mesa groove is divided into the light emitting region of the semiconductor light emitting element 10.

Next, in the electrode forming step shown in fig. 4G, a cathode electrode 19n is formed on the surface of the base layer 12 exposed in the mesa groove, and an anode electrode 19p is formed on the buried layer 18. Further, annealing after electrode formation, passivation film formation, and element division are performed as needed to obtain the semiconductor light-emitting element 10.

In the semiconductor light-emitting element 10 of the present embodiment, when a voltage is applied between the cathode electrode 19n and the anode electrode 19p, current flows through the buried layer 18, the p-type layer 16, the active layer 15, the nanowire layer 14, and the underlayer 12 in this order, and light is generated in the active layer 15 by recombination of light emission. The light emitted from the active layer 15 reaches the side surface reflection portion 17, and a part thereof is reflected, but the reflected light travels in the vertical direction according to the incident angle, and is extracted in the main surface direction of the semiconductor light emitting element 10 by repeating the reflection a plurality of times.

As described above, the side surface reflection portion 17 preferably has a reflectance in the range of 30 to 90% and more preferably a reflectance in the range of 40 to 75% with respect to the light emitted from the active layer 15. If the reflectance is too high, the absorbance at which light emitted from the active layer 15 is repeatedly reflected and absorbed in the columnar semiconductor layer becomes high, and it is difficult to increase the amount of light taken out to the outside. If the reflectance is too low, the amount of light extracted from the side surface direction of the semiconductor light-emitting element 10 increases, and it is difficult to improve the light extraction efficiency in the main surface direction.

In one columnar semiconductor layer, light emitted from the active layer 15 is reflected by a side surface reflection portion 17 formed on a side surface of the columnar semiconductor layer to be directed upward, and the remaining part of the light transmits the side surface reflection portion 17. The light transmitted through the side surface reflection portion 17 propagates through the buried layer 18, reaches the other side surface reflection portion 17 provided in the other columnar semiconductor layer, and is partially reflected and directed upward. Therefore, by setting the reflectance of the side surface reflection portions 17 to the above range, the light emitted from one active layer 15 is reflected upward by the plurality of side surface reflection portions 17, and the light extraction amount in the main surface direction in the entire semiconductor light emitting element 10 can be improved.

Since the side surface of the nanowire layer 14 is an m-plane formed by selective growth, the active layer 15 and the p-type layer 16 formed on the outer periphery thereof are also in contact with each other with the m-plane. Since the m-plane is a nonpolar plane, no polarization occurs, the light emission efficiency in the active layer 15 is high, and since all the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light emitting element 10 can be improved. Further, since the thickness of the active layer can be made thicker, the volume of the active layer 15 can be increased by about 3 to 10 times compared with the conventional semiconductor light emitting element, and the injected carrier density can be reduced, thereby greatly reducing the efficiency.

As described above, in the semiconductor light-emitting element and the method for manufacturing a semiconductor light-emitting element according to the present embodiment, the side surface reflection portion 17 is formed in contact with the side surface of the columnar semiconductor layer including the nanowire layer 14, the active layer 15, and the p-type layer 16, and therefore, a part of light emitted from the active layer 15 is reflected, and the amount of light extracted in the main surface direction can be increased.

In addition, by setting the reflectance of the side reflection portion 17 to a range of 30 to 90% with respect to the light emitted from the active layer 15, the light emitted from one active layer 15 is reflected by the plurality of side reflection portions 17, and thus the light extraction amount in the main surface direction in the entire semiconductor light emitting element 10 can be improved.

(second embodiment)

Next, a second embodiment of the present disclosure will be described with reference to fig. 5. The description of the overlapping contents with the first embodiment will be omitted. Fig. 5 is a schematic cross-sectional view showing the semiconductor light-emitting element 10 of the present embodiment. The present embodiment is different from the first embodiment in that the semiconductor light emitting element 10 is flip-chip mounted. As shown in fig. 5, the semiconductor light emitting element 10 includes a growth substrate 11, a base layer 12, a mask 13, a nanowire layer 14, an active layer 15, a p-type layer 16, a side surface reflecting portion 17, a buried layer 18, a cathode electrode 19n, an anode electrode 19p, a mounting portion 20, an upper surface reflecting portion 21, and solder 22.

The mounting portion 20 is a member for mounting the semiconductor light emitting element 10 by flip chip connection, and a wiring pattern or a pad for supplying current to the semiconductor light emitting element 10 is formed on the upper surface of the mounting portion 20. The specific configuration of the mounting portion 20 is not limited, and a known sub-mount, a printed wiring board, or the like can be used. The material constituting the mounting portion 20 is not limited, and a ceramic, an insulator, a glass epoxy resin, a composite substrate of a metal and an insulating film, or the like can be used.

The upper surface reflection portion 21 is provided on the surface of the buried layer 18 opposite to the growth substrate 11. The upper surface reflection portion 21 is a film-like member that reflects light emitted from the active layer 15 toward the growth substrate 11. The upper surface reflection portion 21 may be formed between the embedded layer 18 and the mounting portion 20, and may be formed on the embedded layer 18 of the semiconductor light emitting element 10 or may be formed on the surface of the mounting portion 20. The material constituting the upper surface reflection portion 21 is not limited, and for example, a metal material such as Al, au, ag, cr can be used.

The solder 22 is a member for electrically connecting the cathode electrode 19n and the wiring pattern on the mounting portion 20. Although not shown in fig. 5, solder is also provided between the anode electrode 19p and the mounting portion 20, and the anode electrode 19p and the wiring pattern on the mounting portion 20 are electrically connected by solder not shown.

In the present embodiment, a part of the light emitted from the active layer 15 is reflected by the side surface reflection portion 17 and extracted from the back surface of the growth substrate 11. A part of the light is reflected by the side surface reflection portion 17, and advances in the direction of the mounting portion 20 to reach the upper surface reflection portion 21. The light reaching the upper surface reflection portion 21 is totally reflected by the upper surface reflection portion 21, and is extracted from the back surface of the growth substrate 11 to the outside. The light transmitted through the side surface reflecting portion 17 propagates through the buried layer 18, reaches the other side surface reflecting portion 17 provided in the other columnar semiconductor layer, and is reflected, and is similarly extracted from the back surface of the growth substrate 11.

As described above, in the semiconductor light emitting element 10 of the present embodiment, the side surface reflection portion 17 is formed in contact with the side surface of the columnar semiconductor layer including the nanowire layer 14, the active layer 15, and the p-type layer 16, and the upper surface reflection portion 21 is formed on the buried layer 18, so that the amount of light extracted from the back surface of the growth substrate 11 can be increased.

(third embodiment)

Next, a third embodiment of the present disclosure will be described with reference to fig. 6A to 7D. The description of the same as that of the first embodiment will be omitted. Fig. 6A and 6B are diagrams showing the semiconductor light emitting element 30 according to the present embodiment, fig. 6A is a schematic cross-sectional view, and fig. 6B is a partial enlarged cross-sectional view showing the columnar semiconductor layer in an enlarged manner.

As shown in fig. 6A, the semiconductor light emitting element 30 of the present embodiment includes: the growth substrate 31, underlayer 32, mask 33, nanowire layer 34, active layer 35, p-type layer 36, buried layer 37, cathode electrode 38n, anode electrode 38p, mounting portion 20, upper surface reflection portion 21, and solder 22. As shown in fig. 6B, the side surface of the p-type layer 36 has an inclined side surface inclined with respect to the main surface of the growth substrate 31.

First, as shown in fig. 7A, a growth substrate 31 having a base layer 32 formed thereon is prepared, and a mask 33 having an opening 33a is formed in a mask forming step. Next, as shown in fig. 7B, a nanowire layer 34 is formed in the nanowire growth process. Next, as shown in fig. 7C, an active layer 35 and a p-type layer 36 are formed. Here, specific examples of the mask forming step, the nanowire growing step, and the forming step of the active layer 35 and the p-type layer 36 are the same as those of the first embodiment.

Next, as shown in fig. 7D, the growth of the p-type layer 36 is continued under the growth condition that the side surface of the p-type layer 36 is an inclined side surface inclined with respect to the main surface of the growth substrate 31, and a side reflection portion forming step is performed. In this case, the conditions under which the side surface of the p-type layer 36 is inclined include a condition that the growth temperature is lower or the V/III ratio is lower than the growth condition under which the m-plane is grown as a facet. As an example, when the growth condition of the p-type layer 36 on the vertical m-plane in fig. 7C is 950 ℃ and the V/III ratio is 4000, the V/III ratio is 2000 at 950 ℃ and 4000 at 900 ℃ and 3000 at 900 ℃.

Here, as shown in fig. 7C and 7D, an example in which the growth conditions of the p-type layer 36 are changed in two steps is shown, but the m-plane side surface is not formed on the p-type layer 36. Therefore, the side surface of the p-type layer 36 may be grown as an inclined side surface under one-stage growth conditions using growth conditions in which the inclined side surface is formed after the formation of the active layer 35.

After the side reflection portion forming step shown in fig. 7D, the buried layer 37 is formed in the buried layer forming step in the same manner as in fig. 4E. Then, the upper surface reflection portion 21 is formed on the buried layer 37, and mesa grooves are formed in the mesa formation step as in fig. 4F, and the cathode electrode 19n and the anode electrode 19p are formed in the electrode formation step as in fig. 4G. Further, annealing after electrode formation, passivation film formation, and element division are performed as needed to obtain the semiconductor light-emitting element 30.

In the present embodiment, the side surface reflection portion is formed by the interface between the inclined side surface of the p-type layer 36 and the buried layer 37, and has a tapered shape in which the diameter thereof becomes smaller in a direction away from the growth substrate 31. The buried layer 37 is made of a material having a refractive index different from that of the p-type layer 36 of the columnar semiconductor layer. Therefore, a part of the light emitted from the active layer 35 is reflected by the refractive index difference at the interface (side reflection portion) between the p-type layer 36 and the buried layer 37, and is extracted from the back surface of the growth substrate 31 to the outside. In addition, a part of the light advances in the direction of the mounting portion 20 and reaches the upper surface reflection portion 21. The light reaching the upper surface reflection portion 21 is totally reflected by the upper surface reflection portion 21, and is taken out from the back surface of the growth substrate 31 to the outside.

Light transmitted from the p-type layer 36 to the buried layer 37 propagates through the buried layer 37, reaches the interface between the other p-type layer 36 provided in the other columnar semiconductor layer and the buried layer 37, and is reflected or refracted, and is similarly extracted from the back surface of the growth substrate 31.

Fig. 7A to 7D are schematic views showing a method for manufacturing the semiconductor light emitting element 30 according to the present embodiment, in which fig. 7A shows a mask forming step, fig. 7B shows a nanowire growth step, fig. 7C shows a growth step of the active layer 35 and the p-type layer 36, and fig. 7D shows a side reflection portion forming step. In the present embodiment, the difference from the first embodiment is that the side surface of the p-type layer 36 is inclined instead of the side surface reflection portion forming step shown in fig. 3D.

As described above, in the semiconductor light emitting element 30 of the present embodiment, the p-type layer 36 and the buried layer 37 are made of materials having different refractive indices, and the side surface of the p-type layer 36 has an inclined side surface inclined with respect to the main surface of the growth substrate 31. Thus, the side surface reflection portion is formed by the interface between the p-type layer 36 and the buried layer 37, and the light emitted from the active layer 35 is extracted from the back surface of the growth substrate 31 by reflection and refraction due to the refractive index difference. Therefore, the amount of light extracted from the back surface of the growth substrate 31 can be increased.

(fourth embodiment)

Fig. 8A and 8B are diagrams showing the semiconductor light emitting element 110 according to the fourth embodiment, fig. 8A is a schematic cross-sectional view, and fig. 8B is a partial enlarged cross-sectional view showing the columnar semiconductor layer in an enlarged manner.

As shown in fig. 8A, the semiconductor light-emitting element 110 includes a growth substrate 111, a underlayer 112, a mask 113, a nanowire layer 114, an active layer 115, a p-type layer 116, a buried layer 117, a cathode electrode 118n, and an anode electrode 118p. Here, the nanowire layer 114, the active layer 115, and the p-type layer 116 are pillar-shaped selectively grown on the growth substrate 111 and vertically provided, and constitute a pillar-shaped semiconductor layer in the present disclosure. As shown in fig. 8B, the columnar semiconductor layer has a side surface (inclined side surface portion) inclined with respect to the main surface of the growth substrate 111, and has a trapezoidal cross section. Here, although the case where the columnar semiconductor layer has a top surface and a trapezoidal cross section is shown, most of the surface may be formed by a side surface inclined by reducing the top surface, and the cross section may be triangular. In addition, the active layer 115 along the side of the nanowire layer 114 constitutes a double heterostructure sandwiched by the nanowire layer 114 and the p-type layer 116.

As shown in fig. 8A, a part of the semiconductor light-emitting element 110 is formed with a mesa groove (mesa structure) by removing the buried layer 117 from the surface to the base layer 112, and the surface of the base layer 112 is exposed to form a cathode electrode 118n. An anode electrode 118p is formed on the buried layer 117. The mesa structure is a structure in which a groove penetrating a plurality of semiconductor layers is formed so as to surround a predetermined region, whereby a cross section of a stacked structure of the semiconductor layers is exposed from a side surface.

The growth substrate 111 is the same as the growth substrate 11 of the first embodiment.

The base layer 112 is the same as the base layer 12 of the first embodiment.

The buffer layer is formed between the growth substrate 111 and the underlayer 112, and is a layer for relaxing lattice mismatch between the two. In the case of using a c-plane sapphire substrate as the growth substrate 111, gaN is preferably used as the buffer layer, but AlN, alGaN, or the like may be used. In the case where the growth substrate 111 and the underlayer 112 are made of the same material, the buffer layer may not be provided. In the case of using a single crystal substrate such as a GaN substrate as the growth substrate 111, the cathode electrode 118n may be formed on the surface of the growth substrate without providing the buffer layer and the underlayer 112.

The mask 113 is the same as the mask 13 of the first embodiment.

The columnar semiconductor layer is a semiconductor layer grown by crystallization in the opening 113a provided in the mask 113, and is formed by standing the semiconductor layer in a vertical direction with respect to the main surface of the growth substrate 111. Such a columnar semiconductor layer is obtained by setting appropriate growth conditions according to the semiconductor material to be formed, and performing selective growth of specific crystal plane orientation growth. In the example shown in fig. 8A, since the plurality of openings 113a are formed periodically in two dimensions on the mask 113, a columnar semiconductor layer is also formed periodically in two dimensions on the growth substrate 111.

The nanowire layer 114 is a columnar semiconductor layer selectively grown on the underlayer 112 exposed from the opening 113a of the mask 113, and is made of GaN doped with an n-type impurity, for example. As shown in fig. 8B, the nanowire layer 114 is composed of a nanowire core 114a and inclined side portions 114B. The nanowire core 114a is a region indicated by a broken line in fig. 8B, and is a columnar layer formed in a region extending in the vertical direction from the opening 113a of the mask 113. The inclined side surface portion 114b is a layer formed around the nanowire core 114a, and is formed so as to partially cover the mask 113. The side surface of the inclined side surface portion 114b forms the side surface of the nanowire layer 114, has a large diameter near the growth substrate 111, is reduced in diameter toward the vicinity of the tip of the nanowire core 114a, is inclined with respect to the main surface of the growth substrate 111, and has a trapezoidal cross section. In fig. 8B, the nanowire core 114a is shown by a broken line, and is described differently from the inclined side surface portion 114B formed around the nanowire core, but both may be made of the same material, and in this case, no clear boundary is formed.

When GaN is used as the nanowire layer 114, the nanowire core 114a selectively grown on the growth substrate 111 is formed in a substantially hexagonal prism shape formed with six m-planes as facets. In fig. 8B, the nanowire core 114a appears to grow only in the region where the opening 113a is formed, but in reality, since the lateral growth also progresses the crystal growth on the mask 113, a hexagonal prism is formed that expands around the opening 113 a. For example, when the opening 113a is formed as a circle having a diameter of about 150nm, it can be formed so as to be equal to the diameterA hexagonal shape inscribed in a circle of about 200nm is a hexagonal prism-shaped nanowire core 114a with a bottom surface of about 1-2 μm. When the underlayer 112 and the nanowire layer 114 are made of GaN, for example, the electron concentration is preferably 10 ¹⁸ atoms/cm ^－3 Left and right n-type semiconductor layers.

In the present embodiment, gaN is used as the nanowire layer 114, but GaInN may be used as the nanowire layer 114 In order to reduce misfit dislocation due to lattice mismatch when the In component of the active layer 115 is increased In order to lengthen the emission wavelength. Similarly, when the wavelength of the semiconductor light-emitting element 110 is shortened, alGaN may be used as the nanowire layer 114, or the well layer and the barrier layer of the active layer 115 may be changed to AlGaN having different compositions.

The composition of the active layer 115 is the same as the active layer 15 of the first embodiment.

Since the active layer 115 is formed on the outer periphery of the nanowire layer 114, it has a semi-polar surface inclined with respect to the main surface of the growth substrate 111, similarly to the side surface of the nanowire layer 114. Here, the semipolar plane in GaN means a plane inclined from the c-plane by a range of more than 0 degrees and less than 90 degrees. Therefore, since a voltage is applied to the semipolar plane inclined from the c-plane of GaN on the active layer 115, the drop characteristic can be improved. In addition, the light emitted from the active layer 115 contains a large amount of components in the direction perpendicular to the inclined side surface portion 114b, and the proportion of the light traveling obliquely upward of the growth substrate 111 increases.

The p-type layer 116 is a semiconductor layer grown on the outer periphery of the active layer 115, and is made of GaN doped with p-type impurities, for example. As shown in fig. 8A, a p-type layer 116 is formed to cover the side and upper surfaces of the active layer 115. Thus, the nanowire layer 114, the active layer 115, and the p-type layer 116 form a double heterostructure, and carriers can be well sealed in the active layer 115, thereby improving the probability of recombination of light emission. Fig. 8A shows an example in which p-type layer 116 is formed of a single layer, but a multilayer layer structure covering the side surface of active layer 115 may be used. Since the p-type layer 116 is formed on the outer periphery of the active layer 115, the p-type layer is inclined with respect to the main surface of the growth substrate 111, similarly to the side surfaces of the nanowire layer 114 and the active layer 115.

The buried layer 117 has the same structure, composition, and function as the buried layer 18 of the first embodiment.

The mesa groove is the same as the mesa groove of the first embodiment.

The cathode electrode 118n is the same as the cathode electrode 19n of the first embodiment.

Fig. 9A to 9D are schematic diagrams showing a method for manufacturing the semiconductor light-emitting element 110, fig. 9A shows a mask formation step, fig. 9B shows a nanowire core growth step in a nanowire layer growth step, fig. 9C shows an inclined side surface portion growth step in a nanowire layer growth step, and fig. 9D shows a growth step of the active layer 115 and the p-type layer 116. The nanowire core growth process and the inclined side surface portion growth process form the nanowire layer 114 having the inclined side surface portion 114b under the two-stage growth condition, which corresponds to the nanowire layer growth process of the present invention. Fig. 10E to 10G are schematic views showing a method of manufacturing the semiconductor light emitting element 110, in which fig. 10E shows a buried layer forming step, fig. 10F shows a mesa forming step, and fig. 10G shows an electrode forming step.

First, as shown in fig. 9A, a growth substrate 111 having a base layer 112 made of n-type GaN formed thereon is prepared. The mask forming process is the same as that of the first embodiment.

Next, in the nanowire core growth step shown in fig. 9B, a nanowire core 114a made of GaN is grown on the underlayer 112 exposed from the opening 113a by selective growth by the MOCVD method. As the growth conditions of the nanowire core 114a, for example, TMG and ammonia were used as raw material gases, the growth temperature was 1100 ℃, the V/III ratio was 20, and hydrogen was used as a carrier gas, and the pressure was 100hPa. Under this growth condition, the nanowire core 114a is grown into a hexagonal prism shape with the m-plane perpendicular to the growth substrate 111 as a facet.

Next, in the inclined side surface portion growth step shown in fig. 9C, crystal growth is continued on the side surfaces and the upper surface of the nanowire core 114a, and an inclined side surface portion 114b having an inclined side surface with respect to the main surface of the growth substrate 111 is grown. The growth conditions of the inclined side surface portion 114b include a decrease in the V/III ratio of the raw material or a decrease in the growth temperature, compared with the growth conditions of the nanowire core 114 a. As an example, the V/III ratio is set in the range of 1000 to 5000, and the growth temperature is set in the range of 900 to 950 ℃.

By performing the inclined-side-surface-portion growth step under these growth conditions, the inclined side surface portion 114b formed around the nanowire core 114a has a side surface with a semipolar surface as a facet, and has a trapezoidal cross section. Since the nanowire core 114a is in a hexagonal prism shape, the nanowire layer 114 including the nanowire core 114a and the inclined side surface portion 114b is formed in a hexagonal pyramid shape. Examples of the facets of the semipolar plane include planes having a higher order surface index represented by [10-11] [10-12] [10-13] [20-21] [30-31], and having inclination angles of 62 degrees, 43 degrees, 32 degrees, 75 degrees, and 80 degrees with respect to the c-plane, respectively.

Next, in a growth process of the active layer 115 and the p-type layer 116 shown in fig. 9D, the active layer 115 and the p-type layer 116 are grown on the side surfaces and the upper surface of the nanowire layer 114 by the MOCVD method. The active layer 115 is, for example, a multi-quantum well structure in which a GaInN quantum well layer having a thickness of 3 to 10nm and a GaN barrier layer having a thickness of 5 to 20nm are stacked for 5 cycles. In addition, as the p-type layer 116, a hole concentration of 10 is exemplified ¹⁸ ～10 ¹⁹ atoms/cm ^－3 Left and right p-GaN layers. The nanowire core growth process of fig. 9B, the inclined side surface portion growth process of fig. 9C, and the growth process of the active layer 115 and the p-type layer 116 of fig. 9D correspond to the pillar-shaped semiconductor layer growth process of the present disclosure.

The growth conditions of the active layer 115 are the same as those of the active layer 15 of the first embodiment.

Next, in the buried layer forming step shown in fig. 10E, the buried layer 117 is formed so as to cover the side surfaces and the upper surfaces of the plurality of columnar semiconductor layers. The growth conditions of the buried layer 117 when the buried layer 117 is formed of a p-type semiconductor layer are the same as those of the buried layer 18 of the first embodiment.

The conditions of the ratio, temperature, pressure, and the like of the source gas for the growth of the buried layer 117 are the same as those of the buried layer 18 of the first embodiment.

Next, in the mesa formation step shown in fig. 10F, a portion from the buried layer 117 to the base layer 112 is selectively removed by dry etching, and the upper surface of the base layer 112 is exposed to form a mesa groove. By forming the mesa groove, the region surrounded by the mesa groove is divided into the light emitting region of the semiconductor light emitting element 110.

Next, in the electrode forming step shown in fig. 10G, a cathode electrode 118n is formed on the surface of the underlayer 112 exposed in the mesa groove, and an anode electrode 118p is formed on the buried layer 117. Further, annealing after electrode formation, passivation film formation, and element division are performed as needed to obtain the semiconductor light-emitting element 110.

In the semiconductor light-emitting element 110 of the present embodiment, when a voltage is applied between the cathode electrode 118n and the anode electrode 118p, current flows through the buried layer 117, the p-type layer 116, the active layer 115, the nanowire layer 114, and the underlayer 112 in this order, and light is generated in the active layer 115 by recombination of light emission. Since the inclined side surface portion 114b and the active layer 115 are inclined with respect to the growth substrate 111, the light emitted from the active layer 115 travels obliquely upward of the growth substrate 111, and the amount of light extracted in the main surface direction increases.

Since the inclined side surface 114b of the nanowire layer 114 is a semi-polar surface, the active layer 115 and the p-type layer 116 formed on the outer periphery thereof are also in contact with each other with the semi-polar surface. Since the polarization of the semi-polar plane is smaller than that of the c-plane, the light emission efficiency in the active layer 115 is also high, and all the side surfaces of the hexagonal prism are semi-polar planes, so that the light emission efficiency of the semiconductor light emitting element 110 can be improved. Further, since the film thickness of the active layer can be made thicker, the volume of the active layer 115 can be increased by about 3 to 10 times compared with the conventional semiconductor light-emitting element, and the injected carrier density can be reduced, thereby greatly reducing the efficiency.

As described above, in the semiconductor light emitting element 110 and the method for manufacturing the semiconductor light emitting element 110 according to the present embodiment, since the side surface of the active layer 115 is inclined with respect to the main surface of the growth substrate 111, light emitted from the active layer 115 is extracted obliquely upward of the growth substrate 111, and the amount of light extracted in the main surface direction can be increased. In addition, since light emitted from the active layer 115 travels obliquely upward, light absorbed by the other nanowire layer 114 can be reduced, and external quantum efficiency can be improved.

(fifth embodiment)

Next, a fifth embodiment of the present disclosure will be described. The description of the contents overlapping with the fourth embodiment will be omitted. In the fourth embodiment, the nanowire layer 114 is formed by two-stage growth under different conditions in the nanowire core growth step and the inclined side surface portion growth step, but in the present embodiment, the nanowire layer 114 having the inclined side surface portion 114b is formed at the same time.

In the present embodiment, after the mask forming step shown in fig. 9A, the nanowire core 114a and the inclined side surface portion 114b are continuously formed in the nanowire layer growth step under the same conditions. The growth conditions in the nanowire growth step are those in which the V/III ratio of the raw material is lower than that of the side surface on which the m-plane facet is formed in the nanowire core growth step, or those in which the growth temperature is low.

As an example, the growth conditions for forming the m-plane facets were TMG and ammonia as raw material gases, the growth temperature was 1100 ℃, the V/III ratio was 20, and hydrogen as carrier gas, at a pressure of 100hPa. Therefore, when the nanowire core 114a and the inclined side surface portion 114b are grown under the growth condition of one time, the V/III ratio is 100, the growth temperature is 1100 ℃, the V/III ratio is 20, the growth temperature is 1000 ℃, the V/III ratio is 100, the growth temperature is 1000 ℃, and the like. By using such growth conditions, after the mask forming step shown in fig. 9A, the growth from the opening 113a upward and the lateral growth to the region covering the mask 113 can be simultaneously performed in parallel, and the nanowire core 114a and the inclined side surface portion 114b can be formed under one growth condition.

The side surface of the nanowire layer 114 formed in the present embodiment also has a semi-polar surface as in the fourth embodiment, and the active layer 115 and the p-type layer 116 are also formed obliquely to the main surface of the growth substrate 111. Therefore, polarization in the active layer 115 can be suppressed, and the light emission efficiency can be improved, and the light extraction amount obliquely upward can be improved.

The present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the claims, and embodiments in which the technical aspects disclosed in the different embodiments are appropriately combined are also included in the technical scope of the present disclosure.

The present invention is based on Japanese patent application Nos. 2021-113350 to 2021, 7 and 8 and Japanese patent application Nos. 2021-113883 to 2021, 7 and 8, the contents of which are incorporated herein by reference.

Industrial applicability

According to the present invention, a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element can be provided, in which the amount of light extracted in the main surface direction or the back surface direction can be increased even in the case of a semiconductor light-emitting element having a columnar semiconductor layer.

Claims (17)

1. A semiconductor light emitting element is characterized by comprising:

Growing a substrate;

a plurality of columnar semiconductor layers on the growth substrate;

a side surface reflection unit which is provided on a side surface of the columnar semiconductor layer and which reflects at least a part of light emitted from the columnar semiconductor layer;

and a buried layer covering the columnar semiconductor layer and the side surface reflection portion.

2. The semiconductor light emitting device according to claim 1, wherein,

the side surface reflection portion is a light reflection film that contacts a side surface of the columnar semiconductor layer.

3. The semiconductor light-emitting device according to claim 2, wherein,

the light reflection film is made of a metal material containing any one of Al, au, ag, cr as a main component.

4. The semiconductor light-emitting device according to claim 2, wherein,

the light reflection film is made of a semiconductor material having a band gap larger than the wavelength of the light, and has an optical thickness larger than the wavelength of the light.

5. The semiconductor light-emitting device according to claim 2, wherein,

the light reflecting film contains HfO ₂ 、TiO ₂ 、Ta ₂ O ₅ 、Al ₂ O ₃ 、SiO ₂ 、MgF ₂ Any one of the dielectric multilayer films.

6. The semiconductor light emitting device according to claim 1, wherein,

the buried layer is composed of a material having a refractive index different from that of the columnar semiconductor layer,

The side surface of the columnar semiconductor layer has an inclined side surface inclined with respect to the main surface of the growth substrate,

the side surface reflection portion is formed by an interface between the inclined side surface and the buried layer.

7. The semiconductor light-emitting element according to any one of claims 1 to 6, wherein,

the reflectance of the light of the side surface reflection portion is in the range of 30 to 90%.

8. The semiconductor light-emitting element according to any one of claims 1 to 7, wherein,

an upper surface reflection portion that reflects the light toward the growth substrate is formed on a surface of the buried layer opposite to the growth substrate.

9. A method for manufacturing a semiconductor light emitting element is characterized by comprising:

a columnar semiconductor growth step of forming a plurality of columnar semiconductor layers on a growth substrate,

A side surface reflection portion forming step of forming a side surface reflection portion on a side surface of the columnar semiconductor layer

And a buried layer forming step of forming a buried layer by covering the columnar semiconductor layer.

10. A semiconductor light emitting element is characterized by comprising:

growing a substrate;

a plurality of columnar semiconductor layers formed on the growth substrate;

A buried layer covering the columnar semiconductor layer,

the columnar semiconductor layer includes:

a nanowire layer,

An active layer on the periphery of the nanowire layer

A p-type layer on the outer periphery of the active layer,

the side surface of the active layer is inclined with respect to the main surface of the growth substrate.

11. The semiconductor light emitting device according to claim 10, wherein,

the nanowire layer has an inclined side surface portion which is a side surface inclined with respect to the main surface.

12. The semiconductor light emitting device according to claim 11, wherein,

the growth substrate is provided with a mask having an opening,

the nanowire layer is selectively grown from the opening portion, and the inclined side portion is formed in a region partially covering the mask.

13. The semiconductor light-emitting element according to any one of claims 10 to 12, wherein,

the nanowire layer, the active layer, and the p-type layer are composed of a nitride semiconductor.

14. A method for manufacturing a semiconductor light emitting element is characterized by comprising:

a columnar semiconductor growth step of forming a plurality of columnar semiconductor layers on a growth substrate, and

a buried layer forming step of forming a buried layer by covering the columnar semiconductor layer,

The columnar semiconductor layer growth step includes: a nanowire layer growth step of forming a nanowire layer having an inclined side surface portion which is an inclined side surface with respect to a main surface of the growth substrate, an active layer growth step of forming an active layer on an outer periphery of the inclined side surface portion, and a p-type layer growth step of forming a p-type layer on an outer periphery of the active layer.

15. The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein,

the nanowire layer growth step comprises: a nanowire core growth step of forming a nanowire core having a side surface perpendicular to the main surface of the growth substrate, and an inclined side surface portion growth step of forming an inclined side surface portion on the outer periphery of the nanowire core.

16. The method for manufacturing a semiconductor light-emitting element according to claim 15, wherein,

the inclined side surface portion growth step reduces the V/III ratio of the raw material compared to the nanowire core growth step.

17. The method for manufacturing a semiconductor light-emitting element according to claim 15 or 16, wherein,

the inclined side surface portion growth step reduces the growth temperature compared to the nanowire core growth step.