JP2022514171A - 半導体処理のためのチャンバ構成部品のインサイチュ保護被膜 - Google Patents
半導体処理のためのチャンバ構成部品のインサイチュ保護被膜 Download PDFInfo
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- JP2022514171A JP2022514171A JP2021521275A JP2021521275A JP2022514171A JP 2022514171 A JP2022514171 A JP 2022514171A JP 2021521275 A JP2021521275 A JP 2021521275A JP 2021521275 A JP2021521275 A JP 2021521275A JP 2022514171 A JP2022514171 A JP 2022514171A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- C—CHEMISTRY; METALLURGY
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
Description
本願の一部として、本明細書と同時にPCT出願書が提出される。同時に出願されたPCT出願書に認められる利益または優先権を本願が主張する各出願は、その全てが全ての目的のために参照により本明細書に援用される。
序文
装置
インサイチュ保護被膜
、(ii)チャンバからの余剰前駆体材料のパージ、および基板表面上に自己制御単層を残すこと、(iii)吸着した前駆体材料と反応する反応材料の供給、および(iv)チャンバからの未反応反応物または反応副生成物のパージ、を含んでよい。ALDサイクルの堆積反応は、熱誘起またはプラズマ誘起されてよい。ALDは、高共形膜を形成するのに用いられてよい。
結論
Claims (20)
- 方法であって、
気相の第1の反応物を反応チャンバに導入して複数のチャンバ構成部品の表面に吸着させる工程であって、前記複数のチャンバ構成部品は、前記反応チャンバの一部である、工程と、
気相の第2の反応物を前記反応チャンバに導入する工程であって、前記第1の反応物および前記第2の反応物が反応して、約200℃よりも高温で前記複数のチャンバ構成部品の前記表面に保護被膜を堆積させる、工程と、
を含む、方法。 - 請求項1に記載の方法であって、
前記第1の反応物は、プラズマ強化原子層堆積(PEALD)プロセスにおいて前記第2の反応物と反応する、方法。 - 請求項2に記載の方法であって、さらに、
前記第2の反応物のプラズマグロー放電の大部分が上部電極と下部電極との間の領域外の1つ以上の領域で形成するように、前記反応チャンバに供給される高周波(RF)信号を制御する工程を含む、方法。 - 請求項3に記載の方法であって、
前記上部電極に供給される前記RF信号の第1の位相と前記下部電極に供給される前記RF信号の第2の位相との間の位相差は、約180度から0度の位相外れである、方法。 - 請求項4に記載の方法であって、
前記位相差は、約0度の位相外れである、方法。 - 請求項1に記載の方法であって、
前記第1の反応物は、熱ALDプロセスにおいて前記第2の反応物と反応する、方法。 - 請求項1~6のいずれか一項に記載の方法であって、
前記保護被膜は、酸化物、窒化物、炭化物、またはこれらの組み合わせを含む、方法。 - 請求項7に記載の方法であって、
前記保護被膜は、酸化シリコン(SiO2)、酸化アルミニウム(Al2O3)、酸化ジルコニウム(ZrO2)、酸化ハフニウム(HfO2)、酸化スズ(SnO2)、または窒化シリコン(Si3N4)を含む、方法。 - 請求項1~6のいずれか一項に記載の方法であって、
前記複数のチャンバ構成部品の1つ以上の材料は、アルミニウム(Al)を含む、方法。 - 請求項1~6のいずれか一項に記載の方法であって、
前記複数のチャンバ構成部品は、少なくとも前記反応チャンバのチャンバ壁を含む、方法。 - 請求項1~6のいずれか一項に記載の方法であって、さらに、
膜材料を前記反応チャンバのウエハおよび前記保護被膜に堆積させる工程と、
前記ウエハ上および前記保護被膜上の前記膜材料をエッチングする工程であって、前記膜材料は、前記保護被膜よりも実質的に高速度でエッチングされる、工程と、
を含む、方法。 - 請求項11に記載の方法であって、
前記膜材料をエッチングするために用いられるエッチング液は、フッ素系種、塩素系種、臭素系種、ヨウ素系種、またはこれらの組み合わせを含む、方法。 - 請求項11に記載の方法であって、さらに、
前記膜材料のエッチング後に、前記反応チャンバの前記複数のチャンバ構成部品の前記表面に前記保護被膜を再堆積させる工程を含む、方法。 - 請求項1~6のいずれか一項に記載の方法であって、
前記第1の反応物は前記第2の反応物と反応して、約250℃から約650℃の温度で前記複数のチャンバ構成部品の前記表面に前記保護被膜を堆積させる、方法。 - 方法であって、
反応チャンバの複数のチャンバ構成部品の表面に保護被膜を堆積させる工程であって、前記複数のチャンバ構成部品は前記反応チャンバの一部であり、前記保護被膜はプラズマ強化化学蒸着(PECVD)、プラズマ強化原子層堆積(PEALD)、または熱原子層堆積(熱ALD)によって約200℃よりも高温で堆積される、工程を含む、方法。 - 請求項15に記載の方法であって、さらに、
前記反応チャンバの前記複数のチャンバ構成部品の前記表面において、前記保護被膜に膜材料を堆積させる工程であって、前記膜材料は、フッ素系種、塩素系種、臭素系種、またはヨウ素系種への暴露の間に、前記保護被膜よりも実質的に高速度でエッチングされる、工程を含む、方法。 - 請求項16に記載の方法であって、さらに、
前記フッ素系種、前記塩素系種、前記臭素系種、または前記ヨウ素系種への暴露の後に、前記反応チャンバの前記複数のチャンバ構成部品の前記表面に前記保護被膜を再堆積させる工程を含む、方法。 - 請求項16に記載の方法であって、
前記保護被膜は、PECVDまたはPEALDによって堆積され、前記方法は、さらに、
プラズマグロー放電の大部分が上部電極と下部電極との間の領域外の1つ以上の領域で形成するように、前記反応チャンバに供給される高周波(RF)信号を制御する工程を含む、方法。 - 請求項18に記載の方法であって、
前記上部電極に供給される前記RF信号の第1の位相と前記下部電極に供給される前記RF信号の第2の位相との間の位相差は、約0度の位相外れである、方法。 - 請求項15~19のいずれか一項に記載の方法であって、
前記保護被膜は、酸化シリコン(SiO2)、酸化アルミニウム(Al2O3)、酸化ジルコニウム(ZrO2)、酸化ハフニウム(HfO2)、酸化スズ(SnO2)、または窒化シリコン(Si3N4)を含み、前記複数のチャンバ構成部品の1つ以上の材料は、アルミニウム(Al)を含む、方法。
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CN111448640A (zh) | 2017-12-07 | 2020-07-24 | 朗姆研究公司 | 在室调节中的抗氧化保护层 |
US10760158B2 (en) | 2017-12-15 | 2020-09-01 | Lam Research Corporation | Ex situ coating of chamber components for semiconductor processing |
JP6999616B2 (ja) * | 2019-08-07 | 2022-01-18 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム |
US20220130713A1 (en) * | 2020-10-23 | 2022-04-28 | Applied Materials, Inc. | Semiconductor processing chamber to accommodate parasitic plasma formation |
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US7604841B2 (en) * | 2004-03-31 | 2009-10-20 | Tokyo Electron Limited | Method for extending time between chamber cleaning processes |
US20130122711A1 (en) * | 2011-11-10 | 2013-05-16 | Alexei Marakhtanov | System, method and apparatus for plasma sheath voltage control |
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US20150218700A1 (en) * | 2013-03-08 | 2015-08-06 | Applied Materials, Inc. | Chamber component with protective coating suitable for protection against flourine plasma |
US9745658B2 (en) * | 2013-11-25 | 2017-08-29 | Lam Research Corporation | Chamber undercoat preparation method for low temperature ALD films |
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