JP2022509539A - エピタキシャル側方過成長を用いて滑らかな表面を取得する方法 - Google Patents
エピタキシャル側方過成長を用いて滑らかな表面を取得する方法 Download PDFInfo
- Publication number
- JP2022509539A JP2022509539A JP2021548562A JP2021548562A JP2022509539A JP 2022509539 A JP2022509539 A JP 2022509539A JP 2021548562 A JP2021548562 A JP 2021548562A JP 2021548562 A JP2021548562 A JP 2021548562A JP 2022509539 A JP2022509539 A JP 2022509539A
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- Prior art keywords
- group iii
- iii nitride
- substrate
- nitride semiconductor
- layer
- Prior art date
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Images
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Abstract
Description
本願は、以下の同時係属中、かつ本発明の譲受人に譲渡された出願の35 U.S.C.Section 119(e)(米国特許法第119条(e))下の利益を主張する:
Takeshi KamikawaおよびSrinivas Gandrothulaによる、「METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH」と題され、2018年10月31日に出願された米国仮出願第62/753,225号(弁理士整理番号第G&C 30794.0693USP1(UC 2019-166-1)号)。
(概要)
(錐体ヒロック)
(製作方法)
(ステップ1.成長制限マスクを形成する)
(ステップ2.III族窒化物半導体層を成長させる)
以下の成長条件が、使用された。
(ステップ3.素子プロセス)
(III族窒化物半導体素子)
図8は、光学共振器と垂直な方向に沿って製作されたIII族窒化物半導体レーザダイオード素子110の断面側面図である。
(ステップ6.基板から素子のバーを除去する)
(バーを除去する)
(m面の表面の別個のエリアにおいて劈開する)
(ステップ7:素子の別個のエリアにおいてn電極を製作する)
(ステップ8.素子のバーをチップに切断する)
(ステップ9.ヒートシンクプレート上に素子を搭載する)
(ステップ10.レーザのファセットをコーティングする)
(ステップ11.コーティングバーを分割する)
(ステップ12.素子をスクリーニングする)
(ステップ13.素子をパッケージの上/中に搭載する)
(LED素子を製作する)
(用語の定義)
(III族窒化物系基板)
(ヘテロ基板)
(成長制限マスク)
(1-100)面に配向されたIII族窒化物系半導体基板101の11-20方向と平行な第1の方向、およびIII族窒化物系半導体基板101の0001方向と平行な第2の方向に配置され、第2の方向に延びている。開放エリア103の長さaは、例えば、200~35,000μmであり、幅bは、例えば、2~180μmであり、開放エリア102の間隔p1は、例えば、20~180μmであり、間隔p2は、例えば、200~35,000μmであり、マスク部分の幅は、60μmであり、1-100方向における開放エリア103と開放エリア103との間の距離は、100μmである。
(III族窒化物系半導体層)
(エピタキシャル側方過成長)
(平坦な表面領域)
(非成長領域)
(層屈曲領域)
(素子)
(ポリマー膜)
(ヒートシンクプレート)
(異なる実施形態)
(第1の実施形態)
(第2の実施形態)
(第3の実施形態)
(プロセスステップ)
(専門用語)
(結論)
Claims (19)
- 方法であって、前記方法は、複数のIII族窒化物半導体層から成る素子を製作することを含み、前記複数のIII族窒化物半導体層は、その中に埋め込まれた少なくとも1つの錐体ヒロックを含み、前記錐体ヒロックは、基板の上または上方に前記複数のIII族窒化物系半導体層のうちの少なくとも1つを堆積させるとき、成長制限マスクの開放エリア内に形成される、方法。
- 前記III族窒化物半導体層のうちの一部は、前記成長制限マスクおよびエピタキシャル側方過成長を使用して、前記基板の上または上方に形成され、前記エピタキシャル側方過成長は、前記III族窒化物半導体層が合体する前に停止させられる、請求項1に記載の方法。
- 前記錐体ヒロックは、前記エピタキシャル側方過成長中に形成され、前記錐体ヒロックは、前記エピタキシャル側方過成長に埋め込まれる、請求項2に記載の方法。
- 前記成長制限マスクは、横方向への前記錐体ヒロックの拡張を限定する、請求項2に記載の方法。
- 前記複数のIII族窒化物半導体層は、III族窒化物基板の上または上方に成長させられる、請求項1に記載の方法。
- 前記複数のIII族窒化物半導体層は、ヘテロ基板の上または上方に成長させられ、III族窒化物テンプレートが、前記複数のIII族窒化物半導体層の前に前記ヘテロ基板の上または上方に堆積させられる、請求項1に記載の方法。
- 前記島状III族窒化物半導体層は、隣接する島状III族窒化物半導体層と合体しない、請求項1に記載の方法。
- 前記複数のIII族窒化物半導体層は、前記III族窒化物基板から除去される、請求項1に記載の方法。
- 前記複数のIII族窒化物半導体層は、
膜を前記III族窒化物半導体層に適用することと、
前記膜に圧力を加えることと、
前記膜および前記基板の温度を変化させることと、
前記圧力が加えられ、前記温度が変化させられた後、前記基板から前記III族窒化物半導体層を伴う前記膜を剥離することと
によって、前記III族窒化物基板から除去される、請求項1に記載の方法。 - 請求項1に記載の方法によって製作された素子。
- 素子であって、前記素子は、複数のIII族窒化物半導体層から成る素子を備え、前記複数のIII族窒化物半導体層は、その中に埋め込まれた少なくとも1つの錐体ヒロックを含み、前記錐体ヒロックは、基板の上または上方に前記複数のIII族窒化物系半導体層のうちの少なくとも1つを堆積させるとき、成長制限マスクの開放エリア内に形成される、素子。
- 前記III族窒化物半導体層のうちの一部は、前記成長制限マスクおよびエピタキシャル側方過成長を使用して、前記基板の上または上方に形成され、前記エピタキシャル側方過成長は、前記III族窒化物半導体層が合体する前に停止させられる、請求項11に記載の素子。
- 前記錐体ヒロックは、前記エピタキシャル側方過成長中に形成され、前記錐体ヒロックは、前記エピタキシャル側方過成長に埋め込まれる、請求項12に記載の素子。
- 前記成長制限マスクは、横方向への前記錐体ヒロックの拡張を限定する、請求項12に記載の素子。
- 前記複数のIII族窒化物半導体層は、III族窒化物基板の上または上方に成長させられる、請求項11に記載の素子。
- 前記複数のIII族窒化物半導体層は、ヘテロ基板の上または上方に成長させられ、III族窒化物テンプレートが、前記複数のIII族窒化物半導体層の前に前記ヘテロ基板の上または上方に堆積させられる、請求項11に記載の素子。
- 前記島状III族窒化物半導体層は、隣接する島状III族窒化物半導体層と合体しない、請求項11に記載の素子。
- 前記複数のIII族窒化物半導体層は、前記III族窒化物基板から除去される、請求項11に記載の素子。
- 請求項11に記載の素子を製作する方法。
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US201862753225P | 2018-10-31 | 2018-10-31 | |
US62/753,225 | 2018-10-31 | ||
PCT/US2019/059086 WO2020092722A1 (en) | 2018-10-31 | 2019-10-31 | Method of obtaining a smooth surface with epitaxial lateral overgrowth |
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WO2023153358A1 (ja) * | 2022-02-10 | 2023-08-17 | 京セラ株式会社 | レーザ素子の製造方法および製造装置 |
WO2023238923A1 (ja) * | 2022-06-09 | 2023-12-14 | 京セラ株式会社 | 半導体レーザデバイスの製造方法および製造装置 |
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WO2023076607A1 (en) * | 2021-10-29 | 2023-05-04 | The Regents Of The University Of California | Light emitting diodes containing epitaxial light control features |
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US20080315222A1 (en) * | 2007-06-22 | 2008-12-25 | Kyung Jun Kim | Semiconductor light emitting device and method of manufacturing the same |
US20150187985A1 (en) * | 2012-07-31 | 2015-07-02 | Osram Opto Semiconductors Gmbh | Method for Producing an Optoelectronic Semiconductor Chip and Optoelectronic Semiconductor Chip |
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WO2023153358A1 (ja) * | 2022-02-10 | 2023-08-17 | 京セラ株式会社 | レーザ素子の製造方法および製造装置 |
WO2023238923A1 (ja) * | 2022-06-09 | 2023-12-14 | 京セラ株式会社 | 半導体レーザデバイスの製造方法および製造装置 |
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CN113287205A (zh) | 2021-08-20 |
US20210381124A1 (en) | 2021-12-09 |
WO2020092722A1 (en) | 2020-05-07 |
WO2020092722A9 (en) | 2020-08-27 |
EP3874544A1 (en) | 2021-09-08 |
EP3874544A4 (en) | 2021-12-29 |
JP7351546B2 (ja) | 2023-11-13 |
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