JP2022506418A5 - - Google Patents

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Publication number
JP2022506418A5
JP2022506418A5 JP2021523783A JP2021523783A JP2022506418A5 JP 2022506418 A5 JP2022506418 A5 JP 2022506418A5 JP 2021523783 A JP2021523783 A JP 2021523783A JP 2021523783 A JP2021523783 A JP 2021523783A JP 2022506418 A5 JP2022506418 A5 JP 2022506418A5
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JP
Japan
Prior art keywords
matrix
submatrix
input register
multiplication
stored
Prior art date
Application number
JP2021523783A
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English (en)
Japanese (ja)
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JPWO2020091848A5 (https=
JP7461945B2 (ja
JP2022506418A (ja
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Priority claimed from US16/176,449 external-priority patent/US11093580B2/en
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Publication of JP2022506418A publication Critical patent/JP2022506418A/ja
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Publication of JPWO2020091848A5 publication Critical patent/JPWO2020091848A5/ja
Priority to JP2023065959A priority Critical patent/JP2023089161A/ja
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JP2021523783A 2018-10-31 2019-06-18 部分行列の順序付けを伴う行列乗算器 Active JP7461945B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023065959A JP2023089161A (ja) 2018-10-31 2023-04-13 部分行列の順序付けを伴う行列乗算器

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/176,449 2018-10-31
US16/176,449 US11093580B2 (en) 2018-10-31 2018-10-31 Matrix multiplier with submatrix sequencing
PCT/US2019/037656 WO2020091848A1 (en) 2018-10-31 2019-06-18 Matrix multiplier with submatrix sequencing

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JP2023065959A Division JP2023089161A (ja) 2018-10-31 2023-04-13 部分行列の順序付けを伴う行列乗算器

Publications (4)

Publication Number Publication Date
JP2022506418A JP2022506418A (ja) 2022-01-17
JP2022506418A5 true JP2022506418A5 (https=) 2022-06-22
JPWO2020091848A5 JPWO2020091848A5 (https=) 2022-06-22
JP7461945B2 JP7461945B2 (ja) 2024-04-04

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JP2021523783A Active JP7461945B2 (ja) 2018-10-31 2019-06-18 部分行列の順序付けを伴う行列乗算器
JP2023065959A Withdrawn JP2023089161A (ja) 2018-10-31 2023-04-13 部分行列の順序付けを伴う行列乗算器

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Country Status (6)

Country Link
US (1) US11093580B2 (https=)
EP (1) EP3891626A4 (https=)
JP (2) JP7461945B2 (https=)
KR (1) KR102586989B1 (https=)
CN (1) CN113168430A (https=)
WO (1) WO2020091848A1 (https=)

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US20210303987A1 (en) * 2020-03-26 2021-09-30 Advanced Micro Devices, Inc. Power reduction for machine learning accelerator background
US11720328B2 (en) 2020-06-26 2023-08-08 Advanced Micro Devices, Inc. Processing unit with small footprint arithmetic logic unit
CN112429475B (zh) * 2020-09-29 2023-06-30 贵州大学 一种胶囊排序送料装置
CN112433760B (zh) * 2020-11-27 2022-09-23 海光信息技术股份有限公司 数据排序方法和数据排序电路
CN112632464B (zh) * 2020-12-28 2022-11-29 上海壁仞智能科技有限公司 用于处理数据的处理装置
US11556337B2 (en) 2021-04-12 2023-01-17 Analog Devices International Unlimited Company Parallel matrix multiplication technique optimized for memory fetches
CN117407640A (zh) * 2022-07-15 2024-01-16 华为技术有限公司 一种矩阵计算方法及装置
KR102640249B1 (ko) * 2023-06-12 2024-02-27 주식회사 하이퍼엑셀 대규모 언어 모델을 위해 멀티-디바이스에 기반한 추론을 수행하는 방법 및 시스템
CN119883379B (zh) * 2024-12-24 2025-11-18 深圳市鸿合创新信息技术有限责任公司 数据排序方法、装置、电子设备和存储介质

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JPH05324700A (ja) * 1992-05-19 1993-12-07 N T T Data Tsushin Kk 行列乗算装置
JP3935678B2 (ja) * 2001-01-31 2007-06-27 富士通株式会社 Ｓｉｍｄ積和演算方法、積和演算回路、および、半導体集積回路装置
US6901422B1 (en) * 2001-03-21 2005-05-31 Apple Computer, Inc. Matrix multiplication in a vector processing system
US20040122887A1 (en) * 2002-12-20 2004-06-24 Macy William W. Efficient multiplication of small matrices using SIMD registers
US20050240646A1 (en) * 2004-04-23 2005-10-27 The Research Foundation Of State University Of New York Reconfigurable matrix multiplier architecture and extended borrow parallel counter and small-multiplier circuits
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